Self-biased, low-harmonic, high-efficiency inverse Class D RF power amplifier circuit

Abstract

This invention provides a power amplifier circuit that enhances performance and efficiency while ensuring precise control over the operation of power transistors, offering advantages for various applications requiring wireless high-frequency signal amplification. [Solution] In the power amplifier circuit 10, the self-bias circuit 12 includes a low-dropout (TX-LDO) regulator 30, a digital-to-analog converter 34, and a digital processor 36 that generate and apply a gate bias voltage vgate_pa in response to a feedback current scaled according to the operating current of the power amplifier 14. The current-based digital-to-analog converter 34 generates a reference current based on a digital value received via a digital bus 38 from the digital processor 36, which generates a digital value in response to the gate bias voltage.

Description

Technical Field

[0001] Related Applications This application claims the benefit of Provisional Patent Application No. 63 / 698,193, filed September 24, 2024, the disclosure of which is hereby incorporated by reference in its entirety.

[0002] The present disclosure is directed to high-efficiency power amplifiers for low-power, low-cost wireless such as unlicensed wireless including ultra-wideband wireless. The present disclosure provides a self-biased inverse class-D radio frequency power amplifier that improves the output power spectrum in response to changes in antenna impedance.

Background Art

[0003] High-efficiency power amplifiers with low harmonic conduction are a challenge for low-power, low-cost wireless such as Zigbee, Bluetooth® Low Energy, and ultra-wideband. Research has focused on improving the trade-off between efficiency and linearity. Class-D switching power amplifiers provide higher efficiency compared to class-A / B / AB radio frequency power amplifiers, however, class-D switching power amplifiers suffer from an increase in third harmonic components. The present disclosure relates to a lower second harmonic / third harmonic inverse class-D radio frequency power amplifier that has been demonstrated to have improved efficiency and very low harmonics generated. By using a current-based digital-to-analog converter to self-bias the power amplifier, the spreading of output power due to antenna impedance and power variations are improved.

Summary of the Invention

[0004] A power amplifier circuit is disclosed, comprising an inverse Class D amplifier functioning as a power amplifier and a self-bias circuit that generates a gate bias voltage for a switching-type power transistor within the power amplifier. The self-bias circuit includes a low-dropout regulator that generates and applies a gate bias voltage in response to a feedback current, scaled according to the operating current of the power amplifier. A current-based digital-to-analog converter is configured to generate a reference current based on a received digital value. Furthermore, a digital processor is configured to generate a digital value supplied to the digital-to-analog converter. The power amplifier circuit enhances performance and efficiency while ensuring precise control over the operation of the power transistor, offering advantages to a variety of applications requiring wireless high-frequency signal amplification.

[0005] In other embodiments, any of the embodiments described herein may be combined individually or together, and / or various distinct embodiments and features described herein may be combined for further advantages. Any of the various features and elements disclosed herein may be combined with one or more other disclosed features and elements unless otherwise indicated herein.

[0006] Those skilled in the art will understand the scope of this disclosure and recognize additional embodiments after reading the following detailed description of preferred embodiments associated with the accompanying drawings. [Brief explanation of the drawing]

[0007] The accompanying drawings incorporated herein and forming part of herein illustrate several aspects of this disclosure and, together with the specification, serve to illustrate the principles of this disclosure.

[0008] [Figure 1] Figure 1 shows an exemplary embodiment of a power amplifier circuit designed to amplify radio frequency (RF) signals using an inverse Class D configuration. [Figure 2] Figure 2 shows a current digital-to-analog converter circuit. [Figure 3] Figure 3 shows a square waveform with a 50% duty cycle. [Figure 4] Figure 4 shows the spectrum of a 50% duty cycle square waveform. [Figure 5] Figure 5 shows a square waveform with a 33.33% duty cycle. [Figure 6] Figure 6 shows the spectrum of a 33.33% duty cycle square waveform. [Figure 7] Figure 7 is a plot showing output power versus different real antenna impedances. [Figure 8] Figure 8 is a graph showing the power amplifier load current versus load reflection coefficient phase angle for various load reflection coefficient magnitudes. [Figure 9] Figure 9 shows how an inverse Class D radio high-frequency power amplifier can be used in communication devices such as wireless communication equipment. [Modes for carrying out the invention]

[0009] The embodiments described below represent the information necessary to enable those skilled in the art to practice the embodiments and illustrate best modes of practice. After reading the following description in reference to the accompanying drawings, those skilled in the art will understand the concepts of this disclosure and recognize the applications of these concepts not specifically described herein. Naturally, these concepts and their applications are included in the scope of this disclosure and the accompanying claims.

[0010] In this specification, various elements may be described using terms such as first, second, etc., but it will be understood that these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. For example, without departing from the scope of this disclosure, the first element may be called the second element, and similarly, the second element may be called the first element. Where used herein, the term "and / or" includes all combinations of one or more of the related enumerated items.

[0011] When an element such as a layer, region, or substrate is described as being "on top of" or "extending upward" of another element, it will be understood that there may also be elements directly on top of, extending directly upward, or intervening to the other element. In contrast, when an element is described as being "directly on top of" or "extending directly upward" of another element, there are no intervening elements. Similarly, when an element such as a layer, region, or substrate is described as being "on top of" or "extending upward" of another element, it will be understood that there may also be elements directly on top of, extending directly upward, or intervening to the other element. In contrast, when an element is described as being "directly on top of" or "extending directly upward" of another element, there are no intervening elements. Furthermore, when an element is described as being "connected" or "joined" to another element, it will be understood that there may also be elements that are directly connected to, joined to, or intervening to the other element. In contrast, when one element is described as "directly connected" or "directly joined" to another, there are no intervening elements.

[0012] As shown in the figure, relative terms such as "below," "above," "upper," or "lower" may be used herein to describe the relationship between one element, layer, or region and another. It is understood that these terms, and those mentioned above, are intended to encompass different orientations of the apparatus in addition to the orientation depicted in the figure.

[0013] The terms used herein are for the purpose of describing specific embodiments and are not intended to limit the disclosure. Where used herein, the singular forms “a,” “an,” and “the” are intended to include the plural form unless otherwise clearly indicated by the context. Where used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” identify the presence of a described feature, integer, process, operation, element, and / or component, but do not preclude the presence or addition of one or more other features, integers, processes, operations, elements, and / or groups thereof.

[0014] Unless otherwise defined, all terms used herein (including technical and academic terms) have the same meaning as those generally understood by those skilled in the art to the extent of this disclosure. Furthermore, terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and the related art, and it will be understood that they should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0015] Embodiments are described herein with reference to schematic drawings of embodiments of the present disclosure. Therefore, the actual dimensions of layers and elements may differ, and are expected to differ from the shapes shown, for example, as a result of manufacturing techniques and / or tolerances. For example, areas illustrated or described as squares or rectangles may have rounded or curved features, and areas shown as straight lines may have some irregularities. Thus, the areas illustrated in the drawings are schematic, and their shapes are not intended to illustrate the exact shapes of areas in the device, nor are they intended to limit the scope of the present disclosure. Furthermore, the size of structures or areas may be exaggerated in comparison to other structures or areas for illustrative purposes, and are therefore provided to illustrate the general structure of the subject matter, and may or may not be drawn to scale. Elements common to both drawings are indicated here by common element numbers and will not be described again thereafter.

[0016] This disclosure addresses the challenge of achieving high efficiency in power amplifiers with low harmonic distortion, particularly for low-power, low-cost radio applications such as Zigbee, Bluetooth® Low Energy, and ultra-wideband. Class D switching power amplifiers offer higher efficiency compared to Class A / B / AB radio radio frequency (RF) power amplifiers, but suffer from increased third-harmonic components. Embodiments disclosed herein demonstrate lower H2 / H3 inverse Class D RF power amplifiers that result in improved efficiency and very low harmonics. Each embodiment of the disclosure employs a feedback loop that controls the output power of an antenna load by comparing the current drawn from the load with a reference current. The comparison is used to adjust the output power so that a constant level of output power is maintained despite changes in load impedance.

[0017] Some advantages of using the embodiments provided in this disclosure may include: ·The self - bias architecture using a current - based digital - to - analog converter simplifies output power programming and its spread over process, voltage, and temperature. ·A proven solution generates very low second - and third - order harmonics, leading to a reduction in RF off - chip filter components and cost savings. ·The high - efficiency power amplifier results in a reduction in current consumption, reduces the overall system cost, and significantly improves battery life.

[0018] Certain embodiments according to the present disclosure may include the following: ·A self - bias loop having power amplifier current stabilization for a desired power output level. ·A fully integrated transformer balun / unbalun and differential inverse class - D RF power amplifier for reducing the generated second - order harmonic (H2). ·Inputting a 33% duty - cycle RF signal to reduce the third - order harmonic (H3) component and improve the drain efficiency of the power amplifier.

[0019] An exemplary embodiment of the power amplifier circuit 10 shown in Figure 1 is designed to amplify radio frequency (RF) signals using an inverse Class D configuration. A self-bias circuit 12 is configured to generate gate bias voltages for a first transistor M1 and a second transistor M2, which constitute a power amplifier 14 configured in an inverse Class D configuration. The first transistor M1 and the second transistor M2 are switching-type power transistors. In the exemplary embodiment of Figure 1, the first transistor M1 and the second transistor M2 are laterally diffused, metal-oxide-semiconductor (LDMOS) type. A third transistor M3 is cascode-coupled with the first transistor M1, and a fourth transistor M4 is cascode-coupled with the second transistor M2. The first transistor M1 and the second transistor M2 isolate the input of the power amplifier 14 from the high output voltage swing at the drains of the first transistor M1 and the second transistor M2, allowing the third transistor M3 and the fourth transistor M4 to switch more efficiently without being damaged by high voltage stress. The fifth transistor M5 is coupled between the power source of the third transistor M3 and ground. The sixth transistor M6 is coupled between the power source of the fourth transistor M4 and ground. The fifth and sixth transistors M5 and M6 operate at relatively high speeds and help form the current waveform that flows through the amplifier 14. In reverse Class D operation, the fifth and sixth transistors M5 and M6 ensure that the current waveform remains close to a square wave, which is essential for efficient RF power transfer. By using a 33.33% duty cycle input signal, the drain efficiency and H3 level are significantly improved. There is no penalty to the H2 level because the design is completely different. This improves the power amplifier efficiency because less power is dissipated on the power amplifier transistors when the metal-oxide-semiconductor transistors are conductive.

[0020] The RF transformer 16 has a tapped input winding 18 coupled to the drains of the first transistor M1 and the second transistor M2. The RF transformer 16 also has an output winding 20 coupled between the antenna 22 and ground. The first capacitor C1 is coupled across the output winding 20 and is configured to adjust, filter, and ensure proper impedance matching at a desired frequency, enhancing the performance and efficiency of the power amplifier 14.

[0021] The power amplifier 14 is driven by a driver 24 that receives a distortion-corrected RF signal from a transmit digital control amplifier 26 configured to provide distortion correction to the RF signals (inp_rf, inn_rf). The transmit digital control amplifier 26 is used to address timing mismatches, or "distortions," between signals. In the present disclosure, distortion refers to the time difference between events that should ideally occur simultaneously. By correcting these timing mismatches, the distortion correction provided by the transmit digital control amplifier 26 ensures that the signals are properly aligned before reaching the power amplifier driver. This helps maintain the quality and reliability of the amplified RF signal, reduce errors, and improve the overall performance of the system.

[0022] The block low dropout (BLDO) regulator 28 supplies an adjusted voltage vdd_Iv to the transmit digital control amplifier 26, the driver 24, and the gate bias voltages of the third transistor M3 and the fourth transistor M4. In the exemplary embodiment of FIG. 1, the BLDO regulator 28 maintains an adjusted voltage vdd_Iv of 0.95V to 0.8V at 10 milliamperes.

[0023] The transmitter low-dropout (TX-LDO) regulator 30, which constitutes the self-bias circuit 12, generates a controlled gate bias voltage vgate_pa for the first transistor M1 and the second transistor M2. The TX-LDO regulator 30 also generates the power amplifier current I_PA and the supply voltage vdd_PA, which supply power to the power amplifier 14. In the exemplary embodiment shown in Figure 1, the power amplifier current I_PA is adjustable from 1mA to 60mA, and the supply voltage vdd_PA is adjustable from 1.2V to 1.8V.

[0024] Referring here to a more detailed schematic diagram of the TX-LDO regulator 30 in the initial diagram of Figure 1, the power amplifier 14 acts as a current source for the power amplifier current I_PA during the switching operation of the first transistor M1 and the second transistor M2, which are thick oxide transconductance transistors in this exemplary embodiment. The power amplifier current I_PA flows through the relatively large first p-type metal-oxide-semiconductor (PMOS) transistor MP1, which is mirrored by the first n-type (NMOS) transistor MN1 and the second NMOS transistor MN2, which are paired with the second PMOS transistor MP2 in a 1:200 ratio. The resulting current is compared to the current-based digital-to-analog converter (I-DAC) current and the feedback voltage that sets the gate bias voltage vgate_pa of the first transistor M1. The supply voltage vdd_PA is filtered by the second capacitor C2 and supplied to the non-inverting terminal of the voltage comparator 32, which compares the supply voltage vdd_PA with an external reference voltage vref_pa and, in response, dynamically biases the gates of the first PMOS transistor MP1 and the second PMOS transistor MP2.

[0025] The I-DAC current is generated by the transmit (TX) I-DAC 34. In the exemplary embodiment shown in Figure 1, the TX IDAC 34 is configured to adjust the I-DAC current from 2 μA to 512 μA. The TX I-DAC 34 is controlled by a digital processor 36 via a digital bus 38. The digital processor 36 is configured to receive feedback of the gate bias voltage vgate_pa and, in response, generate a digital value via the digital bus and transmit it to the TX I-DAC 34. The digital processor 36 may generate digital values ​​under the control of firmware and / or a lookup table. The I-DAC current, and mirroring by the digital processor 36, provides self-bias program adjustment of the power amplifier current I_PA and, therefore, the output power delivered by the power amplifier 14.

[0026] An exemplary embodiment of the TX I-DAC34 is shown in Figure 2. In this exemplary embodiment, the TX I-DAC34 provides a 4-bit binary-scale PMOS current source. The four most significant bits are implemented as a thermometer coded with a 16x scale PMOS current source. The TX-DAC34 consists of series-coupled resistors R1-RN, current sources Q1-QN, and bit switch b <0> From TERMO <15> It has parallel branches configured up to that point.

[0027] Figure 3 shows a 50% duty cycle square waveform used in a conventional inverse Class D RF power amplifier. The Fast Fourier Transform result of the associated 50% duty cycle signal is shown in Figure 4.

[0028] Figure 5 shows a 33.33% duty cycle square waveform used in embodiments of this disclosure. By using a 33.33% duty cycle input signal, the drain efficiency and third harmonic (H3) level are substantially improved compared to the H3 level produced by the 50% duty cycle square waveform shown in Figure 3, compared to the H3 level shown in Figure 4. There is no penalty for the second harmonic (H2) level because the design is entirely different.

[0029] As shown in Figure 6, even with a 33.33% RF input signal duty cycle, the first harmonic power remains virtually unchanged and the H3 component is reduced. The H2 component is in phase with both differential outputs of the RF power amplifier and is suppressed by the transformer. Releasing the input signal early also improves the efficiency of the power amplifier. When the first transistor M1 and the second transistor M2 are conductive, less power is dissipated by the power amplifier 14. As shown in Figure 6, compared to a 50% duty cycle power amplifier, the 33.33% duty cycle inverse Class D RF power amplifier improves drain efficiency and H3 levels.

[0030] As shown in Figure 7, output power variation with different antenna impedances is significantly better compared to conventional steady-state bias power amplifier architectures. Figure 8 is a graph of power amplifier load current versus magnitude and phase angle for various load reflection coefficients. Overall, the performance shown in Figures 7 and 8 demonstrates that the disclosed power amplifier circuit provides a substantial improvement in efficiency and harmonic distortion for low-power, low-cost radios. By using a self-bias architecture with the I-DAC34, output power programming is simplified and spread across process voltage and temperature is improved. The RF transformer 16 can be fully integrated and configured as a balun so that the differential inverse Class D RF power amplifier reduces second harmonic generation while the 33% duty cycle RF signal reduces third harmonic components, resulting in reduced current consumption and improved battery life.

[0031] Figure 9 shows how the disclosed power amplifier circuit 10 may be used in communication devices such as wireless communication devices. Referring to Figure 9, the above concept may be implemented in various types of wireless communication devices or user elements 40, such as mobile terminals, smartwatches, tablets, computers, navigation devices, and access points, which support wireless communication such as cellular, wireless local area network (WLAN), Bluetooth, short-range wireless communication, and ultra-wideband. User elements 40 generally include a control system 42, a baseband processor 44, a transmitting circuit 46, a receiving circuit 48, an antenna switching circuit 50, multiple antennas 52, and a user interface circuit 54. The amplifier in the transmitting circuit 46 is powered by the power amplifier circuit 10. The baseband processor 44 is configured to set an appropriate output voltage for the transmitting circuit 46. The receiving circuit 48 receives radio high-frequency signals, including ultra-wideband signals, from one or more base stations and / or other wireless communication devices configured similarly to the wireless communication device 40, via the antennas 52 and the antenna switching circuit 50. Low-noise amplifiers and filters work together to amplify and remove broadband interference from the received signal for processing. Down-conversion and digitization circuits (not shown) then down-convert the filtered received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams.

[0032] The baseband processor 44 processes the digitized received signal to extract the information, or data bits, transmitted in the received signal. This processing typically includes demodulation, decoding, and error correction operations. The baseband processor 44 is generally implemented in one or more digital signal processors and application-specific integrated circuits.

[0033] For transmission, the baseband processor 44 receives digitized data from the control system 42, which it codes for transmission, which may represent voice, data, or control information. The encoded data is output to the transmission circuit 46, which is used by a modulator to modulate a carrier signal at a desired transmission frequency(s), such as an ultra-wideband high frequency ranging from 3.1 GHz to 10.5 GHz. The ultra-wideband bandwidth is greater than 500 MHz.

[0034] The power amplifier amplifies the modulated carrier signal to a level suitable for transmission and delivers the modulated carrier signal to the antenna 52 through the antenna switching circuit 50. The antenna 52, as well as the duplicated transmitting circuit 46 and receiving circuit 48, can provide spatial diversity. Details of the adjustment and processing will be understood by those skilled in the art.

[0035] Any of the embodiments described herein, and / or various other embodiments and features described herein, can be combined to obtain further advantages. Any of the various embodiments disclosed herein can be combined with one or more other disclosed embodiments unless otherwise specifically stated herein.

[0036] Those skilled in the art will recognize improvements and modifications to preferred embodiments of this disclosure. All such improvements and modifications are deemed to be within the scope of the concepts disclosed herein and the following claims.

Claims

1. A power amplifier circuit, A power amplifier configured as an inverse Class D amplifier, It is a self-bias circuit, A low-dropout regulator configured to generate and apply a gate bias voltage to a switching-type power transistor comprising the power amplifier in response to a feedback current scaled to the power amplifier current flowing within the power amplifier, A current-based digital-to-analog converter configured to generate the feedback current based on the received digital value, A power amplifier circuit comprising a digital processor configured to generate the digital value in response to the gate bias voltage, and a self-bias circuit.

2. The power amplifier circuit according to claim 1, wherein the switching type transistors are a first transistor and a second transistor, which are laterally diffused metal oxide film semiconductor type switching transistors.

3. The power amplifier circuit according to claim 2, further comprising a third transistor and a fourth transistor, each cascode-coupled with the first transistor and the second transistor, in order to isolate the input of the power amplifier from high output voltage swings and improve switching efficiency.

4. The power amplifier circuit according to claim 2, further comprising an RF transformer having a tapped input winding coupled to the drains of the first and second transistors, and an output winding coupled between the antenna and ground.

5. The power amplifier circuit according to claim 1, wherein the feedback current is generated based on the power amplifier current flowing within the power amplifier and scaled by a first p-type metal-oxide-semiconductor transistor that mirrors the power amplifier current.

6. The power amplifier circuit according to claim 1, wherein a self-bias feedback loop is closed between the power amplifier and the self-bias circuit to provide power amplifier current stabilization with respect to a desired output power level.

7. The power amplifier circuit according to claim 6, wherein the self-bias feedback loop controls the output power level by adjusting the output power level so that the current supplied to the antenna load by the power amplifier is compared with a reference current and the output power level is maintained at a constant level despite changes in load impedance.

8. The power amplifier circuit according to claim 1, wherein the power amplifier is configured to amplify a 33% duty cycle RF signal, reduce third harmonic components, and improve the drain efficiency of the power amplifier.

9. The power amplifier circuit according to claim 1, wherein the current-based digital-to-analog converter includes a 4-bit binary-scale current source.

10. The power amplifier circuit according to claim 1, wherein the current-based digital-to-analog converter is configured to adjust the feedback current generated by the current-based digital-to-analog converter to 2 μA to 512 μA.

11. A method for operating a power amplifier circuit, wherein the method is The purpose is to amplify radio frequency (RF) signals using an inverse Class D configuration with a power amplifier, A low-dropout regulator is used to generate and apply a gate bias voltage to a switching-type power transistor constituting the power amplifier, in response to a feedback current that is scaled to the power amplifier current flowing within the power amplifier. Using a current-based digital-to-analog converter, a reference current is generated based on the received digital value, A method comprising using a digital processor to generate the digital value in response to the gate bias voltage.

12. The method according to claim 11, further comprising fabricating a metal-oxide-semiconductor type switching transistor in which the switching type transistor is diffused laterally.

13. The method according to claim 12, further comprising cascode-coupled a third transistor and a fourth transistor with the first transistor and the second transistor, respectively, to isolate the input of the power amplifier from high output voltage swings and improve switching efficiency.

14. The method according to claim 12, further comprising using an RF transformer having a first transistor, tapped input windings coupled to the drains of a second transistor, and an output winding coupled between an antenna and ground.

15. The method according to claim 11, wherein generating the feedback current includes mirroring the power amplifier current using a first p-type metal-oxide-semiconductor (PMOS) transistor.

16. The method according to claim 11, further comprising closing the self-bias feedback loop between the power amplifier and the self-bias circuit to provide power amplifier current stabilization for a desired output power level.

17. The method according to claim 16, wherein controlling the output power level includes adjusting the output power level such that the current supplied by the power amplifier is compared to an antenna load having a reference current, and the output power level is maintained at a constant level despite changes in load impedance.

18. The method according to claim 11, further comprising amplifying a 33% duty cycle RF signal to reduce third-harmonic components and improve the drain efficiency of a power amplifier.

19. The method according to claim 11, wherein the current-based digital-to-analog converter includes a 4-bit binary-scale current source.

20. The method according to claim 11, wherein adjusting the feedback current includes adjusting the feedback current from 2 μA to 512 μA using the current-based digital-to-analog converter.

21. A wireless communication device, A receiving circuit configured to receive radio frequency (RF) signals, A baseband processor configured to process the digitized version of the RF signal received by the receiving circuit and to extract information or data bits transmitted in the received RF signal, A transmission circuit configured to receive encoded data from the baseband processor and adjust the carrier signal with the encoded data, A power amplifier circuit coupled to the aforementioned transmitting circuit, wherein the power amplifier circuit is A power amplifier configured as an inverse Class D amplifier, It is a self-bias circuit, A low-dropout regulator configured to generate and apply a gate bias voltage to a switching-type power transistor comprising the power amplifier in response to a feedback current scaled to the power amplifier current flowing within the power amplifier, A current-based digital-to-analog converter configured to generate a reference current based on a received digital value, A wireless communication device comprising a power amplifier circuit, which comprises a digital processor configured to generate the digital value in response to the gate bias voltage, and a self-bias circuit.

22. The wireless communication device according to claim 21, wherein the switching type transistors are a first transistor and a second transistor, which are laterally diffused metal oxide film semiconductor type switching transistors.

23. The wireless communication device according to claim 22, further comprising a third transistor and a fourth transistor, each cascode-coupled with the first transistor and the second transistor, in order to separate the input of the power amplifier from high output voltage swings and improve switching efficiency.

24. The wireless communication device according to claim 22, further comprising an RF transformer having a tapped input winding coupled to the drains of the first transistor and the second transistor, and an output winding coupled between the antenna and ground.

25. The wireless communication device according to claim 21, wherein the feedback current is generated based on a power amplifier current flowing within the power amplifier and scaled by a first p-type metal-oxide-semiconductor transistor that mirrors the power amplifier current.

26. The wireless communication device according to claim 21, wherein a self-bias feedback loop is closed between the power amplifier and the self-bias circuit to provide power amplifier current stabilization for a desired output power level.

27. The wireless communication device according to claim 26, wherein the self-bias feedback loop controls the output power level by adjusting the output power level so that the current supplied to the antenna load by the power amplifier is compared with a reference current and the output power level is maintained at a constant level despite changes in load impedance.

28. The wireless communication device according to claim 21, wherein the power amplifier is configured to amplify a 33% duty cycle RF signal, reduce third harmonic components, and improve the drain efficiency of the power amplifier.

29. The wireless communication device according to claim 21, wherein the current-based digital-to-analog converter includes a 4-bit binary-scale current source.

30. The wireless communication device according to claim 21, wherein the current-based digital-to-analog converter is configured to adjust the feedback current generated by the current-based digital-to-analog converter to 2 μA to 512 μA.

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