Semiconductor equipment

Abstract

One of the challenges is to improve the aperture ratio of semiconductor devices. [Solution] The drive circuit section and the display section (also called the pixel section) are located on the same substrate, and the drive The circuit section consists of source and drain electrodes made of metal, and the channel layer is made of oxide. A channel etch thin-film transistor for a drive circuit made of semiconductors, and made of metal The display unit has wiring for a drive circuit configured as follows: source electrode layer and drain electrode layer A pixel in which the upper layer is made of an oxide conductor and the semiconductor layer is made of an oxide semiconductor. A channel-protected thin-film transistor and wiring for the display unit made of oxide conductors It is a semiconductor device.

Description

[Technical Field]

[0001] This invention relates to a semiconductor device using an oxide semiconductor and a method for manufacturing the same.

[0002] In this specification, a semiconductor device refers to a device that can function by utilizing semiconductor properties. This refers to all types of semiconductor devices, including electro-optical devices such as display devices, semiconductor circuits, and electronic equipment. be. [Background technology]

[0003] Translucent metal oxides are used in semiconductor devices. For example, indi oxide Metal oxides that possess conductivity, such as tin (ITO) (hereinafter referred to as oxide conductors), are liquid crystals. It is used as a transparent electrode material required in display devices such as screens.

[0004] In addition, translucent metal oxides are attracting attention as materials that exhibit semiconductor properties. For example, in-Ga-Zn-O oxides are required in display devices such as liquid crystal displays. It is expected to be applied to semiconductor materials in particular. It is expected to be applied to the channel layer of FT (also known as FT).

[0005] TFTs using metal oxides with semiconductor properties (hereinafter referred to as oxide semiconductors) are low-temperature It can be manufactured by process. Therefore, ammo used in display devices, etc. There are growing expectations that it will be a substitute for or even surpass Rufus silicon.

[0006] Furthermore, both oxide conductors and oxide semiconductors are translucent. Therefore, using these... By constructing a TFT in this way, a translucent TFT can be fabricated (for example) (See Non-Patent Document 1.)

[0007] Furthermore, TFTs using oxide semiconductors have high field-effect mobility. Therefore, the TFT It is also possible to configure a drive circuit for a display device or the like using this (see, for example, Non-Patent Document 2). . ) . [Prior art documents] [Non-patent literature]

[0008] [Non-Patent Document 1] Tetsuo Nozawa, "Transparent Circuits," Nikkei Electronics, August 27, 2007 (no. 959), pp. 39-52. [Non-Patent Document 2] T.Osada, and 8 others, SID '09 DIGEST, pp.184-187(2009) [Overview of the project] [Problems that the invention aims to solve]

[0009] One aspect of the present invention aims to reduce the manufacturing cost of semiconductor devices.

[0010] One aspect of the present invention aims to improve the aperture ratio of a semiconductor device.

[0011] One aspect of the present invention addresses the issue of increasing the resolution of images displayed on the display unit of a semiconductor device. do.

[0012] One aspect of the present invention aims to provide a semiconductor device capable of high-speed operation. [Means for solving the problem]

[0013] One aspect of the present invention has a drive circuit section and a display section (also called a pixel section) on the same substrate, The drive circuit section includes a source electrode (also called a source electrode layer) and a drain electrode (drain electrode). (also referred to as a layer) is composed of a metal and the channel layer is composed of an oxide semiconductor It has a thin film transistor for a driving circuit and a wiring for a driving circuit composed of a metal. The display unit includes a thin film transistor for pixels in which the source electrode layer and the drain electrode layer are composed of an oxide conductor and the semiconductor layer is composed of an oxide semiconductor, and a wiring for a display unit composed of an oxide conductor. It is a semiconductor device having

[0014] As the thin film transistor for pixels and the thin film transistor for a driving circuit, an inverted staggered type thin film transistor having a bottom gate structure is used. The thin film transistor for pixels is a channel protection type (channel stop type) thin film transistor in which a channel protection layer is provided on the channel formation region of the semiconductor layer. On the other hand, the thin film transistor for a driving circuit is a channel etch type thin film transistor in which an oxide insulating film is provided in contact with the semiconductor layer exposed between the source electrode layer and the drain electrode layer.

[0015] Note that Non-Patent Document 1 does not disclose the manufacturing process of a specific TFT and the structures of other elements (for example, a capacitor element, etc.) constituting the semiconductor device. Also, there is no description of manufacturing a driving circuit and a light-transmissive TFT on the same substrate.

[0016] In a semiconductor device according to an aspect of the present invention, on the same substrate, a driving circuit portion having a TFT for a driving circuit and a display portion having a TFT for pixels are manufactured. Therefore, the manufacturing cost of the semiconductor device can be reduced.

[0017] Also, in a semiconductor device according to an aspect of the present invention, in the display portion, the source electrode and the drain electrode are made of an oxide ​​​​​​​​A pixel TFT composed of a conductor and having a semiconductor layer composed of an oxide semiconductor, , and wiring for the display unit made of an oxide conductor. In other words, the semiconductor device is Therefore, the area in which the pixel TFT and wiring for the display unit are formed can be made into an opening. Therefore, the aperture ratio of the semiconductor device can be improved.

[0018] Furthermore, in one aspect of the present invention, the semiconductor device has a display unit in which the source electrode and drain electrode are made of oxide A pixel TFT composed of a conductor and having a semiconductor layer composed of an oxide semiconductor, , and wiring for the display unit made of an oxide conductor. In other words, the semiconductor device is This allows for the design of pixel sizes without being limited by the size of the TFT used for pixels. Therefore, the image displayed on the display unit of the semiconductor device can be made higher resolution.

[0019] Furthermore, in one aspect of the present invention, the semiconductor device has a drive circuit section in which the source electrode and drain electrode are made of gold. A TFT for a drive circuit, composed of a group and with a channel layer made of oxide semiconductor. It has a drive circuit wiring made of metal. In other words, the semiconductor device is high The drive circuit is constructed using a TFT that exhibits high field-effect mobility and low-resistance wiring. Therefore, the semiconductor device can be made capable of high-speed operation.

[0020] Furthermore, the oxide semiconductor used in this specification is InMO3(ZnO) m (m>0) A thin film is formed, and a thin-film transistor is fabricated using this thin film as an oxide semiconductor layer. M is one or more metallic elements selected from Ga, Fe, Ni, Mn, and Co. This indicates a metallic element. For example, M can be Ga, or Ga and Ni, or Ga and In addition, the above oxide semiconductor may contain metal elements other than Ga, such as Fe. In addition to the metallic elements included as M, Fe, Ni, and other transition metals are included as impurity elements. Some contain elements or oxides of the transition metal. In this specification, In MO3(ZnO) m Among oxide semiconductor layers with a structure represented by (m>0), where M is Ga Oxide semiconductors with a structure containing are called In-Ga-Zn-O based oxide semiconductors, and their thin films are called I It is also called an n-Ga-Zn-O non-single crystal film.

[0021] In addition to the above, other metal oxides that can be applied to oxide semiconductor layers include In-Sn-Zn-O In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn -Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In- O-based, Sn-O-based, and Zn-O-based metal oxides can be applied. Silicon oxide may be included in the oxide semiconductor layer made of the material.

[0022] Under an inert gas atmosphere of nitrogen or a noble gas (argon, helium, etc.), or under reduced pressure When heat treatment is performed, the oxide semiconductor layer becomes oxygen-deficient due to the heat treatment, resulting in low resistance. , in other words, N-type transformation (N - (e.g., chemical treatment), and then the formation of an oxide insulating film in contact with the oxide semiconductor layer. By performing this process, the oxide semiconductor layer is made into an oxygen-rich state, thereby increasing its resistance, i.e., making it type I. It can also be said that this allows for thin-film transistors with good electrical characteristics and high reliability. This makes it possible to manufacture and provide semiconductor devices.

[0023] Dehydration or dehydrogenation is performed using nitrogen or an inert gas such as a noble gas (argon, helium, etc.). Under ambient temperature or reduced pressure, the temperature should be 350°C or higher, preferably 400°C or higher, below the substrate's strain point. By performing heat treatment, impurities such as moisture contained in the oxide semiconductor layer can be reduced.

[0024] In the above dehydration or dehydrogenation process, the oxide semiconductor layer after dehydration or dehydrogenation is heated. Thermal Desorption Spectroscopy: Even when measuring up to 450°C using TDS, two peaks appear in water, at least around 300°C. The heat treatment conditions should be such that no peak is detected. Therefore, dehydration or dehydrogenation should occur. For thin-film transistors using an oxide semiconductor layer that has undergone modification, TDS measurements were taken up to 450°C. Even after performing the test, no water peak, which typically appears around 300°C, is detected.

[0025] Then, the temperature is lowered from the heating temperature T used for dehydration or dehydrogenation of the oxide semiconductor layer. When doing so, use the same furnace that performed the dehydration or dehydrogenation, and without exposing it to the atmosphere, water or hydrogen It is important not to re-introduce it. Dehydration or dehydrogenation is performed to remove the oxide semiconductor layer. Lowering the resistance, i.e., making it N-type (N - After performing (etc.), the oxide semiconductor layer is made into a type I layer by increasing its resistance. When a thin-film transistor is fabricated using this method, the threshold voltage value of the thin-film transistor becomes positive. This makes it possible to realize a so-called normally-off switching element. Thin film transistor The gate voltage of the terminal is as close as possible to 0V when a positive threshold voltage is used to form the channel. It is desirable for semiconductor devices (display devices). However, the threshold voltage value of the thin-film transistor is minus In the case of an eggplant, current flows between the source electrode and the drain electrode even when the gate voltage is 0V. It is prone to becoming what is known as normally-on. In active-matrix display devices, the circuit The electrical characteristics of the thin-film transistors that make up the device are important, and these electrical characteristics will affect the performance of the display device. Right. In particular, the threshold voltage (Vth) is important among the electrical characteristics of thin-film transistors. Even if the field-effect mobility is high, the threshold voltage value is high, or the threshold voltage value is negative. Therefore, it is difficult to control as a circuit. The threshold voltage value is high, In the case of thin-film transistors with a large absolute value, when the driving voltage is low, the TFT It may fail to perform its switching function and become a load. In the case of a transistor, a channel is formed only when a positive voltage is applied to the gate voltage. A transistor that allows rain current to flow is desirable. If the drive voltage is not high enough, a channel will form. Transistors that do not form channels, or transistors that form channels and allow drain current to flow even under negative voltage conditions. Transistors are unsuitable as thin-film transistors for use in circuits.

[0026] Furthermore, the gas atmosphere used when lowering the temperature from the heating temperature T is the same as the gas atmosphere that was heated to the heating temperature T. You may switch to a different gas atmosphere. For example, the same gas atmosphere used for dehydration or dehydrogenation. Without exposing the material to the atmosphere in the furnace, high-purity oxygen gas or N2O gas, ultra-dry esters are used inside the furnace. The mixture is filled with a solution (with a dew point of -40°C or lower, preferably -60°C or lower) and cooled.

[0027] After reducing the moisture content in the membrane by heat treatment that involves dehydration or dehydrogenation, the moisture content is reduced. Slow cooling (or cooling) in an atmosphere where there is no dew (dew point of -40°C or lower, preferably -60°C or lower). Using the following oxide semiconductor film, the electrical characteristics of the thin film transistor are improved, and a thin film transistor having both mass productivity and high performance is realized.

[0028] In this specification, heat treatment under an inert gas atmosphere of nitrogen or a noble gas (such as argon or helium), or under reduced pressure is called heat treatment for dehydration or dehydrogenation. In this specification, only the desorption as H2 by this heat treatment is not called dehydrogenation, but for the sake of convenience, dehydration or dehydrogenation including the desorption of H, OH, etc. is also called.

[0029] When heat treatment is performed under an inert gas atmosphere of nitrogen or a noble gas (such as argon or helium), or under reduced pressure, the oxide semiconductor layer becomes oxygen-deficient type by the heat treatment and the resistance is reduced, that is, it is made N-type (N - -type, etc.). As a result, a region overlapping with the drain electrode layer is formed as a high-resistance drain region (also called HRD region) that is oxygen-deficient type.

[0030] Specifically, the carrier concentration of the high-resistance drain region is within the range of 1×10 17 / cm 3 or more, and is a region higher than at least the carrier concentration (less than 1×10 17 / cm 3 ) of the channel formation region. Note that the carrier concentration in this specification refers to the value of the carrier concentration obtained from Hall effect measurement at room temperature.

[0031] And by making at least a part of the dehydrated or dehydrogenated oxide semiconductor layer in an oxygen-excess state, the resistance is increased, that is, it is made I-type to form a channel formation region. Note that the dehydration ​Alternatively, a process to create an oxygen-rich state in a portion of a dehydrogenated oxide semiconductor layer is dehydration. Alternatively, the deposition of an oxide insulating film in contact with a dehydrogenated oxide semiconductor layer by sputtering, or oxidation Heat treatment after deposition of a material insulating film, or heat treatment in an oxygen-containing atmosphere, or in an inert gas atmosphere A process of heating under ambient air followed by cooling in an oxygen atmosphere, using ultra-dry air (with a dew point of -40°C or lower, preferred). This is done by cooling the temperature to -60°C or below.

[0032] Furthermore, at least a portion of the dehydrated or dehydrogenated oxide semiconductor layer (overlapping with the gate electrode layer) By selectively creating an oxygen-rich state in the (part) to form a channel-forming region, high resistance is achieved. It can also be converted to type I. It is in contact with a dehydrated or dehydrogenated oxide semiconductor layer. Then, a source electrode layer and a drain electrode layer made of metal electrodes such as Ti are formed, and the source electrode layer The exposed region that does not overlap with the drain electrode layer is selectively treated as an oxygen-rich state to form a channel. This can be formed. When selectively creating an oxygen-rich state, the second layer overlaps the source electrode layer. A first high-resistance drain region and a second high-resistance drain region overlapping the drain electrode layer are formed. The region between the first high-resistance drain region and the second high-resistance drain region is channel-shaped. This becomes a channel-forming region. That is, the channel-forming region self-regulates between the source electrode layer and the drain electrode layer. It is formed comprehensively.

[0033] This allows for the fabrication of semiconductor devices with thin-film transistors that exhibit good electrical characteristics and high reliability. And it becomes possible to provide it.

[0034] Furthermore, in the oxide semiconductor layer superimposed on the drain electrode layer (and source electrode layer), high resistance By forming a rain region, the reliability of the drive circuit can be improved. Specifically, by forming a high-resistance drain region, the high-resistance drain electrode layer can be separated from the drain electrode layer. The structure is designed to allow for a stepwise change in conductivity from the rain region to the channel formation region. Therefore, the drain electrode layer is connected to the wiring that supplies the high power potential VDD. When operated in this manner, even if a high electric field is applied between the gate electrode layer and the drain electrode layer, the resistance remains high. The drain region acts as a buffer, preventing the application of a localized high electric field and improving the transistor's breakdown voltage. This configuration can be achieved.

[0035] Furthermore, in the oxide semiconductor layer superimposed on the drain electrode layer (and source electrode layer), high resistance By forming a rain region, leakage in the channel formation region when the drive circuit is formed is reduced. This can reduce the current. Specifically, by forming a high-resistance drain region, the current can be reduced. As a path for the leakage current of a transistor flowing between the rain electrode layer and the source electrode layer, Rain electrode layer, high-resistance drain region on the drain electrode layer side, channel formation region, source electrode The order is the high-resistance drain region on the layer side, followed by the source electrode layer. In this case, in the channel formation region, The leakage current flowing from the low-resistance N-type region on the drain electrode layer side to the channel formation region is transmitted through the transistor. The zistor is concentrated near the interface between the gate insulating layer and the channel formation region, where it has high resistance when off. This is possible, and the back channel portion (the surface of the channel-forming region that is separated from the gate electrode layer) It is possible to reduce leakage current in some areas.

[0036] Furthermore, there is a first high-resistance drain region overlapping the source electrode layer, and a second drain electrode region overlapping the drain electrode layer. The high-resistance drain region depends on the width of the gate electrode layer, but it is a part of the gate electrode layer and gate isolation. By overlapping via the marginal layer, the electric field strength near the edge of the drain electrode layer is more effectively reduced. It is possible.

[0037] One embodiment of the invention disclosed herein comprises a first thin-film transistor on the same substrate. It has a pixel section and a drive circuit having a second thin-film transistor, and the first thin-film transistor is A gate electrode layer is placed on the substrate, a gate insulating layer is placed on the gate electrode layer, and an oxide layer is placed on the gate insulating layer. A semiconductor layer, a first oxide insulating layer in contact with a part of the oxide semiconductor layer, and the first oxide insulating layer and a source electrode layer and a drain electrode layer on the oxide semiconductor layer, and a first oxide insulating layer It has an elementary electrode layer and a gate electrode layer, gate insulating layer, oxide semiconductor of the first thin film transistor. The body layer, source electrode layer, drain electrode layer, first oxide insulating layer, and pixel electrode layer are light-transmitting. The source electrode layer and drain electrode layer of the second thin-film transistor are made of a second oxide insulating material. It is covered with layers, and the source electrode layer and drain electrode layer of the first thin-film transistor are made of different materials. ...with a conductive material having lower resistance than the source electrode layer and drain electrode layer of the first thin-film transistor. It is a semiconductor device.

[0038] One embodiment of the invention disclosed herein is a first gate electrode layer and a second gate electrode layer Form a gate insulating layer on the first gate electrode layer and the second gate electrode layer, A first oxide semiconductor layer overlapping the first gate electrode layer on an insulating layer, and a second gate electrode layer A second oxide semiconductor layer is formed that overlaps with the first oxide semiconductor layer and the second oxide semiconductor layer. After dehydrating or dehydrogenating the layer, without exposure to the atmosphere, the first oxide semiconductor layer and This prevents the re-importation of water and hydrogen into the second oxide semiconductor layer, and the second soaring onto the second oxide semiconductor layer. A drain electrode layer and a second drain electrode layer are formed, and a second is in contact with a part of the second oxide semiconductor layer. In the region where the oxide insulating layer and the first gate electrode layer of the first oxide semiconductor layer overlap, the first acid A oxide insulating layer is formed, and the first source electricity is placed on the first oxide semiconductor layer and the first oxide insulating layer. A polar layer and a first drain electrode layer are formed, and a first oxide insulating layer, a first source electrode layer, and A protective insulating layer is formed on the drain electrode layer (1) and the oxide insulating layer (2), and on the protective insulating layer A pixel electrode layer electrically connected to a first drain electrode layer or a first source electrode layer, and a second This is a method for fabricating a semiconductor device in which an oxide semiconductor layer and a conductive layer overlapping it are formed.

[0039] In the above configuration, the oxide semiconductor layer of the second thin-film transistor is the source electrode layer or The second thin film trace may have a region with a thinner film thickness than the region overlapping with the rain electrode layer. The oxide semiconductor layer of the inverter is thinner in the region that overlaps with the source electrode layer or drain electrode layer. It has a thin channel-forming region, and a second oxide insulating layer is provided on the channel-forming region. A structure with an electrolytic layer is also acceptable.

[0040] Since the first oxide insulating layer and the second oxide insulating layer can be formed in the same process, they have the same light transmittance. Insulating materials can be used.

[0041] Furthermore, the source electrode layer and drain electrode layer of the second thin-film transistor are made of Al, Cr, and Cu. , a film mainly composed of elements selected from Ta, Ti, Mo, and W, or an alloy film thereof It is preferable to use a metal conductive film consisting of a laminated film combining these elements.

[0042] On the other hand, the source electrode layer, drain electrode layer, and pixel electrode layer of the first thin-film transistor are as follows: Indium oxide, indium oxide tin alloy, indium oxide zinc alloy, or acid It is preferable to use a light-transmitting conductive film such as zinc oxide.

[0043] In the above configuration, the same substrate further has a capacitance section, and the capacitance section comprises capacitance wiring and the capacitance distribution The device has capacitive electrodes that overlap with the wires, and the capacitive wiring and capacitive electrodes may be translucent.

[0044] Furthermore, the source electrode layer or drain electrode layer of the oxide semiconductor layer of the second thin-film transistor A structure with overlapping high-resistance drain regions is also acceptable.

[0045] The ordinal numbers "1st" and "2nd" are used for convenience only and do not represent the order of processes or stacking. This does not indicate that the invention is uniquely named. This does not indicate anything.

[0046] In addition, as a display device having a drive circuit, besides liquid crystal display devices, there are also light-emitting devices using light-emitting elements. Examples include display devices and electronic paper displays that use electrophoretic display elements. .

[0047] In a light-emitting display device using a light-emitting element, the pixel section has multiple thin-film transistors, In the basic structure, the gate electrode of one thin-film transistor and the source wiring of another transistor (so The point where the drain wiring (also called the drain wiring layer) is connected. It has a location. Furthermore, in the drive circuit of a light-emitting display device using a light-emitting element, thin film tracer Connect the gate electrode of the transistor to the source or drain wiring of the thin-film transistor. It has a part that allows it to do so. [Effects of the Invention]

[0048] We can fabricate and provide thin-film transistors with stable electrical characteristics. Therefore, It is possible to provide a semiconductor device having a thin-film transistor with good electrical characteristics and high reliability. Cut. [Brief explanation of the drawing]

[0049] [Figure 1] A diagram illustrating a semiconductor device. [Figure 2] A diagram illustrating the method for manufacturing semiconductor devices. [Figure 3] A diagram illustrating the method for manufacturing semiconductor devices. [Figure 4] A diagram illustrating the method for manufacturing semiconductor devices. [Figure 5] A diagram illustrating the method for manufacturing semiconductor devices. [Figure 6] A diagram illustrating the method for manufacturing semiconductor devices. [Figure 7] A diagram illustrating a semiconductor device. [Figure 8] A diagram illustrating a semiconductor device. [Figure 9] A diagram illustrating a semiconductor device. [Figure 10] A diagram illustrating a semiconductor device. [Figure 11] A diagram illustrating a semiconductor device. [Figure 12] A diagram illustrating the pixel equivalent circuit of a semiconductor device. [Figure 13] A diagram illustrating a semiconductor device. [Figure 14] A diagram illustrating the block diagram of a semiconductor device. [Figure 15] Circuit diagram and timing chart for the signal line drive circuit. [Figure 16] A circuit diagram showing the configuration of a shift register. [Figure 17] Circuit diagram and timing chart explaining the operation of the shift register. [Figure 18] A diagram illustrating a semiconductor device. [Figure 19] A diagram illustrating a semiconductor device. [Figure 20] An external view showing an example of an e-book. [Figure 21] External view showing examples of television equipment and digital photo frames. [Figure 22] An external view showing an example of a gaming machine. [Figure 23] An external view showing an example of a portable computer and mobile phone. [Figure 24] A diagram illustrating a semiconductor device. [Figure 25] A diagram illustrating a semiconductor device. [Figure 26] A diagram illustrating a semiconductor device. [Figure 27] Circuit diagram of a semiconductor device. [Figure 28] A diagram illustrating a semiconductor device. [Figure 29] A diagram illustrating a semiconductor device. [Figure 30] Circuit diagram of a semiconductor device. [Figure 31] A diagram illustrating a semiconductor device. [Figure 32] A diagram illustrating a semiconductor device. [Figure 33] A diagram illustrating a semiconductor device. [Figure 34] A diagram illustrating a semiconductor device. [Figure 35] A diagram illustrating a semiconductor device. [Figure 36] A diagram illustrating a semiconductor device. [Figure 37] A diagram illustrating a semiconductor device. [Figure 38] A diagram illustrating a semiconductor device. [Figure 39] A diagram illustrating the method for manufacturing semiconductor devices. [Figure 40] A diagram illustrating the method for manufacturing semiconductor devices. [Modes for carrying out the invention]

[0050] The embodiments will be described in detail with reference to the drawings. However, the following description is not limited to the present invention. The form and details can be changed in various ways without departing from the gist and scope thereof, as is the case for those skilled in the art. Therefore, it is easy to understand. Accordingly, the description of the embodiment shown below should be interpreted as being limited to the following. It is not the case that... The same reference numeral is used consistently across different drawings for parts that are repeated, and explanations of their repetition are omitted.

[0051] (Embodiment 1) A semiconductor device and a method for manufacturing such a device will be described using Figures 1 to 3.

[0052] Figures 1(A1) to (C) show two thin-film transients with different structures fabricated on the same substrate. An example of the cross-sectional structure of the transistor is shown. The thin-film transistor 410 shown in Figures 1(A1) to (C) is It is a type of bottom gate structure called channel etch type, and the thin-film transistor 420 is This is one type of bottom gate structure called channel protection type (also called channel stop type). Thin-film transistors 410 and 420 are inverse staggered thin-film transistors. It is also said that.

[0053] Figure 1(A1) shows the plan view of the channel etch type thin-film transistor 410 arranged in the drive circuit. This is a diagram, and Figure 1(B) is a cross-sectional view along the line C1-C2 in Figure 1(A1). Also, Figure 1 (C) is a cross-sectional view along the line C3-C4 in Figure 1(A1).

[0054] The thin-film transistor 410 placed in the drive circuit is a channel-etch type thin-film transistor. A gate electrode layer 411 and a first gate insulating layer 40 are placed on a substrate 400 having an insulating surface. 2a, second gate insulating layer 402b, at least channel forming region 413, first high resistance Oxide semiconductor layer having drain region 414a and second high-resistance drain region 414b It includes a source electrode layer 415a and a drain electrode layer 415b. Also, thin-film transistor An oxide insulating layer 416 is provided that covers 410 and is in contact with the channel-forming region 413.

[0055] The first high-resistance drain region 414a is self-aligned in contact with the lower surface of the source electrode layer 415a. A second high-resistance drain region is formed in contact with the lower surface of the drain electrode layer 415b. Region 414b is formed in a self-aligned manner. In addition, channel formation region 413 is an oxide isolation region. It is in contact with the edge layer 416 and has a thin film thickness, and the first high-resistance drain region 414a, and This region has higher resistance than the second high-resistance drain region 414b (Type I region).

[0056] Furthermore, the thin-film transistor 410 has a source electrode layer 415a and It is preferable to use a metal material as the drain electrode layer 415b.

[0057] Furthermore, in a liquid crystal display device, when the pixel section and the driving circuit are formed on the same substrate, the driving circuit In this context, logic gates such as inverter circuits, NAND circuits, NOR circuits, and latch circuits are used. Thin-film transistors, sense amplifiers, constant voltage generators, VCOs, and other analog components make up the system. Thin-film transistors that make up a circuit have only positive polarity between the source electrode and the drain electrode. Only negative polarity is applied. Therefore, the second high-resistance drain region 41 where voltage withstand capability is required. The width of 4b may be designed to be wider than the width of the first high-resistance drain region 414a. The first high-resistance drain region 414a and the second high-resistance drain region 414b are at the gate electrode. You can widen the overlap with the layer.

[0058] Furthermore, the thin-film transistor 410 placed in the drive circuit is a single-gate thin-film transistor Although I explained using a zistor, a multi-gate with multiple channel formation regions can be used as needed. Thin-film transistors with this structure can also be formed.

[0059] Furthermore, a conductive layer 417 is provided that overlaps the channel formation region 413. By electrically connecting the electrode layer 411 and the conductive layer 4, the gate electrode layer 411 and the conductive layer 4 A gate voltage can be applied from above and below to the oxide semiconductor layer positioned between 17. Furthermore, the gate electrode layer 411 and the conductive layer 417 are at different potentials, for example, a fixed potential, GND, 0V and In such cases, the electrical characteristics of the TFT, such as the threshold voltage, can be controlled. That is, the gate electrode layer 411 functions as the first gate electrode layer, and the conductive layer 417 functions as the second By making it function as the gate electrode layer, the thin-film transistor 410 becomes a 4-terminal thin-film transistor It can be used as a ZISTA.

[0060] Furthermore, between the conductive layer 417 and the oxide insulating layer 416, there is a protective insulating layer 403 and a planar insulating layer 4 Stack 04 and 04.

[0061] Furthermore, the protective insulating layer 403 is provided below the first gate insulating layer 402 It is preferable to have a configuration that is in contact with a substrate insulating film, and moisture from the sides of the substrate , hydrogen ions, oxygen ions, OH - It blocks the entry of impurities such as the above. The first gate insulating layer 402a or the underlying insulating film that is in contact with the protective insulating layer 403 is nitrogen-filled. A silicon dioxide film is effective.

[0062] Furthermore, Figure 1(A2) shows the planar view of the channel-protected thin-film transistor 420 placed in the pixel. This is a diagram, and Figure 1(B) is a cross-sectional view along the line D1-D2 in Figure 1(A2). Also, Figure 1 (C) is a cross-sectional view along the line D3-D4 in Figure 1(A2).

[0063] The thin-film transistor 420 placed in the pixel is a channel-protected thin-film transistor. A gate electrode layer 421 and a first gate insulating layer 402a are provided on a substrate 400 having an insulating surface. Second gate insulating layer 402b, oxide semiconductor layer 422 including channel formation region, channel Oxide insulating layer 426, source electrode layer 425a, and drain electrode layer, which function as protective layers. Includes 425b. Also covers the thin-film transistor 420, oxide insulating layer 426, source power A protective insulating layer 403 and a planar insulating layer are in contact with the electrode layer 425a and the drain electrode layer 425b. Layer 404 is provided in a stacked manner. A drain electrode layer 425b is placed on the planar insulating layer 404. A pixel electrode layer 427 is provided that is in contact with the thin-film transistor 420 and is electrically connected to it. It is.

[0064] Furthermore, after the deposition of the oxide semiconductor film, a heat treatment (dehydration) is performed to reduce impurities such as water. Alternatively, heat treatment for dehydrogenation is performed. Heat treatment for dehydration or dehydrogenation. Then, after slow cooling, the oxide semiconductor layer is brought into contact with the oxide semiconductor layer to form an oxide insulating film. Reducing the carrier concentration in the body layer improves the electrical characteristics and reliability of the thin-film transistor 420. This will lead to improved reliability.

[0065] The channel formation region of the thin-film transistor 420 placed in the pixel is the oxide semiconductor layer 422 Of these, the oxide insulating layer 426, which is the channel protective layer, is in contact with the gate electrode layer 421. This is the region. The thin-film transistor 420 is protected by the oxide insulating layer 426. Therefore, in the etching process that forms the source electrode layer 425a and the drain electrode layer 425b, oxidation This prevents the crystalline semiconductor layer 422 from being etched.

[0066] Furthermore, the thin-film transistor 420 has a high aperture ratio as a light-transmitting thin-film transistor. To realize a display device, the source electrode layer 425a and the drain electrode layer 425b are light-transmitting. A conductive film having the following properties is used.

[0067] Furthermore, the gate electrode layer 421 of the thin-film transistor 420 also uses a transparent conductive film.

[0068] Furthermore, pixels on which thin-film transistors 420 are placed have a pixel electrode layer 427, or other The electrode layer (such as a capacitive electrode layer) and other wiring layers (such as a capacitive wiring layer) are transparent to visible light. A display device with a high aperture ratio is realized using a photosensitive conductive film. Of course, the first gate The insulating layer 402a, the second gate insulating layer 402b, and the oxide insulating layer 426 are also transparent to visible light. It is preferable to use a photosensitive film.

[0069] In this specification, a film that is transparent to visible light is defined as a film with a visible light transmittance of 75 to 100. This refers to a film with a thickness of %; if the film is conductive, it is also called a transparent conductive film. Also, gate electrode layer, source electrode layer, drain electrode layer, pixel electrode layer, or other electrodes As a metal oxide applied to the layer and other wiring layers, a conductive film that is semi-transparent to visible light is used. It is acceptable. Semi-transparent to visible light means that the transmittance of visible light is between 50% and 75%. .

[0070] Hereinafter, using Figures 2 and 3(A) to (E), a thin-film transistor 410 and This section describes the process for fabricating the thin-film transistor 420.

[0071] First, a translucent conductive film is formed on a substrate 400 having an insulating surface, and then the first film The gate electrode layers 411 and 421 are formed by the trisography process. In addition, the pixel area is equipped with Using a material having the same light-transmitting properties as the electrode layers 411 and 421, the first photolithograph A capacitive wiring layer is formed by the following process. Furthermore, if capacitance is required not only in the pixel section but also in the drive circuit... In addition, a capacitive wiring layer is formed in the drive circuit. It may also be formed by an inkjet method. If the resist mask is formed by an inkjet method, a photomask is used. Therefore, manufacturing costs can be reduced.

[0072] There are no major restrictions on the substrates that can be used for the substrate 400 having an insulating surface, however In addition, it is necessary that it has sufficient heat resistance to withstand subsequent heat treatment. The substrate 400 has glass such as barium borosilicate glass and aluminoborosilicate glass. A stainless steel substrate can be used.

[0073] Furthermore, if the temperature of the subsequent heat treatment is high, the strain point of the substrate 400 will be 730°C or higher. It is best to use the following. Also, for the glass substrate, for example, aluminosilicate glass, Glass materials such as luminoborosilicate glass and bariumborosilicate glass are used. Furthermore, by including more barium oxide (BaO) compared to boric acid, it becomes more practical. Heat-resistant glass can be obtained. Therefore, a glass substrate containing more BaO than B2O3 is used. This is preferable.

[0074] In addition, ceramic substrates, quartz substrates, sapphire substrates, etc. can be used instead of the glass substrates mentioned above. A substrate made of edge material may also be used. Other materials, such as crystallized glass, can also be used.

[0075] Alternatively, an insulating film that serves as the base layer may be provided between the substrate 400 and the gate electrode layers 411 and 421. The undercoat has the function of preventing the diffusion of impurity elements from the substrate 400, and is a silicon nitride film. The compound is formed by one or more films selected from silicon oxide films, silicon nitride films, or silicon oxidoxide-nitride films. It can be formed by a layered structure.

[0076] The material of the gate electrode layers 411 and 421 is a conductive material that is transparent to visible light, for example In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-G a-Zn-O series, Sn-Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al -Zn-O, In-O, Sn-O, and Zn-O metal oxides can be applied. The film thickness is appropriately selected within the range of 50 nm to 300 nm. Guard gate layer 411, 4 The metal oxide film deposition method used in 21 is sputtering or vacuum deposition (such as electron beam deposition). ) or the arc discharge ion plating method or the spray method are used. In addition, the sputtering method is used. When used, the film is deposited using a target containing 2% to 10% by weight of SiO2. The transparent conductive film contains SiOx (X>0) which inhibits crystallization, and in a later step... It is desirable to suppress crystallization during heat treatment for dehydration or dehydrogenation. It seems so.

[0077] Next, a gate insulating layer is formed on the gate electrode layers 411 and 421.

[0078] The gate insulating layer is formed using plasma CVD or sputtering, and consists of a silicon oxide layer and nitrided layer. A silicon layer, a silicon oxide nitride layer, or a silicon nitride oxide layer can be formed as a single layer or in multiple layers. For example, using SiH4, oxygen, and nitrogen as film-forming gases, an acid-based CVD method is used. A silicon nitride layer should be formed.

[0079] In this embodiment, a first gate insulating layer 402a with a film thickness of 50 nm to 200 nm, A gate insulating layer of a stack of second gate insulating layers 402b with a film thickness of 50 nm to 300 nm and The first gate insulating layer 402a is a silicon nitride film or oxidized nitride film with a thickness of 100 nm. A silicon film is used. In addition, the second gate insulating layer 402b is a silicon oxide film with a thickness of 100 nm. A film is used.

[0080] On the second gate insulating layer 402b, an oxide semiconductor film 43 with a thickness of 2 nm to 200 nm is placed. Formation of 0. Heat treatment for dehydration or dehydrogenation after the formation of the oxide semiconductor film 430. Even if this is done, the oxide semiconductor film will be in an amorphous state, so the film thickness will be thinned to 50 nm or less. This is preferable. By making the thickness of the oxide semiconductor film thin, the heat treatment after the formation of the oxide semiconductor layer is performed. This process can suppress crystallization.

[0081] Furthermore, before depositing the oxide semiconductor film 430 by sputtering, argon gas was introduced. Reverse sputtering is performed to generate plasma, and it adheres to the surface of the second gate insulating layer 402b. It is preferable to remove any debris. Reverse sputtering is a process where voltage is not applied to the target side. Under an argon atmosphere, a voltage is applied to the substrate side using an RF power supply to form a plasma near the substrate. This is a method for modifying the surface. Note that nitrogen, helium, and oxygen can be used instead of an argon atmosphere. You may also use the following:

[0082] The oxide semiconductor film 430 is an In-Ga-Zn-O non-single crystal film, an In-Sn-Zn-O system In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn- Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O In this embodiment, In-Ga - A film is deposited by sputtering using a Zn-O-based oxide semiconductor target. The semiconductor film 430 is subjected to a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas It can be formed by sputtering under an atmosphere of (typically argon) and oxygen. Furthermore, when using the sputtering method, the target contains 2% to 10% by weight of SiO2. A film is formed using a net, and SiOx (X>0) which inhibits crystallization is formed on the oxide semiconductor film 430. It contains a substance that crystallizes during subsequent heat treatments for dehydration or dehydrogenation. It is preferable to suppress the growth.

[0083] Furthermore, the oxide semiconductor film is preferably an oxide semiconductor containing In, and more preferably, This is an oxide semiconductor film containing In and Ga. The oxide semiconductor film is considered to be type I (intrinsic). Therefore, dehydration or dehydrogenation is effective.

[0084] Next, the oxide semiconductor film 430 is transformed into island-shaped oxide semiconductors by a second photolithography process. The material is processed into layers. Additionally, a resist mask is used to form island-shaped oxide semiconductor layers. It may also be formed by the jet method. If the resist mask is formed by the inkjet method, photomask Because no screws are used, manufacturing costs can be reduced.

[0085] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature for the heat treatment in step 1 shall be 350°C or higher, but below the strain point of the substrate, preferably 400°C or higher. Here, a substrate is introduced into an electric furnace, which is one of the heat treatment devices, and the oxide semiconductor layer is subjected to After heat treatment under a nitrogen atmosphere, the oxide semiconductor layer is subjected to a process without exposure to air. This prevents the re-imposition of water and hydrogen, and yields oxide semiconductor layers 431 and 432 (see Figure 2(B)). In this embodiment, the heating temperature T used for dehydrating or dehydrogenating the oxide semiconductor layer is changed again The same furnace is used to reach a temperature that is sufficient to prevent water from entering, specifically 100°C higher than the heating temperature T. Slowly cool under a nitrogen atmosphere until the temperature drops below a certain level. Furthermore, the atmosphere is not limited to nitrogen; helium, nitrogen, etc., can also be used. Dehydration or dehydrogenation is carried out under a noble gas atmosphere such as ON or argon, or under reduced pressure.

[0086] In the first heat treatment, nitrogen or a noble gas such as helium, neon, or argon is used. It is preferable that it does not contain water, hydrogen, etc. Alternatively, nitrogen introduced into the heat treatment device, Alternatively, the purity of noble gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably 7N (99.99999%) or higher (i.e., impurity concentration of 1 ppm or less, preferably Preferably, the concentration is 0.1 ppm or less.

[0087] Furthermore, depending on the conditions of the first heat treatment or the material of the oxide semiconductor film, crystallization may occur, and microcrystalline formation may occur. It may also form a crystalline film or a polycrystalline film.

[0088] Furthermore, the first heat treatment of the oxide semiconductor layer is performed on the oxide before it is processed into an island-shaped oxide semiconductor layer. This can also be done on the semiconductor film 430. In that case, after the first heat treatment, the heating device is used The substrate is removed, and the photolithography process is performed.

[0089] Furthermore, before depositing the oxide semiconductor film 430, an inert gas atmosphere (nitrogen, or helium, nitrate) is used. Heat treatment (400°C or higher) under oxygen atmosphere or reduced pressure (such as argon, etc.) for substrates Even if you perform a procedure (below the strain point) and remove impurities such as hydrogen and water contained in the gate insulating layer, good.

[0090] Next, a metal conductive layer is placed on the second gate insulating layer 402b and the oxide semiconductor layers 431 and 432. After forming the film, a third photolithography step is performed to create resist masks 433a and 43 Form 3b and selectively etch to form metal electrode layers 434 and 435 (Figure 2) (See (C)). Materials for metal conductive films include Al, Cr, Cu, Ta, Ti, Mo, and W. The selected elements, or alloys containing the above-mentioned elements, or combinations of the above-mentioned elements. There are alloys, etc.

[0091] As a metallic conductive film, an aluminum layer is placed on a titanium layer, and a titanium layer is placed on the aluminum layer. A laminated structure consisting of three layers, or a molybdenum layer with an aluminum layer and the aluminum A three-layer laminated structure with a molybdenum layer laminated on top of the other layers is preferable. Of course, a metal conductive film is also preferable. It may be a single-layer, two-layer, or four-layer or more laminated structure.

[0092] Furthermore, a resist mask for forming the metal electrode layers 434 and 435 is made using an inkjet method. It may be formed. If the resist mask is formed by the inkjet method, a photomask is used. Therefore, manufacturing costs can be reduced.

[0093] Next, the resist masks 433a and 433b are removed, and the process moves to the fourth photolithography step. Further resist masks 436a and 436b are formed, and selective etching is performed on the source electricity. The polar layer 415a and the drain electrode layer 415b are formed (see Figure 2(D)). In the photolithography process, only a portion of the oxide semiconductor layer 431 is etched, and grooves are formed. The oxide semiconductor layer 437 has a portion (recess). Also, the oxide semiconductor layer 431 has a groove portion ( Resist masks 436a and 436b for forming recesses are formed by an inkjet method. It is also acceptable. If the resist mask is formed by the inkjet method, a photomask is not used. Therefore, manufacturing costs can be reduced.

[0094] Next, the resist masks 436a and 436b are removed, and the process moves to the fifth photolithography step. A resist mask 438 is formed to further cover the oxide semiconductor layer 437, and the oxide semiconductor layer 432 Remove the upper metal electrode layer 435 (see Figure 2(E)).

[0095] Furthermore, in the fifth photolithography step, the metal electrode layer 435 overlaps with the oxide semiconductor layer 432. In order to remove it, the oxide semiconductor layer 432 is also removed when etching the metal electrode layer 435. Adjust the materials and etching conditions as appropriate to prevent damage.

[0096] It is in contact with the upper and side surfaces of the oxide semiconductor layer 432 and in contact with the grooves (recesses) of the oxide semiconductor layer 437. An oxide insulating film 439 is formed, which serves as a protective insulating film.

[0097] The oxide insulating film 439 has a thickness of at least 1 nm, and is manufactured by an oxidation process such as sputtering. The insulating film 439 can be formed using an appropriate method that prevents the inclusion of impurities such as water and hydrogen. In this embodiment, a silicon oxide film with a thickness of 300 nm is used as the oxide insulating film 439. The film is deposited using the dermatization method. The substrate temperature during film deposition should be between room temperature and 300°C. In this embodiment, the temperature is set to 100°C. The deposition of silicon oxide films by sputtering is rare. Under a gaseous atmosphere (typically argon), under an oxygen atmosphere, or under a noble gas atmosphere (typically argon) It can be carried out in an oxygen atmosphere. Also, silicon dioxide can be used as a target. A GET or silicon target can be used. For example, using a silicon target, Silicon oxide can be formed by sputtering under oxygen and nitrogen atmospheres. The oxide insulating film 439, formed in contact with the resistive oxide semiconductor layer, is resistant to moisture and hydrogen ions. No, oxygen ions, OH - It does not contain impurities such as these, and blocks them from entering from the outside. These inorganic insulating films are typically used, such as silicon oxide films, silicon nitride films, and aluminum oxide films. A film or aluminum oxide nitride is used.

[0098] Next, a second heat treatment (preferably 2) is performed under an inert gas atmosphere or an oxygen gas atmosphere. Perform the procedure at temperatures between 00°C and 400°C, for example, between 250°C and 350°C (see Figure 3(A)). ). For example, a second heat treatment is performed at 250°C for 1 hour under a nitrogen atmosphere. Second heat treatment When this is done, the grooves of the oxide semiconductor layer 437, the upper surface and side surfaces of the oxide semiconductor layer 432 become oxide It is heated while in contact with the insulating film 439.

[0099] Through the above process, the oxide semiconductor film after deposition is dehydrated or dehydrogenated. After performing a heat treatment to reduce resistance, a portion of the oxide semiconductor film is selectively treated to remove excess oxygen. This is the state. As a result, the channel formation region 413 that overlaps with the gate electrode layer 411 is type I and This results in a first high-resistance drain region 414a overlapping the source electrode layer 415a, and a drain electrode The second high-resistance drain region 414b, which overlaps with the polar layer 415b, is formed in a self-aligned manner. Furthermore, the oxide semiconductor layer 422, which overlaps with the gate electrode layer 421, is entirely I-type.

[0100] However, with the high-resistance (Type I) oxide semiconductor layer 422 exposed, When heat treatment is performed under nitrogen, an inert gas atmosphere, or under reduced pressure, the resistance is increased (Type I). Because the oxide semiconductor layer 422 (which has been exposed) becomes less resistive, the oxide semiconductor layer 422 is exposed. Heat treatment performed in this state is carried out under an oxygen gas, N2O gas atmosphere, or ultra-dry air (with a dew point of The procedure is carried out at -40°C or below, preferably -60°C or below.

[0101] In the oxide semiconductor layer superimposed on the drain electrode layer 415b (and source electrode layer 415a), This forms a second high-resistance drain region 414b (or a first high-resistance drain region 414a). This improves the reliability of the drive circuit when it is formed. Specifically, By forming a second high-resistance drain region 414b, the second high-resistance drain region is formed from the drain electrode layer. The conductivity can be changed in steps from the anti-drain region 414b to the channel formation region. This structure can be formed. Therefore, the drain electrode layer 415b is set to a high power supply potential VDD. When connected to the supply wiring and operated, the gate electrode layer 411 and the drain electrode layer 415b Even if a high electric field is applied between them, the high-resistance drain region acts as a buffer, and the localized high electric field is not applied. This configuration does not require additional processing, and the transistor's voltage rating can be improved.

[0102] Furthermore, an oxide semiconductor layer superimposed on the drain electrode layer 415b (and source electrode layer 415a) in the second high-resistance drain region 414b (or the first high-resistance drain region 414a) By forming this, the leakage current in the channel formation region 413 when the drive circuit is formed This can help reduce the problem.

[0103] Next, a sixth photolithography step is performed to shape the resist masks 440a and 440b. The oxide insulating film 439 is then selectively etched to form oxide insulating layers 416 and 426. (See Figure 3(B)). The oxide insulating layer 426 is channel-shaped of the oxide semiconductor layer 422. It is provided on the formed region and functions as a channel protection layer. Note that, as in this embodiment, When an oxide insulating layer is used as the insulating layer 402b, etching of the oxide insulating film 439 During the process, a portion of the gate insulating layer 402b is also etched, resulting in a thinner film thickness. (This may occur.) The gate insulating layer 402b is made of an oxide insulating film 439 and a nitride insulating film with a high selectivity. When using a border film, it is possible to prevent the gate insulating layer 402b from being partially etched. ru.

[0104] Next, a transparent conductive film is formed on the oxide semiconductor layer 422 and the oxide insulating layer 426. After that, the source electrode layer 425a and the drain electrode are formed by a seventh photolithography step. A polar layer 425b is formed (see Figure 3(C)). The method for forming a transparent conductive film is as follows: Putter method, vacuum deposition method (such as electron beam deposition), and arc discharge ion plating method Alternatively, a spray method can be used. The conductive film material is a conductive material that is transparent to visible light. Materials, for example, In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system , Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn- Apply metal oxides of the following types: O-based, Al-Zn-O-based, In-O-based, Sn-O-based, and Zn-O-based. This can be done, and the film thickness can be appropriately selected within the range of 50 nm to 300 nm. Also, spa When using the T method, a target containing 2% to 10% by weight of SiO2 is used for film deposition. This process involves incorporating SiOx (X>0), which inhibits crystallization, into a light-transmitting conductive film, and then proceeding with the subsequent process. It is preferable to suppress crystallization during the heat treatment process.

[0105] Note that a resist mask is used to form the source electrode layer 425a and the drain electrode layer 425b. The resist mask may be formed by an inkjet method. Because it does not use a photomask, manufacturing costs can be reduced.

[0106] Next, oxide insulating layers 416, 426, source electrode layer 425a, drain electrode layer 425b A protective insulating layer 403 is formed on top. In this embodiment, silicon nitride is formed using the RF sputtering method. A film is formed. RF sputtering is used as the method for forming the protective insulating layer 403 because it offers good mass production capabilities. This is preferable. The protective insulating layer 403 is protected from moisture, hydrogen ions, and OH - It does not contain impurities such as Using an inorganic insulating film that blocks these from entering from the outside, a silicon nitride film, an aluminium nitride film is used. Aluminum film, silicon nitride film, aluminum oxide nitride, etc. are used. Of course, a protective insulating layer is also used. 403 is a light-transmitting insulating film.

[0107] Furthermore, the protective insulating layer 403 is provided below the first gate insulating layer 402 It is preferable to have a configuration that is in contact with a or the underlying insulating film, and water from near the side surface of the substrate Minutes, hydrogen ions, OH - It blocks the intrusion of impurities such as these. In particular, protective insulation The first gate insulating layer 402a in contact with the edge layer 403 or the underlying insulating film is a silicon nitride film. This is effective. That is, silicon nitride is placed around the bottom, top, and sides of the oxide semiconductor layer. Adding a film improves the reliability of the display device.

[0108] Next, a planar insulating layer 404 is formed on the protective insulating layer 403. For example, heat-resistant materials such as polyimide, acrylic, benzocyclobutene, polyamide, and epoxy. Organic materials having the above properties can be used. In addition to the above organic materials, low dielectric constant materials (lo wk materials), siloxane resins, PSG (phosphorus glass), BPSG (phosphorus boron glass) ) etc. can be used. Furthermore, multiple insulating films formed from these materials can be stacked. A planar insulating layer 404 may be formed in this manner.

[0109] Siloxane-based resins are formed using siloxane-based materials as the starting material for Si-OS. This corresponds to a resin containing i-bonds. Siloxane resins use organic groups (e.g., alkyl groups) as substituents. You may also use aryl groups or fluoro groups. Furthermore, organic groups may have fluoro groups. You can.

[0110] The method for forming the planar insulating layer 404 is not particularly limited and can be done by sputtering, SO2, or other methods depending on the material. G method, spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen coating) Methods such as screen printing, offset printing, etc., as well as doctor knives, roll coaters, and curtains A coater, a knife coater, etc. can be used.

[0111] Next, an eighth photolithography process is performed to form a resist mask, and contact holes 441 reaching the drain electrode layer 425b are formed by etching the planarization insulating layer 404 and the protective insulating layer 403 (see Fig. 3(D)). Also, contact holes reaching the gate electrode layers 411 and 421 are formed by the etching here. Further, a resist mask for forming contact holes reaching the drain electrode layer 425b may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced.

[0112] Next, after removing the resist mask, a conductive film having light-transmitting properties is formed. As materials for the conductive film having light-transmitting properties, indium oxide (In2O3), indium oxide-tin oxide alloy (In2O3 - SnO2, abbreviated as ITO), etc. are formed using a sputtering method, a vacuum evaporation method, etc. As other materials for the conductive film having light-transmitting properties, an Al-Zn-O-based non-single crystal film containing nitrogen, that is, an Al-Zn-O-N-based non-single crystal film, a Zn-O-based non-single crystal film containing nitrogen, or a Sn-Zn-O-based non-single crystal film containing nitrogen may be used. Note that the composition ratio (atomic %) of zinc in the Al-Zn-O-N-based non-single crystal film is 47 atomic % or less, is larger than the composition ratio (atomic %) of aluminum in the non-single crystal film, and the composition ratio (atomic %) of aluminum in the non-single crystal film is larger than the composition ratio (atomic %) of nitrogen in the non-single crystal film. The etching treatment of such materials is performed with a hydrochloric acid-based solution. However, especially for the etching of ITO, residues are generated. ​​​​​​​​​​​​​​​Since it is inexpensive, indium zinc oxide alloy (In2O 3―ZnO) may be used to improve the etching processability.

[0113] The unit of the composition ratio of the conductive film having translucency is atomic%, and it shall be evaluated by analysis using an electron probe microanalyzer (EPMA: Electron Probe X-ray MicroAnalyzer ).

[0114] Next, the ninth photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching to form the pixel electrode layer 427 and the conductive layer 417 (see Fig. 3(E) .). .

[0115] Through the above processes, using nine masks, the thin film transistor 410 and the thin film transistor 420 can be respectively fabricated as a drive circuit or a pixel portion on the same substrate . The thin film transistor 410 for the drive circuit is a channel etch type thin film transistor including the first high-resistance drain region 414a, the second high-resistance drain region 414b, and the channel formation region 413, and an oxide semiconductor layer 41 2, and the thin film transistor 420 for the pixel is a channel protection type thin film transistor including an oxide semiconductor layer 422 that is entirely of the I-type .

[0116] Also, a holding capacitor formed by the first gate insulating layer 402a, the second gate insulating layer 402b as dielectrics, a capacitance wiring layer, and a capacitance electrode can be formed on the same substrate. The thin film trans istors 420 and the holding capacitor are arranged in a matrix corresponding to individual pixels to constitute a pixel portion, and a drive circuit having the thin film transistor 410 is arranged around the pixel portion to act This specification can be used as one of the substrates for fabricating a video matrix type display device. For convenience, we will refer to such a substrate as an active matrix substrate.

[0117] Furthermore, the pixel electrode layer 427 is formed on the planar insulating layer 404 and the protective insulating layer 403. It is electrically connected to the capacitive electrode via a contact hole. The capacitive electrode is located in the source electrode layer. 425a is made of the same light-transmitting material as the drain electrode layer 425b and is formed using the same process. It is possible.

[0118] By providing the conductive layer 417 in a position that overlaps with the channel formation region 413 of the oxide semiconductor layer, This refers to the bias-thermal stress test (BT) used to investigate the reliability of thin-film transistors. In the test, the threshold voltage of the thin-film transistor 410 before and after the BT test was The amount of change can be reduced. Also, the conductive layer 417 has the same potential as the gate electrode layer 411. They can be the same or different, and they can also function as a second gate electrode layer. Furthermore, the potential of the conductive layer 417 may be GND, 0V, or in a floating state. .

[0119] Furthermore, a resist mask for forming the pixel electrode layer 427 is formed by an inkjet method. This is also good. Because if the resist mask is formed by the inkjet method, a photomask is not used. This can reduce manufacturing costs.

[0120] (Embodiment 2) In this embodiment, the heat treatment in the pixel thin-film transistor differs from that in Embodiment 1. This is shown in Figure 4. Figure 4 is the same as Figures 1 to 3 except that the process is slightly different. The same symbols are used for the same locations, and detailed explanations of the same locations are omitted.

[0121] First, according to Embodiment 1, the process up to FIG. 3(B) in Embodiment 1 is performed. FIG. 4( A) shows the state after removing the resist masks 440a and 440b in the process of FIG. 3(B). .

[0122] On a substrate 400 having an insulating surface, gate electrode layers 411 and 421, a first gate insulating layer 4 02a, and a second gate insulating layer 402b are formed. In the drive circuit portion, a channel formation region 413, a first high-resistance drain region 414a, and a second high-resistance drain region 414b are included in an oxide semiconductor layer 412, a source electrode layer 415a, a drain electrode layer 415b, and an oxide insulating layer 416 are formed. In the pixel portion, an oxide semiconductor layer 422 and an oxide insulating layer 426 are formed (see FIG. 4(A)). The oxide semiconductor layer 422 is a highly resistive type I .

[0123] In this embodiment, heat treatment is performed in a nitrogen , inert gas atmosphere, or under reduced pressure with at least a part of the oxide semiconductor layer 422 exposed. When heat treatment is performed in a nitrogen or inert gas atmosphere or under reduced pressure with the highly resistive (type-I) oxide semiconductor layer 422 exposed, the exposed highly resistive (type-I) region in the oxide semiconductor layer 422 can be made to have a lower resistance.

[0124] The heat treatment for reducing the resistance of the highly resistive (type-I) region in the oxide semiconductor layer 422 is preferably performed at 200°C or higher and 400°C or lower, for example, at 250°C or higher and 350°C or lower . For example, heat treatment is performed at 250°C for 1 hour in a nitrogen atmosphere.

[0125] ​​In this embodiment, a substrate is introduced into an electric furnace, which is one of the heat treatment devices, and an oxide semiconductor layer 4 After heat treatment of 22 under a nitrogen atmosphere, without exposure to air, the heating temperature The mixture is slowly cooled under a nitrogen atmosphere from temperature T until it drops by more than 100°C below the heating temperature T. Not limited to plain atmospheres, but also under noble gas atmospheres such as helium, neon, and argon, or under reduced pressure. Dehydration or dehydrogenation is carried out. In addition, nitrogen or helium is used during the heat treatment. It is preferable that the noble gases such as neon and argon do not contain water, hydrogen, etc. Alternatively, The purity of nitrogen, or noble gases such as helium, neon, and argon, introduced into the heat treatment device is determined by the following criteria: 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher, (i.e., non It is preferable to have a pure substance concentration of 1 ppm or less, preferably 0.1 ppm or less.

[0126] Heat treatment of the oxide semiconductor layer 422 under nitrogen, inert gas atmosphere, or reduced pressure Therefore, the exposed region of the oxide semiconductor layer 422 has low resistance, and the region with different resistance (Figure 4(B)) In this case, the oxide semiconductor layer 442 has (shown as a shaded area and a white area).

[0127] Next, a transparent conductive film is formed on the oxide semiconductor layer 442 and the oxide insulating layer 426. After that, the source electrode layer 425a and the drain electrode are formed by a seventh photolithography step. It forms polar layer 425b (see Figure 4(C)).

[0128] Next, oxide insulating layers 416, 426, source electrode layer 425a, drain electrode layer 425b A protective insulating layer 403 and a planar insulating layer 404 are laminated on top to form the structure.

[0129] Next, an eighth photolithography step is performed to form a resist mask and a planar insulating layer 4 04, and etching of the protective insulating layer 403 leads to the contacts reaching the drain electrode layer 425b This forms a duct hole 441 (see Figure 4(D)).

[0130] Next, after removing the resist mask, a light-transmitting conductive film is deposited.

[0131] Next, a ninth photolithography step is performed to form a resist mask, and etching is performed. Unnecessary portions are removed to form the pixel electrode layer 427 and the conductive layer 417 (see Figure 4(E)). . ) .

[0132] Through the above process, using nine masks, thin-film transistors 410 and thin-film transistors are placed on the same substrate. The film transistors 448 can be fabricated separately as either a drive circuit or a pixel unit. The thin-film transistor 410 for the drive circuit has a first high-resistance drain region 414a, and a second Oxide semiconductor layer 41 including high-resistance drain region 414b and channel-forming region 413 It is a channel etch thin-film transistor including 2, and also a thin-film transistor 448 for pixels. , first high-resistance drain region 424a, second high-resistance drain region 424b, and channel A channel-protected thin-film transistor comprising an oxide semiconductor layer 442 including a channel formation region 423, Therefore, thin-film transistors 410 and 448 have high resistance even when a high electric field is applied. The 'n' region acts as a buffer, preventing the application of a localized high electric field and improving the transistor's breakdown voltage. It is structured as follows.

[0133] Furthermore, the first gate insulating layer 402a and the second gate insulating layer 402b are used as dielectrics for capacitive wiring. The retaining capacitance formed by the layer and the capacitive electrode can also be formed on the same substrate. The pixel section is constructed by arranging the ZISTA 448 and the retention capacitance in a matrix corresponding to each individual pixel. By arranging a drive circuit having a thin-film transistor 410 around the pixel area, the act It can be used as one of the substrates for fabricating a web matrix type display device.

[0134] By providing the conductive layer 417 in a position that overlaps with the channel formation region of the oxide semiconductor layer 412, This refers to the bias-thermal stress test (BT) used to investigate the reliability of thin-film transistors. In the test, the threshold voltage of the thin-film transistor 410 before and after the BT test was The amount of change can be reduced. Also, the conductive layer 417 has the same potential as the gate electrode layer 411. They can be the same or different, and they can also function as a second gate electrode layer. Furthermore, the potential of the conductive layer 417 may be GND, 0V, or in a floating state. .

[0135] (Embodiment 3) In this embodiment, Figure 5 shows an example in which the first heat treatment differs from that of Embodiment 1. Since the process is the same as in Figures 1 through 3 except for some differences in the steps, the same reference numerals are used for the same parts. Detailed explanations of the same sections will be omitted.

[0136] First, according to Embodiment 1, a translucent conductive film is applied to a substrate 400 having an insulating surface. After formation, gate electrode layers 411 and 421 are formed by a first photolithography process. ru.

[0137] Next, the first gate insulating layer 402a and the second gate insulating layer are placed on the gate electrode layers 411 and 421. The marginal layer 402b is formed (see Figure 5(A)). Note that Figure 5(A) is different from Figure 2(A). They are identical. Furthermore, the steps up to this point are the same as in Embodiment 1.

[0138] Next, an oxide semiconductor film with a thickness of 2 nm to 200 nm is placed on the second gate insulating layer 402b. A body membrane 430 is formed (see Figure 5(A)). Note that the steps up to this point are the same as in Embodiment 1. They are identical, and Figure 5(A) corresponds to Figure 2(A).

[0139] Next, the oxide semiconductor film 430 is dehydrated under an inert gas atmosphere or under reduced pressure. Dehydrogenation is performed. The temperature of the first heat treatment for dehydration or dehydrogenation is 350°C or higher. The temperature should be below the strain point of the substrate, preferably 400°C or higher. Here, one of the heat treatment devices is The substrate is introduced into the electric furnace, and the oxide semiconductor film 430 is heat-treated under a nitrogen atmosphere. After this process, the re-importation of water and hydrogen into the oxide semiconductor film 430 is prevented without exposure to the atmosphere. The oxide semiconductor film 430 is made oxygen-deficient to reduce its resistance, i.e., N-type (N - (etc.) Afterward, high-purity oxygen gas, high-purity N2O gas, or ultra-dry air (dew point -4) is added to the same furnace. Cooling is performed by introducing oxygen gas or N2O gas (preferably below 0°C, preferably below -60°C). It is preferable that it does not contain water, hydrogen, etc. Alternatively, oxygen gas introduced into the heat treatment device may be used. The purity of the s or N2O gas should be 6N (99.9999%) or higher, preferably 7N (99. 99999% or more (i.e., the impurity concentration in oxygen gas or N2O gas is 1 ppm or less) Preferably, the concentration is 0.1 ppm or less.

[0140] Furthermore, after the first heat treatment in which dehydration or dehydrogenation is performed, the temperature is preferably between 200°C and 400°C. Alternatively, heating treatment at a temperature between 200°C and 300°C under an oxygen or N2O gas atmosphere. It is permissible to act rationally.

[0141] By going through the above process, the entire oxide semiconductor film is made into an oxygen-rich state, To counteract, that is, to convert to type I.

[0142] As a result, the reliability of the thin-film transistors that are formed later can be improved.

[0143] Next, the oxide semiconductor film is transformed into an island-like oxide semiconductor layer by a photolithography process. The material is processed into ionized semiconductor layers 444 and 422 (see Figure 5(B)). Note that in Figure 5(B) The oxide semiconductor layer 422 is the same high-resistance layer as the oxide semiconductor layer 422 in Figure 3(A). Since it is a modified (Type I) oxide semiconductor layer, the same reference numeral is used. Similarly, in this specification Even thin films formed using different methods can have equivalent functions and characteristics (e.g., resistance). The same designation may be used for thin films that possess the same properties.

[0144] In this embodiment, an example is given in which dehydration or dehydrogenation is performed after the deposition of the oxide semiconductor film. As shown, but not limited to, the first heat treatment of the oxide semiconductor film is an island-shaped oxide semiconductor layer This can also be done on an oxide semiconductor layer after it has been processed.

[0145] Furthermore, dehydration or dehydrogenation of oxide semiconductor films under an inert gas atmosphere or reduced pressure. After oxidation and cooling in an inert gas atmosphere, island-shaped oxidation is performed using a photolithography process. The oxide semiconductor layers 444 and 422, which are material semiconductor layers, are processed and then heated to over 200°C and 400°C. At a temperature of 200°C or lower, preferably between 200°C and 300°C, under the influence of oxygen gas or N2O gas. Heat treatment may be performed.

[0146] Furthermore, before depositing the oxide semiconductor film, an inert gas atmosphere (nitrogen, or helium, neon, Heat treatment (400°C or higher) under argon, oxygen atmosphere, or reduced pressure to reduce substrate distortion. The process may involve removing impurities such as hydrogen and water contained within the gate insulating layer by performing a test (less than 100%).

[0147] However, the high-resistivity (Type I) oxide semiconductor layers 444 and 422 are exposed. When heat treatment is performed under nitrogen, an inert gas atmosphere, or under reduced pressure, the resistance is increased. Because the (Type I) oxide semiconductor layers 444 and 422 become low resistance, the oxide semiconductor The heat treatment performed with layers 444 and 422 exposed is carried out under an oxygen gas or N2O gas atmosphere. Alternatively, the process may be carried out using ultra-dry air (with a dew point of -40°C or lower, preferably -60°C or lower).

[0148] The rest is the same as in Figures 2(C) to (E) and 3(A) to (E) in Embodiment 1. In the peripheral drive circuit section, only a portion of the oxide semiconductor layer 444 is etched to form grooves ( An oxide semiconductor layer 443 having a recess is formed, and a source electrode layer 415a which is a metal conductive layer is formed. A drain electrode layer 415b and an oxide insulating layer 416 in contact with the oxide semiconductor layer 443 are formed. Then, a thin-film transistor 449 for the drive circuit is fabricated. Meanwhile, in the pixel area, an oxide An oxide insulating layer 426 is formed on the channel formation region of the semiconductor layer 422, and a light-transmitting conductive A source electrode layer 425a and a drain electrode layer 425b are formed as the electrolayer, and a thin film trace for the pixel is formed. We will manufacture the 420.

[0149] Next, a second heat treatment (preferably 2) is performed under an inert gas atmosphere or an oxygen gas atmosphere. Perform the procedure at temperatures between 0°C and 400°C (for example, between 250°C and 350°C). For example, under a nitrogen atmosphere. A second heat treatment is performed at 250°C for 1 hour under low pressure.

[0150] Next, the thin-film transistors 449 and 420 are covered with oxide insulating layers 416 and 426 and saw A protective insulating layer 403 is in contact with the drain electrode layer 425a and the drain electrode layer 425b, and a planar insulating layer is in contact with the drain electrode layer 425b. Layer 404 is formed by stacking layers. Drain electricity is applied to the protective insulating layer 403 and the planar insulating layer 404. A contact hole is formed that reaches the polar layer 425b, and the contact hole and the planar insulating layer 4 A translucent conductive film is formed on 04. The translucent conductive film is selectively etched. The pixel electrode layer 427 and conductive layer 417 are electrically connected to the thin-film transistor 420. To form.

[0151] Through the above process, using nine masks, thin-film transistors 449 and thin-film transistors are placed on the same substrate. The film transistors 420 can be fabricated separately as either drive circuits or pixel units. The thin-film transistor 449 for the drive circuit has an oxide semiconductor layer 443 that is entirely I-shaped. It includes channel etch thin-film transistors, and thin-film transistors 420 for pixels are also included. This is a channel-protected thin-film transistor containing an oxide semiconductor layer 422 with a type I body.

[0152] Furthermore, the first gate insulating layer 402a and the second gate insulating layer 402b are used as dielectrics for capacitive wiring. The retaining capacitance formed by the layer and the capacitive electrode can also be formed on the same substrate. The pixel section is constructed by arranging the ZISTA 420 and the retaining capacitance in a matrix corresponding to each individual pixel. By arranging a drive circuit having a thin-film transistor 449 around the pixel area, the act It can be used as one of the substrates for fabricating a web matrix type display device.

[0153] By providing the conductive layer 417 in a position that overlaps with the channel formation region of the oxide semiconductor layer 443, This refers to the bias-thermal stress test (BT) used to investigate the reliability of thin-film transistors. In the test, the threshold voltage of the thin-film transistor 449 before and after the BT test was The amount of change can be reduced. Also, the conductive layer 417 has the same potential as the gate electrode layer 411. They can be the same or different, and they can also function as a second gate electrode layer. Furthermore, the potential of the conductive layer 417 may be GND, 0V, or in a floating state. .

[0154] (Embodiment 4) In this embodiment, the first heating treatment in the pixel thin-film transistor differs from that in Embodiment 3. An example is shown in Figure 6. Figure 6 is the same as Figures 1 to 5 except that the process is slightly different. The same symbols are used for the same sections, and detailed explanations of the same sections are omitted.

[0155] First, according to Embodiment 3, the process is carried out up to the step shown in Figure 5(B) in Embodiment 3. Figure 6( A) is the same as the process in Figure 5(B).

[0156] On a substrate 400 having an insulating surface, gate electrode layers 411, 421, and a first gate insulating layer 4 02a, the second gate insulating layer 402b is formed, and in the drive circuit section, an oxide semiconductor layer 444 is formed, and in the pixel area, an oxide semiconductor layer 422 is formed (Figure 6(A (See reference.) The oxide semiconductor layers 444 and 422 are high-resistance type I.

[0157] In the peripheral drive circuit section, only a portion of the oxide semiconductor layer 444 is etched to form grooves ( An oxide semiconductor layer 443 having a recess is formed, and a source electrode layer 415a which is a metal conductive layer is formed. A drain electrode layer 415b and an oxide insulating layer 416 in contact with the oxide semiconductor layer 443 are formed. Then, a thin-film transistor 449 for the drive circuit is fabricated. Meanwhile, in the pixel area, an oxide An oxide insulating layer 426 is formed on the channel formation region of the semiconductor layer 422 (see Figure 6(B)). . ) .

[0158] In this embodiment, as in Embodiment 2, at least a portion of the oxide semiconductor layer 422 is exposed. In this state, heat treatment is performed under nitrogen, an inert gas atmosphere, or under reduced pressure. With the modified (Type I) oxide semiconductor layer 422 exposed, nitrogen and an inert gas atmosphere When heat treatment is performed under ambient air or reduced pressure, the exposed high The resisted (Type I) region can be made to have low resistance.

[0159] In the oxide semiconductor layer 422, the region that has been made high-resistance (type I) is made low-resistance. The heat treatment is preferably carried out at a temperature of 200°C to 400°C, for example, 250°C to 350°C. For example, heat treatment at 250°C for 1 hour under a nitrogen atmosphere.

[0160] In this embodiment, a substrate is introduced into an electric furnace, which is one of the heat treatment devices, and an oxide semiconductor layer 4 After heat treatment of 22 under a nitrogen atmosphere, without exposure to air, the heating temperature The mixture is slowly cooled under a nitrogen atmosphere from temperature T until it drops by more than 100°C below the heating temperature T. Not limited to plain atmospheres, decongestants can be removed under helium, neon, argon, or other atmospheres or under reduced pressure. Hydration or dehydrogenation is performed. In the heat treatment, nitrogen, helium, or neon may be used. It is preferable that the noble gas, such as argon, does not contain water, hydrogen, etc. Alternatively, heat treatment may be used. The purity of nitrogen, or noble gases such as helium, neon, or argon, introduced into the apparatus should be set to 6N (9 9.9999% or more, preferably 7N (99.99999%) or more (i.e., impurity concentration) It is preferable to set the concentration to 1 ppm or less, preferably 0.1 ppm or less.

[0161] Heat treatment of the oxide semiconductor layer 422 under nitrogen, inert gas atmosphere, or reduced pressure Therefore, the exposed region of the oxide semiconductor layer 422 has low resistance, and the region with different resistance (Figure 6(C)) In this case, the oxide semiconductor layer 442 has (shown as a shaded area and a white area).

[0162] Next, a transparent conductive film is formed on the oxide semiconductor layer 442 and the oxide insulating layer 426. After that, the source electrode layer 425a and the drain electrode are formed by a seventh photolithography step. It forms polar layer 425b.

[0163] Next, oxide insulating layers 416, 426, source electrode layer 425a, drain electrode layer 425b A protective insulating layer 403 and a planar insulating layer 404 are laminated on top to form the structure.

[0164] The protective insulating layer 403 and the planar insulating layer 404 have contacts that reach the drain electrode layer 425b A transparent conductive film is formed on the contact hole and the planar insulating layer 404. A thin film is formed. A transparent conductive film is selectively etched to form a thin-film transistor 448. An electrically connected pixel electrode layer 427 and a conductive layer 417 are formed (see Figure 6(D)). .

[0165] Through the above process, using nine masks, thin-film transistors 449 and thin-film transistors are placed on the same substrate. The film transistors 448 can be fabricated separately as either a drive circuit or a pixel unit. The thin-film transistor 449 for the drive circuit has an oxide semiconductor layer 443 that is entirely I-shaped. It includes channel etch thin-film transistors, and thin-film transistor 448 for pixels is the A first high-resistance drain region 424a, a second high-resistance drain region 424b, and a channel type This is a channel-protected thin-film transistor that includes an oxide semiconductor layer 442 containing a formation region 423. The thin-film transistor 448 has a high-resistance drain region that acts as a buffer even when a high electric field is applied. This configuration prevents the application of a localized high electric field, thereby improving the transistor's breakdown voltage.

[0166] Furthermore, the first gate insulating layer 402a and the second gate insulating layer 402b are used as dielectrics for capacitive wiring. The retaining capacitance formed by the layer and the capacitive electrode can also be formed on the same substrate. The pixel section is constructed by arranging the ZISTA 448 and the retention capacitance in a matrix corresponding to each individual pixel. By arranging a drive circuit having a thin-film transistor 449 around the pixel area, the act It can be used as one of the substrates for fabricating a web matrix type display device.

[0167] By providing the conductive layer 417 in a position that overlaps with the channel formation region of the oxide semiconductor layer 443, This refers to the bias-thermal stress test (BT) used to investigate the reliability of thin-film transistors. In the test, the threshold voltage of the thin-film transistor 449 before and after the BT test was The amount of change can be reduced. Also, the conductive layer 417 has the same potential as the gate electrode layer 411. They can be the same or different, and they can also function as a second gate electrode layer. Furthermore, the potential of the conductive layer 417 may be GND, 0V, or in a floating state. .

[0168] (Embodiment 5) In this embodiment, the active matrix substrate shown in Embodiment 1 is used, This document shows an example of fabricating a matrix-type liquid crystal display device. This can also be applied to the active matrix substrates shown in 2 to 4.

[0169] An example of the cross-sectional structure of an active matrix substrate is shown in Figure 7(A).

[0170] In Embodiment 1, the thin-film transistors of the drive circuit and the thin-film transistors of the pixel are mounted on the same substrate. Although the diagram shows the transistors, in this embodiment, in addition to those thin-film transistors, the holding capacitance and gate The terminal sections for wiring and source wiring will also be illustrated and explained. Capacitance, gate wiring, and source wiring terminal sections This can be formed using the same process as the manufacturing process shown in Embodiment 1, and the number of photomasks It can be manufactured without increasing the number of components or processes. Furthermore, the display area of ​​the pixel portion... In this section, the gate wiring, source wiring, and capacitive wiring layers are all transparent conductive. It is formed of a film, achieving a high aperture ratio. In addition, source distribution in areas not covered by the display area Metal wiring can be used for the wire layers to reduce wiring resistance.

[0171] In Figure 7(A), the thin-film transistor 210 is connected to a channel etched into the drive circuit. This is a thin-film transistor of type 1, and in this embodiment, the thin-film transistor 41 of Embodiment 1 The same structure as in 0 is used. The thin-film transistor 220 that is electrically connected to the pixel electrode layer 227 is , a channel-protected thin-film transistor provided in the pixel section, and in this embodiment, The same structure as the thin-film transistor 420 in embodiment 1 is used.

[0172] A material having the same light-transmitting properties as the gate electrode layer of the thin-film transistor 220, and formed using the same process. The capacitance wiring layer 230 consists of a first gate insulating layer 202a which acts as a dielectric, and a second gate insulating layer It overlaps with the capacitive electrode 231 via the marginal layer 202b, forming a retained capacitance. 31 has the same light transmittance as the source electrode layer or drain electrode layer of the thin-film transistor 220. The material and the process are used to form it. Therefore, the thin-film transistor 220 has light-transmitting properties. In addition to this, each of the holding capacities also has light-transmitting properties, thus improving the aperture ratio. It is possible.

[0173] The fact that the holding capacity is light-transmitting is important for improving the aperture ratio, especially for 10-inch lenses. In the following small LCD display panel, increasing the number of gate wires, etc., improves the display image quality. To achieve higher resolution, even when pixel dimensions are reduced, a high aperture ratio can be achieved. By using a light-transmitting film for the components of the thin-film transistor 220 and the retaining capacitor, To achieve a wide viewing angle, a high aperture ratio is achieved even when one pixel is divided into multiple subpixels. This is possible. In other words, even when arranging a high-density group of thin-film transistors, it is possible to achieve a large aperture ratio. This allows for sufficient display area to be secured. For example, 2- When there are four subpixels and a retaining capacitance, the thin-film transistor is translucent. In addition, since each of the holding capacities is also light-transmitting, the aperture ratio can be improved. ru.

[0174] Furthermore, the retaining capacitance is provided below the pixel electrode layer 227, and the capacitance electrode 231 is located below the pixel electrode layer 2 It is electrically connected to 27.

[0175] In this embodiment, a capacitive electrode 231 and a capacitive wiring layer 230 are used to form a retained capacitance. Although an example has been given, the structure that forms the retention capacity is not particularly limited. For example, capacitive wiring Without providing a layer, the pixel electrode layer is connected to the gate wiring of adjacent pixels, a planar insulating layer, a protective insulating layer, and The retention capacitance may be formed by overlapping the first gate insulating layer and the second gate insulating layer.

[0176] Furthermore, gate wiring, source wiring, and capacitive wiring layers are provided in multiple layers depending on the pixel density. Furthermore, at the terminal section, there is a first terminal electrode at the same potential as the gate wiring, and a source wiring. Multiple terminal electrodes, such as a second terminal electrode at the same potential as the capacitive wiring layer and a third terminal electrode at the same potential as the capacitive wiring layer, are arranged in a row. They are arranged. The number of each terminal electrode can be any number you like. The contractor should make the decision as appropriate.

[0177] In the terminal section, the first terminal electrode, which is at the same potential as the gate wiring, has the same light transmission as the pixel electrode layer 227. It can be formed from a material having properties. The first terminal electrode reaches the gate wiring. It is electrically connected to the gate wiring via a contact hole. The wire electrically connects the drain electrode layer of the thin-film transistor 220 and the pixel electrode layer 227. Using the same photomask as the contact holes for continuation, a planar insulating layer 204, protective insulating Edge layer 203, oxide insulating layer 216, second gate insulating layer 202b, and first gate insulating Layer 202a is formed by selective etching.

[0178] Furthermore, the gate electrode layer of the thin-film transistor 210 of the drive circuit is located above the oxide semiconductor layer. The structure may also be one in which the conductive layer 217 is electrically connected. In that case, the thin film tracer A connector for electrically connecting the drain electrode layer of the inverter 220 and the pixel electrode layer 227. Using the same photomask as Tact Hole, planar insulating layer 204, protective insulating layer 203, oxidation A material insulating layer 216, a second gate insulating layer 202b, and a first gate insulating layer 202a are selected. The target is etched to form contact holes. A conductive layer is then passed through these contact holes. 217 is electrically connected to the gate electrode layer of the thin-film transistor 210 of the drive circuit.

[0179] Furthermore, the second terminal electrode 235, which is at the same potential as the source wiring 234 of the drive circuit, is connected to the pixel electrode layer 22 It can be formed from a material having the same light-transmitting properties as 7. The second terminal electrode 235 is the source It is electrically connected to the source wiring via a contact hole that reaches wiring 234. The wiring is metal wiring, made of the same material and process as the source electrode layer of the thin-film transistor 210. They are formed and have the same potential.

[0180] Furthermore, the third terminal electrode, which is at the same potential as the capacitive wiring layer 230, has the same light transmission properties as the pixel electrode layer 227. It can be formed from a material having the following properties. Also, contact holes reaching the capacitive wiring layer 230 The capacitive electrode 231 has contact holes for electrically connecting with the pixel electrode layer 227. The same photomask can be formed using the same process.

[0181] Furthermore, when manufacturing an active matrix type liquid crystal display device, the active matrix A liquid crystal layer is provided between the substrate and the counter substrate on which the counter electrode (also called the counter electrode layer) is provided. The active matrix substrate and the opposing substrate are fixed together. A common electrode is provided on the active matrix substrate that is electrically connected to the electrodes, and the common electrode and electricity A fourth terminal electrode is provided at the terminal section for target connection. This fourth terminal electrode fixes the common electrode. This is a terminal for setting the potential, such as GND or 0V. The fourth terminal electrode is for pixel electricity It can be formed from a material having the same light-transmitting properties as the polar layer 227.

[0182] Furthermore, the source electrode layer of thin-film transistor 220 and the source electrode layer of thin-film transistor 210 The configuration for electrically connecting the two is not particularly limited; for example, the source of the thin-film transistor 220 A connecting electrode that connects the electrode layer and the source electrode layer of the thin-film transistor 210 is located in the pixel electrode layer 227. It may also be formed using the same process. In addition, in the area that is not a display area, thin film transistor 2 The 20 source electrode layers and the source electrode layer of the thin-film transistor 210 are in contact and stacked together. That's fine.

[0183] The cross-sectional structure of the gate wiring 232 of the drive circuit is shown in Figure 7(A). This is an example of a small LCD display panel of 10 inches or less, therefore the gate wiring 23 of the drive circuit 2 uses a material with the same light-transmitting properties as the gate electrode layer of thin-film transistor 220.

[0184] Also, gate electrode layer, source electrode layer, drain electrode layer, pixel electrode layer, or other electrodes Using the same material for the layers and other wiring layers allows for the use of common sputtering targets and common manufacturing equipment. It can be used, and the material cost and the etchant used during etching (or This reduces the cost required for etching gas, and as a result, reduces manufacturing costs. It is possible.

[0185] Furthermore, in the structure shown in Figure 7(A), a photosensitive resin material is used as the planar insulating layer 204. In this case, the step of forming a resist mask can be omitted.

[0186] Furthermore, Figure 7(B) shows a cross-sectional structure that differs in part from that of Figure 7(A). Figure 7(B) is a reference to Figure 7( A) is the same as A) except that the planar insulating layer 204 is absent, therefore the same signs are used in the same locations. Using this, a detailed explanation of the same area will be omitted. In Figure 7(B), in contact with the protective insulating layer 203 The pixel electrode layer 227, the conductive layer 217, and the second terminal electrode 235 are formed.

[0187] With the structure shown in Figure 7(B), the process of forming the planarized insulating layer 204 can be omitted.

[0188] This embodiment can be freely combined with embodiments 1 to 4.

[0189] (Embodiment 6) In this embodiment, the size of the liquid crystal display panel exceeds 10 inches, and is 60 inches, and furthermore... If the screen size is set to 120 inches, the wiring resistance of the translucent wiring may become a problem. This example shows how to reduce wiring resistance by using metal wiring for part of the gate wiring.

[0190] Note that Figure 8(A) uses the same reference numerals as Figure 7(A), and detailed explanations of the same parts are provided separately. Details omitted. Note that this embodiment is an active matrix substrate as shown in Embodiments 1 to 4. It can be applied to this.

[0191] Figure 8(A) shows that a portion of the gate wiring of the drive circuit is made of metal wiring, and the thin-film transistor 210 This is an example of forming a gate electrode layer in contact with wiring that has the same light-transmitting properties as the gate electrode layer. To achieve this, the number of photomasks increases compared to Embodiment 1.

[0192] First, a substrate 200 that can withstand a first heat treatment for dehydration or dehydrogenation A heat-resistant conductive material film (thickness between 100 nm and 500 nm) is formed.

[0193] In this embodiment, the first metal wiring layer is a tungsten film with a thickness of 370 nm and the second gold A tantalum nitride film with a thickness of 50 nm is formed as the main wiring layer. Here, the conductive film is made of tantalum nitride. The lamination of a film and a tungsten film was described, but it is not particularly limited to Ta, W, Ti, Mo, Al. , elements selected from Cu, or alloys containing the above elements, or combinations of the above elements Formed from a combined alloy film or a nitride containing the aforementioned elements. Heat-resistant conductive material. The film is not limited to a single layer containing the elements mentioned above, but can also be a laminate of two or more layers.

[0194] A first photolithography process forms the metal wiring, and the first metal wiring layer 236 and the second A metal wiring layer 237 is formed. For etching the tungsten film and the tantalum nitride film, I CP (Inductively Coupled Plasma) It is best to use an etching method. Use the ICP etching method and the etching conditions (coil type) (The amount of power applied to the electrodes, the amount of power applied to the electrodes on the substrate side, the temperature of the electrodes on the substrate side, etc.) By adjusting the settings, the film can be etched into a desired tapered shape. The metal wiring layer 236 and the second metal wiring layer 237 are formed in contact with each other by tapering their shape. This can reduce defects in the deposition of conductive films that have light-transmitting properties.

[0195] Next, after forming a light-transmitting conductive film, a second photolithography process is performed. The wiring layer 238, the gate electrode layer of the thin-film transistor 210, and the gate electrode layer of the thin-film transistor 220 A translucent electrode layer is formed. The light-transmitting conductive film is directed towards visible light as described in Embodiment 1. A conductive material with light-transmitting properties is used.

[0196] Furthermore, depending on the material of the light-transmitting conductive film, for example, the gate wiring layer 238 may be the first gold If there is an interface in contact with the secondary wiring layer 236 or the second metal wiring layer 237, it will affect subsequent heat treatment, etc. Therefore, an oxide film may form, potentially increasing contact resistance, so the second metal wiring layer 237 It is preferable to use a metal nitride film to prevent oxidation of the first metal wiring layer 236.

[0197] Next, a gate insulating layer, an oxide semiconductor layer, and the like are formed using the same process as in Embodiment 1. The next step involves fabricating an active matrix substrate according to Embodiment 1.

[0198] Furthermore, in this embodiment, after forming the planar insulating layer 204, a photomask is used to form the terminals. This shows an example of selectively removing the planar insulating layer in a given area. In the terminal area, the planar insulating layer is present. It is preferable not to do so in order to ensure a good connection with the FPC.

[0199] In Figure 8(A), the second terminal electrode 235 is formed on the protective insulating layer 203. In 8(A), a gate wiring layer 238 overlapping with a portion of the second metal wiring layer 237 was shown, It can also be used as a gate wiring layer that covers the entirety of the first metal wiring layer 236 and the second metal wiring layer 237. Good. That is, the first metal wiring layer 236 and the second metal wiring layer 237 are gate wiring layer 23 This can be called auxiliary wiring for reducing resistance.

[0200] Furthermore, at the terminal section, the first terminal electrode, which is at the same potential as the gate wiring, is located on the protective insulating layer 203. It is formed and electrically connected to the second metal wiring layer 237. The wiring routed from the terminal is also metal. It is formed by wiring.

[0201] Furthermore, the gate wiring layer and capacitive wiring layer in areas not within the display area are designed to have low wiring resistance. Metal wiring, i.e., the first metal wiring layer 236 and the second metal wiring layer 237, as auxiliary wiring. It can also be used.

[0202] Furthermore, Figure 8(B) shows a cross-sectional structure that differs in part from that of Figure 8(A). Figure 8(B) is a reference to Figure 8( A) is the same as the drive circuit except for the material of the gate electrode layer of the thin-film transistor. Therefore, the same symbols are used for the same sections, and detailed explanations of the same sections are omitted.

[0203] Figure 8(B) shows an example where the gate electrode layer of the thin-film transistor in the drive circuit is made of metal wiring. In the drive circuit, the gate electrode layer is not limited to a translucent material.

[0204] In Figure 8(B), the thin-film transistor 240 of the drive circuit is located on the first metal wiring layer 242. The gate electrode layer is formed by stacking the second metal wiring layer 241. Layer 2 can be formed using the same material and process as the first metal wiring layer 236. The second metal wiring layer 241 is formed using the same material and process as the second metal wiring layer 237. It is possible.

[0205] Furthermore, when the first metal wiring layer 242 is electrically connected to the conductive layer 217, the first metal wiring It is preferable that the second metal wiring layer 241, which prevents oxidation of layer 242, is a metal nitride film. .

[0206] In this embodiment, metal wiring is partially used to reduce wiring resistance, and the size of the liquid crystal display panel is Even when exceeding 10 inches, reaching 60 inches, or even 120 inches, the displayed image This allows for higher resolution and a higher aperture ratio.

[0207] (Embodiment 7) In this embodiment, an example of the configuration of the holding capacity that differs from that of Embodiment 5 is shown in Figure 9(A) and This is shown in Figure 9(B). Figure 9(A) is the same as Figure 7(A) except that the configuration of the holding capacity is different. Therefore, the same symbols are used for the same locations, and detailed explanations of the same locations are omitted. (See Figure 9) (A) shows the cross-sectional structure of the thin-film transistor 220 and retaining capacitance in the pixel area.

[0208] Figure 9(A) shows the dielectric material consisting of an oxide insulating layer 216, a protective insulating layer 203, and a planar insulating layer 20 4. The pixel electrode layer 227 and the capacitive wiring layer 250 overlapping the pixel electrode layer 227 hold the capacitor. This is an example of forming a quantity. The capacitive wiring layer 250 is the source of the thin-film transistor 220 in the pixel area. Because it is made of a material with the same light-transmitting properties as the electrode layer and is formed using the same process, thin-film transistor 2 It is laid out so as not to overlap with the 20 source wiring layers.

[0209] The retention capacity shown in Figure 9(A) is due to the fact that the pair of electrodes and dielectric material are translucent, and the total retention capacity is It is translucent as a body.

[0210] Furthermore, Figure 9(B) is an example of a different storage capacity configuration from Figure 9(A). Since it is the same as 7(A) except for the difference in the configuration of the holding capacity, the same symbols are used for the same parts. I will omit a detailed explanation of the same section.

[0211] Figure 9(B) shows the dielectric material with a first gate insulating layer 202a and a second gate insulating layer 202b. The capacitive wiring layer 230, the oxide semiconductor layer 251 overlapping the capacitive wiring layer 230, and the capacitive electrode This is an example of forming a retained capacitance by stacking with 231. Also, capacitive capacitance is formed on the oxide semiconductor layer 251. Electrode 231 is stacked in contact with the other electrodes and functions as one of the electrodes for holding capacitance. The semiconductor layer 251 is the same as the source electrode layer or drain electrode layer of the thin-film transistor 220. A translucent material is formed using the same process. In addition, the capacitive wiring layer 230 is a thin film transient Because it is made of the same translucent material as the gate electrode layer of T220 and formed using the same process, it is a thin film. The layout is designed so as not to overlap with the gate wiring layer of the Rangitta 220.

[0212] Furthermore, the capacitive electrode 231 is electrically connected to the pixel electrode layer 227.

[0213] The retention capacity shown in Figure 9(B) is also due to the fact that the pair of electrodes and dielectric material are translucent, and the total retention capacity It is translucent as a body.

[0214] The holding capacities shown in Figures 9(A) and 9(B) are translucent and the number of gate wires To increase the resolution of the displayed image by increasing the number of pixels, even if the pixel dimensions are reduced, sufficient capacity is required. It can be obtained, and a high aperture ratio can be achieved.

[0215] This embodiment can be freely combined with other embodiments.

[0216] (Embodiment 8) In this embodiment, at least a part of the drive circuit and a thin film to be placed in the pixel area are placed on the same substrate. An example of how to fabricate a lunger is described below.

[0217] The thin-film transistors placed in the pixel area are formed according to Embodiments 1 to 4. Since the thin-film transistors shown in embodiments 1 to 4 are n-channel TFTs, the driving circuit Of these, a portion of the driving circuit that can be constructed with an n-channel TFT is a thin-film transistor in the pixel area. It is formed on the same substrate as the zista.

[0218] An example of a block diagram of an active-matrix display device is shown in Figure 14(A). On the substrate 5300 are a pixel section 5301, a first scan line drive circuit 5302, and a second scan line drive circuit. It has a motion circuit 5303 and a signal line drive circuit 5304. The pixel section 5301 has multiple signal lines The signal line drive circuit 5304 extends and is arranged, and multiple scan lines are connected to the first scan line drive circuit 5302, and the second scan line drive circuit 5303 are arranged as extensions. In the intersection region of the signal line, pixels, each having a display element, are arranged in a matrix. Furthermore, the substrate 5300 of the display device is FPC (Flexible Printed Circuit Board). The timing control circuit 5305 (controller, control I) is connected via a connection part such as rcuit. (Also known as C) It is connected.

[0219] Figure 14(A) shows the first scan line drive circuit 5302, the second scan line drive circuit 5303, and The line drive circuit 5304 is formed on the same substrate 5300 as the pixel section 5301. Furthermore, since the number of external components such as drive circuits is reduced, costs can be lowered. Furthermore, when a drive circuit is provided outside the circuit board 5300, extending the wiring at the connection point can cause problems. This can reduce the number of connections, leading to improved reliability or yield.

[0220] The timing control circuit 5305 is, for example, related to the first scan line drive circuit 5302. Then, the start signal (GSP1) (also called the start pulse) for the first scan line drive circuit is sent, It supplies the clock signal (GCK1) for the probe drive circuit. Also, the timing control circuit 530 5 is a second scan line drive circuit 5303, and as an example, a second scan line drive circuit 5303 It supplies the clock signal (GSP2) and the clock signal (GCK2) for the scan line drive circuit. The drive circuit 5304 receives a start signal (SSP) for the signal line drive circuit and a crossover signal for the signal line drive circuit. SCK signal, video signal data (DATA) (also simply called video signal), A clock signal (LAT) shall be supplied. Each clock signal shall consist of multiple signals with different periods. It can be a clock signal, or it can be supplied along with an inverted clock signal (CKB). It may also be a first scan line drive circuit 5302 and a second scan line drive circuit 53 It is possible to omit either 03 or 03.

[0221] In Figure 14(B), a circuit with a low drive frequency (for example, the first scan line drive circuit 5302, the second The scan line driving circuit 5303 is formed on the same substrate 5300 as the pixel section 5301, and the signal line driving This diagram shows a configuration in which the dynamic circuit 5304 is formed on a separate substrate from the pixel section 5301.

[0222] Furthermore, the thin-film transistors shown in Embodiments 1 to 4 are n-channel type TFTs. Figure 1 Figures 5(A) and 15(B) show the configuration and operation of a signal line driving circuit composed of n-channel TFTs. I will explain this by giving an example.

[0223] The signal line driving circuit includes a shift register 5601 and a switching circuit 5602. Switching circuit 5602 is a switching circuit 5602_1~5602_N (where N is natural). It has multiple circuits, each of which is called a number. Switching circuits 5602_1 to 5602_N are, , multiple transistors called thin-film transistors 5603_1~5603_k (where k is a natural number) It has a thin-film transistor 5603_1~5603_k, which is an N-channel type TFT. Let me explain an example.

[0224] The connection relationships of the signal line drive circuit will be explained using the switching circuit 5602_1 as an example. The first terminals of thin-film transistors 5603_1 to 5603_k are connected to wiring 5604_1, respectively. Connected to ~5604_k. Second terminal of thin-film transistor 5603_1~5603_k These are connected to signal lines S1~Sk, respectively. Thin-film transistors 5603_1~5603_ The gate of k is connected to wiring 5605_1.

[0225] The shift register 5601 sequentially supplies high levels (high signals) to the wiring 5605_1 to 5605_N. It outputs a signal at a high power supply potential level, also known as the switching circuit 5602_1~56 It has the function of selecting 02_N in order.

[0226] Switching circuit 5602_1 consists of wiring 5604_1~5604_k and signal lines S1~Sk A function to control the conductivity state (conduction between the first terminal and the second terminal), i.e., wiring 5604_ It has a function to control whether or not to supply potentials between 1 and 5604k to signal lines S1 and Sk. Thus, the switching circuit 5602_1 functions as a selector. The film transistors 5603_1 to 5603_k are connected to wiring 5604_1 to 5604_k, respectively. A function to control the continuity state between this and the signal lines S1~Sk, i.e., wiring 5604_1~5604_k It has the function of supplying the potential to the signal lines S1~Sk. Thus, thin-film transistor 56 Each of the 03_1 to 5603_k functions as a switch.

[0227] Note that wiring 5604_1 to 5604_k each contain video signal data (DATA). The input is video signal data (DATA), which is image information or analog corresponding to the image signal. It is often a G signal.

[0228] Next, regarding the operation of the signal line drive circuit in Figure 15(A), see the timing chart in Figure 15(B). Refer to the explanation. Figure 15(B) shows signals Sout_1 to Sout_N, and signals An example of Vdata_1 to Vdata_k is shown. Signals Sout_1 to Sout_N are each The following is an example of the output signals of the shift register 5601, with signals Vdata_1 to Vdata _k represents an example of a signal input to wiring 5604_1~5604_k. One operating period of the signal line drive circuit corresponds to one gate selection period in the display device. The selection period is divided into, for example, periods T1 to TN. Periods T1 to TN are each , a period for writing video signal data (DATA) to pixels belonging to the selected row be.

[0229] Note that the signal waveform distortions, etc., of each configuration shown in the drawings, etc. of this embodiment are for clarity. The figures may be exaggerated for aesthetic reasons. Therefore, they are not necessarily limited to that scale. It should be noted that...

[0230] During periods T1 to TN, the shift register 5601 receives a high-level signal via wiring 560 Outputs are sent sequentially from 5_1 to 5605_N. For example, during period T1, shift register 5 601 outputs a high-level signal to wiring 5605_1. Then the thin-film transistor... Since 5603_1~5603_k will be turned on, the wiring 5604_1~5604_k and signal Lines S1 to Sk become conductive. At this time, wiring 5604_1 to 5604_k are Data(S1) to Data(Sk) are entered. Each of these belongs to the selected row via thin-film transistors 5603_1 to 5603_k. Of the pixels, the data is written to the pixels in columns 1 through k. In this way, during the period T1 to TN... Then, the video signal data (DATA) is sequentially placed in k columns for each pixel belonging to the selected row. It will be written.

[0231] As described above, video signal data (DATA) is written to pixels in multiple columns. This allows for a reduction in the number of video signal data (DATA) or the number of wires. Therefore, the number of connections to external circuits can be reduced. Also, the video signal is displayed in multiple columns. By writing directly, the writing time can be extended, and the video signal can be written. This can prevent overcrowding and under-concentration.

[0232] Note that the shift register 5601 and the switching circuit 5602 are as described in Embodiment 1. It is possible to use a circuit composed of thin-film transistors as shown in section 4.

[0233] A form of shift register used in part of a scan line drive circuit and / or signal line drive circuit. This will be explained using Figures 16 and 17.

[0234] The scan line drive circuit has a shift register. In some cases, it also has a level shifter or a bar It may have a ff, etc. In a scan line driving circuit, a clock signal is input to the shift register. A selection signal is generated when the (CLK) and start pulse signal (SP) are input. The generated selection signal is buffered and amplified in a buffer and supplied to the corresponding scan line. The scan line is connected to the gate electrode of the transistor for one pixel line. Therefore, the transistors of the pixels for one line must be turned ON all at once, so buff A component capable of carrying a large current is used.

[0235] The shift register consists of the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N( N is a natural number greater than or equal to 3 (see Figure 16(A)). The shift rate shown in Figure 16(A) The first pulse output circuit 10_1 to the Nth pulse output circuit 10_N of the ZISTA are: The first clock signal CK1 is transmitted from wiring 11, and the second clock signal CK2 is transmitted from the second wiring 12. The third clock signal CK3 is transmitted from the third wire 13, and the fourth clock signal is transmitted from the fourth wire 14. CK4 is supplied. Also, in the first pulse output circuit 10_1, from the fifth wiring 15 The start pulse SP1 (the first start pulse) is input. Also, the nth pulse from the second stage onward In the pulse output circuit 10_n (where n is a natural number between 2 and N), the pulse output cycle of the preceding stage A signal from the road (referred to as the preceding signal OUT(n-1)) is input. Also, the first pulse output Circuit 10_1 receives a signal from the third pulse output circuit 10_3, which is two stages later. Similarly, in the nth pulse output circuit 10_n from the second stage onward, the (n+2)th pulse of the second stage onward The signal from the output circuit 10_(n+2) (referred to as the subsequent signal OUT(n+2)) is input. Therefore, the pulse output circuit of each stage outputs the pulse output of the subsequent stage and / or the stage two stages prior. The first output signal for input to the path (OUT(1)(SR)~OUT(N)(SR)), A second output signal (OUT(1)~OUT(N)) is output, which is then input to another circuit or similar. However, as shown in Figure 16(A), the last two stages of the shift register have subsequent signals. Since OUT(n+2) is not input, one example is a separate second start pulse SP2. The configuration should involve inputting a third start pulse SP3 to each of these.

[0236] The clock signal (CK) alternates between high and low levels (L signal, low power supply potential) at regular intervals. This is a signal that repeats the same values ​​(also called the level). Here, the first clock signal (CK1) to the second... The 4th clock signal (CK4) is delayed by 1 / 4 period in sequence. In this embodiment, Using the first clock signal (CK1) to the fourth clock signal (CK4), pulse output cycles It controls the drive of the road, etc. The clock signal is GCK depending on the input drive circuit. Although it is sometimes referred to as SCK, we will use CK in this explanation.

[0237] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 11~ It is electrically connected to one of the fourth wires 14. For example, in Figure 16(A), The first pulse output circuit 10_1 has a first input terminal 21 that is electrically connected to the first wiring 11. The second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is It is electrically connected to the third wiring 13. Also, the second pulse output circuit 10_2 is Input terminal 21 is electrically connected to the second wiring 12, and input terminal 22 is connected to the third wiring The third input terminal 23 is electrically connected to the fourth wiring 14, and the third input terminal 23 is electrically connected to the fourth wiring 14. Yes, they are.

[0238] Each of the first pulse output circuits 10_1 to the Nth pulse output circuits 10_N has a first input terminal Child 21, second input terminal 22, third input terminal 23, fourth input terminal 24, fifth input terminal Assume that it has a child 25, a first output terminal 26, and a second output terminal 27 (see Figure 16(B)). (See). In the first pulse output circuit 10_1, the first clock signal is connected to the first input terminal 21. When signal CK1 is input, the second clock signal CK2 is input to the second input terminal 22, and the third The third clock signal CK3 is input to input terminal 23, and the start signal is input to the fourth input terminal 24. A pulse is input, and the subsequent signal OUT(3) is input to the 5th input terminal 25, and the 1st output The first output signal OUT(1)(SR) is output from terminal 26, and the second output terminal 27 This indicates that the second output signal, OUT(1), is being output.

[0239] The first pulse output circuit 10_1 to the Nth pulse output circuit 10_N are 3-terminal thin film In addition to transistors (also known as TFT: Thin Film Transistors), The four-terminal thin-film transistor described in the embodiment can be used. In this book, when a thin-film transistor has two gate electrodes separated by a semiconductor layer, A gate electrode below the body layer is called the lower gate electrode, and a gate electrode above the semiconductor layer is called the upper gate electrode. It is also called the gate electrode of the right side.

[0240] When oxide semiconductors are used in the semiconductor layer including the channel formation region of a thin-film transistor, manufacturing Depending on the process, the threshold voltage may shift to the negative or positive side. Therefore, in thin-film transistors that use oxide semiconductors in the semiconductor layer including the channel formation region, A configuration that allows control of the threshold voltage is preferred. The threshold voltage is determined by controlling the potential of the upper and / or lower gate electrodes. It can be controlled by a value.

[0241] Next, let's look at an example of a specific circuit configuration of the pulse output circuit shown in Figure 16(B). (D) will explain this.

[0242] The pulse output circuit shown in Figure 16(D) consists of the first transistor 31 to the thirteenth transistor It has a 43. Also, the first input terminal 21 to the fifth input terminal 25 described above, and In addition to the first output terminal 26 and the second output terminal 27, the first high power supply potential VDD is supplied to the power supply terminal 26. Power line 51, power line 52 to which a second high power potential VCC is supplied, and power line 52 to which a low power potential VSS is supplied. Signals are sent from the power line 53 to the first transistor 31 to the thirteenth transistor 43, and The power supply potential is supplied. Here, the relative magnitudes of the power supply potentials of each power line in Figure 16(D) are The first power supply potential VDD is set to be at or above the second power supply potential VCC, and the second power supply potential VCC The potential shall be greater than the third power supply potential VSS. Note that the first clock signal (CK1) ~ The fourth clock signal (CK4) is a signal that alternates between high and low levels at regular intervals. However, assume that VDD is at the H level and VSS is at the L level. Note that the power supply line 51 Raising the potential VDD above the potential VCC of the power line 52 will affect the operation. This allows the potential applied to the gate electrode of the transistor to be kept low, and the transistor The threshold shift of the first transistor can be reduced and degradation can be suppressed. Of the transistors 31 to the 13th transistor 43, the first transistor 31 and the sixth transistor For transistors 36 to the 9th, it is preferable to use 4-terminal thin-film transistors. The first transistor 31, the sixth transistor 36 to the ninth transistor 39 The operation involves the potential of the node to which one of the electrodes, which will be the source or drain, is connected, and the gate voltage... This is a transistor that is required to be switched by a control signal of its poles, and the gate electrode is... Faster response to applied control signals (steep rise of on-current) results in more pulsed This transistor can reduce malfunctions in the output circuit. Therefore, the thin terminals shown in Figure 4 By using film transistors, the threshold voltage can be controlled, resulting in a lower rate of malfunction. This allows for a pulse output circuit that can reduce the frequency.

[0243] In Figure 16(D), the first transistor 31 has its first terminal electrically connected to the power line 51. The second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode The (lower gate electrode and the upper gate electrode) are electrically connected to the fourth input terminal 24. The second transistor 32 has its first terminal electrically connected to the power line 53, and its second terminal The first terminal of the ninth transistor 39 is electrically connected, and the gate electrode is connected to the fourth transistor It is electrically connected to the gate electrode of transistor 34. The third transistor 33 is connected to the first terminal The first input terminal 21 is electrically connected, and the second terminal is electrically connected to the first output terminal 26. The fourth transistor 34 has its first terminal electrically connected to the power line 53. The second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 is The first terminal is electrically connected to the power line 53, and the second terminal is connected to the gate of the second transistor 32. The electrode and the gate electrode of the fourth transistor 34 are electrically connected, and the gate electrode is the fourth It is electrically connected to input terminal 24. The sixth transistor 36 has its first terminal connected to the power line. Electrically connected to 52, the second terminal is the gate electrode of the second transistor 32 and the fourth terminal It is electrically connected to the gate electrode of the transistor 34, and the gate electrode (the lower gate electrode and the upper The gate electrode of the transistor is electrically connected to the fifth input terminal 25. 37 has its first terminal electrically connected to the power line 52, and its second terminal connected to the eighth transistor 38. It is electrically connected to the second terminal, and the gate electrodes (lower gate electrode and upper gate electrode) The third input terminal 23 is electrically connected to the eighth transistor 38, the first terminal The gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34 are electrically charged. They are connected to the second input terminal, with the gate electrodes (lower gate electrode and upper gate electrode) connected to the second input terminal. It is electrically connected to 22. The ninth transistor 39 has its first terminal connected to the first transistor It is electrically connected to the second terminal of the sta 31 and the second terminal of the second transistor 32, and the second terminal The child is connected to the gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40. Electrically connected, the gate electrodes (lower gate electrode and upper gate electrode) are connected to power line 52 It is electrically connected to the first input terminal 2. The tenth transistor 40 has its first terminal connected to the first input terminal 2. It is electrically connected to terminal 1, and the second terminal is electrically connected to the second output terminal 27, and the gate electrode is electrically connected to terminal 1. This is electrically connected to the second terminal of the ninth transistor 39. The eleventh transistor 41 has its first terminal electrically connected to the power line 53, and its second terminal electrically connected to the second output terminal 27. Connected electrically, the gate electrode of the second transistor 32 and the fourth transistor It is electrically connected to the gate electrode of transistor 34. Transistor 42 is the 12th terminal The child is electrically connected to the power line 53, and the second terminal is electrically connected to the second output terminal 27. , the gate electrode is the gate electrode of the 7th transistor 37 (the lower gate electrode and the upper gate electrode It is electrically connected to the electrode. The 13th transistor 43 has its first terminal connected to the power line 5 It is electrically connected to 3, and the second terminal is electrically connected to the first output terminal 26, and the gate electrode is electrically connected to 3. The electrode of the seventh transistor 37 (the lower gate electrode and the upper gate electrode) is charged. They are connected by energy.

[0244] In Figure 16(D), the gate electrode of the third transistor 33 and the tenth transistor 4 The connection point between the gate electrode of transistor 0 and the second terminal of transistor 9 39 is defined as node A. Also, the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, and The second terminal of transistor 35 (number 5), the second terminal of transistor 36 (number 6), and the eighth transistor The connection point between the first terminal of transistor 38 and the gate electrode of transistor 41 (number 11) is at node B. Let's assume that.

[0245] Figure 17(A) shows the pulse output circuit described in Figure 16(D) as the first pulse output circuit 10_ When applied to 1, the first input terminals 21 to the fifth input terminals 25 and the first output terminal 26 The signals input to or output to the second output terminal 27 are shown.

[0246] Specifically, the first clock signal CK1 is input to the first input terminal 21, and the second input terminal The second clock signal CK2 is input to child 22, and the third clock signal is input to the third input terminal 23. When signal CK3 is input, a start pulse is input to the fourth input terminal 24, and the fifth input terminal The subsequent signal OUT(3) is input to terminal 25, and the first output signal OUT is output from the first output terminal 26. (1)(SR) is output, and the second output signal OUT(1) is output from the second output terminal 27. It will be done.

[0247] A thin-film transistor is defined as a transistor with at least three components, including a gate, a drain, and a source. It is an element having terminals. Furthermore, a channel region is formed in the region superimposed on the gate in a semiconductor. It has a body and controls the gate potential, allowing the drain and saw through the channel region. The current flowing between the source and drain can be controlled. Here, the source and drain are thin film transistors. It depends on the structure and operating conditions of the converter, so which is the source and which is the drain. It is difficult to limit the extent of this. Therefore, the regions that function as source and drain are defined as They are sometimes not called drains or suctions. In that case, for example, each is called the first It may be referred to as terminal or second terminal.

[0248] Note that in Figures 16(D) and 17(A), the boot process is performed by setting node A to a floating state. A capacitive element may be provided separately to perform the strapping action. Also, the potential of node B may be maintained. Therefore, a capacitive element with one electrode electrically connected to node B may be provided separately.

[0249] Here, the timing of a shift register equipped with multiple pulse output circuits as shown in Figure 17(A) The chart is shown in Figure 17(B). Note that if the shift register is a scan line drive circuit... In total, period 61 in Figure 17(B) is the vertical retrace period, and period 62 corresponds to the gate selection period. do.

[0250] Furthermore, as shown in Figure 17(A), the ninth gate to which the second power supply potential VCC is applied By installing the Rangista 39, the following occurs before and after the bootstrap operation: It has advantages like these.

[0251] If there is no 9th transistor 39 to which the second power supply potential VCC is applied to the gate electrode, then When the potential of node A rises due to the trapping action, the second of the first transistor 31 The potential of the source terminal rises and becomes greater than the first power supply potential VDD. Then, the source of the first transistor 31 switches to the first terminal side, that is, to the power line 51 side. Therefore, in the first transistor 31, between the gate and source, and between the gate and drain Both are subjected to significant stress due to the application of a large bias voltage, and the transistor This can be a factor in degradation. Therefore, the 9th gate electrode is subjected to a second power supply potential VCC. By providing transistor 39, the power of node A is supplied by the bootstrap operation. Although the position rises, the potential of the second terminal of the first transistor 31 does not rise. This can be done. In other words, by providing the ninth transistor 39, the first transistor The value of the negative bias voltage applied between the gate and source of the zistor 31 can be reduced. Yes, it is possible. Therefore, by using the circuit configuration of this embodiment, the first transistor 31 The negative bias voltage applied between the gate and source can also be reduced, thus reducing stress. This makes it possible to suppress the degradation of the first transistor 31.

[0252] Furthermore, the location where the ninth transistor 39 is installed is the second transistor 31 The terminal is connected to the gate of the third transistor 33 via the first and second terminals. Any configuration that is set up in this manner is acceptable. Note that the pulse output circuit in this embodiment may be equipped with multiple pulse output circuits. In the case of a soft register, in a signal line drive circuit with more stages than a scan line drive circuit, the 9th transistor The ZISTA39 can be omitted, which has the advantage of reducing the number of transistors.

[0253] Furthermore, the semiconductor layers of the first transistor 31 to the thirteenth transistor 43 are made of oxide semiconductor material. By using a conductor, the off-current of the thin-film transistor is reduced, as well as the on-current and Because it is possible to increase the field effect mobility and reduce the degree of degradation. This can reduce malfunctions within the circuit. Also, transistors using oxide semiconductors, Compared to transistors using morphous silicon, a high potential is applied to the gate electrode. The degree of transistor degradation caused by this is small. Therefore, the second power supply potential VCC is supplied. The same operation can be obtained by supplying the first power potential VDD to the power line, and the connections between circuits are also This allows for a reduction in the number of power lines, thus enabling the miniaturization of the circuit.

[0254] Note that the gate electrodes of the seventh transistor 37 (the lower gate electrode and the upper gate electrode) The clock signal supplied by the third input terminal 23, and the gateway of the eighth transistor 38. The electrodes (lower gate electrode and upper gate electrode) are supplied by the second input terminal 22. The clock signal is transmitted to the gate electrode of the 7th transistor 37 (the lower gate electrode and the upper The clock signal supplied by the second input terminal 22 to the gate electrode of the eighth transistor The gate electrodes of terminal 38 (lower gate electrode and upper gate electrode) are connected to the third input terminal 23. Therefore, the same effect can be achieved by reversing the wiring so that it becomes the supplied clock signal. In addition, in the shift register shown in Figure 17(A), the seventh transistor 37 and From a state where both transistors 38 are ON, the 7th transistor 37 turns OFF, and the 8th transistor turns OFF. Transistor 38 is ON, then transistor 37 (number 7) is OFF, and the eighth transistor By turning off the 38, the second input terminal 22 and the third input terminal 23 The decrease in potential at node B, which occurs as a result of the potential drop, affects the gate of the seventh transistor 37. Due to the decrease in electrode potential and the decrease in the potential of the gate electrode of transistor 8 38, 2 This will occur multiple times. On the other hand, the shift register shown in Figure 17(A) during the period shown in Figure 17(B) Thus, from a state where both the seventh transistor 37 and the eighth transistor 38 are ON, Transistor 7, 37 is ON, and transistor 8, 38 is OFF, then the 7th By turning off transistor 37 and the eighth transistor 38, the second The potential of node B decreases due to a decrease in the potential of input terminal 22 and the third input terminal 23. The decrease can be reduced to a single event by a decrease in the potential of the gate electrode of the eighth transistor 38. Yes, it is possible. Therefore, the gate electrode of the seventh transistor 37 (the lower gate electrode and the upper The clock signal supplied from the third input terminal is supplied to the gate electrode, and the eighth transistor The gate electrodes of ZISTA 38 (lower gate electrode and upper gate electrode) are connected to the second input terminal. It is preferable to have a wiring configuration in which a clock signal is supplied. This is because the potential of node B This is because the number of fluctuations is reduced, and noise can also be reduced.

[0255] In this way, the period during which the potential of the first output terminal 26 and the second output terminal 27 is maintained at the L level In between, a configuration is set in which a high-level signal is periodically supplied to node B, and the pulse output This can suppress malfunctions in the force circuit.

[0256] (Embodiment 9) Thin-film transistors are fabricated, and these thin-film transistors are used in the pixel section and further in the driving circuit. It is possible to fabricate semiconductor devices (also called display devices) that have display functions. A part or all of the drive circuit having a transistor is integrally formed on the same substrate as the pixel section, Stem-on-panel can be formed.

[0257] A display device includes display elements. Display elements include liquid crystal elements (also called liquid crystal display elements) and light-emitting elements. A light-emitting element (also called a light-emitting display element) can be used. The light-emitting element is activated by current or voltage. This category includes elements whose brightness is controlled, specifically inorganic EL (Electrical LEDs). This includes Luminescence elements, organic EL elements, etc. Also, electronic inks. Furthermore, display media in which the contrast changes due to electrical effects can also be applied.

[0258] Furthermore, the display device includes a panel in which the display elements are sealed, and a controller on the panel. It includes a module on which ICs and the like are mounted. Furthermore, it is a device for manufacturing the display device. In the process, the element substrate, which corresponds to one form before the display element is completed, supplies current to the display element. Each of the multiple pixels is provided with means for supplying power. Specifically, the element substrate is the pixel of the display element. It is acceptable to have only the electrodes formed, or to have the conductive film that will become the pixel electrode formed first. It may be the state before etching and forming the pixel electrodes, or any form may apply. I'm hooked.

[0259] In this specification, the term "display device" refers to an image display device, a display device, or an optical display device. This refers to the power source (including lighting equipment). It also refers to connectors, such as FPC (Flexible Printed Circuit). (inted circuit) or TAB (Tape Automated Bon) (ding) tape or TCP (Tape Carrier Package) Modules that have a printed circuit board attached to the end of the TAB tape or TCP. The display element or IC (integrated circuit board) is integrated using the COG (Chip On Glass) method. All modules in which the road is directly implemented are also included in the display device.

[0260] Figure 10 shows the external appearance and cross-section of a liquid crystal display panel, which is a form of semiconductor device. Let me explain. Figures 10(A1)(A2) show thin-film transistors 4010 and 4011, and liquid crystal. A sealing material 4005 is placed between the element 4013 and the first substrate 4001 and the second substrate 4006. Figure 10(B) is a plan view of the panel sealed by [a certain method], and Figure 10(A1)(A2) This corresponds to a cross-sectional view in MN.

[0261] The pixel section 4002 and the scanning line driving circuit 4004 are surrounded on the first substrate 4001. A sealing material 4005 is provided in this manner. Also, the pixel section 4002 and the scan line drive rotation A second substrate 4006 is provided on the path 4004. Therefore, the pixel section 4002 and the scanning The line drive circuit 4004 consists of the first substrate 4001, the sealing material 4005, and the second substrate 4006. It is sealed together with the liquid crystal layer 4008. Also, the seal on the first substrate 4001 A single crystal is placed on a separately prepared substrate in a region different from the area enclosed by material 4005. A signal line driving circuit 4003, formed from a semiconductor film or a polycrystalline semiconductor film, is mounted.

[0262] Furthermore, the method of connecting the separately formed drive circuit is not particularly limited, and COG method, Wire bonding methods or TAB methods can be used. Figure 10(A1) This is an example of implementing the signal line drive circuit 4003 using the COG method, and Figure 10(A2) shows, This is an example of implementing the signal line drive circuit 4003 using the TAB method.

[0263] Furthermore, the pixel section 4002 and the scanning line driving circuit 4004 provided on the first substrate 4001 are, It has multiple thin-film transistors, and in Figure 10(B), the thin film included in the pixel section 4002 Transistor 4010 and thin-film transistor 4011 included in scan line drive circuit 4004 This illustrates the following: Insulating layers 4041 and 404 are placed on thin-film transistors 4010 and 4011. 2, 4020, and 4021 are provided.

[0264] Thin-film transistors 4010 and 4011 have an oxide semiconductor layer as shown in Embodiments 1 to 4. Highly reliable thin-film transistors can be applied. Thin-film transistors for drive circuits As for st 4011, thin-film transistors 410, 499 shown in Embodiments 1 to 4, Thin-film transistors 420 and 498 are used as the thin-film transistor 4010 for the pixels. This is possible. In this embodiment, thin-film transistors 4010 and 4011 are n-channel It is a type 1 / 2 thin-film transistor.

[0265] On the insulating layer 4021, the oxide semiconductor layer of the thin-film transistor 4011 for the drive circuit A conductive layer 4040 is provided in a position that overlaps with the channel formation region. The conductive layer 4040 is acid By placing it in a position that overlaps with the channel formation region of the synthetic semiconductor layer, before and after BT testing... This can reduce the change in the threshold voltage of the thin-film transistor 4011. The conductive layer 4040 may have the same potential as the gate electrode layer of the thin-film transistor 4011. They can be different, and can also function as a second gate electrode layer. Also, the conductive layer The potential of 4040 may be GND, 0V, or floating.

[0266] Furthermore, the pixel electrode layer 4030 of the liquid crystal element 4013 is connected to the thin-film transistor 4010. They are electrically connected. And the counter electrode layer 4031 of the liquid crystal element 4013 is on the second substrate 40 Formed on 06. Pixel electrode layer 4030, counter electrode layer 4031, and liquid crystal layer 4008 The overlapping portion corresponds to the liquid crystal element 4013. Note that the pixel electrode layer 4030 and the opposite The electrode layer 4031 is provided with insulating layers 4032 and 4033, which function as alignment films. The liquid crystal layer 4008 is sandwiched between insulating layers 4032 and 4033.

[0267] Furthermore, translucent substrates can be used as the first substrate 4001 and the second substrate 4006. Glass, ceramics, and plastics can be used. As for plastics... , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film or acrylic resin film Room can be used.

[0268] Furthermore, 4035 is a columnar spacer obtained by selectively etching an insulating film. To control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 It is provided in [location]. A spherical spacer may also be used. Also, the counter electrode layer 4031 It is electrically connected to a common potential line provided on the same substrate as the thin-film transistor 4010. Using a common connection part, the opposing electrode layer 40 is connected via conductive particles placed between the pair of substrates. 31 and the common potential line can be electrically connected. Note that the conductive particles are the sealing material 40 It will be included in 05.

[0269] Alternatively, a liquid crystal exhibiting a blue phase without an alignment layer may be used. The blue phase is one of the liquid crystal phases. Yes, as the temperature of a cholesteric liquid crystal is increased, it transitions from the cholesteric phase to the isotropic phase. This is the phase that appears earlier. The blue phase only appears within a narrow temperature range, so improving the temperature range is necessary. To achieve this, a liquid crystal composition containing 5% or more by weight of a chiral agent is used in the liquid crystal layer 4008. The liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 1 msec. It is short, optically isotropic, and therefore requires no orientation processing, and has low dependence on viewing angle.

[0270] In addition to transmissive liquid crystal displays, this method can also be applied to semi-transmissive liquid crystal displays.

[0271] In addition, in liquid crystal displays, a polarizing plate is provided on the outside (viewing side) of the substrate, and a colored layer (color) is provided on the inside. The example shows the order of arrangement: filter, electrode layer used for display element, but the polarizing plate is on the inside of the substrate. It may also be provided in this embodiment. Furthermore, the laminated structure of the polarizing plate and the colored layer is not limited to this embodiment, and the polarizing plate Furthermore, the materials and manufacturing process conditions of the colored layer should be set appropriately. A light-shielding film that functions as a black matrix may be provided.

[0272] Thin-film transistor 4011 is in contact with a semiconductor layer containing a channel formation region as a protective insulating film. An insulating layer 4041 is formed, and the thin-film transistor 4011 has an insulating layer as a channel protection layer. 4042 is formed. The insulating layers 4041 and 4042 are oxide insulating layers as shown in Embodiment 1. The same materials and methods as for the marginal layers 416 and 426 may be used to form them. Also, thin film transistors The structure is such that the surface is covered with an insulating layer 4021 that functions as a planar insulating film to reduce surface irregularities. Here, as insulating layers 4041 and 4042, the sputtering method is used with Embodiment 1. This further forms a silicon oxide film.

[0273] Furthermore, an insulating layer 4020 is formed on insulating layers 4041 and 4042. Insulating layer 4041 If 4042 is formed using the same material and method as the protective insulating layer 403 shown in Embodiment 1, Good. Here, a silicon nitride film is formed as the insulating layer 4020 by the RF sputtering method.

[0274] Furthermore, an insulating layer 4021 is formed as a planarizing insulating film. It can be formed using the same materials and methods as the planarized insulating layer 404 shown in Embodiment 1, i.e., polyimide. heat-resistant organic materials such as acrylic, benzocyclobutene, polyamide, and epoxy. In addition to the above organic materials, low dielectric constant materials (low-k materials) can be used. Use roxane-based resins, PSG (phosphorus glass), BPSG (phosphorus boron glass), etc. This can be achieved. Furthermore, by stacking multiple insulating films formed from these materials, an insulating layer 40 21 may be formed.

[0275] In this embodiment, multiple thin-film transistors in the pixel section are collectively surrounded by a nitride insulating film. Alternatively, a nitride insulating film can be used for the insulating layer 4020 and the gate insulating layer, as shown in Figure 10. The insulating layer 4020 surrounds at least the periphery of the pixel portion of the active matrix substrate. A configuration is provided in which the gate insulating layer and the outer layer are in contact. In this manufacturing process, the outer It can prevent moisture from entering. Also, semiconductor devices, such as display devices, Even after the construction is complete, it can prevent external moisture from entering for a long period of time, ensuring long-term reliability of the device. It can improve reliability.

[0276] Siloxane-based resins are formed using siloxane-based materials as the starting material for Si-OS. This corresponds to a resin containing i-bonds. Siloxane resins use organic groups (e.g., alkyl groups) as substituents. You may also use aryl groups or fluoro groups. Furthermore, organic groups may have fluoro groups. You can.

[0277] The method for forming the insulating layer 4021 is not particularly limited and can be sputtered or SOG depending on the material. Spin coating, dip coating, spray coating, droplet ejection (inkjet method, screen coating) Printing methods (offset printing, etc.), doctor knife, roll coater, curtain coater - A knife coater or the like can be used. The firing process of the insulating layer 4021 and the semiconductor layer By combining the role of Neil, it becomes possible to efficiently manufacture semiconductor devices.

[0278] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Titanium oxide-containing indium tin oxide, indium tin oxide (hereinafter referred to as ITO), Translucent materials such as indium zinc oxide and indium tin oxide with added silicon dioxide. A translucent conductive material can be used.

[0279] Furthermore, conductive polymers are used as the pixel electrode layer 4030 and the counter electrode layer 4031. It can be formed using a conductive composition containing (also known as). The resulting pixel electrodes have a sheet resistance of 10,000 Ω / □ or less and a light transmittance at a wavelength of 550 nm. It is preferable that the ratio is 70% or higher. The sheet resistance is preferably lower. Also, the guide It is preferable that the resistivity of the conductive polymer contained in the electrochemical composition is 0.1 Ω·cm or less. .

[0280] As the conductive polymer, so-called π-electron conjugated conductive polymers can be used. For example For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene Examples include derivatives thereof, or copolymers of two or more of these.

[0281] In addition, a separately formed signal line drive circuit 4003 and a scan line drive circuit 4004 or pixel unit 4 The various signals and potentials supplied to 002 are provided by the FPC4018.

[0282] Is the connection terminal electrode 4015 made of the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013? The terminal electrode 4016 is formed from the source electrode layer of the thin-film transistors 4010 and 4011. It is formed of the same conductive film as the drain electrode layer.

[0283] The connecting terminal electrode 4015 is connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. They are electrically connected.

[0284] Furthermore, in Figure 10, a signal line drive circuit 4003 is formed separately and implemented on the first substrate 4001. The example shown illustrates this configuration, but it is not limited to this setup. A separate scan line drive circuit can be formed to implement it. Alternatively, you may install it, or separately form only a part of the signal line drive circuit or a part of the scan line drive circuit. It's okay to implement it.

[0285] Figure 19 shows a semi-finished TFT substrate 2600 fabricated by the fabrication method disclosed herein. This shows an example of how a liquid crystal display module can be configured as a conductive device.

[0286] Figure 19 shows an example of a liquid crystal display module, in which the TFT substrate 2600 and the opposing substrate 2601 are The pixel portion 2603, which includes a TFT and the like, is fixed in place by a material 2602, and the liquid crystal layer is also included between them. A display element 2604 and a colored layer 2605 are provided to form a display area. Colored layer 2605 This is necessary for color display, and in the case of the RGB method, it corresponds to red, green, and blue. A colored layer is provided corresponding to each pixel. The TFT substrate 2600 and the opposing substrate 2601 Polarizing plates 2606, 2607, and 2613 are arranged on the outside. The light source is cold It consists of a cathode tube 2610 and a reflector 2611, and the circuit board 2612 is flexible The wiring circuit section 2608 of the TFT board 2600 is connected by the wire board 2609, and the control External circuits such as polarizing circuits and power supply circuits are incorporated. Also, between the polarizing plate and the liquid crystal layer The layers may be stacked with a phase difference plate in place.

[0287] The LCD display module has TN (Twisted Nematic) mode and IPS (I n-Plane-Switching) mode, FFS (Fringe Field Switching) (witching) mode, MVA (Multi-domain Vertical A) alignment) mode, PVA(Patterned Vertical Alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optically Compensated) Birefringence mode, FLC (Ferroelectric Liq uid Crystal) mode, AFLC(AntiFerroelectric L You can use modes such as iquid Crystal.

[0288] Through the above process, a highly reliable liquid crystal display panel can be manufactured as a semiconductor device. ru.

[0289] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0290] (Embodiment 10) An example of electronic paper as a form of semiconductor device is shown.

[0291] Electronic paper drives electronic ink using switching elements and electrically connected elements. - May be used for this purpose. Electronic paper is also called an electrophoretic display device (electrophoretic display). It has been discovered that it offers the same readability as paper, lower power consumption compared to other display devices, and a thin and light form factor. It has the advantage of making it possible to do so.

[0292] Electrophoretic displays can take various forms, but one involves a first particle with a positive charge. A microcapsule containing a child and a second particle having a negative charge is placed in a solvent or solute. It is a dispersed substance, and by applying an electric field to the microcapsules, micro Move the particles inside the capsule in opposite directions and display only the color of the particles that have gathered on one side. It is such that the first or second particle contains dye and, in the absence of an electric field, It does not move. Also, the color of the first particle and the color of the second particle are different (colorless). (Includes)

[0293] Thus, in electrophoretic displays, substances with high dielectric constants move to regions with high electric fields. This is a display that utilizes the so-called electrophoretic effect. Electrophoretic displays are liquid crystal displays. The display device does not require a polarizing filter.

[0294] When the above microcapsules are dispersed in a solvent, it is called an electronic ink. This electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. Color display is also possible by using color filters or particles containing pigments.

[0295] Furthermore, the microphone is placed on the active matrix substrate, appropriately sandwiched between the two electrodes. By arranging multiple microcapsules, an active-matrix type display device can be completed. By applying an electric field to the cell, a display can be created. For example, the thin film of Embodiments 1 to 4 An active matrix substrate obtained by a transistor can be used.

[0296] Furthermore, the first and second particles in the microcapsules are made of conductive material, insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, electro A type of material selected from trochromic materials, magnetophoretic materials, or a composite material thereof Use it.

[0297] Figure 18 shows an active-matrix electronic paper as an example of a semiconductor device. The thin-film transistor 581 used in the device is the thin-film transistor shown in Embodiment 1. It can be fabricated in the same way as a transistor and is a highly reliable thin-film transistor containing an oxide semiconductor layer. The thin-film transistors shown in embodiments 2 to 4 are also used as the thin-film transistor 581 in this embodiment. It can also be applied.

[0298] Figure 18 shows an example of an electronic paper display using a twist ball display method. The Toball display method is an electrode layer that uses spherical particles painted in white and black as display elements. It is placed between the first electrode layer and the second electrode layer, and a potential difference is applied between the first electrode layer and the second electrode layer. This method of display is achieved by controlling the orientation of spherical particles by generating a phenomenon.

[0299] The thin-film transistor 581 formed on the substrate 580 is a thin-film transistor with a bottom gate structure. It is covered by an insulating film 583 that is in contact with the semiconductor layer. - The electrode layer or drain electrode layer consists of the first electrode layer 587 and an opening formed in the insulating layer 585. They are in contact and electrically connected. The first electrode layers 583, 587 and the substrate 596 are formed on the substrate 596. Between the second electrode layer 588 and the surrounding area, there is a black region 590a and a white region 590b, and A spherical particle 589 is provided, which includes a cavity 594 filled with liquid. The area surrounding the particle 589 is filled with a filler material 595 such as resin. The first electrode layer 587 is a pixel It corresponds to an electrode, and the second electrode layer 588 corresponds to a common electrode. The second electrode layer 588 is a thin film It is electrically connected to a common potential line provided on the same circuit board as transistor 581. Using the connecting portion, the second electrode layer 588 and the conductive particles placed between the pair of substrates are connected. It can be electrically connected to the potential line.

[0300] Alternatively, an electrophoretic element can be used instead of a twist ball. (Transparent liquid) And, positively charged white particles and negatively charged black particles are enclosed in a diameter of 10 μm to 20 Microcapsules of approximately 0 μm are used. They are placed between the first electrode layer and the second electrode layer. The microcapsules, when an electric field is applied, are formed by the first electrode layer and the second electrode layer, and white The white and black particles move in opposite directions, allowing for the display of either white or black. An electrophoretic display element is a display element that applies the principle, and a device using an electrophoretic display element. It is commonly called electronic paper. Electrophoretic display elements are more reactive than liquid crystal display elements. Due to its high visibility, an auxiliary light is unnecessary, and it consumes little power, allowing it to be displayed even in dimly lit places. It is possible to recognize a part of it. Also, even if power is not supplied to the display unit, Because it is possible to retain the displayed image, the display function of the semiconductor device can be transmitted from the radio wave source. When the display device (also simply called a display device, or a semiconductor device equipped with a display device) is moved away Furthermore, it becomes possible to save the displayed image.

[0301] Through the above process, highly reliable electronic paper can be manufactured as a semiconductor device. .

[0302] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0303] (Embodiment 11) An example of a light-emitting display device is shown as a semiconductor device. The display elements of the display device are as follows: This is demonstrated using a light-emitting element that utilizes electroluminescence. Light-emitting devices that utilize luminescence depend on whether the light-emitting material is an organic compound or an inorganic compound. They are distinguished and generally referred to as organic EL elements and inorganic EL elements.

[0304] Organic EL elements emit electrons and holes from a pair of electrodes when a voltage is applied to the light-emitting element. Each of these is injected into a layer containing a luminescent organic compound, and an electric current flows through it. Then, these... The recombination of electrons and holes causes the luminescent organic compound to form an excited state. And when that excited state returns to the ground state, it emits light. From this mechanism, Such light-emitting devices are called current-excited light-emitting devices.

[0305] Inorganic electroluminescent (EL) elements are classified into dispersed inorganic EL elements and thin-film inorganic EL elements based on their element configuration. They are classified as such. Dispersive inorganic EL elements have a light-emitting layer in which particles of light-emitting material are dispersed in a binder. The luminescence mechanism utilizes donor and acceptor levels, and the donor-acceptor level is the key to this process. This is a receptor recombination type light emission. Thin-film inorganic EL elements sandwich the light-emitting layer between dielectric layers. Furthermore, it has a structure where it is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. This is a localized light emission. Here, we will explain using an organic EL element as the light-emitting element. ru.

[0306] Figure 12 shows an example of a pixel configuration to which digital time-gradation driving can be applied as an example of a semiconductor device. This is a diagram.

[0307] This section describes the pixel configuration and operation to which digital time-based gradation driving can be applied. This uses an n-channel transistor with an oxide semiconductor layer as the channel formation region as one pixel. Here are two examples of its use.

[0308] Pixel 6400 consists of a switching transistor 6401 and a transistor for driving the light-emitting element. It has 6402, a light-emitting element 6404 and a capacitive element 6403. Switching transistor Zistor 6401 has its gate connected to scan line 6406, and the first electrode (source electrode and dray One of the electrodes is connected to signal line 6405, and the second electrode (source electrode and drain electrode) The other side is connected to the gate of the light-emitting element drive transistor 6402. The drive transistor 6402 has its gate connected to the power line 6407 via a capacitive element 6403. The first electrode is connected to the power line 6407, and the second electrode is connected to the first electrode of the light-emitting element 6404. It is connected to the (pixel electrode). The second electrode of the light-emitting element 6404 corresponds to the common electrode 6408. The common electrode 6408 is electrically connected to a common potential line formed on the same substrate.

[0309] Furthermore, a low power supply potential is set for the second electrode (common electrode 6408) of the light-emitting element 6404. The low power supply potential is defined as the low power supply potential set on power line 6407 relative to the high power supply potential. The potential is the potential that satisfies the high power supply potential, and low power supply potentials include, for example, GND and 0V. It may be fixed. The potential difference between this high power supply potential and the low power supply potential is applied to the light-emitting element 6404. Then, in order to pass current through the light-emitting element 6404 and make the light-emitting element 6404 emit light, a high power supply potential is used. The potential difference between the low power supply potential and the light-emitting element 6404 is set to be greater than or equal to the forward threshold voltage of the light-emitting element 6404. Set the potential for each.

[0310] Furthermore, the capacitive element 6403 substitutes for the gate capacitance of the driving transistor 6402 of the light-emitting element. It is also possible to omit this. Regarding the gate capacitance of the 6402 transistor for driving the light-emitting element... In this case, a capacitance may be formed between the channel region and the gate electrode.

[0311] Here, in the case of a voltage input voltage drive method, the gate of the drive transistor 6402 of the light-emitting element The circuit has two components: one that turns the 6402 transistor for driving the light-emitting element on, and another that turns it off. A video signal is input that results in one of two states. In other words, the drive transistor 6 of the light-emitting element 402 operates in the linear region. The luminescent element driver transistor 6402 operates in the linear region. To achieve this, a voltage higher than the voltage of the power line 6407 is supplied to the drive transistor 6 of the light-emitting element. Connect to gate 402. Note that signal line 6405 has (power line voltage + for driving the light-emitting element) Apply a voltage greater than or equal to the Vth of transistor 6402.

[0312] Furthermore, when using analog gradation drive instead of digital time gradation drive, the signal input is different. By doing so, the same pixel configuration as in Figure 12 can be used.

[0313] When performing analog grayscale driving, the gate of the light-emitting element of the light-emitting element is connected to the gate of the driving transistor 6402 of the light-emitting element. The forward voltage of child 6404 + the voltage of transistor 6402 for driving the light-emitting element is greater than or equal to Vth. The forward voltage of the light-emitting element 6404 refers to the voltage required to achieve the desired brightness. , including at least a forward threshold voltage. Note that the light-emitting element is driven by transistor 6402 By inputting a video signal that operates in the saturation region, current flows to the light-emitting element 6404. This is possible. In order to operate the 6402 driving transistor for the light-emitting element in the saturation region, The potential of the power line 6407 is higher than the gate potential of the transistor 6402 that drives the light-emitting element. By converting the video signal to analog, the light-emitting element 6404 receives power corresponding to the video signal. It can drive the flow and perform analog gradation driving.

[0314] Note that the pixel configuration shown in Figure 12 is not limited to this. For example, if new pixels are added to the pixels shown in Figure 12... Switches, resistors, capacitives, transistors, or logic circuits may be added to it.

[0315] Next, the configuration of the light-emitting element will be explained using Figure 13. Here, the driving TFT is n Let's take the case of a type as an example to explain the cross-sectional structure of a pixel. Figure 13(A)(B)(C) The driver TFTs 7001, 7011, and 7021 used in the semiconductor device are as follows in Embodiment 1. It can be fabricated in the same way as the thin-film transistor shown, and is a highly reliable thin-film transistor including an oxide semiconductor layer. It is a zista. Also, the thin film transistor shown in Embodiments 2 to 4 is driven by TFT700 It can also be applied as 1, 7011, and 7021.

[0316] A light-emitting element only needs to have at least one of its electrodes, either the anode or the cathode, transparent in order to extract light. Then, a thin-film transistor and a light-emitting element are formed on the substrate, and light is emitted from the side opposite to the substrate. This includes top-side emission, bottom-side emission which extracts light from the substrate side, and on the substrate side and the opposite side of the substrate. There is a light-emitting element with a double-sided emission structure that extracts light from the side surface, and the pixel configuration is which emission structure It can also be applied to optical elements.

[0317] The light-emitting element with an upper surface injection structure will be explained using Figure 13(A).

[0318] Figure 13(A) shows that the driving TFT 7001 is n-type, and the light emitted from the light-emitting element 7002 is Figure 13(A) shows a cross-sectional view of the pixel when the light passes through to the anode 7005 side. The cathode 7003 and the driver TFT 7001 of 02 are electrically connected, and on the cathode 7003 The light-emitting layer 7004 and the anode 7005 are stacked in order. The cathode 7003 has a small work function. Furthermore, a variety of materials can be used as long as they are conductive films that reflect light. For example, C α, Al, MgAg, AlLi, etc. are preferred. The light-emitting layer 7004 is composed of a single layer. It is fine whether it is configured as a single layer or as multiple layers stacked on top of each other. If composed of the above, then on the cathode 7003 there is an electron injection layer, an electron transport layer, an electron emission layer, and a hole transport layer. The layers are stacked in the order of the layer and the hole injection layer. Note that it is not necessary to provide all of these layers. Anode 700 5 is formed using a light-transmitting conductive material, for example, indigo containing tungsten oxide. Indium oxide, indium zinc oxide containing tungsten oxide, indium zinc oxide containing titanium oxide Indium tin oxide containing oxides, titanium oxide, and indium tin oxide (hereinafter referred to as ITO) (This refers to the light-transmitting properties of indium zinc oxide, indium tin oxide with added silicon oxide, etc.) A conductive film having the properties of the conductive film may also be used.

[0319] Furthermore, between cathode 7003 and the cathode 7008 of the adjacent pixel, partitions cover each end. A 7009 partition wall will be installed. The partition wall 7009 will be made of polyimide, acrylic, polyamide, epoxy, etc. It is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. The partition wall 7009 is In particular, a photosensitive resin material is used, and the side surface of the partition wall 7009 is formed with a continuous curvature. It is preferable to form it as a slope. A photosensitive resin material is used as the partition wall 7009. In this case, the step of forming a resist mask can be omitted.

[0320] The region between the cathode 7003 and the anode 7005, which sandwiches the light-emitting layer 7004, is the light-emitting element 7002. It corresponds to the pixel shown in Figure 13(A), where the light emitted from the light-emitting element 7002 is the arrow. As indicated by the mark, inject towards the anode 7005 side.

[0321] Next, the light-emitting element with a bottom-extrusion structure will be explained using Figure 13(B). Driving TFT7 When 011 is n-type and the light emitted from the light-emitting element 7012 is directed toward the cathode 7013 side, Figure 13(B) shows a cross-sectional view of the pixel. In Figure 13(B), the driving TFT7011 is electrically connected to the pixel. The cathode 7013 of the light-emitting element 7012 is deposited on a light-transmitting conductive film 7017. The light-emitting layer 7014 and the anode 7015 are stacked in order on the cathode 7013. If 015 is translucent, a shielding material to reflect or block light should be used to cover the anode. A film 7016 may be formed. The cathode 7013 is as in the case of Figure 13(A). Various materials can be used if the conductivity function is small. However, the film thickness is The film should be transparent enough to transmit light (preferably around 5 nm to 30 nm). For example, a 20 nm film. A thick aluminum film can be used as the cathode 7013. And the light-emitting layer 7 014, as in Figure 13(A), consists of a single layer, but multiple layers are stacked on top of each other. Either configuration is acceptable. The anode 7015 does not need to transmit light, but as shown in the diagram... Similar to 13(A), it can be formed using a light-transmitting conductive material. The shielding film 7016 can be made of, for example, a light-reflecting metal, but is not limited to a metal film. It's not possible. For example, a resin with black pigment added can be used.

[0322] Furthermore, between the conductive film 7017 and the conductive film 7018 of the adjacent pixel, the edges of each film are covered. A partition wall 7019 is provided. The partition wall 7019 is made of polyimide, acrylic, polyamide, epoxy. Formed using organic resin films, inorganic insulating films, or organic polysiloxanes. (Partition 7019) In particular, a photosensitive resin material is used, and the side surface of the partition wall 7019 is formed with a continuous curvature. It is preferable to form it so that it becomes an inclined surface. A photosensitive resin material is used as the partition wall 7019. When used, the step of forming a resist mask can be omitted.

[0323] The region between the cathode 7013 and anode 7015, sandwiching the light-emitting layer 7014, is the light-emitting element 7012. This corresponds to the pixel shown in Figure 13(B), where the light emitted from the light-emitting element 7012 is As indicated by the arrow, the material is injected towards the cathode 7013.

[0324] Next, a light-emitting element with a double-sided injection structure will be explained using Figure 13(C). Figure 13(C) Then, on the light-transmitting conductive film 7027 electrically connected to the driving TFT 7021, The cathode 7023 of the light-emitting element 7022 is formed by depositing a film, and the light-emitting layer 7024 is on the cathode 7023. The anodes 7025 are stacked in order. The cathode 7023 is, as in the case of Figure 13(A), Various materials can be used if the conductivity function is small. However, the film thickness is ...to the extent that it transmits light. For example, Al with a film thickness of 20 nm is used as cathode 7023. It can be used. The light-emitting layer 7024 is composed of a single layer, as in Figure 13(A). It is acceptable whether it is configured as a single layer or as multiple layers stacked on top of each other. Anode 70 25 can be formed using a light-transmitting conductive material, similar to Figure 13(A). ru.

[0325] Furthermore, between the conductive film 7027 and the conductive film 7028 of the adjacent pixel, the respective edges are covered. A partition wall 7029 is provided. The partition wall 7029 is made of polyimide, acrylic, polyamide, epoxy. It is formed using organic resin films, inorganic insulating films, or organic polysiloxanes. (Partition 7029) In particular, a photosensitive resin material is used, and the side surface of the partition wall 7029 is formed with a continuous curvature. It is preferable to form it so that it becomes an inclined surface. A photosensitive resin material is used as the partition wall 7029. When used, the step of forming a resist mask can be omitted.

[0326] The portion where the cathode 7023, the light-emitting layer 7024, and the anode 7025 overlap is the light-emitting element 70 This corresponds to 22. In the case of the pixel shown in Figure 13(C), the light emitted from the light-emitting element 7022 As indicated by the arrows, the material is injected into both the anode 7025 side and the cathode 7023 side.

[0327] Here, we have discussed organic EL elements as light-emitting elements, but inorganic EL elements can also be used as light-emitting elements. It is also possible to incorporate an L element.

[0328] Furthermore, the thin-film transistor (driving TFT) that controls the driving of the light-emitting element and the light-emitting element are electrically connected. An example of connection was shown, but a current control TFT is connected between the driving TFT and the light-emitting element. It may be a continuation of the same configuration.

[0329] The semiconductor device is not limited to the configuration shown in Figure 13, but is disclosed herein. Various modifications are possible based on the technical concept.

[0330] Next, the appearance of a light-emitting display panel (also called a light-emitting panel), which corresponds to a form of semiconductor device, and The cross-section will be explained using Figure 11. Figure 11(A) shows a thin layer formed on the first substrate. A panel in which a film transistor and a light-emitting element are sealed between a second substrate and a sealing material. This is a plan view, and Figure 11(B) corresponds to the cross-sectional view at HI in Figure 11(A).

[0331] Pixel section 4502, signal line driving circuit 4503a, 450 provided on the first substrate 4501 3b, and the scan line drive circuits 4504a and 4504b are surrounded by a sealing material 4505 A pixel unit 4502, signal line driving circuits 4503a, 4503b, and A second substrate 4506 is provided on top of the scan line driving circuits 4504a and 4504b. The pixel section 4502, signal line driving circuits 4503a, 4503b, and scan line driving circuit 45 04a and 4504b consist of a first substrate 4501, a sealing material 4505, and a second substrate 4506. It is sealed together with the filler 4507. Highly dense protective film with minimal degassing (laminated film, UV-curing resin film) It is preferable to package (seal) the product with a cover material such as a linoleum.

[0332] Also provided on the first substrate 4501 are the pixel section 4502, the signal line driving circuit 4503a, 4 503b, and the scan line driving circuits 4504a and 4504b have multiple thin-film transistors. In Figure 11(B), the thin-film transistor 4510 included in the pixel section 4502 and the signal The thin-film transistor 4509 included in the wire drive circuit 4503a is shown as an example.

[0333] Thin-film transistors 4509 and 4510 have an oxide semiconductor layer as shown in Embodiments 1 to 4. Highly reliable thin-film transistors can be applied. Thin-film transistors for drive circuits As for sta 4509, thin-film transistors 410, 499 shown in Embodiments 1 to 4, Thin-film transistors 420 and 498 are used as the thin-film transistor 4510 for the pixels. This is possible. In this embodiment, thin-film transistors 4509 and 4510 are n-channel It is a type 1 / 2 thin-film transistor.

[0334] On the insulating layer 4544, the oxide semiconductor layer of the thin-film transistor 4509 for the drive circuit A conductive layer 4540 is provided in a position that overlaps with the channel formation region. The conductive layer 4540 is oxidized. By placing it in a position that overlaps with the channel formation region of the semiconductor layer, before and after BT testing This can reduce the change in the threshold voltage of the thin-film transistor 4509. The potential of the electrode layer 4540 may be the same as that of the gate electrode layer of the thin-film transistor 4509, or it may be different. It may also function as a second gate electrode layer. The potential of 540 may be GND, 0V, or floating.

[0335] Thin-film transistor 4509 is in contact with a semiconductor layer including a channel formation region as a protective insulating film. Then an insulating layer 4541 is formed, and the thin-film transistor 4510 has an insulating layer as a channel protection layer 4542 is formed. The insulating layers 4541 and 4542 are oxide insulating layers as shown in Embodiment 1. The same materials and methods as for the marginal layers 416 and 426 may be used to form them. Also, thin film transistors The structure is such that the surface is covered with an insulating layer 4544 that functions as a planar insulating film to reduce surface irregularities. Here, as insulating layers 4541 and 4542, the sputtering method is used with Embodiment 1. This further forms a silicon oxide film.

[0336] Furthermore, an insulating layer 4543 is formed on insulating layers 4541 and 4542. Insulating layer 4543 This can be formed using the same materials and methods as the protective insulating layer 403 shown in Embodiment 1. Next, a silicon nitride film is formed as the insulating layer 4543 by the RF sputtering method.

[0337] Furthermore, an insulating layer 4544 is formed as a planar insulating film. It can be formed using the same materials and methods as the planarized insulating layer 404 shown in Embodiment 1. Here, Acrylic is used as the insulating layer 4544.

[0338] In this embodiment, multiple thin-film transistors in the pixel section are collectively surrounded by a nitride insulating film. Alternatively, a nitride insulating film can be used for the insulating layer 4543 and the gate insulating layer, as shown in Figure 11. Insulating layer 4543 surrounds at least the periphery of the pixel portion of the active matrix substrate. A configuration is provided in which the gate insulating layer and the outer layer are in contact. In this manufacturing process, the outer It can prevent moisture from entering. Also, semiconductor devices, such as display devices, Even after the construction is complete, it can prevent external moisture from entering for a long period of time, ensuring long-term reliability of the device. It can improve reliability.

[0339] Furthermore, 4511 corresponds to a light-emitting element, and the first electrode is a pixel electrode of the light-emitting element 4511. Layer 4517 is electrically connected to the source electrode layer or drain electrode layer of the thin-film transistor 4510. It is connected to the following. The configuration of the light-emitting element 4511 is a first electrode layer 4517 and an electroluminescent layer The structure is a stacked structure of 4512 and a second electrode layer 4513, but is not limited to the configuration shown. The configuration of the light-emitting element 4511 is changed as appropriate to match the direction of the light extracted from the element 4511. It is possible.

[0340] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. In particular, using a photosensitive material, an opening is formed on the first electrode layer 4517, and the side wall of the opening It is preferable to form it so that it becomes an inclined surface with a continuous curvature.

[0341] Even if the electroluminescent layer 4512 consists of a single layer, it is configured to be stacked with multiple layers. It's fine either way.

[0342] To prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light-emitting element 4511, the second electrode layer A protective film may be formed on 4513 and the partition wall 4520. The protective film may be a silicon nitride film. It can form silicon nitride oxide films, DLC films, and the like.

[0343] Also, signal line drive circuits 4503a, 4503b and scan line drive circuits 4504a, 4504b The various signals and potentials applied to the pixel section 4502 are FPC4518a, 4518 It is supplied by b.

[0344] The connection terminal electrode 4515 has the same conductive film as the first electrode layer 4517 of the light-emitting element 4511. Formed from, the terminal electrode 4516 has the same sole as that of the thin-film transistors 4509 and 4510. The drain electrode layer and the drain electrode layer are formed from the same conductive film.

[0345] The connecting terminal electrode 4515 is connected to the terminal of FPC4518a via the anisotropic conductive film 4519. They are electrically connected.

[0346] The second substrate located in the direction of light extraction from the light-emitting element 4511 must be translucent. No. In that case, glass plate, plastic plate, polyester film or acrylic A light-transmitting material, such as a film, is used.

[0347] Furthermore, in addition to inert gases such as nitrogen and argon, UV-curable resin can also be used as the filler 4507. Oils or thermosetting resins can be used, such as PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used. For example, nitrogen can be used as a filler. That's all you need to do.

[0348] Furthermore, if necessary, a polarizing plate or circular polarizing plate (including elliptical polarizing plate) may be placed on the emission surface of the light-emitting element. You may also appropriately incorporate optical films such as phase difference plates (λ / 4 plate, λ / 2 plate) and color filters. Furthermore, an anti-reflective coating may be provided on the polarizing plate or circular polarizing plate. For example, by the surface irregularities An anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0349] The signal line drive circuits 4503a and 4503b, and the scan line drive circuits 4504a and 4504b are Drive turns formed by a single-crystal semiconductor film or polycrystalline semiconductor film on a separately prepared substrate It may be implemented in the circuit. Also, only the signal line drive circuit, or part of it, or the scan line drive circuit The road may be formed separately or partially, and the configuration is not limited to that shown in Figure 11.

[0350] Through the above process, a highly reliable light-emitting display device (display panel) is manufactured as a semiconductor device. It is possible.

[0351] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0352] (Embodiment 12) The semiconductor device disclosed herein can be used as electronic paper. PA can be used in electronic devices in any field that displays information. For example, using e-paper, e-books, posters, and trains This can be applied to in-vehicle advertisements for goods, displays on various cards such as credit cards, etc. An example of an electronic device is shown in Figure 20.

[0353] Figure 20 shows the e-book 2700. For example, the e-book 2700 has a casing 2701 It consists of two enclosures, and enclosure 2703. Enclosures 2701 and 2703 are It is integrated with the shaft portion 2711, and the shaft portion 2711 is used as the axis for opening and closing operations. This configuration allows it to function like a physical book.

[0354] The display unit 2705 is incorporated into the housing 2701, and the display unit 2707 is incorporated into the housing 2703. It is included. Display units 2705 and 2707 are configured to display a continuation screen. Alternatively, a configuration that displays different screens is also acceptable. For example, text is displayed on the right-hand display unit (display unit 2705 in Figure 20), and the left-hand display unit An image can be displayed on the display unit 2707 in Figure 20.

[0355] Furthermore, Figure 20 shows an example in which the housing 2701 is equipped with an operating unit, etc. For example, housing 2 Unit 701 is equipped with a power supply 2721, operation keys 2723, speaker 2725, and the like. The page can be turned using operation key 2723. Note that the key is located on the same side as the display unit of the casing. It may also be configured to include a board or pointing device. Furthermore, the back of the enclosure or On the side, there are external connection terminals (earphone jack, USB terminal, or AC adapter and USB A configuration that includes terminals that can connect to various cables such as cables, a recording medium insertion section, and so on. It may also be done this way. Furthermore, the eBook 2700 is configured to have the functionality of an electronic dictionary. That's fine.

[0356] Furthermore, the e-book 2700 may be configured to transmit and receive information wirelessly. By wireless means, The system will be configured to allow users to purchase and download desired book data from an e-book server. It is also possible.

[0357] (Embodiment 13) The semiconductor devices disclosed herein are applicable to a variety of electronic devices (including amusement machines). This is possible. As an electronic device, for example, a television set (television, or television Receivers (also called receivers), computer monitors, digital cameras, digital video cameras Digital photo frame, mobile phone (also called mobile phone or mobile phone device), portable Examples include game consoles, personal digital assistants, audio playback devices, and large game machines such as pachinko machines. ru.

[0358] Figure 21(A) shows the television equipment 9600. The television equipment 9600 is The display unit 9603 is incorporated into the housing 9601. The display unit 9603 displays images. It is possible to demonstrate this. Furthermore, here, the stand 9605 supports the housing 9601. This shows the configuration.

[0359] The television unit 9600 is operated using the control switches on the housing 9601 and a separate remote control. This can be done using the control unit 9610. The remote control unit 9610 has control keys The 9609 allows you to control the channel and volume, and the information is displayed on the display unit 9603. The video can be controlled. Furthermore, the remote control unit 9610 can be controlled by the remote control unit. A display unit 9607 may be provided to display the information output from 9610.

[0360] The television system 9600 will consist of a receiver, modem, and other components. It can receive more general television broadcasts, and furthermore, it can connect via a modem, either wired or wirelessly. By connecting to the communication network, one-way (sender to receiver) or two-way communication is possible. It is also possible to communicate information (between a sender and a receiver, or between receivers, etc.).

[0361] Figure 21(B) shows the digital photo frame 9700. For example, a digital photo The frame 9700 has a display unit 9703 incorporated into the housing 9701. 03 can display various images, such as images taken with a digital camera. By displaying image data, it can function just like a regular picture frame.

[0362] The Digital Photo Frame 9700 includes an operating unit and external connection terminals (USB terminal, USB port). A structure that includes terminals that can connect to various cables such as B cables, a recording medium insertion section, etc. These components may be incorporated on the same surface as the display unit, but may also be on the sides or back. It's desirable to include it because it improves the design. For example, the 9700 digital photo frame. Insert a memory device containing image data taken with a digital camera into the recording medium insertion slot. Image data can be captured and displayed on the display unit 9703. ru.

[0363] Furthermore, the digital photo frame 9700 may be configured to send and receive information wirelessly. It is also possible to configure the system to acquire and display desired image data wirelessly.

[0364] Figure 22(A) shows a portable gaming machine, which consists of two cabinets, cabinet 9881 and cabinet 9891. It is connected by a connecting part 9893 so that it can be opened and closed. The housing 9881 has a display unit The 9882 is incorporated, and the display unit 9883 is incorporated into the housing 9891. The portable gaming machine shown in 22(A) also includes a speaker section 9884 and a recording medium insertion section 988 6. LED lamp 9890, input means (operation key 9885, connection terminal 9887, sensor 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, Chemical substances, sound, time, hardness, electric field, electric current, voltage, power, radiation, flow rate, humidity, gradient, vibration Equipped with a function to measure motion, odor, or infrared radiation, a microphone (9889), etc. Of course, the configuration of portable gaming machines is not limited to those described above, and at least in this specification. Any configuration that includes the semiconductor device disclosed herein, and other auxiliary equipment as appropriate, is acceptable. This can be done. The portable gaming machine shown in Figure 22(A) has the data recorded on the recording medium. Functions for reading programs or data and displaying them on the display unit, and wireless communication with other portable gaming machines. It has the function of sharing information by doing so. The functions are not limited to these, and it can have a variety of functions.

[0365] Figure 22(B) shows the large-scale gaming machine, slot machine 9900. The 9900 has a display unit 9903 integrated into the casing 9901. Also, a slot machine... The 9900 also features other operating mechanisms such as a start lever and stop switch, and a coin slot. It is equipped with speakers, etc. Of course, the configuration of the slot machine 9900 is as described above. Not limited to, but including any configuration comprising at least one semiconductor device as disclosed herein, The configuration may include other auxiliary equipment as appropriate.

[0366] Figure 23(A) is a perspective view showing an example of a portable computer.

[0367] The portable computer in Figure 23(A) is constructed by connecting the upper casing 9301 and the lower casing 9302. The hinge unit is in the closed position, and the upper housing 9301 has a display unit 9303, and the keyboard The lower housing 9302, which has code 9304, can be stacked on top of each other, making it easy to carry. This is convenient, and when the user is typing on the keyboard, the hinge unit can be opened. Therefore, input operations can be performed by looking at the display unit 9303.

[0368] In addition, the lower casing 9302 houses the keyboard 9304 and a pointing device for input operations. It has a chair 9306. Also, if the display unit 9303 is a touch input panel, one of the display units Input operations can also be performed by touching the part. In addition, the lower chassis 9302 contains the CPU and hardware. It has a processing unit such as a disk. Furthermore, the lower enclosure 9302 can be used with other devices, for example, U It has an external connection port 9305 into which a communication cable compliant with SB's communication standards is plugged in. Yes, they are.

[0369] The upper housing 9301 also contains a display unit 93 which can be slid and stored inside the upper housing 9301. It has 07, which enables a large display screen. It also has a retractable display unit 93 The user can adjust the orientation of the 07 screen. Additionally, the retractable display unit 9307 can be used for touch input. If it's a panel, input operations can also be performed by touching a part of the retractable display.

[0370] The display unit 9303 or the retractable display unit 9307 is a liquid crystal display panel, an organic light-emitting element, or This uses an image display device such as an inorganic light-emitting element or other light-emitting display panel.

[0371] Furthermore, the portable computer shown in Figure 23(A) is configured to include a receiver and other components, and can also function as a television. The system can receive broadcasts and display the video on display unit 9303 or display unit 9307. Furthermore, the hinge unit connecting the upper housing 9301 and the lower housing 9302 is left in the closed position. Well, you slide the display unit 9307 to expose the entire screen, and then adjust the screen angle so that the user can Television broadcasts can also be viewed. In this case, the hinge unit is in the open position and the display unit 9 To avoid displaying 303 and to activate only the circuit that displays the television broadcast, It can consume minimal power, making it suitable for portable computers with limited battery capacity. It is useful in that context.

[0372] Furthermore, Figure 23(B) shows a portable device that can be worn on the user's wrist like a wristwatch. This is a perspective illustrating one example of the story.

[0373] This mobile phone includes a communication device having at least telephone functionality and a main unit having a battery, A band portion 9204 for attaching the body to the arm, and the state of fixation of the band portion 9204 to the arm. The system consists of a control unit 9205, a display unit 9201, a speaker 9207, and a microphone 9208. It has been done.

[0374] The main unit also has an operation switch 9203, a power input switch, and a display switching switch. In addition to the start-up switch for imaging, for example, pressing a switch will activate an internet program. Each function can be associated with a specific event, such as when a particular function is activated.

[0375] Input operations on this mobile phone are performed by touching the display unit 9201 with a finger or input pen, or by operating it. This is done by operating switch 9203 or by voice input to microphone 9208. In 23(B), the display button 9202 displayed on the display unit 9201 is shown, and a finger Input can be performed by touching the screen.

[0376] Furthermore, the main unit is an imaging device that converts the image of the subject formed through the imaging lens into an electronic image signal. It has a camera section 9206 with a step. However, the camera section is not required.

[0377] Furthermore, the mobile phone shown in Figure 23(B) is configured to include a television broadcast receiver, etc. It can receive TV broadcasts and display the images on the display unit 9201, and furthermore, it can store memory and other data. With a configuration that includes a storage device, television broadcasts can be recorded into memory. Also, Figure 23( The mobile phone shown in B) may have a function that can collect location information such as GPS.

[0378] The display unit 9201 is a light-emitting display panel such as a liquid crystal display panel, an organic light-emitting element, or an inorganic light-emitting element. A video display device such as a NEL is used. The mobile phone shown in Figure 23(B) is small and lightweight. Therefore, the battery capacity is limited, and the display device used in the display unit 9201 is low power consumption. It is preferable to use a panel that can be driven by force.

[0379] Note that Figure 23(B) illustrates an electronic device that is worn on the "arm," but it is not particularly limited to this. In short, it just needs to be something that can be carried around.

[0380] (Embodiment 14) In this embodiment, as one form of a semiconductor device, the thin film transient shown in Embodiments 1 to 4 Examples of display devices having a sta will be described with reference to Figures 24 to 37. This embodiment is a display An example of a liquid crystal display device using liquid crystal elements as components will be explained with reference to Figures 24 to 37. The TFTs 628 and 629 used in the liquid crystal display devices shown in Figures 24 to 37 are from Embodiment 1 to A thin-film transistor as shown in 4 can be applied, and the process is the same as shown in Embodiments 1 to 4. It is a thin-film transistor with electrical characteristics and high reliability that can be fabricated. The TFT628 is a channel The TFT629 has a channel protection layer 608 and a channel protection layer 611, respectively, and is an oxide semiconductor. This is an inverse staggered thin-film transistor in which the layer is used as the channel formation region.

[0381] First, we will explain VA (Vertical Alignment) type liquid crystal display devices. A VA-type liquid crystal display device is a type of method that controls the arrangement of liquid crystal molecules in a liquid crystal display panel. Yes, there is. VA-type liquid crystal display devices have a liquid crystal component on the panel surface when no voltage is applied. This is a method in which the child faces vertically. In this embodiment, in particular, several pixels are used. It is designed to divide the image into regions (subpixels) and tilt the molecules in a different direction for each region. This is called multi-domainization or multi-domain design. In the following explanation, multi-domain This section describes a liquid crystal display device that takes design considerations into account.

[0382] Figures 25 and 26 show the pixel electrode and counter electrode, respectively. Figure 25 shows the pixel This is a plan view of the substrate side on which the electrodes are formed, and the cross-sectional structure corresponding to the cutting line EF shown in the figure is This is shown in Figure 24. Figure 26 is a plan view of the substrate side where the counter electrodes are formed. The explanation will be explained using these diagrams.

[0383] Figure 24 shows the TFT 628, the pixel electrode layer 624 connected to it, and the holding capacitance section 630. The formed substrate 600 and the opposing substrate 601 on which the opposing electrode layer 640 etc. are formed are superimposed. This indicates that the liquid crystal has been injected.

[0384] A colored film 636 and a counter electrode layer 640 are formed on the opposing substrate 601, and on the counter electrode layer 640 A protrusion 644 is formed thereon. An alignment film 648 is formed on the pixel electrode layer 624, similarly. An orientation film 646 is also formed on the counter electrode layer 640 and the protrusion 644. A liquid crystal layer 650 is formed between the opposing substrates 601.

[0385] On the substrate 600 are a TFT 628, a pixel electrode layer 624 connected to it, and a holding capacitance section 6 30 is formed. The pixel electrode layer 624 consists of a TFT 628, wiring 616, and a holding capacitance portion 6 Contacts that penetrate the insulating film 620 covering 30 and the insulating film 622 covering the insulating film 620, respectively The TFT 628 is connected to the wiring 618 at the hole 623. The TFT 628 is thin as shown in Embodiments 1 to 4. A film transistor can be used as appropriate. Also, the retaining capacitance section 630 is a TFT628 The first capacitive wiring 604 formed simultaneously with the gate wiring 602, the gate insulating film 606, and It consists of a second capacitive wiring 617 formed simultaneously with lines 616 and 618.

[0386] The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 overlap, forming the shape of the liquid crystal element. It has been done.

[0387] Figure 25 shows the planar structure on the substrate 600. The pixel electrode layer 624 is made of the material shown in Embodiment 1. It is formed using [a certain method]. A slit 625 is provided in the pixel electrode layer 624. The slit 625 is liquid This is for controlling the orientation of the crystals.

[0388] The TFT 629 shown in Figure 25, the pixel electrode layer 626 connected thereto, and the holding capacitance unit 631 are, Each of these can be formed in the same manner as the TFT628, the pixel electrode layer 624, and the holding capacitance section 630. Yes, it is. Both the TFT628 and TFT629 are connected to wiring 616. This LCD display A pixel in Nell is composed of a pixel electrode layer 624 and a pixel electrode layer 626. Pixel electrode layers 624 and 626 are subpixels.

[0389] Figure 26 shows the planar structure on the opposing substrate side. The opposing electrode layer 640 is formed on the light-shielding film 632. The counter electrode layer 640 is preferably formed using the same material as the pixel electrode layer 624. Furthermore, protrusions 644 that control the orientation of the liquid crystal are formed on the counter electrode layer 640. Figure 26 shows the pixel electrode layers 624 and 626 formed on the substrate 600, indicated by dashed lines. The opposing electrode layer 640 and the pixel electrode layer 624 and pixel electrode layer 626 are arranged to overlap. This shows the state of being.

[0390] The equivalent circuit of this pixel structure is shown in Figure 27. Both TFT628 and TFT629 have gate configurations. It is connected to wire 602 and wiring 616. In this case, the power of capacitive wiring 604 and capacitive wiring 605 By changing their positions, the operation of liquid crystal elements 651 and 652 can be made different. In other words, by individually controlling the potential of capacitive wiring 604 and capacitive wiring 605, liquid crystals can be formed. The field of view is widened by precisely controlling the orientation of the elements.

[0391] When a voltage is applied to the pixel electrode layer 624 with the slit 625, near the slit 625... This generates distortion of the electric field (oblique electric field). This slit 625 and the protrusion on the opposing substrate 601 side By arranging 644 and other elements in an alternating interlocking manner, a diagonal electric field is effectively generated, resulting in a liquid crystal. By controlling the orientation, the direction in which the liquid crystals align varies depending on the location. That is, The multi-domain architecture widens the viewing angle of the LCD display panel.

[0392] Next, a VA-type liquid crystal display device, different from the one described above, will be explained using Figures 28 to 31. ru.

[0393] Figures 28 and 29 show the pixel structure of a VA-type liquid crystal display panel. Figure 29 shows the substrate 600 This is a plan view, and Figure 28 shows the cross-sectional structure corresponding to the cutting line YZ shown in the figure.

[0394] This pixel structure has multiple pixel electrodes for each pixel, and a TFT is in contact with each pixel electrode. It continues. Each TFT is configured to be driven by a different gate signal. In a multi-domain designed pixel, the signals applied to each pixel electrode are independently It has a configuration that controls it.

[0395] The pixel electrode layer 624 has contact holes that penetrate the insulating film 620 and the insulating film 622, respectively. In the line 623, it is connected to the TFT 628 by wiring 618. Also, the pixel electrode layer 62 6 is located in the contact holes 627 that penetrate the insulating film 620 and the insulating film 622, respectively. It is connected to the TFT629 with wiring 619. The gate wiring 602 of the TFT628, The gate wiring 603 of the TFT629 can be divided to allow different gate signals to be applied. They are separated. Meanwhile, wiring 616, which functions as a data line, connects TFT628 and TFT62 It is commonly used in 9. TFT628 and TFT629 are thin as shown in Embodiments 1 to 4. Film transistors can be used as appropriate. Note that gate wiring 602 and gate wiring 603 Furthermore, a gate insulating film 606 is formed on the capacitive wiring 690.

[0396] The shapes of the pixel electrode layer 624 and the pixel electrode layer 626 are different, with the pixel electrode layer spreading out in a V-shape. A pixel electrode layer 626 is formed to surround the outside of 624. Pixel electrode layer 624 and pixel By making the voltage applied to the electrode layer 626 different for TFT628 and TFT629, This controls the orientation of the liquid crystal. The equivalent circuit of this pixel structure is shown in Figure 31. The TFT628 is TFT629 is connected to gate wiring 603, and T Both the FT628 and TFT629 are connected to wiring 616. Gate wiring 602 and gate By applying different gate signals to the wiring 603, the movement of liquid crystal elements 651 and 652 is controlled. The operation can be made different. That is, the operation of TFT628 and TFT629 can be controlled individually. By doing so, the alignment of the liquid crystals in liquid crystal elements 651 and 652 is precisely controlled to control the field of view. The corners can be widened.

[0397] A colored film 636 and a counter electrode layer 640 are formed on the opposing substrate 601. A planarization film 637 is formed between 636 and the counter electrode layer 640 to prevent the alignment of the liquid crystal. Figure 30 shows the planar structure on the opposing substrate side. The opposing electrode layer 640 is common across different pixels. The electrode is formed with a slit 641. The elementary electrode layer 624 and the slit 625 on the pixel electrode layer 626 side are arranged to interlock alternately. By doing so, a diagonal electric field can be effectively generated to control the orientation of the liquid crystal. This allows the orientation of the liquid crystal to vary depending on the location, thereby widening the viewing angle. Note that in Figure 30, the pixel electrode layers 624 and 626 formed on the substrate 600 are indicated by dashed lines. As shown, the opposing electrode layer 640 and the pixel electrode layer 624 and pixel electrode layer 626 are arranged to overlap. This shows how it is placed.

[0398] An alignment film 648 is formed on the pixel electrode layer 624 and the pixel electrode layer 626, and similarly the counter electrode An alignment film 646 is also formed on layer 640. A liquid crystal is formed between substrate 600 and opposing substrate 601. Layer 650 is formed. Also, the pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 The overlapping of these elements forms the first liquid crystal element. Furthermore, the pixel electrode layer 626 and the liquid crystal... The second liquid crystal element is formed by the overlapping of layer 650 and the counter electrode layer 640. (Figure) The pixel structure of the display panel described in Figures 28 to 31 is such that each pixel contains a first liquid crystal element and a second liquid crystal element. It has a multi-domain structure with crystal elements.

[0399] Next, we will describe a transverse electric field type liquid crystal display device. In the transverse electric field type, the liquid crystal molecules within the cell This method drives the liquid crystal by applying an electric field in the horizontal direction to express gradation. This allows the field of view to be expanded to approximately 180 degrees. The following explanation uses a transverse electric field method. The liquid crystal display device used will be described below.

[0400] Figure 32 shows the shape of the electrode layer 607, TFT 628, and the pixel electrode layer 624 connected to the TFT 628. This shows the completed substrate 600 and the opposing substrate 601 superimposed, with liquid crystal injected. A colored film 636, a planarization film 637, etc., are formed on the opposing substrate 601. No opposing electrodes are provided on the opposing substrate 601 side. Also, between substrate 600 and opposing substrate 601 A liquid crystal layer 650 is formed on top of this via alignment films 646 and 648.

[0401] On the substrate 600 are an electrode layer 607 and capacitive wiring 604 connected to the electrode layer 607, and T FT628 is formed. The electrode layer 607 is the pixel electrode layer 427 shown in Embodiments 1 to 4. Similar materials can be used. Capacitive wiring 604 is the gate wiring 602 of TFT628. It can be formed at the same time. As for TFT628, the thin as shown in Embodiments 1 to 5 A film transistor can be applied. The electrode layer 607 is divided into roughly pixel-like sections. It is formed as follows. Furthermore, a gate insulating film 606 is formed on the electrode layer 607 and the capacitance wiring 604. It can be done.

[0402] The wiring 616 and wiring 618 of the TFT628 are formed on the gate insulating film 606. 6 is a data line in an LCD display panel that carries video signals and is a unidirectional wiring. At the same time, it connects to the source or drain area of ​​the TFT628, and the source and drain It becomes one electrode. Wiring 618 becomes the other electrode of the source and drain, and the pixel electrode layer This is the wiring that connects to 624.

[0403] An insulating film 620 is formed on wiring 616 and wiring 618. In addition, an insulating film is formed on the insulating film 620. In the contact hole formed in the edge film 620, the pixel electrode layer 6 is connected to the wiring 618. 24 is formed. The pixel electrode layer 624 is made of the same material as the pixel electrode layer shown in Embodiment 1. To use and form.

[0404] In this way, the TFT 628 and the pixel electrode layer 624 connected to it are formed on the substrate 600. The retention capacity is formed between the electrode layer 607 and the pixel electrode layer 624.

[0405] Figure 33 is a plan view showing the configuration of the pixel electrode. The section corresponding to the cutting line OP shown in Figure 33 The surface structure is shown in Figure 32. A slit 625 is provided in the pixel electrode layer 624. The 625 is for controlling the orientation of the liquid crystal. In this case, the electric field is between the electrode layer 607 and It occurs between the pixel electrode layer 624. Gate insulation is present between electrode layer 607 and pixel electrode layer 624. A film 606 is formed, but the thickness of the gate insulating film 606 is 50-200 nm, 2 Since it is sufficiently thin compared to the thickness of the liquid crystal layer, which is approximately 10 μm, it is practically parallel to the substrate 600. An electric field is generated in the horizontal direction. This electric field controls the orientation of the liquid crystal. By using an electric field in a nearly parallel direction, the liquid crystal molecules are rotated horizontally. In this case, which Because it remains horizontal even in this state, the influence of contrast and other factors depending on the viewing angle is minimal, resulting in a wide viewing angle. This will result in... Also, since both electrode layer 607 and pixel electrode layer 624 are light-transmitting electrodes... This can improve the aperture ratio.

[0406] Next, we will show another example of a transverse electric field type liquid crystal display device.

[0407] Figures 34 and 35 show the pixel structure of an IPS-type liquid crystal display device. Figure 35 is a plan view. Yes, and the cross-sectional structure corresponding to the cutting line VW shown in the figure is shown in Figure 34. This will be explained by referring to these two figures.

[0408] Figure 34 shows a substrate 600 on which a TFT 628 and a pixel electrode layer 624 connected thereto are formed, This shows the state after the opposing substrate 601 has been placed on top and liquid crystal has been injected. A colored film 636, a planarization film 637, etc., are formed on the opposing substrate 601 side. No poles are provided. Between the substrate 600 and the opposing substrate 601, there is an alignment film 646 and an alignment film 6 A liquid crystal layer 650 is formed via 48.

[0409] A common potential line 609 and a TFT 628 are formed on the substrate 600. 9 can be formed simultaneously with the gate wiring 602 of the TFT628. Therefore, the thin-film transistors shown in Embodiments 1 to 4 can be applied.

[0410] The wiring 616 and wiring 618 of the TFT628 are formed on the gate insulating film 606. 6 is a data line in an LCD display panel that carries video signals and is a unidirectional wiring. At the same time, it connects to the source or drain area of ​​the TFT628, and the source and drain It becomes one electrode. Wiring 618 becomes the other electrode of the source and drain, and the pixel electrode layer This is the wiring that connects to 624.

[0411] An insulating film 620 is formed on wiring 616 and wiring 618. In addition, an insulating film is formed on the insulating film 620. Pixel electrical signals connected to wiring 618 via contact holes 623 formed in the edge film 620 A polar layer 624 is formed. The pixel electrode layer 624 is similar to the pixel electrode layer shown in Embodiment 1. It is formed using materials. As shown in Figure 35, the pixel electrode layer 624 is connected to a common potential line 6 The comb-shaped electrodes formed simultaneously with 09 are formed to generate a transverse electric field. Also, the pixel electrodes The comb-shaped portions of layer 624 interlock alternately with the comb-shaped electrodes formed simultaneously with the common potential line 609. It is formed in this way.

[0412] When an electric field is generated between the potential applied to the pixel electrode layer 624 and the potential of the common potential line 609, This electric field controls the orientation of the liquid crystal. The liquid crystal is formed using an electric field approximately parallel to the substrate. Rotate the molecules horizontally. In this case, since the liquid crystal molecules are horizontal in any state, the viewing angle... The impact on contrast and other factors is minimal, resulting in a wider viewing angle.

[0413] In this way, the TFT 628 and the pixel electrode layer 624 connected to it are formed on the substrate 600. The retention capacitance is achieved by providing a gate insulating film 606 between the common potential line 609 and the capacitive electrode 615. , thereby forming the capacitive electrode 615 and the pixel electrode layer 624 in contact hole 63 It is connected via 3.

[0414] Next, we will describe the configuration of TN-type liquid crystal display devices.

[0415] Figures 36 and 37 show the pixel structure of a TN-type liquid crystal display device. Figure 37 is a plan view. Figure 36 shows the cross-sectional structure corresponding to the cutting line KL shown in the figure. This explanation will be given with reference to these two figures.

[0416] The pixel electrode layer 624 is connected to the TFT 628 by wiring 618 via contact holes 623. The wiring 616, which functions as a data line, is connected to the TFT628. 28 can be any of the TFTs shown in Embodiments 1 to 4.

[0417] The pixel electrode layer 624 is formed using the pixel electrode layer shown in Embodiment 1. Capacitive wiring 604 can be formed simultaneously with the gate wiring 602 of the TFT628. Gate wiring 6 A gate insulating film 606 is formed on 02 and the capacitance wiring 604. The retained capacitance is the capacitance wiring A gate insulating film 606 is formed between 604 and the capacitive electrode 615. 5 and the pixel electrode layer 624 are connected via a contact hole 623.

[0418] A colored film 636 and a counter electrode layer 640 are formed on the opposing substrate 601. A planarization film 637 is formed between 636 and the counter electrode layer 640 to prevent the alignment of the liquid crystal. The liquid crystal layer 650 has an alignment film 648 and an alignment film between the pixel electrode layer 624 and the counter electrode layer 640. It is formed via film 646.

[0419] The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 overlap, forming the shape of the liquid crystal element. It has been done.

[0420] Furthermore, the colored film 636 may also be formed on the substrate 600 side. A polarizing plate is attached to the side opposite to the side where the transistor is formed, and the opposing substrate 601 A polarizing plate is attached to the side opposite to the side where the counter electrode layer 640 is formed.

[0421] Through the above steps, a liquid crystal display device can be manufactured as a display device. (Embodiment) This liquid crystal display device is a liquid crystal display device with a high aperture ratio.

[0422] (Embodiment 15) In this embodiment, an example of a process with fewer steps and photomasks than that of Embodiment 1 is shown. This is shown in Figures 39(A) to 39(D). Figures 39(A) to 39(D) are the same as Figures 1 to 3. Since they are the same except for some differences in the process, the same symbols are used for the same parts, and the same parts are detailed I will omit the detailed explanation.

[0423] First, according to Embodiment 1, a translucent conductive film is applied to a substrate 400 having an insulating surface. After formation, gate electrode layers 411 and 421 are formed by a first photolithography process. ru.

[0424] Next, the first gate insulating layer 402a and the second gate insulating layer 402a are placed on the gate electrode layers 411 and 421. A stack of gate insulating layers 402b is formed.

[0425] Next, an oxide semiconductor film with a thickness of 2 nm to 200 nm is placed on the second gate insulating layer 402b. It forms a body membrane 430 (see Figure 39(A)). Note that Figure 39(A) is the same as Figure 2(A). That is the case.

[0426] Next, the oxide semiconductor film 430 is transformed into island-shaped oxide semiconductors by a second photolithography process. Process into layers.

[0427] Dehydration or dehydrogenation of island-shaped oxide semiconductor layers is performed. The heat treatment temperature shall be 350°C or higher and below the strain point of the substrate, preferably 400°C or higher. Here, a substrate is introduced into an electric furnace, which is one of the heat treatment devices, and nitrogen is applied to the oxide semiconductor layer. After heat treatment in an ambient atmosphere, water is added to the oxide semiconductor layer without exposure to air. This prevents the re-imposition of hydrogen and obtains oxide semiconductor layers 431 and 432 (see Figure 39(B)). Oh, the steps up to this point are the same as in Embodiment 1, and Figure 39(B) is the same as Figure 2(B). be.

[0428] Next, a metal conductive layer is placed on the second gate insulating layer 402b and the oxide semiconductor layers 431 and 432. After forming the film, a third photolithography step is performed to create resist masks 445a and 44 5b is formed, and selective etching is performed to form the source electrode layer 415a and the drain electrode layer Form 415b. By using resist masks 445a and 445b, the implementation The resist masks 433a and 433b in the morphology can be omitted.

[0429] Next, using the resist masks 445a and 445b, a portion of the oxide semiconductor layer is used. Thinning the material creates an oxide semiconductor layer 437 having grooves (recesses) (see Figure 39(C)). However, even without forming grooves (recesses) in the oxide semiconductor layer, the thin-film transistor can switch. If the element is to function as an etching element, this etching process may not be necessary.

[0430] Next, the resist masks 445a and 445b are removed, and the process moves to the fourth photolithography step. A resist mask 438 is formed to further cover the oxide semiconductor layer 437, and the oxide semiconductor layer 432 Remove the upper metal electrode layer 435 (see Figure 39(D)). Selective etching is performed. Therefore, by using an alkaline etchant, the state shown in Figure 39(D) can be obtained. The material for the metal conductive film is an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W. Alternatively, there are alloys containing the aforementioned elements, or alloys combining the aforementioned elements. In this embodiment, a Ti film is used as the metallic conductive film, and oxide semiconductor layers 431 and 432 are used. This uses an In-Ga-Zn-O oxide semiconductor film, with ammonia peroxide as the etchant. Use water (a mixture of ammonia, water, and hydrogen peroxide).

[0431] In order to maintain an amorphous state, the oxide semiconductor layer is preferably made with a thickness of 50 nm or less. In particular, channel etch type thin-film transistors are further etched, resulting in a thinner film thickness. The thickness of the channel-forming region, i.e., the channel-forming region, becomes 30 nm or less, and the final fabricated thin film The film thickness in the thin region of the lunger should be between 5 nm and 20 nm.

[0432] Furthermore, the channel width of the final fabricated thin-film transistor was between 0.5 μm and 10 μm. It is preferable to do so.

[0433] The subsequent steps are the same as in Embodiment 1, and the steps shown in Figures 3(A) to (E) are performed to create a thin film transient. A st 410 and a thin-film transistor 420 are formed, along with a protective insulating layer 403 and a planar insulating layer. After forming 404, a contact hole is formed that reaches the drain electrode layer 425b, and the pixels An electrode layer 427 and a conductive layer 417 are formed.

[0434] Through the above process, using eight photomasks, thin-film transistors 410 are produced on the same substrate. The thin-film transistor 420 is fabricated separately for the drive circuit or the pixel section. This allows for the assignment of transistors with optimal structures onto the same substrate without increasing the number of manufacturing steps. This allows for the construction of various circuits.

[0435] This embodiment can be freely combined with other embodiments.

[0436] (Embodiment 16) In this embodiment, the number of steps and photomasks are greater than in Embodiments 1 and 15. Examples of fewer steps are shown in Figures 40(A) to (C). Figures 40(A) to (C) are derived from Figures 1 to (C). Since it is the same as Figure 3 except for some differences in the process, the same symbols are used for the same parts. I will omit a detailed explanation of the place.

[0437] First, according to Embodiment 1, a translucent conductive film is applied to a substrate 400 having an insulating surface. After formation, gate electrode layers 411 and 421 are formed by a first photolithography process. ru.

[0438] Next, the first gate insulating layer 402a and the second gate insulating layer 402a are placed on the gate electrode layers 411 and 421. A stack of gate insulating layers 402b is formed.

[0439] Next, an oxide semiconductor film with a thickness of 2 nm to 200 nm is placed on the second gate insulating layer 402b. It forms a body membrane 430 (see Figure 40(A)). Note that Figure 40(A) is the same as Figure 2(A). That is the case.

[0440] Next, the oxide semiconductor film 430 is transformed into island-shaped oxide semiconductors by a second photolithography process. Process into layers.

[0441] Dehydration or dehydrogenation of island-shaped oxide semiconductor layers is performed. The heat treatment temperature shall be 350°C or higher and below the strain point of the substrate, preferably 400°C or higher. Here, a substrate is introduced into an electric furnace, which is one of the heat treatment devices, and nitrogen is applied to the oxide semiconductor layer. After heat treatment in an ambient atmosphere, water is added to the oxide semiconductor layer without exposure to air. This prevents the re-imposition of hydrogen and obtains oxide semiconductor layers 431 and 432 (see Figure 40(B)). Oh, the steps up to this point are the same as in Embodiment 1, and Figure 40(B) is the same as Figure 2(B). be.

[0442] Next, a metal conductive layer is placed on the second gate insulating layer 402b and the oxide semiconductor layers 431 and 432. After forming the film, a third photolithography step is performed to create resist masks 446a and 44 Form 6b and selectively etch the source electrode layer 415a and the drain electrode layer Form 415b and remove the metal conductive film on the oxide semiconductor layer 432 (Figure 40(D)). (See reference.) By using resist masks 446a and 446b, in the embodiment The resist masks 433a, 433b, and 438 can be omitted.

[0443] When the selectivity ratio in etching between the oxide semiconductor layers 431 and 432 and the metal conductive film is high, As shown in Figure 40(C), the oxide semiconductor layers 431 and 432 undergo the etching process of the metal conductive film. This can reduce film loss.

[0444] To selectively etch the material, an alkaline etchant is used, as shown in Figure 40(C). This state can be obtained. Suitable materials for the metal conductive film include Al, Cr, Cu, Ta, and Ti. , elements selected from Mo, W, or alloys containing the above elements, or the above elements There are alloys and the like that which are combined. In this embodiment, a Ti film is used as the metal conductive film, and oxidation In-Ga-Zn-O based oxide semiconductor films are used in the semiconductor layers 431 and 432, and etching is performed. Hydrogen peroxide solution (a mixture of ammonia, water, and hydrogen peroxide solution) is used as the chancre.

[0445] The subsequent steps are the same as in Embodiment 1, and the steps shown in Figures 3(A) to (E) are performed to create a thin film transient. A st 410 and a thin-film transistor 420 are formed, along with a protective insulating layer 403 and a planar insulating layer. After forming 404, a contact hole is formed that reaches the drain electrode layer 425b, and the pixels An electrode layer 427 and a conductive layer 417 are formed.

[0446] Through the above process, using seven photomasks, thin-film transistors 410 are produced on the same substrate. The thin-film transistor 420 is fabricated separately for the drive circuit or the pixel section. This allows for the assignment of transistors with optimal structures onto the same substrate without increasing the number of manufacturing steps. This allows for the construction of various circuits.

[0447] This embodiment can be freely combined with other embodiments.

[0448] (Embodiment 17) In this embodiment, Figure 38 shows an example where the oxide semiconductor layer is surrounded by a nitride insulating film when viewed in cross-section. Figure 38 shows that the top surface shape and edge position of the oxide insulating layer 416 differ from those in Figure 1, and the gate insulating layer Since they are the same except for the difference in the structure of the margins, the same symbols are used for the same locations. Detailed explanations will be omitted.

[0449] The thin-film transistor 410 placed in the drive circuit is a channel-etch type thin-film transistor. There is a gate electrode layer 411 and a nitride insulating film layer on a substrate 400 having an insulating surface. Insulating layer 402, at least channel forming region 413, first high-resistance drain region 41 Oxide semiconductor layer having 4a and a second high-resistance drain region 414b, source electrode layer 4 It includes 15a and the drain electrode layer 415b. It also covers the thin film transistor 410. An oxide insulating layer 416 is provided in contact with the channel formation region 413.

[0450] The oxide insulating layer 416 serves as a channel protection layer for the thin-film transistor 420 placed in the pixel. When forming the oxide insulating layer 426 that functions in a photolithography process, the thin film transient Process the outer gate insulating layer 402 of T410 so that it is exposed. At least oxide insulating The top surface shape of layer 416 is wider than the top surface shape of the oxide semiconductor layer, and thin-film transistor 410 It is preferable to have a top surface shape that covers it.

[0451] Furthermore, a protective insulating layer made of a nitride insulating film covers the upper and side surfaces of the oxide insulating layer 416. Forms 403.

[0452] Furthermore, the first high-resistance drain region 414a self-regulates in contact with the lower surface of the source electrode layer 415a. It is formed in a collectively. In addition, a second high-resistance drain is in contact with the lower surface of the drain electrode layer 415b. The in region 414b is formed in a self-aligned manner. In addition, the channel-forming region 413 is acid It is in contact with the oxide insulating layer 416 and has a thin film thickness, and is the first high-resistance drain region 414 a is defined as a region with higher resistance than the second high-resistance drain region 414b (Type I region).

[0453] Furthermore, the channel formation region 413, the first high-resistance drain region 414a, and the second high-resistance A gate insulating layer 402 made of a nitride insulating film is formed in contact with the lower surface of the drain region 414b. It is being done.

[0454] The protective insulating layer 403, which is made of a nitride insulating film, is a silicon nitride film obtained by sputtering, oxidative nitride Moisture, hydrogen ions, and Oxide in silicon films, aluminum nitride films, aluminum oxide nitride films, etc. H - An inorganic insulating film that does not contain impurities such as these and blocks them from entering from the outside. Use.

[0455] In this embodiment, the protective insulating layer 403, which is made of a nitride insulating film, is an oxide semiconductor layer 41 RF sputtering was used to coat the bottom, top, and sides of part 2 with silicon nitride to a thickness of 100 nm. A base film is provided. In addition, the protective insulating layer 403 is brought into contact with the gate insulating layer 402, which is made of a nitride insulating film. The configuration will be as follows.

[0456] By adopting the structure shown in Figure 38, the manufacturing process after the formation of the protective insulating layer 403 made of a nitride insulating film is performed. In the process, it is possible to prevent the intrusion of moisture from the outside. Also, semiconductor devices, for example Even after the device is completed as a liquid crystal display, it will not be able to prevent moisture from entering from the outside over the long term. This can improve the long-term reliability of the device.

[0457] Similarly, the thin-film transistor 420 also has a protective insulating layer 403 made of a nitride insulating film. , film thickness formed by RF sputtering so as to surround the top and sides of the oxide semiconductor layer 422 A 100 nm silicon nitride film is used. In addition, the protective insulating layer 403 is made of a nitride insulating film. The configuration is such that it is in contact with the insulating layer 402.

[0458] Furthermore, this embodiment shows a configuration in which one thin-film transistor is surrounded by a nitride insulating film, but The configuration is not limited to this, and multiple thin-film transistors may be surrounded by a nitride insulating film, or pixels A configuration in which multiple thin-film transistors are grouped together and surrounded by a nitride insulating film is also possible. The protective insulating layer 403 and gate insulating layer surround the periphery of the pixel area of ​​the active matrix substrate. The configuration should include a region that is in contact with layer 402.

[0459] This embodiment can be freely combined with other embodiments.

Claims

[Claim 1] It has a pixel section having a first thin-film transistor and a pixel electrode on the same substrate, and a drive circuit having a second thin-film transistor, The first thin-film transistor comprises a gate electrode layer on the substrate, a gate insulating layer on the gate electrode layer, an oxide semiconductor layer on the gate insulating layer, a first oxide insulating layer having a region in contact with a part of the oxide semiconductor layer, and a source electrode layer and a drain electrode layer on the oxide semiconductor layer. The gate electrode layer, gate insulating layer, oxide semiconductor layer, source electrode layer, drain electrode layer, first oxide insulating layer, and pixel electrode layer of the first thin-film transistor are each transparent, A semiconductor device wherein the source electrode layer and drain electrode layer of the second thin-film transistor are made of a conductive material that is different from the material of the source electrode layer and drain electrode layer of the first thin-film transistor and has lower resistance than the source electrode layer and drain electrode layer of the first thin-film transistor.

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