Communication device and communication method

Abstract

The present invention provides a communication device that prevents the time relationship between the write start signal and the read start signal of the data input / output device of the communication device from falling outside a predetermined standard. [Solution] A communication device comprising: a first frequency divider circuit that divides a first clock and generates a phase comparison reference signal; a second frequency divider circuit that divides a second clock and generates a phase comparison comparison signal; an abnormality detection circuit that detects an abnormal state of a reference frame signal; a signal generation circuit that generates a signal based on the reference frame signal; and a phase shift detection circuit that detects whether the time relationship between the signal generated by the signal generation circuit and the second frequency divided output signal of the second frequency divider circuit satisfies a predetermined standard, wherein if the phase shift detection result of the phase shift detection circuit indicates that the predetermined standard is not met, the predetermined value is loaded into the first frequency divider circuit, even if the abnormality detection result of the abnormality detection circuit does not indicate the abnormal state.

Description

Technical Field

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[0001] The present invention relates to a communication device and a communication method.

Background Art

[0002] Regarding a DPLL (Digital Phase Locked Loop), the following documents can be cited.

[0003] Patent Document 1 relates to selecting whether a transmission unit uses the clock reproduced by the DPLL or the clock of an oscillator according to the phase difference calculated by the phase comparison unit of the DPLL.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The following analysis is provided by the present inventor.

[0006] After a change in the transient state from abnormal to normal of the clock supplied to the communication device and the reference frame signal, a signal generated based on the reference frame signal, for example, a write start signal (WR (Write Reset) signal) supplied to write received data to the data input / output unit (ES (Elastic Store memory)) of the communication device, and the second divided output of the second divided circuit that is further phase-locked to the first divided output of the first divided circuit phase-locked to the reference frame signal, for example, the time relationship of the read start signal (RR (Read Reset) signal) supplied to read data from the data input / output unit, may rarely become fixed in a state deviated from the expected state.

[0007] Generally, the write start signal and read start signal of a data input / output unit have an allowable interval to ensure the integrity of the data being read. However, if the counter included in the first frequency divider circuit, whose output is input to the phase-locked circuit, deviates from the expected state, the timing of the read start signal generated by the second frequency divider circuit, which is phase-locked to the first frequency divider circuit, will also be shifted. This can result in the time relationship between the write start signal and read start signal of the data input / output unit not meeting the predetermined standard. For example, the time interval between the write start signal and read start signal input to the data input / output unit may fall outside the allowable range. In such cases, the data input / output control for the data input / output unit may not operate normally.

[0008] In other words, even if the reference frame signal supplied to the communication device does not indicate an abnormal state, the time relationship between the signal generated based on the reference frame signal and the second divided output of the second divided circuit, which is phase-synchronized to the first divided output of the first divided circuit, which is loaded with a predetermined value according to the reference frame signal, may not meet a predetermined standard. In such cases, the control of components included in the communication device, for example, the data input / output control for the data input / output device, may not function properly.

[0009] The present invention aims to provide a communication device and a communication method that contribute to preventing the time relationship between a signal generated based on a reference frame signal and the second divided output of a second divided circuit, which is phase-synchronized to the first divided output of a first divided circuit loaded with a predetermined value according to the reference frame signal, from failing to meet a predetermined standard, even when the reference frame signal supplied to the communication device does not indicate an abnormal state. [Means for solving the problem]

[0010] According to a first aspect of the present invention, a first frequency divider circuit that divides a first clock and generates a phase comparison reference signal, into which a predetermined value is loaded according to a reference frame signal, A second frequency divider circuit that divides the second clock to generate a phase comparison signal, A phase synchronization circuit generates the second clock such that the phase comparison reference signal and the phase comparison comparison signal are phase-synchronized, An abnormality detection circuit for detecting an abnormal state of the reference frame signal, A counter load suppression control circuit is provided, which loads the predetermined value into the first frequency divider circuit if the abnormality detection result of the abnormality detection circuit indicates the abnormal state, and suppresses the loading of the predetermined value if the abnormality detection result does not indicate the abnormal state. A signal generation circuit that generates a signal based on the aforementioned reference frame signal, The circuit includes a phase shift detection circuit that detects whether the time relationship between the signal generated by the signal generation circuit and the second divided output signal of the second frequency divider circuit satisfies a predetermined criterion. If the phase shift detection result of the phase shift detection circuit indicates that the predetermined criteria are not met, the counterload suppression control circuit can provide a communication device that loads the predetermined value into the first frequency divider circuit, even if the abnormality detection result of the abnormality detection circuit does not indicate the abnormal state.

[0011] According to a second aspect of the present invention, A first frequency divider circuit that divides a first clock and generates a phase comparison reference signal, into which a predetermined value is loaded according to a reference frame signal, A second frequency divider circuit that divides the second clock to generate a phase comparison signal, The communication device includes a phase synchronization circuit that generates the second clock so that the phase comparison reference signal and the phase comparison comparison signal are phase-synchronized, and is performed by the communication device. An abnormality detection step for detecting an abnormal state of the reference frame signal, A counter load suppression control step is performed, in which, if the abnormality detection result of the abnormality detection step indicates the abnormal state, the predetermined value is loaded into the first frequency divider circuit, and if the abnormality detection result does not indicate the abnormal state, the loading of the predetermined value is suppressed. A signal generation step of generating a signal based on the aforementioned reference frame signal, The step includes detecting whether the time relationship between the signal generated by the signal generation step and the second divided output signal of the second frequency divider circuit satisfies a predetermined criterion, The counter load suppression control step includes a step of loading the predetermined value into the first frequency divider circuit if the phase shift detection result of the phase shift detection step indicates that the predetermined criteria are not met, even if the abnormality detection result of the abnormality detection step does not indicate the abnormal state. [Effects of the Invention]

[0012] According to the present invention, even when the reference frame signal supplied to the communication device does not indicate an abnormal state, it is possible to provide a communication device and a communication method that contribute to preventing the time relationship between a signal generated based on the reference frame signal and the second divided output of a second divided circuit, which is phase-synchronized to the first divided output of a first divided circuit that is loaded with a predetermined value according to the reference frame signal, from failing to meet a predetermined standard. [Brief explanation of the drawing]

[0013] [Figure 1] This block diagram shows an example of the configuration of the communication device related to this disclosure. [Figure 2] This is a block diagram showing an example of the configuration of a conventional communication device. [Figure 3] This figure shows an example of the operation of a conventional communication device under normal conditions. [Figure 4] This figure shows an example of how a conventional communication device operates when it is in an abnormal state. [Figure 5] This block diagram shows an example of the configuration of the communication device related to this disclosure. [Figure 6] This figure shows an example of the operation of the communication device related to this disclosure. [Figure 7] This figure shows an example of the operation of the detection method for the phase shift detection circuit of the communication device according to this disclosure.

Best Mode for Carrying Out the Invention

[0014] In the present disclosure, the drawings may be associated with one or more embodiments. Also, each of the embodiments described below can be combined with other embodiments as appropriate, and the present invention is not limited by each embodiment.

[0015] First, an overview of one embodiment will be described with reference to the drawings. Note that the reference numerals of the drawings appended to this overview are those appended to each element for convenience as an example to assist understanding, and are not intended to limit the present invention to the illustrated aspects. Also, the connection lines between blocks such as the drawings referred to in the following description include both bidirectional and unidirectional ones. For the one-way arrow, it schematically shows the flow of the main signal (data) and does not exclude bidirectionality.

[0016] FIG. 1 is a block diagram showing an example of the configuration of a communication device according to the present disclosure. Referring to FIG. 1, the communication device 200A includes a first frequency division circuit 203, a second frequency division circuit 207, a phase synchronization circuit 210, an abnormality detection circuit 201, a counter load suppression control circuit 202A, a signal generation circuit 208A, and a phase shift detection circuit 310.

[0017] The first frequency division circuit 203 is composed of a circuit including a counter (not shown). A predetermined counter value is loaded according to a reference frame signal (FP (Frame Pulse)) 410, the counter is counted up by a first clock 1502, and a phase comparison reference side signal 450 which is a frequency division signal of the first clock 1502 is generated from the counter value.

[0018] The second frequency division circuit 207 is composed of a circuit including a counter (not shown). The counter is counted up by a second clock 2061, and a phase comparison comparison side signal 460 which is a frequency division signal of the second clock 2061 is generated from the counter value.

[0019] The phase-locking circuit 210 generates a second clock 2061 so that the phase comparison reference signal 450 and the phase comparison comparison signal 460 are phase-locked.

[0020] The anomaly detection circuit 201 detects an abnormal state in the reference frame signal 410, for example, an abnormal state in the reference frame signal 410 caused by a disturbance.

[0021] The counter load suppression control circuit 202A loads a predetermined value into the first frequency divider circuit 203 if the abnormality detection result 420 of the abnormality detection circuit 201 indicates an abnormal state, and suppresses the loading of the predetermined value if the abnormality detection result 420 does not indicate an abnormal state. The loading of the predetermined value into the first frequency divider circuit 203 is performed, for example, by the first frequency divider circuit 203 including a counter and loading the predetermined value into the counter.

[0022] The signal generation circuit 208A generates signal 470A based on the reference frame signal 410.

[0023] The phase shift detection circuit 310 detects whether the time relationship between the signal 470A generated by the signal generation circuit 208A and the second divided output signal 480A of the second frequency divider circuit 207 meets a predetermined criterion. If the predetermined criterion is not met, it is detected as a phase shift.

[0024] If the phase shift detection result 610 of the phase shift detection circuit 310 indicates that it does not meet a predetermined standard, the counter load suppression control circuit 202A loads a predetermined value into the first frequency divider circuit 203, even if the abnormality detection result of the abnormality detection circuit 201 does not indicate an abnormal state.

[0025] In one embodiment of the present invention, the phase shift detection circuit 310 constantly monitors the time relationship between signal 470A and the second divided output signal 480A of the second frequency divider circuit 207. If a predetermined criterion is not met, the suppression of the load on the counter of the first frequency divider circuit 203 by the counter load suppression control circuit 202A is released. As a result, even if the first frequency divider circuit 203 deviates from the expected state and the second frequency divider circuit 207 also deviates in sync, the first frequency divider circuit 203 can be counterloaded and reset to the correct state. As a result, the phase of the second divided output signal 480A of the second frequency divider circuit 207, which is phase-synchronized with the first frequency divider circuit 203, can be returned to a normal state.

[0026] According to one embodiment of the present invention, even when the reference frame signal supplied to the communication device does not indicate an abnormal state, it is possible to provide a communication device and a communication method that contribute to preventing the time relationship between a signal generated based on the reference frame signal and the second divided output of a second divided circuit which is phase-synchronized to the first divided output of a first divided circuit which is loaded with a predetermined value according to the reference frame signal from failing to meet a predetermined standard.

[0027] [First Embodiment] Next, the first embodiment will be described in detail with reference to the drawings. First, an example of the configuration and operation of a conventional communication device will be described with reference to the drawings. Figure 2 is a block diagram showing an example of the configuration of a conventional communication device. Figure 3 is a diagram showing an example of the operation of a conventional communication device in a normal state. Figure 4 is a diagram showing an example of the operation of a conventional communication device in an abnormal state.

[0028] A conventional communication device (clock supply device) 200, as an example, includes an abnormality detection circuit 201, a counter load suppression control circuit 202, a first frequency divider circuit 203, a second frequency divider circuit 207, a phase synchronization circuit 210, a write reset signal (WR) generation circuit 208, a data input / output section 209, and the phase synchronization circuit 210. The phase synchronization circuit 210 includes a phase comparator 204, a low-pass filter (LPF) 205, and a voltage-controlled oscillator (VCO) 206.

[0029] In the conventional communication device 200, a reference frame signal (FP (Frame Pulse)) 410 is supplied from the clock source 101 of the clock supply device 100. In addition, a clock 102 is supplied from the clock source 101 of the clock supply device 100 to the data output device 150, and the data output device 150 supplies input data 430 and a first clock 1502 according to the clock 102 to the communication device 200.

[0030] [Basic operation of each part of the conventional communication device 200] First, the basic operation of each part of the conventional communication device 200 will be outlined. The first frequency divider circuit 203 includes, for example, a counter (not shown), and a predetermined value is loaded into the counter at a timing corresponding to the reference frame signal (FP) 410, and the counter divides the first clock 1502. The second frequency divider circuit 207 includes, for example, a counter (not shown), and divides the second clock 2061.

[0031] The phase-locked circuit 210 includes a phase comparator 204, an LPF 205, and a VCO 206. The phase comparator 204 compares the phase of the phase comparison reference signal 450 of the first frequency divider 203 and the phase comparison comparison signal 460 of the second frequency divider 207 to generate a phase difference signal 2041, which is output to the LPF 205. The phase difference signal 2041 that has passed through the LPF 205 is supplied to the VCO 206 as a control signal 2051 for the VCO 206. The VCO 206 outputs a second clock 2061 with a frequency according to the control signal 2051. The second clock 2061 output by the VCO 206 is divided by the second frequency divider 207, which generates a phase comparison comparison signal 460 and a readout start signal 480.

[0032] The second frequency divider circuit 207 and the phase-locked circuit 210 form a phase-locked loop (PLL), and the frequency of the second clock 2061 is controlled so that the phase comparison reference signal 450 of the first frequency divider circuit 203 and the phase comparison comparison signal 460 of the second frequency divider circuit 207 are phase-locked.

[0033] [Normal operation of conventional communication device 200] Figure 3 shows an example of the normal operation of a conventional communication device.

[0034] The anomaly detection circuit 201 detects an abnormal state in the reference frame signal 410. The anomaly detection circuit 201 supplies an anomaly detection result 420, indicating whether the reference frame signal 410 is in an abnormal state, to the counter load suppression control circuit 202.

[0035] If the abnormality detection result 420 of the reference frame signal 410 indicates a normal state, the counter load suppression control circuit 202 supplies a counter load suppression signal 440 indicating a suppression state to the first frequency divider circuit 203, thereby suppressing the loading of a predetermined value into the counter at the timing of the reference frame signal 410. When the counter load is suppressed, the predetermined value is not counterloaded into the first frequency divider circuit 203 at the timing corresponding to the reference frame signal 410, and the counter included in the first frequency divider circuit 203 is counted up as usual.

[0036] On the other hand, if the abnormality detection result 420 of the reference frame signal 410 indicates an abnormal state, the counter load suppression control circuit 202 supplies a counter load suppression signal 440 indicating a suppression release state to the first frequency divider circuit 203, so that a predetermined value is loaded into the counter at the timing of the reference frame signal 410. Note that loading a predetermined value into the counter in the first frequency divider circuit 203 may also be done by resetting the first frequency divider circuit or the counter within it.

[0037] The first frequency divider circuit 203 loads a predetermined value into its counter at timing 411 corresponding to the reference frame signal (FP) 410, and the counter value of the first frequency divider circuit 203 increases from 0 to N, as shown in counter value 451. The counter value of the second frequency divider circuit 207, which is synchronized with the first frequency divider circuit 203, also increases from 0 to N, as shown in counter value 461. Note that the second frequency divider circuit 207, which is synchronized with the first frequency divider circuit 203, does not always load its counter.

[0038] The write start signal generation circuit 208 generates a write start signal 470 based on the reference frame signal 410, which indicates the timing to write the input data 430 to the data input / output unit (ES (Elastic Store memory)) 209. An example of the write start signal 470 is shown as the write start signal 471 generated according to the timing 411. The input data 430 supplied from the data output device 150 is written to the data input / output unit 209 as write data (WD (Write Data)) according to the write start signal and the first clock (WC (Write Clock) 1502) supplied from the data output device 150.

[0039] Meanwhile, the second frequency divider circuit 207 outputs a phase comparison signal 460 and a readout start signal 480 using an internal counter. Since the first frequency divider circuit 203 and the second frequency divider circuit 207 are phase-synchronized by the phase synchronization circuit 210, the second frequency divider circuit 207 outputs the readout start signal 480 with the counter value M462 of its internal counter so that the time interval between the write start signal 470 and the readout start signal 480, which are generated based on the reference frame signal 410, is within the acceptable range for the output data to be read normally from the data input / output unit 209. Note that the readout start signal 480 shown in Figure 2 corresponds to the second frequency divider output signal 480A (shown in Figure 1) of the second frequency divider circuit 207 described in one embodiment.

[0040] The data written to the data input / output unit 209 is read out as read data (RD (Read Data)) 490 according to the read start signal 480 and the second clock (RC (Read Clock)) 2061 output by the VCO 206. Figure 3 shows an example where the time interval between the write start signal 471 and the read start signal 481 is within the acceptable range (normal value). In this case, when the time interval is within the acceptable range (normal value), the read data 490 is read out as normal 491 from the data input / output unit 209.

[0041] In other words, the input data 430 written to the data input / output unit 209 according to the write start signal 470 and the first clock 1502 is read out normally from the data input / output unit 209 according to the read start signal 480, which is within an acceptable time interval from the write start signal 470, and the second clock (RC) 2061.

[0042] In some cases, the first clock 1502 or the reference frame signal 410 may enter an abnormal state due to disturbance, be subsequently disconnected, and then return to a normal state. An abnormal state includes, for example, cases where the period of the reference frame signal 410, etc., changes significantly from its normal value or is missing.

[0043] If the first clock 1502 or the reference frame signal 410 enters an abnormal state, the counter load suppression signal 440 of the counter load suppression control circuit 202 will temporarily indicate a state of counter load suppression release. After this, once the system returns to a normal state, and the abnormality detection result 420 of the reference frame signal 410 changes from an abnormal state to a normal state, the counter load suppression signal 440 of the counter load suppression control circuit 202 will also change from a state indicating counter load suppression release to a state indicating counter load suppression. When the first frequency divider circuit 203 is counter load suppressed, the counters included in the first frequency divider circuit 203 and the second frequency divider circuit 207 will not be reset at the timing 411 corresponding to the reference frame signal 410, as shown in Figure 3, but will continue to count up. This state is a normal operating state.

[0044] However, there may be cases where the system behaves differently from the normal operating state described above. The behavior in such cases is explained below.

[0045] Next, we will explain the operation when the first clock 1502 and the reference frame signal 410 supplied by the clock supply device 100 to the communication device (clock supply destination device) 200, after the clock supply device 100 is powered on or a card is inserted, change from a disturbed state to a normal state.

[0046] When the abnormality detection result 420 of the abnormality detection circuit 201 of the reference frame signal 410 of the communication device 200 changes from an abnormal state to a normal state, the counterload suppression control circuit 202 changes the counterload suppression signal 440 supplied to the first frequency divider circuit 203 from a state indicating counterload suppression release to a state indicating counterload suppression.

[0047] At this time, due to the differences in the transient states that occur between the transition of the reference frame signal 410 from a disturbed state to a normal state, the counter in the first frequency divider circuit 203 may enter a normal state, as shown in Figure 3, where it remains in the same state as when a predetermined value is loaded by the reference frame signal 410. Alternatively, it may enter an abnormal state where it deviates from the state when a predetermined value is loaded by the reference frame signal 410. Figure 4 shows an example of the operation of a conventional communication device in an abnormal state. The operation of section 1000 in Figure 4 will be explained below. Note that in Figure 4, the operation of section 1100 is the same as the operation of section 1000, so the operation of section 1100 will be omitted.

[0048] The abnormality detection circuit 201, which detects abnormal states in the reference frame signal 410, notifies that the state has changed from an abnormal state to a normal state after a certain period of time has elapsed since the abnormal state, which indicates a disturbance in the input first clock 1502 and the reference frame signal 410, changed to a normal state, by an abnormality detection result 420.

[0049] However, if the input first clock 1502 and reference frame signal 410 undergo an irregular process, such as repeatedly fluctuating between an abnormal state indicating a disturbance and a normal state, before reaching (or recovering from) a normal state, the following situation may occur. That is, the abnormality detection result 420 of the abnormality detection circuit 201 changes from an abnormal state to a normal state, and the operation of the counter load suppression control circuit 202 to change the counter load suppression signal 440 from suppression release to suppression may not be able to be made slower than the actual change in the first clock 1502 and reference frame signal 410 from a disturbance state to a normal state.

[0050] In other words, during transient states such as power-on, the first clock 1502 and the reference frame signal 410 change states irregularly, making it difficult to accurately detect abnormal and normal states of the reference frame signal 410.

[0051] As a result, when the input first clock 1502 and reference frame signal 410 are in a disturbed state, if the counter load suppression control circuit 202 changes the counter load suppression signal 440 from a state indicating counter load suppression release to a state indicating counter load suppression, then after returning from a disturbed state to a normal state, a predetermined value cannot be loaded into the counter in the first frequency divider circuit 203 at the timing corresponding to the reference frame signal (FP) 410.

[0052] When such operation occurs, after the first clock 1502 and the reference frame signal 410 change from an abnormal state indicating a disturbance to a normal state, the count value of the counter in the first frequency divider circuit 203 may become fixed, as shown in Figure 4, with a time difference corresponding to the count value X relative to the reference frame signal (FP) 410. The time corresponding to the count value X is not always the same.

[0053] Furthermore, if the count value of the counter in the first frequency divider circuit 203 becomes fixed with respect to the reference frame signal (FP) 410 by a time difference equivalent to the count value X, the phase synchronization circuit 210 controls and outputs the frequency of the second clock 2061 so that the phase comparison comparison signal 460 of the second frequency divider circuit 207 synchronizes with the phase comparison reference signal 450 of the first frequency divider circuit 203. As a result, the count value of the counter in the second frequency divider circuit 207 also becomes fixed with respect to the reference frame signal (FP) 410 by a time difference equivalent to the count value X, as shown in Figure 4, and the counter value M462 of the second frequency divider circuit 207 also becomes shifted with respect to the reference frame signal (FP) 410 by a time difference equivalent to the count value X. Furthermore, since the read-start signal 480 corresponds to the counter value M462 of the second frequency divider circuit 207, the read-start signal 480 is also shifted from the reference frame signal 410 by a time equivalent to the count value X. As a result, the time interval between the write-start signal 470 and the read-start signal 480 is also shifted by a time equivalent to the count value X.

[0054] Generally, the write start signal 470 and read start signal 480 of the data input / output unit 209 have an allowable time interval (tolerance range) between them to ensure the integrity of the data. However, as described above, if the time interval between the write start signal 470 and the read start signal 480 is shifted by a time equivalent to the count value X, the time interval between the write start signal 470 and the read start signal 480 of the data input / output unit 209 may fall outside the allowable range. In this case, the data input / output control to the data input / output unit may not operate normally.

[0055] Next, an example of the configuration and operation of the communication device according to this disclosure will be described in detail with reference to the drawings. Figure 5 is a block diagram showing an example of the configuration of the communication device according to this disclosure. In Figure 5, components with the same reference numerals as in Figure 2 represent the same components. The communication device 200A shown in Figure 5 is a configuration in which a phase shift detection circuit 310 is added to the conventional communication device 200 shown in Figure 2.

[0056] The phase shift detection circuit 310 takes the write start signal 470 and the read start signal 480 as inputs and detects whether the time relationship between the write start signal 470 and the read start signal 480 satisfies a predetermined criterion by checking whether the time interval from the write start signal 470 to the read start signal 480 is within the acceptable range for read data to be normally read from the data input / output unit 209. The predetermined criterion is a time relationship that allows read data to be normally read from the data input / output unit 209.

[0057] Figure 6 is a diagram illustrating an example of the operation of the communication device according to this disclosure. In section 1000 of Figure 6, similar to section 1000 of Figure 4, the count value of the counter (not shown) in the first frequency divider circuit 203 is shifted by a time corresponding to the count value X relative to the reference frame signal (FP) 410, for example, and the time interval from the write start signal 470 to the read start signal 480 becomes "X + M". If the time interval "X + M" is outside the acceptable range for normal reading of data from the data input / output unit 209, the phase shift detection circuit 310 detects that the time relationship between the write start signal 470 and the read start signal 480 does not meet a predetermined standard and outputs a phase shift detection result 610 indicating that the phase is shifted (i.e., abnormal) to the counter load suppression control circuit 202A. As a result, the counter load suppression control circuit 202A releases the suppression of the counter load of the first frequency divider circuit 203 by the counter load suppression signal 440A.

[0058] As a result, if the phase shift detection result 610 of the phase shift detection circuit 310 indicates that it does not meet a predetermined standard, a predetermined value is loaded into the counter in the first frequency divider circuit 203, even if the abnormality detection result 420 of the abnormality detection circuit 201 does not indicate an abnormal state.

[0059] Unlike the operation in section 1100 shown in Figure 4, in section 1100 of Figure 6, a predetermined value is loaded into the counter in the first frequency divider circuit 203 at the timing of the reference frame signal 412. As a result, the state in which the counter in the first frequency divider circuit 203 is shifted by a time equivalent to the count value X from the reference frame signal 412 is eliminated, and the time interval from the write start signal 470 to the read start signal 480 becomes "M". Consequently, the time interval from the write start signal 470 to the read start signal 480 becomes a value within the acceptable range for normal reading of data from the data input / output unit 209, and the data is read normally from the data input / output unit 209.

[0060] Furthermore, since the time relationship between the write start signal 470 and the read start signal 480 satisfies a predetermined standard, the counter load suppression control circuit 202A suppresses the counter load of the first frequency divider circuit 203 again using the counter load suppression signal 440.

[0061] As described above, according to the first embodiment of the present invention, a phase shift detection circuit 310 is provided to constantly monitor for any time difference between the write start signal 470 and the read start signal 480, and if a shift occurs, the suppression of the counter load by the counter load suppression control circuit 202A is released. As a result, even if the counter of the first frequency divider circuit 203 is shifted due to an abnormal condition caused by a disturbance in the reference frame signal 410, the counter shift is detected, the suppression of the counter load by the counter load suppression control circuit 202A is released, the counter of the first frequency divider circuit 203 performs a counter load, and the counter is reset to the correct state. After the first clock 1502 and the reference frame signal 410 have stabilized, the operation of the counter of the first frequency divider circuit 203 can always be restored to a normal state.

[0062] Accordingly, according to the first embodiment of the present invention, even when the reference frame signal supplied to the communication device does not indicate an abnormal state, it is possible to provide a communication device and a communication method that contribute to preventing the time interval between the write start signal and the read start signal of the data input / output device of the communication device from falling outside the acceptable range, that is, preventing the time relationship from failing to meet a predetermined standard.

[0063] [Second Embodiment] Next, a second embodiment will be described in detail with reference to the drawings. The second embodiment relates to a method for detecting phase shift in a phase shift detection circuit of a communication device according to the present disclosure. Figure 7 is a diagram showing an example of the operation of the detection method for the phase shift detection circuit of a communication device according to the present disclosure. The detection method for the phase shift detection circuit of a communication device according to the present disclosure will be described with reference to Figures 5 and 7. In Figure 7, components with the same reference numerals as in Figure 6 will be considered to represent the same components.

[0064] The phase shift detection circuit 310 of the communication device 200A shown in Figure 5 is supplied with a write start signal 470 and a read start signal 480, and measures the time between, for example, the write start signal 471 and the read start signal 483 using a clock or the like. Similarly, it measures the time between the write start signal 472 and the read start signal 482 using a clock or the like.

[0065] The phase shift detection circuit 310 determines whether the measured time interval between the write start signal 471 and the read start signal 483 is within the acceptable range for normal reading of data from the data input / output unit 209. The acceptable range for normal reading of data from the data input / output unit 209 is assumed to be predetermined as a unique value for the data input / output unit 209 and is provided to the phase shift detection circuit 310.

[0066] For example, if the measured time interval between the write start signal 471 and the read start signal 483 is outside the acceptable range for the data input / output unit 209, for example, if it is greater than the upper limit of the acceptable range, the phase shift detection circuit 310 determines that there is an abnormal phase shift between the write start signal 471 and the read start signal 483 and outputs a phase shift detection result 610 indicating an abnormal state. The same applies if it is smaller than the lower limit of the acceptable range.

[0067] On the other hand, if the measured time interval between the write start signal 472 and the read start signal 482 is within the allowable range for the data input / output unit 209, for example, within the range including the allowable lower limit and upper limit, the phase shift detection circuit 310 determines that there is no abnormal phase shift between the write start signal 471 and the read start signal 483, and outputs a phase shift detection result 610 indicating a normal state.

[0068] Accordingly, according to the second embodiment of the present invention, a phase shift detection circuit 310 for a communication device 200A is provided that contributes to determining whether the time interval between the write start signal 470 and the read start signal 480 is within an acceptable range for normal reading of data from the data input / output unit 209.

[0069] Although embodiments of the present invention have been described above, the present invention is not limited to the embodiments described above, and further modifications, substitutions, and adjustments can be made without departing from the basic technical idea of ​​the present invention. For example, the network configuration, the configuration of each element, and the message representation form shown in each drawing are examples to aid in understanding the present invention, and are not limited to the configurations shown in these drawings. Also, "A and / or B" is used to mean at least one of A or B.

[0070] Finally, preferred embodiments of the present invention are summarized. [First form] The communication device may include a first frequency divider circuit that divides a first clock and generates a phase comparison reference signal, into which a predetermined value is loaded according to a reference frame signal. The communication device may include a second frequency divider circuit that divides the second clock and generates a phase comparison signal. The communication device may include a phase synchronization circuit that generates the second clock so that the phase comparison reference signal and the phase comparison comparison signal are phase-synchronized. The communication device may include an abnormality detection circuit for detecting abnormal conditions in the reference frame signal. The communication device may include a counter load suppression control circuit that loads the predetermined value into the first frequency divider circuit if the abnormality detection result of the abnormality detection circuit indicates the abnormal state, and suppresses the loading of the predetermined value if the abnormality detection result does not indicate the abnormal state. The communication device may include a signal generation circuit that generates a signal based on the reference frame signal. The system may also include a phase shift detection circuit that detects whether the time relationship between the signal generated by the signal generation circuit and the second divided output signal of the second frequency divider circuit satisfies a predetermined criterion. If the phase shift detection result of the phase shift detection circuit indicates that the predetermined criteria are not met, the counterload suppression control circuit may load the predetermined value into the first frequency divider circuit, even if the abnormality detection result of the abnormality detection circuit does not indicate the abnormal state. [Second form] The communication device described in the first embodiment is It further includes a data input / output section, The second divided output signal of the second frequency divider circuit is the readout starting signal. The aforementioned signal generation circuit is a write start signal generation circuit that generates a write start signal, In accordance with the first clock and the write start signal, input data is written to the data input / output unit. It is preferable to read the data from the data input / output unit as read data according to the second clock and the read start signal. [Third form] The communication device described in the second embodiment is: Preferably, the write start signal generation circuit generates the write start signal by delaying the reference frame signal by a predetermined time. [Fourth form] The communication device described in the third embodiment is: Preferably, the predetermined time is zero. [Fifth form] The communication device described in the second or third embodiment is: Preferably, the phase shift detection circuit detects whether the predetermined criterion is met by determining whether the time interval from the write start signal to the read start signal is within an acceptable range for normal reading of the read data from the data input / output unit. [Sixth form] The communication device described in the first embodiment is It is preferable that the predetermined value is loaded into the first frequency divider circuit by resetting the first frequency divider circuit. [Seventh form] A first frequency divider circuit that divides a first clock and generates a phase comparison reference signal, into which a predetermined value is loaded according to a reference frame signal, A second frequency divider circuit that divides the second clock to generate a phase comparison signal, A communication method performed by a communication device includes a phase synchronization circuit that generates the second clock so that the phase comparison reference signal and the phase comparison comparison signal are phase-synchronized, The step may include an abnormality detection step for detecting an abnormal state in the reference frame signal. The communication method may include a counter load suppression control step in which, if the abnormality detection result of the abnormality detection step indicates the abnormal state, the predetermined value is loaded into the first frequency divider circuit, and if the abnormality detection result does not indicate the abnormal state, the loading of the predetermined value is suppressed. The communication method may include a signal generation step of generating a signal based on the reference frame signal. The communication method may include a phase shift detection step that detects whether the time relationship between the signal generated by the signal generation step and the second divided output signal of the second frequency divider circuit satisfies a predetermined criterion. The communication method may include a step of loading the predetermined value into the first frequency divider circuit if the phase shift detection result of the phase shift detection step indicates that the predetermined criteria are not met, even if the abnormality detection result of the abnormality detection step does not indicate the abnormal state. [Eighth form] The communication method described in the seventh form is: The communication device further includes a data input / output unit, The second divided output signal of the second frequency divider circuit is the readout starting signal. The aforementioned signal generation step is a write start signal generation step that generates a write start signal, The steps include writing input data to the data input / output unit according to the first clock and the write start signal, Preferably, the process includes a step of reading output data from the data input / output unit according to the second clock and the readout start signal. [Ninth form] The communication method described in the eighth embodiment preferably includes the step of generating the write start signal by delaying the reference frame signal by a predetermined time. [Tenth form] In the communication method described in the ninth embodiment, it is preferable that the predetermined time is zero. Furthermore, the seventh form described above can be expanded into the fifth and sixth forms, similar to the first form.

[0071] Furthermore, the disclosures in the above-mentioned patent documents are incorporated into this work by reference. Within the framework of the full disclosure of the present invention (including the claims), further modifications and adjustments to the embodiments or examples are possible based on the fundamental technical concept. Also, within the framework of the disclosure of the present invention, various combinations or selections of various disclosure elements (including each element of each claim, each element of each embodiment or example, each element of each drawing, etc.) are possible. In other words, the present invention naturally includes the full disclosure, including the claims, and various modifications and alterations that a person skilled in the art could make in accordance with the technical concept. In particular, with respect to the numerical ranges described in this work, any numerical value or sub-range included within that range should be interpreted as being specifically described, even if not otherwise stated. Furthermore, each disclosure item of the above-mentioned cited documents may, if necessary, be used in combination with the items described in this work as part of the disclosure of the present invention, in accordance with the spirit of the present invention, in whole or in part, and this is also considered to be included in the disclosure of this application. [Explanation of symbols]

[0072] 100 Clock supply device 101 Clock power source 150 Data Output Device 200, 200A communication equipment 201 Anomaly detection circuit 202, 202A Counterload Suppression Control Circuit 203 First frequency divider circuit 204 Phase comparator 205 Low-pass filter 206 Voltage-controlled oscillator 207 Second frequency divider circuit 208 Write-start signal generation circuit 208A signal generation circuit 209 Data Input / Output Section 210 Phase-locked circuit 310 Phase shift detection circuit 440, 440A Counterload suppression signal 450 Phase comparison reference side signal 460 Phase comparison comparison side signal 470, 471, 472 Write start signal 480, 481, 482, 483, 484 Readout start signal 480A Second divided output signal

Claims

1. A first frequency divider circuit that divides a first clock and generates a phase comparison reference signal, into which a predetermined value is loaded according to a reference frame signal, A second frequency divider circuit that divides the second clock to generate a phase comparison comparison signal, A phase synchronization circuit that generates the second clock such that the phase comparison reference signal and the phase comparison comparison signal are phase-synchronized, An abnormality detection circuit for detecting an abnormal state of the reference frame signal, A counter load suppression control circuit is provided, which loads the predetermined value into the first frequency divider circuit if the abnormality detection result of the abnormality detection circuit indicates the abnormal state, and suppresses the loading of the predetermined value if the abnormality detection result does not indicate the abnormal state. A signal generation circuit that generates a signal based on the aforementioned reference frame signal, The circuit includes a phase shift detection circuit that detects whether the time relationship between the signal generated by the signal generation circuit and the second divided output signal of the second frequency divider circuit satisfies a predetermined criterion. If the phase shift detection result of the phase shift detection circuit indicates that the predetermined criteria are not met, the counterload suppression control circuit loads the predetermined value into the first frequency divider circuit, even if the abnormality detection result of the abnormality detection circuit does not indicate the abnormal state, in a communication device.

2. It further includes a data input / output section, The second frequency-divided output signal of the second frequency divider circuit is the readout start signal, The aforementioned signal generation circuit is a write start signal generation circuit that generates a write start signal, In accordance with the first clock and the write start signal, input data is written to the data input / output unit. The communication device according to claim 1, which reads data from the data input / output unit as read data according to the second clock and the read start signal.

3. The communication device according to claim 2, wherein the write start signal generation circuit generates the write start signal by delaying the reference frame signal by a predetermined time.

4. The communication device according to claim 3, wherein the predetermined time is zero.

5. The communication device according to claim 2 or 3, wherein the phase shift detection circuit detects whether the predetermined criterion is met by determining whether the time interval from the write start signal to the read start signal is within an acceptable range for normal reading of the read data from the data input / output unit.

6. The communication device according to claim 1, wherein loading the predetermined value into the first frequency divider circuit is performed by resetting the first frequency divider circuit.

7. A first frequency divider circuit that divides a first clock and generates a phase comparison reference signal, into which a predetermined value is loaded according to a reference frame signal, A second frequency divider circuit that divides the second clock to generate a phase comparison comparison signal, The communication device includes a phase synchronization circuit that generates the second clock so that the phase comparison reference signal and the phase comparison comparison signal are phase-synchronized, An abnormality detection step for detecting an abnormal state of the reference frame signal, A counter load suppression control step is performed, in which, if the abnormality detection result of the abnormality detection step indicates the abnormal state, the predetermined value is loaded into the first frequency divider circuit, and if the abnormality detection result does not indicate the abnormal state, the loading of the predetermined value is suppressed. A signal generation step of generating a signal based on the aforementioned reference frame signal, The step includes detecting whether the time relationship between the signal generated by the signal generation step and the second divided output signal of the second frequency divider circuit satisfies a predetermined criterion, A communication method comprising the steps of loading the predetermined value into the first frequency divider circuit if the phase shift detection result of the phase shift detection step indicates that the predetermined criterion is not met, even if the abnormality detection result of the abnormality detection step does not indicate the abnormal state.

8. The communication device further includes a data input / output unit, The second frequency-divided output signal of the second frequency divider circuit is the readout start signal, The aforementioned signal generation step is a write start signal generation step that generates a write start signal, The steps include writing input data to the data input / output unit according to the first clock and the write start signal, The communication method according to claim 7, further comprising the step of reading data from the data input / output unit as read data in accordance with the second clock and the read start signal.

9. The communication method according to claim 8, further comprising the step of generating the write start signal by delaying the reference frame signal by a predetermined time.

10. The communication method according to claim 9, wherein the predetermined time is zero.

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