Switched Capacitor Equalizer Using an Integrating Amplifier

Abstract

This invention provides a switched-capacitor equalizer that can simultaneously compensate for interference between noise and signals generated in a channel. [Solution] The switched-capacitor equalizer 1210 includes a first integrating amplifier 1211 that integrates the input voltage in accordance with odd clock periods and outputs a first output voltage V_ODD, a second integrating amplifier 1212 that integrates the input voltage in accordance with even clock periods and outputs a second output voltage V_EVEN, a coupling capacitor 1213 that transmits the first output voltage to the second integrating amplifier in accordance with odd clock periods and transmits the second output voltage to the first integrating amplifier in accordance with even clock periods, a first transistor T1 that outputs an odd data signal in accordance with odd clock periods, and a second transistor T2 that outputs an even data signal in accordance with even clock periods.

Description

Technical Field

[0001] The present invention relates to a switched capacitor equalizer using an integrating amplifier.

Background Art

[0002] Communication between devices or between chips can be performed through an interface. At this time, in the communication process, the signal can be distorted and transmitted between devices or between chips. In order to compensate for such signal distortion, the interface can include an equalizer.

[0003] The equalizer can generate a plurality of feedback signals and perform an operation of adding the plurality of feedback signals and an input signal through an adder. The adder can receive and add the plurality of feedback signals and the input signal, and output the added result to a plurality of sense amplifiers. At this time, since a plurality of sense amplifiers, output nodes of the plurality of feedback signals, and an input node of the input signal are connected to the adder, a problem that it is difficult to sufficiently secure the bandwidth of the adder can occur. Therefore, there is a need for an equalizer that can simultaneously compensate for the interference between noise and signals generated in the channel.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The present invention is for solving the above-described problems, and an object of the present invention is to provide a switched capacitor equalizer using an integrating amplifier.

Means for Solving the Problems

[0006] The present invention may include a first integrating amplifier that integrates an input voltage in accordance with odd clock periods and outputs a first output voltage, a second integrating amplifier that integrates the input voltage in accordance with even clock periods and outputs a second output voltage, a coupling capacitor that transmits the first output voltage to the second integrating amplifier in accordance with odd clock periods and transmits the second output voltage to the first integrating amplifier in accordance with even clock periods, a first transistor that outputs an odd data signal in accordance with odd clock periods, and a second transistor that outputs an even data signal in accordance with even clock periods.

[0007] The first integrating amplifier according to some embodiments of the present invention can initialize the input voltage in accordance with the even clock period.

[0008] The second integrating amplifier according to some embodiments of the present invention can initialize the input voltage in accordance with the odd clock period.

[0009] The switched-capacitor equalizer according to some embodiments of the present invention may further include a reset timing controller that is coupled to the first transistor and the second transistor to control their timing.

[0010] The present invention may include a first integral amplifier with one end connected to an input node and the other end connected to a first output node, a second integral amplifier with one end connected to the input node and the other end connected to a second output node, a coupling capacitor with one end connected to the first output node and the other end connected to a second output node, a first transistor with one end connected to a power supply and the other end connected to a first output node, and a second transistor with one end connected to a power supply and the other end connected to a second output node.

[0011] According to some embodiments of the present invention, the first integrating amplifier can integrate the input voltage in accordance with odd clock periods, initialize the input voltage in accordance with even clock periods, and output a first output voltage in accordance with odd clock periods.

[0012] The second integrating amplifier according to some embodiments of the present invention can integrate the input voltage in accordance with the even clock period, initialize the input voltage in accordance with the odd clock period, and output a second output voltage in accordance with the even clock period.

[0013] The coupling capacitor according to some embodiments of the present invention can transmit the first output voltage to the second integrating amplifier in accordance with the odd clock period and the second output voltage to the first integrating amplifier in accordance with the even clock period.

[0014] According to some embodiments of the present invention, the first transistor can output an odd data signal corresponding to the odd clock period, and the second transistor can output an even data signal corresponding to the even clock period.

[0015] The switched-capacitor equalizer according to some embodiments of the present invention may further include a reset timing controller that is coupled to the first transistor and the second transistor to control their timing. [Effects of the Invention]

[0016] The switched-capacitor equalizer utilizing an integral amplifier according to the present invention can eliminate inter-signal interference occurring in the channel, reduce the error rate, and increase the data rate. Furthermore, as an equalizer utilizing an integral amplifier, the present invention can provide an equalizer that reduces power consumption and is robust against noise in the high-frequency band. [Brief explanation of the drawing]

[0017] [Figure 1]Block diagram of a transceiver according to some embodiments of the present invention. [Figure 2] Circuit diagram of a switched capacitor equalizer according to some embodiments of the present invention. [Figure 3] Circuit diagram of an integrating amplifier according to some embodiments of the present invention. [Figure 4A] Timing diagram for explaining an example of the operation of a switched capacitor equalizer according to some embodiments of the present invention. [Figure 4B] Timing diagram for explaining an example of the operation of a switched capacitor equalizer according to some embodiments of the present invention. [Figure 5A] Circuit diagram of an integrating amplifier according to other embodiments of the present invention. [Figure 5B] Circuit diagram of an integrating amplifier according to other embodiments of the present invention. [Figure 5C] Circuit diagram of an integrating amplifier according to other embodiments of the present invention. [Figure 6] Circuit diagram further including a reset timing controller according to other embodiments of the present invention. [Figure 7] Timing diagram for explaining the operation of a reset timing controller according to other embodiments of the present invention. [Figure 8A] It shows the simulation of the reset timing controller in FIG. 6. [Figure 8B] It shows the simulation of the reset timing controller in FIG. 6. [Figure 9A] Block diagram in which switched capacitor equalizers according to other embodiments of the present invention are connected to each other. [Figure 9B] Block diagram in which switched capacitor equalizers according to other embodiments of the present invention are connected to each other. [Figure 9C] Block diagram in which switched capacitor equalizers according to other embodiments of the present invention are connected to each other. [Figure 10A] It shows the eye diagram of the input / output voltage according to some embodiments of the present invention. [Figure 10B] This shows an eye diagram of the input and output voltages according to some embodiments of the present invention. [Modes for carrying out the invention]

[0018] Embodiments of the present invention will be described below clearly and in detail with reference to the accompanying drawings.

[0019] Figure 1 is a block diagram of a transceiver according to some embodiments of the present invention.

[0020] The transceiver 1000 according to an embodiment of the present invention can be embodied in a device that transmits and receives data. For example, the transceiver 1000 can be embodied in desktop computers, laptop computers, tablet computers, smartphones, wearable devices, etc., that support channel interface standards such as PCIe (Peripheral Component Interconnection express) and PCIe Gen (Generation) 6.0, and memory standards such as SSD (Solid State Drive), embedded UFS (Universal Flash Storage), and DDR (Double Data Rate).

[0021] Referring to Figure 1, the transceiver 1000 can include a transmitter 1100 and a receiver 1200.

[0022] The transmitter 1100 can transmit a signal according to the data to the receiver 1200 via channel CH. The transmitter 1100 can transmit a signal that includes serially arranged bits of data. For example, the transmitter 1100 can transmit the signal using a single-ended signaling method.

[0023] A channel CH can be a path that physically or electrically connects the transmitter 1100 and the receiver 1200. For example, a channel CH can be implemented using a trace on a PCB (Printed Circuit Board) or a coaxial cable. A channel CH can degrade the high-frequency components of data transmitted through it due to the skin effect, dielectric loss, etc. If a signal is transmitted through a channel CH, channel loss can occur in the receiver 1200. Therefore, each bit of data that has passed through the channel CH can interfere with the next bit due to channel loss or bandwidth limitations, causing adjacent symbols to overlap and increasing the BER (Bit Error Rate), i.e., intersymbol interference (ISI).

[0024] The receiver 1200 is connected to the transmitter 1100 via channel CH and can receive signals transmitted from the transmitter 1100. The receiver 1200 may integrate and restore the transmitted signal or include a switched-capacitor equalizer 1210 to compensate for channel loss.

[0025] The switched-capacitor equalizer 1210 integrates and initializes the input voltage according to the clock period to amplify the output voltage, and can output a data signal using the amplified output voltage. A more detailed explanation is given in Figure 2 below.

[0026] Figure 2 is a circuit diagram of a switched-capacitor equalizer according to some embodiments of the present invention.

[0027] Referring to Figure 2, the switched-capacitor equalizer 1210 may include a first integrating amplifier 1211, a second integrating amplifier 1212, a coupling capacitor 1213, a first transistor T1, and a second transistor T2.

[0028] The first integrating amplifier 1211 can receive an input voltage V_IN and output a first output voltage V_ODD. More specifically, the first integrating amplifier 1211 can integrate or initialize the input voltage V_IN in accordance with the clock period and output a first output voltage V_ODD.

[0029] For example, the first integrating amplifier 1211 can output a first output voltage V_ODD that integrates the input voltage V_IN in accordance with odd clock periods and initializes the input voltage V_IN in accordance with even clock periods.

[0030] For this purpose, one end of the first integral amplifier 1211 can be connected to the input node N_IN, and the other end can be connected to the first output node N_OUT1.

[0031] The second integrating amplifier 1212 can receive the input voltage V_IN and output the second output voltage V_EVEN. More specifically, the second integrating amplifier 1212 can integrate or initialize the input voltage V_IN in accordance with the clock period and output the second output voltage V_EVEN.

[0032] For example, the second integrating amplifier 1212 can output a second output voltage V_EVEN that integrates the input voltage V_IN in correspondence with even clock periods and initializes the input voltage V_IN in correspondence with odd clock periods.

[0033] For this purpose, one end of the second integral amplifier 1212 can be connected to the input node N_IN, and the other end can be connected to the second output node N_OUT2.

[0034] The coupling capacitor 1213 can repeatedly charge and discharge in accordance with the clock period. In other words, the coupling capacitor 1213 can transmit the voltage charged in accordance with the clock period to the first integrating amplifier 1211 or the second integrating amplifier 1212 for compensation.

[0035] For example, the coupling capacitor 1213 can transmit the first output voltage V_ODD to the second integrating amplifier 1212 at odd clock cycles and the second output voltage V_EVEN to the first integrating amplifier 1211 at even clock cycles.

[0036] The first transistor T1 can output a data signal D corresponding to the clock period. For example, the first transistor T1 can output an odd data signal D_ODD corresponding to an odd clock.

[0037] For this purpose, the first transistor T1 can be configured as a PMOS transistor, with one end connected to the power supply VDD and the other end connected to the first output node N_OUT1.

[0038] The second transistor T2 can output a data signal D corresponding to the clock period. For example, the second transistor T2 can output an even data signal D_EVEN corresponding to an even clock cycle.

[0039] For this purpose, the second transistor T2 can be configured as a PMOS transistor, with one end connected to the power supply VDD and the other end connected to the second output node N_OUT2.

[0040] As described above, the switched-capacitor equalizer 1210 according to some embodiments of the present invention can eliminate inter-signal interference occurring in the channel, reduce the error rate, and increase the data rate. Furthermore, the switched-capacitor equalizer 1210 can reduce power consumption by utilizing an integrating amplifier and provide an equalizer that is robust against noise in the high-frequency band.

[0041] Furthermore, the switched-capacitor equalizer 1210 can reduce low-frequency noise by utilizing the signal before demodulation, eliminate delays in the feedback path, and increase the equalizer's effectiveness and bandwidth. In addition, since the switched-capacitor equalizer 1210 does not use an additional amplifier, the size of the equalizer can be reduced.

[0042] Figure 3 is a circuit diagram of an integral amplifier according to some embodiments of the present invention. Specifically, Figure 3 explains only the first integral amplifier 1211 as an example, but the second integral amplifier 1212 can also have the same circuit configuration.

[0043] Referring to Figure 3, the first integrating amplifier 1211 may include the third to sixth transistors T3, T4, T5, T6, load capacitors CL1, CL2, current sources CS1, CS2, and resistor R.

[0044] The third transistor T3 can receive the clock CK through its gate terminal. The source terminal of the third transistor T3 can be connected to the power supply VDD, and the drain terminal of the third transistor T3 can be connected to the first node N1. The third transistor T3 can control the voltage flowing between its source terminal and drain terminal in response to the clock CK. In addition, one end of the first load capacitor CL1 can be connected to ground, and the other end can be connected to the first node N1.

[0045] The fourth transistor T4 can receive the input voltage V_IN through its gate terminal. The drain terminal of the fourth transistor T4 can be connected to the first node N1, and the source terminal of the fourth transistor T4 can be connected to the second node N2. The fourth transistor T4 can control the amount of current flowing between its source terminal and drain terminal according to the input voltage V_IN. For this purpose, one end of the first current source CS1 can be connected to the second node N2, and the other end can be connected to ground.

[0046] The fifth transistor T5 can receive the clock CK through its gate terminal. The source terminal of the fifth transistor T5 can be connected to the power supply VDD, and the drain terminal of the fifth transistor T5 can be connected to the third node N3. The fifth transistor T5 can control the voltage flowing between its source terminal and drain terminal in response to the clock CK. In addition, one end of the second load capacitor CL2 can be connected to ground, and the other end can be connected to the third node N3.

[0047] The sixth transistor T6 can receive the inverted input voltage V_INB through its gate terminal. The drain terminal of the sixth transistor T6 can be connected to the third node N3, and the source terminal of the sixth transistor T6 can be connected to the fourth node N4. The sixth transistor T6 can control the amount of current flowing between its source terminal and drain terminal according to the inverted input voltage V_INB. For this purpose, one end of the second current source CS2 can be connected to the fourth node N4, and the other end can be connected to ground.

[0048] Furthermore, resistor R can function as a variable resistor, with one end connected to the second node N2 and the other end connected to the fourth node N4. As a variable resistor with adjustable resistance, resistor R can be used to control the output voltage of the circuit or to finely adjust the signal strength.

[0049] Here, the output path of the first integrating amplifier 1211 is connected to the fifth node N5 and the sixth node N6, allowing the first output voltage V_ODD to be output differentially. In addition, the coupling capacitor 1213 is connected to the output path and can be connected to the second integrating amplifier 1212.

[0050] Figures 4A and 4B are timing diagrams illustrating an example of the operation of a switched capacitor equalizer according to some embodiments of the present invention. Specifically, Figure 4A is a timing diagram showing an example in which the coupling capacitor 1213 of the switched capacitor equalizer 1210 is not applied, and Figure 4B is a timing diagram showing an example in which the coupling capacitor 1213 of the switched capacitor equalizer 1210 is applied.

[0051] Here, the switched-capacitor equalizer 1210 can output an odd data signal D_ODD and an inverted odd data signal DB_ODD based on the first differentially output voltage V_ODD. Furthermore, the switched-capacitor equalizer 1210 can output an even data signal D_EVEN and an inverted even data signal DB_EVEN based on the second differentially output voltage V_EVEN.

[0052] Referring to Figure 4A, from the first time point t1 to the second time point t2, the switched-capacitor equalizer 1210 can integrate and output the odd data signal D_ODD and the inverted odd data signal DB_ODD in accordance with the odd clock period. In addition, the switched-capacitor equalizer 1210 can initialize the even data signal D_EVEN and the inverted even data signal DB_EVEN.

[0053] From the second time point t2 to the third time point t3, the switched-capacitor equalizer 1210 can integrate and output the even data signal D_EVEN and the inverted even data signal DB_EVEN in accordance with the even clock period. In addition, the switched-capacitor equalizer 1210 can initialize the odd data signal D_ODD and the inverted odd data signal DB_ODD.

[0054] Here, in Figure 4A, the switched-capacitor equalizer 1210 does not have a coupling capacitor 1213 applied, so it can repeat integration or initialization corresponding to the clock period from the third time point t3 to the fourth time point t4.

[0055] Referring to Figure 4B, from the fifth time point t5 to the sixth time point t6, the switched-capacitor equalizer 1210 can integrate and output the odd data signal D_ODD and the inverted odd data signal DB_ODD in accordance with the odd clock period. The switched-capacitor equalizer 1210 can also initialize the even data signal D_EVEN and the inverted even data signal DB_EVEN. At this point, a voltage can be charged into the coupling capacitor 1213.

[0056] From time point 6 t6 to time point 7 t7, the switched-capacitor equalizer 1210 can integrate and output the even data signal D_EVEN and the inverted even data signal DB_EVEN in accordance with the even clock period. The switched-capacitor equalizer 1210 can also initialize the odd data signal D_ODD and the inverted odd data signal DB_ODD. At this time, by compensating the voltage charged to the coupling capacitor 1213, the output signal can be prevented from being affected by its previous state.

[0057] Here, the switched-capacitor equalizer 1210 in Figure 4B compensates for the voltage charged in accordance with the clock period from the 7th time point t7 to the 8th time point t8 by utilizing the coupling capacitor 1213, thereby preventing the output signal from being affected by the previous state.

[0058] Figures 5A to 5C are circuit diagrams of integral amplifiers according to other embodiments of the present invention. Specifically, Figures 5A to 5C are designed with a structure that performs the same function as the first integral amplifier 1211 in Figures 1 to 4B.

[0059] Figures 5A to 5C are circuit diagrams of the first integrating amplifier 1211, each representing a different design. All of Figures 5A to 5C are based on the same operating principle and can provide the same function and effect.

[0060] In other words, even if the circuit configurations in Figures 5A to 5C differ from those of the first integrating amplifier 1211 in their connection methods, each circuit can provide the same functions and effects as the first integrating amplifier 1211. Furthermore, although Figures 5A to 5C are explained using only the first integrating amplifier 1211 as an example, the second integrating amplifier 1212 can also have the same circuit configuration.

[0061] Figure 6 is a circuit diagram further including a reset timing controller according to another embodiment of the present invention.

[0062] Referring to Figure 6, the switched-capacitor equalizer 1210A may further include a reset timing controller 1214. The reset timing controller 1214 can control the timing when a reset signal is generated in the digital circuit. The reset timing controller 1214 can sense the time delay that occurs when switching the clock CK from 0 to 1, or from 1 to 0, and adjust the intermediate state.

[0063] For this purpose, the reset timing controller 1214 is coupled to a transistor that outputs an odd data signal D_ODD and an even data signal D_EVEN, so that the transistor does not operate together instantaneously.

[0064] Figure 7 is a timing diagram illustrating the operation of a reset timing controller according to another embodiment of the present invention.

[0065] Referring to Figure 7, the reset timing controller 1214 can delay the operation of some transistors by adjusting the reset clock CK_RST and the inverted reset clock CKB_RST.

[0066] Therefore, the reset timing controller 1214 can prevent the loss of the initialization signal and ensure the normal operation of the circuit.

[0067] Figures 8A and 8B show a simulation of the reset timing controller in Figure 6.

[0068] Figure 8A shows a simulation of what happens when the reset timing controller 1214 is not applied, confirming that the operation becomes unstable due to the lack of timing control.

[0069] On the other hand, Figure 8B shows a simulation of the case where the reset timing controller 1214 according to the embodiment described above in Figure 6 is applied, confirming that the timing is controlled by the reset signal and the stability of the overall circuit is ensured.

[0070] Figures 9A to 9C are block diagrams showing switched-capacitor equalizers connected to each other according to another embodiment of the present invention.

[0071] Referring to Figures 9A to 9C, multiple switched capacitor equalizers 1210 can be linked together. For example, the first switched capacitor equalizer 1210 can receive and process the input voltage V_IN and then pass it on to the next switched capacitor equalizer 1210. Thus, multiple switched capacitor equalizers 1210 can further amplify the signal or fine-tune it to improve the performance of the receiver 1200.

[0072] Furthermore, multiple switched-capacitor equalizers 1210 can include sample-and-hold circuits between the equalizers. Here, the sample-and-hold circuit is a circuit that samples a specific instantaneous value of the input signal and maintains that value for a certain period of time, thereby stabilizing the change in the signal.

[0073] Furthermore, the signal transmitted from the tip-switched capacitor equalizer 1210 can be stabilized to ensure accurate digital conversion.

[0074] Therefore, the multiple switched-capacitor equalizers 1210 can improve the signal quality of the overall system and prevent distortion.

[0075] Figures 10A and 10B show eye diagrams of input and output voltages according to some embodiments of the present invention. In the following, the input and output voltages will be described using PAM-4 (Pulse Amplitude Modulation-4Level) as an example, but this is merely illustrative and not limiting.

[0076] Referring to Figure 10A, which shows the PAM-4 signal of input voltage V_IN input from transmitter 1100, it can be seen that the opening of the eye diagram has narrowed due to the channel attenuation effect, and the voltage / time margin has deteriorated.

[0077] On the other hand, referring to Figure 10B, which shows the output voltage output of the PAM-4 signal of input voltage V_IN input to receiver 1200 through switched capacitor equalizer 1210, it can be seen that the opening of the eye diagram is separated by the removal of signal interference, and the voltage / time margin is improved.

[0078] The above-described content is a specific embodiment for carrying out the present invention. In addition to the embodiments described above, the present invention may also include embodiments that can be simply redesigned or easily modified. Furthermore, the present invention may also include technologies that can be easily modified and carried out using the embodiments. Therefore, the scope of the present invention should not be limited to the embodiments described above, but should be defined not only by the claims described later, but also by claims equivalent to those of this application.

[0079] This research was supported by the Korea Research Foundation (NRF), funded by the Ministry of Science and ICT (MSIT) (Identification No.: RS-2023-0281047). [Explanation of symbols]

[0080] 1000: Transmitter / Receiver 1100: Transmitter 1200: Receiver 1210: Switched Capacitor Equalizer 1211: First Integral Amplifier 1212: Second Integral Amplifier 1214: Coupling Capacitor 1214: Reset timing controller

Claims

1. A first integrating amplifier that integrates the input voltage in accordance with odd clock periods and outputs a first output voltage, A second integrating amplifier that integrates the input voltage in accordance with even clock periods and outputs a second output voltage, A coupling capacitor that transmits the first output voltage to the second integrating amplifier in accordance with the odd clock period and the second output voltage to the first integrating amplifier in accordance with the even clock period, A first transistor that outputs an odd data signal corresponding to the odd clock period, A switched-capacitor equalizer including a second transistor that outputs an even data signal corresponding to the aforementioned even clock period.

2. The first integrating amplifier is, The switched-capacitor equalizer according to claim 1, wherein the input voltage is initialized in accordance with the even clock period.

3. The second integral amplifier is, The switched-capacitor equalizer according to claim 2, wherein the input voltage is initialized in accordance with the odd clock period.

4. The switched capacitor equalizer is, The switched-capacitor equalizer according to claim 1, further comprising a reset timing controller connected to the first transistor and the second transistor for timing control.

5. A first integrating amplifier, with one end connected to an input node and the other end connected to a first output node, A second integral amplifier, one end of which is connected to the input node and the other end of which is connected to the second output node, A coupling capacitor, with one end connected to the first output node and the other end connected to the second output node, A first transistor, one end of which is connected to a power supply and the other end of which is connected to a first output node, A switched-capacitor equalizer including a second transistor, one end of which is connected to a power supply and the other end of which is connected to a second output node.

6. The switched-capacitor equalizer according to claim 5, wherein the first integrating amplifier integrates the input voltage in accordance with odd clock periods, initializes the input voltage in accordance with even clock periods, and outputs a first output voltage in accordance with odd clock periods.

7. The switched-capacitor equalizer according to claim 6, wherein the second integrating amplifier integrates the input voltage in accordance with the even clock period, initializes the input voltage in accordance with the odd clock period, and outputs a second output voltage in accordance with the even clock period.

8. The aforementioned coupling capacitor is A switched-capacitor equalizer according to claim 7, wherein the first output voltage is transmitted to the second integrating amplifier in accordance with the odd clock period, and the second output voltage is transmitted to the first integrating amplifier in accordance with the even clock period.

9. The first transistor outputs an odd data signal corresponding to the odd clock period, The switched-capacitor equalizer according to claim 8, wherein the second transistor outputs an even data signal corresponding to the even clock period.

10. The switched capacitor equalizer is, The switched-capacitor equalizer according to claim 5, further comprising a reset timing controller connected to the first transistor and the second transistor for timing control.

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