Systems, computer implementation methods, computer programs (error mitigation related to Clifford circuits using generalized Pauli checks)

Abstract

A system / technique is provided to facilitate error reduction in Clifford circuits using generalized Pauli checks. [Solution] In various embodiments, the system can execute a Clifford circuit on a set of data qubits. In various embodiments, the system can detect errors in the execution of the Clifford circuit by measuring a set of check qubits that control a set of Pauli operators inserted into the Clifford circuit. In various cases, the product of the backpropagation of the set of Pauli operators may satisfy an error mitigation criterion. In some cases, the error mitigation criterion may be: the product is equal to the identity operator up to the global phase; the product is equal to the backpropagation of randomly inserted Pauli operators in the Clifford circuit; or the product is in a set of stabilizers associated with the Clifford circuit.

Description

[Technical Field]

[0001] This disclosure relates to quantum error mitigation. [Overview of the project] [Problems that the invention aims to solve]

[0002] The following outline provides a summary to give a basic understanding of one or more embodiments. This outline is not intended to identify any important or essential elements or to define any scope of any particular embodiment or any scope of any claim. Its sole purpose is to present the concepts in a simplified form as a prelude to the more detailed description that will be presented later. One or more embodiments described herein describe a device, system, method, or apparatus that can facilitate error mitigation related to Clifford circuits by generalized Pauli checks. [Means for solving the problem]

[0003] A system is provided according to one or more embodiments. In various embodiments, the system may comprise a processor capable of executing computer executable instructions stored in non-temporary computer-readable memory. In various cases, such execution may facilitate various operations on the processor. In various cases, such operations may include a procedure for executing a Clifford circuit on a set of data qubits. In various embodiments, such operations may comprise a procedure for detecting errors in the execution of a Clifford circuit by measuring a set of check qubits that control a set of Pauli operators inserted into the Clifford circuit, where the product of the backpropagation of the set of Pauli operators satisfies an error mitigation criterion.

[0004] In various forms, the systems described above can be reconstructed, reformatted, or otherwise implemented as computer implementations or as computer program products. [Brief explanation of the drawing]

[0005] [Figure 1] This is a block diagram of an exemplary and non-limiting system that facilitates error mitigation of Clifford circuits by generalized Pauli check, according to one or more embodiments described herein.

[0006] [Figure 2] This specification includes a block diagram of an exemplary and non-limiting system comprising a set of generalized Pauli checks and errors that facilitate error mitigation related to Clifford circuits by generalized Pauli checks, according to one or more embodiments described herein.

[0007] [Figure 3] This is an exemplary and non-limiting block diagram relating to a generalized Pauliczek according to one or more embodiments described herein.

[0008] [Figure 4] This specification provides an exemplary and non-limiting schematic diagram relating to a generalized Pauli check according to one or more embodiments described herein. [Figure 5] This specification provides an exemplary and non-limiting schematic diagram relating to a generalized Pauli check according to one or more embodiments described herein. [Figure 6] This specification provides an exemplary and non-limiting schematic diagram relating to a generalized Pauli check according to one or more embodiments described herein.

[0009] [Figure 7] This is a block diagram of an exemplary and non-limiting system, including multiple candidate locations, that facilitates error mitigation for Clifford circuits by generalized Pauli checks, according to one or more embodiments described herein.

[0010] [Figure 8]This is an exemplary and non-limiting system block diagram illustrating how a set of generalized Pauli checks may be obtained or identified with respect to a Clifford circuit, given a number of candidate positions, according to one or more embodiments described herein.

[0011] [Figure 9] This is a flowchart illustrating an exemplary and non-limiting computer implementation method that facilitates error mitigation of Clifford circuits by generalized Pauli checks, according to one or more embodiments described herein.

[0012] [Figure 10] This specification includes an exemplary and non-limiting schematic diagram illustrating how a generalized Pauli check may be effective even for qubit topologies with limited coupling, according to one or more embodiments described herein. [Figure 11] This specification includes an exemplary and non-limiting schematic diagram illustrating how a generalized Pauli check may be effective even for qubit topologies with limited coupling, according to one or more embodiments described herein.

[0013] [Figure 12] This is an illustrative and non-limiting schematic diagram illustrating how daisy-chained check qubits may be involved in a generalized Pauli check according to one or more embodiments described herein. [Figure 13] This is an illustrative and non-limiting schematic diagram illustrating how daisy-chained check qubits may be involved in a generalized Pauli check according to one or more embodiments described herein. [Figure 14] This is an illustrative and non-limiting schematic diagram illustrating how daisy-chained check qubits may be involved in a generalized Pauli check according to one or more embodiments described herein.

[0014] [Figure 15]This is a diagram illustrating the results of exemplary and non-limiting experiments according to one or more embodiments described herein. [Figure 16] This is a diagram illustrating the results of exemplary and non-limiting experiments according to one or more embodiments described herein.

[0015] [Figure 17] This is a flowchart illustrating an exemplary and non-limiting computer implementation method that facilitates error mitigation of Clifford circuits by generalized Pauli checks, according to one or more embodiments described herein.

[0016] [Figure 18] This is a block diagram of an exemplary and non-limiting operating environment in which one or more embodiments described herein may be facilitated. [Modes for carrying out the invention]

[0017] The detailed description below is illustrative and is not intended to limit any embodiments or applications or uses of any embodiments. Furthermore, it is not intended to be bound by any express or implied information presented in the preceding background art or summary section of the invention or the section on embodiments for carrying out the invention.

[0018] Herein, one or more embodiments are described with reference to the drawings, and throughout, similar reference numerals are used to refer to similar elements. In the following description, for illustrative purposes, numerous specific details are provided to give a more complete understanding of one or more embodiments. However, it is clear that in various cases one or more embodiments may be carried out without these specific details.

[0019] A quantum computer can be any suitable device that utilizes a qubit lattice (e.g., multiple superconducting qubits fabricated on one or more quantum substrates and exhibiting any suitable connection topology) for information processing. A quantum circuit can be any suitable sequence of any number of parallel or serial quantum gates that can be executed on a quantum computer. Quantum gates can be fundamental components of a quantum circuit that can change, rewrite, or otherwise affect the state of qubits. As some non-restrictive examples, a quantum gate can be any suitable one-qubit gate (e.g., Pauli X gate, Pauli Y gate, Pauli Z gate, phase gate, rotation gate, Hadamard gate) or any suitable entanglement or two-qubit gate (e.g., controlled NOT gate, controlled phase gate). Quantum gates can be combined in series by matrix multiplication or in parallel by tensor product. A Clifford circuit can be any quantum circuit that can be represented using only Clifford gates; that is, it can be represented using only Hadamard gates, phase gates, or controlled Not gates. A quantum circuit can be considered to have a Clifford depth d if, for any suitable positive integer d, the quantum circuit can be represented as a composite of d Clifford circuits separated by any layer of 1-qubit non-Clifford gates.

[0020] Quantum error mitigation (QEM) can be considered a set of tools or strategies for improving the reliability of quantum circuits running on noisy quantum hardware. Unlike quantum error correction (QEC), QEM can involve overhead reduction in terms of auxiliary qubits or circuit depth. Non-restrictive examples of QEM may include zero-noise extrapolation, stochastic error cancellation, virtual entanglement distillation, and symmetry verification.

[0021] Unfortunately, most QEM techniques are only applicable to quantum algorithms that utilize the readout of expected values ​​(for example, expected values

number

number

[0022] One QEM technique applicable to quantum algorithms that utilize single-shot readouts is the two-face Pauli check. The two-face Pauli check enables single-shot error mitigation for any circuit composed of Clifford gates. In particular, for any given Clifford circuit, the two-face Pauli check detects errors in the given Clifford circuit by verifying the commutativity law (e.g., a commutative identity or equivalence relation) between the given Clifford circuit and a pair of Pauli operators controlled by the auxiliary qubit that sandwich the given Clifford circuit (e.g., located on both its left and right sides). Due to such sandwiching, the two-face Pauli check may be called a Pauli sandwich. To increase the likelihood of error detection, multiple two-face Pauli checks, each controlled by its own or unique auxiliary qubit, can be nested together around a given Clifford circuit. For the sake of simplicity, a given Clifford circuit and controlled Pauli operator can be referred to as a data qubit, while an auxiliary qubit that controls the controlled Pauli operator can be referred to as a check qubit instead.

[0023] While two-sided Pauli checks can enable the reduction of single errors and may therefore be considered advantageous over most QEM techniques, the inventors of the various embodiments described herein recognized that two-sided Pauli checks may nevertheless be considered plagued by various disadvantages.

[0024] Specifically, the inventors recognized that two-faced Pauli checks suffer from significant hardware limitations. Indeed, two-faced Pauli checks are generally implemented by an all-to-all connection topology between check qubits and data qubits. In other words, two-faced Pauli checks typically require each data qubit to be physically coupled to each check qubit so that each two-faced Pauli check can be controlled by its respective check qubit. Unfortunately, such an all-to-all connection topology can be considered a complex and difficult hardware architecture to implement, and such complexity and difficulty can become severe as the number of data qubits and check qubits increases. Here, such an all-to-all connection topology can be avoided by implementing interleaved SWAP gates. That is, for any suitable positive integer n, each n-qubit controlled Pauli operator in a two-faced Pauli check can be considered as the tensor product of n controlled Pauli gates, each of which can be followed by its respective SWAP gate. In other words, SWAP gates can be interleaved, scattered, or otherwise interdigitated across the entire two-faced Pauli check. When implemented on a linear nearest neighbor connection topology (which may be easier or less complex to construct than an all-to-all connection topology), such interleaved SWAP gates can combine the logical states of each data qubit and each check qubit at some point in time. More generally, for any given connection topology and any given controlled Pauli gate, SWAP gates can be executed until the target qubit and controlled qubit of the given controlled Pauli gate are in a coupled neighborhood. At that point, the given controlled Pauli gate may be executed to return the qubit connectivity to its original order, and more SWAP gates may be executed. This process can be repeated for any suitable number of controlled Pauli gates.Such use of SWAP gates may allow two-sided Pauli checks to be performed in the absence of an all-to-all connected topology, but it significantly increases circuit depth and, consequently, computational overhead (for example, the number of required SWAP gates can increase exponentially with the number of data or check qubits). Thus, two-sided Pauli checks require an undesirable trade-off between architectural complexity and circuit depth (for example, a lower circuit depth can be utilized if a difficult-to-implement hardware topology is used; or, if the circuit depth is significantly increased by SWAP gates, an easier-to-implement hardware topology can be used).

[0025] In addition, the inventors recognized that two-sided Pauli checks may be considered to have a post-select rate that is not as high as they could inherently be, and a logic error rate that is not as low as they could inherently be. The term "post-select rate" may refer to the probability or possibility that all of the set of Pauli checks associated with a given Clifford circuit indicate that no error occurred during the execution of the given Clifford circuit. In contrast, the term "logic error rate" may refer to the probability or possibility that an error occurred during the execution of a given Clifford circuit, even though all of the set of two-sided Pauli checks indicate that no error occurred. In other words, the term "post-select rate" may be considered to be the probability that a set of Pauli checks indicates no error, while the term "logic error rate" may instead be considered to be the probability that a set of Pauli checks produces a false negative (e.g., incorrectly indicates no error). It may be desirable to maximize or otherwise increase the post-select rate while simultaneously minimizing or otherwise reducing the logic error rate.

[0026] The inventors have devised various techniques, described herein, that may help address or improve upon the various technical problems described above that plague two-sided Pauli checks. In particular, the inventors have devised what they call generalized Pauli checks. As described herein, generalized Pauli checks may include or otherwise consist of one or more controlled Pauli operators, which are inserted inside, within, or otherwise throughout a given Clifford circuit, such that the multiplicative product of the backpropagation of the one or more controlled Pauli operators satisfies some error mitigation criterion. In some cases, the error mitigation criterion may be that the multiplicative product is equal to that of the identity operator (without regard to phase). In other cases, the error mitigation criterion may instead be that the multiplicative product is equal to the backpropagation of some other Pauli operator randomly inserted into a given Clifford circuit. In further instances, the error mitigation criterion may be that the multiplication product is an element of a stabilizer group known to be associated with a given Clifford circuit. In any such case, as long as the error mitigation criterion is met, one or more controlled Pauli operators can function as a valid Pauli check for a given Clifford circuit, or otherwise play a role. Unlike two-face Pauli checks, the generalized Pauli checks described herein do not require any particular hardware topology or implementation of interleaved SWAP gates. In other words, as described herein, the generalized Pauli checks can be identified for a given Clifford circuit regardless of the qubit coupling topology on which the given Clifford circuit is executed. Thus, the various embodiments described herein can be considered to have significantly reduced or mitigated hardware constraints or computational overhead compared to two-face Pauli checks. Furthermore, the inventors experimentally verified that a generalized Pauli check set can exhibit a significantly higher post-selection rate and a significantly lower logic error rate than an equivalent two-sided Pauli check set.In other words, the various embodiments described herein not only have fewer constraints and lower overhead than the two-sided Pauli check, but such embodiments also significantly surpass the two-sided Pauli check in terms of error reduction capabilities. Therefore, the various embodiments described herein can be considered a technical improvement over the two-sided Pauli check.

[0027] Various embodiments described herein may be considered computerized tools (e.g., any preferred combination of computer executable hardware or computer executable software) that can facilitate error mitigation of Clifford circuits by generalized Pauli checks. In various embodiments, such computerized tools may include access components and detection components.

[0028] In various embodiments, quantum computers may exist. In various embodiments, a quantum computer may contain any suitable number of qubits. In various cases, such qubits may exhibit any suitable structure, construction, or architecture (e.g., superconducting qubits, spin qubits, or quantum dots). In various cases, some of such qubits may be considered or otherwise referred to as data qubits, and others of such qubits may be considered or otherwise referred to as check qubits. In various embodiments, the data qubits and check qubits of a quantum computer may be arranged or connected according to any suitable coupling topology.

[0029] Clifford circuits can exist in various scenarios. In various cases, Clifford circuits can be configured to operate on data qubits in a quantum computer.

[0030] In various embodiments, it may be desirable to execute Clifford circuits on the data qubits of a quantum computer in a single-shot noise reduction manner. As described herein, computerized tools can facilitate such execution.

[0031] In various embodiments, the access component of a computerized tool may electronically access a quantum computer via any suitable wired or wireless electronic connection. In various cases, the access component may further access, or otherwise receive, acquire, or import, a Clifford circuit from any suitable source. For example, the access component may obtain a Clifford circuit remotely or locally from any suitable centralized or decentralized data structure (e.g., graph data structures, relational data structures, hybrid data structures). In any case, the access component is able to access the quantum computer or the Clifford circuit, and as a result, other components of the computerized tool may electronically interact with the quantum computer (e.g., power on, power off, initialize, control) or electronically interact with the Clifford circuit (e.g., read, write, edit, copy, manipulate, execute).

[0032] In various embodiments, the detection component of a computerized tool may electronically detect errors in a Clifford circuit by leveraging a set of generalized Pauli checks. More specifically, the generalized Pauli checks may be one or more Pauli operators that can operate on the data qubits of a quantum computer, which may be inserted inside or otherwise throughout the Clifford circuit and may be controlled by each or a unique check qubit of the quantum computer. In various embodiments, one or more Pauli operators may be selected such that their backpropagation (e.g., to the front or starting position of the Clifford circuit) may have a multiplication product that satisfies any preferred error mitigation criterion. In some cases, the error mitigation criterion may be that the multiplication product of the backpropagation is equal to the identity operator up to the global phase (e.g., if phase information is ignored). In other cases, the error mitigation criterion may be that the multiplication product of the backpropagation is equal to the backpropagation of some other Pauli operator randomly inserted within the Clifford circuit. In further instances, the error mitigation criterion may be that the backpropagation multiplication product is an element of a stabilizer group known to be associated with a Clifford circuit. In any such case, the detection component can initialize the data qubit and check qubit in any preferred manner (e.g., all initialized to |0>) and perform the Clifford circuit and generalized Pauli check on the quantum computer. After such an execution, the detection component can measure the quantum states of the check qubit and data qubit in any preferred basis (e.g., an X basis).

[0033] In various embodiments, the measured state of the check qubits can be considered to indicate whether or not an error was detected in the Clifford circuit. For example, if each of the measured states of the check qubits is |0>, the detection component may conclude that no error was detected in the Clifford circuit (e.g., that no error occurred in the Clifford circuit, or that an undetected error occurred in the Clifford circuit). In such a case, the measured state of the data qubits can be considered reliable. On the other hand, if at least one of the measured states of the check qubits is |1>, the detection component may conclude that an error was detected in the Clifford circuit. In such a case, the measured state of the data qubits can be considered unreliable (e.g., contaminated by some error). Therefore, the detection component may reinitialize the data qubits and check qubits and rerun the Clifford circuit and generalized Pauli checks until all of the measured states of the check qubits are |0>. In other words, the detection component may post-select that all check qubits are |0>.

[0034] In various embodiments, each particular generalized Pauli check can be considered capable of detecting a certain percentage of any errors (e.g., Pauli errors) that may occur within a Clifford circuit. In other words, each additional generalized Pauli check can be considered to progressively or incrementally reduce the percentage of undetected errors that may occur within a Clifford circuit, regardless of the particular form of the Clifford circuit. To put it another way, generalized Pauli checks can significantly reduce the likelihood that non-identifiability errors affecting a Clifford circuit may remain undetected, and such error reductions apply regardless of which particular Clifford gates are implemented within the Clifford circuit and how those particular Clifford gates are arranged or ordered.

[0035] It should be noted that a generalized Pauli check does not require any special qubit coupling topology or interleaved SWAP gates to operate or function. That is, a valid generalized Pauli check can be identified for any Clifford circuit, regardless of the specific coupling topology used to execute the Clifford circuit.

[0036] In particular, in some embodiments, the detection component may identify which generalized Pauli check should be used for a Clifford circuit based on the locations of several candidate locations associated with the Clifford circuit. In some embodiments, the locations of the several candidate locations may be identified or provided by a user or technician of the quantum computer (e.g., via any suitable human-computer interface device, e.g., a keyboard or touchscreen), and each candidate location is a qubit-timestep tuple in the Clifford circuit that has been designated or indicated as suitable or acceptable for the insertion of a Pauli operator. In other words, each candidate location may be any suitable electronic data that identifies each data qubit that a controlled Pauli operator could potentially treat as a target (e.g., data qubits not coupled to any check qubit may be excluded from the locations of the several candidate locations); and each circuit timestep on which a controlled Pauli operator may be executed (e.g., the circuit timestep may indicate where in the sequence of all quantum gates executed on each data qubit a controlled Pauli operator may be inserted or positioned). In some cases, multiple candidate positions may strategically include a "hole" in the Clifford circuit, where the "hole" could be some qubit-timestep tuple in the Clifford circuit where the quantum gate of the Clifford circuit is not executed.

[0037] In any case, each given candidate position may be filled with one of three candidate Pauli operators: a controlled Pauli-X operator with weight 1 may be inserted at the given candidate position; a controlled Pauli-Y operator with weight 1 may be inserted at the given candidate position; or a controlled Pauli-Z operator with weight 1 may be inserted at the given candidate position. Thus, multiple candidate positions can be considered to correspond to multiple candidate Pauli operators, respectively. In various embodiments, the detection component may compute a backpropagation for each of the multiple candidate Pauli operators, thereby yielding multiple backpropagations. In various embodiments, the detection component may convert each of the above multiple backpropagations into its respective Boolean encoding (e.g., its respective bit string), thereby yielding multiple Boolean encodings. In various embodiments, the detection component may stack multiple Boolean encodings on top of each other, thereby yielding a stacked array. In some embodiments, the detection component may randomly shuffle the stacked array. In various cases, the detection component may identify which generalized Pauli checks are valid for a Clifford circuit by analyzing a stacked array according to an error mitigation criterion. As a non-restrictive example, if the error mitigation criterion is equality to the identity operator, the detection component may identify generalized Pauli checks by computing the zero space of the stacked array (e.g., by identifying which combinations of rows in the stacked array sum to zero). As another non-restrictive example, if the error mitigation criterion is equality to the backpropagation of randomly inserted Pauli operators or the belonging of a group of stabilizers in a Clifford circuit, the detection component may identify generalized Pauli checks by applying any suitable syndrome decoding technique to the stacked array. In either case, the detection component can be considered to be performing linear algebraic operations on the stacked area to identify which combinations of rows in the stacked array, and consequently which combinations of the above candidate Pauli operators, form a valid generalized Pauli check.Following such a search, the detection component may insert one or more of the effective generalized Pauli checks into the Clifford circuit.

[0038] Therefore, the generalized Pauli check described herein can be applied regardless of the hardware coupling topology that will be used to implement the Clifford circuit, and without interleaving a vast number of SWAP gates within the Clifford circuit. This should be contrasted with the two-sided Pauli check, which requires either: an all-to-all coupling topology that is extremely difficult to manufacture; or, in the absence of an all-to-all coupling topology, a multitude of SWAP gates resulting in excessively extended circuit depth.

[0039] In addition, the inventors experimentally verified that generalized Pauli checks may outperform two-sided Pauli checks in terms of error reduction. Indeed, various experiments conducted by the inventors confirmed that a set of generalized Pauli checks can achieve both a significantly improved post-select rate and a significantly reduced logic error rate compared to an equivalent set of two-sided Pauli checks. Thus, generalized Pauli checks are not only more relaxed than two-sided Pauli checks in terms of hardware constraints and circuit depth, but they also offer extended or improved error reduction compared to two-sided Pauli checks.

[0040] Various embodiments described herein may be employed using hardware or software to solve problems that are inherently highly technical, not abstract, and cannot be performed as a set of mental activities by humans (e.g., facilitating improvements in error mitigation for Clifford circuits by generalized Pauli checks). Furthermore, some of the processes performed may be carried out by a dedicated computer (e.g., a quantum computer with tangible qubits capable of executing or implementing quantum circuits). In various embodiments, some defined tasks associated with the various embodiments described herein may include: a device operably coupled to a processor executing a Clifford circuit on a set of data qubits; and the device detecting errors in the execution of the Clifford circuit by measuring a set of check qubits that control a set of Pauli operators inserted in the Clifford circuit, where the product of the backpropagation of the set of Pauli operators satisfies the error mitigation criterion. In some cases, a device may identify a set of Pauli operators to be inserted into a Clifford circuit based on: the device computes the backpropagation of each candidate Pauli operator associated with a candidate position in the Clifford circuit, thereby yielding backpropagations of multiple candidates; the device stacks the Boolean encodings of each of the above candidate backpropagations, thereby yielding a stacked array; and the device computes the zero space of the stacked array, or otherwise the device applies a syndrome decoding algorithm or technique to the stacked array. In some cases, the error mitigation criterion may be that the product is equal to the identity operator up to the global phase. In other cases, the error mitigation criterion may be that the product is equal to the backpropagation of randomly inserted Pauli operators in the Clifford circuit. In yet another case, the error mitigation criterion may be that the product exists in a set of stabilizers associated with the Clifford circuit.

[0041] Neither the human mind nor a person with a pen and paper can electronically access a Clifford circuit, electronically insert controlled Pauli operators into a Clifford circuit such that the multiplication product of its own backpropagation satisfies some threshold criterion, nor can it electronically detect errors in a Clifford circuit by executing controlled Pauli operators. Ultimately, a quantum computer is a dedicated piece of computing hardware that utilizes physical qubits (e.g., superconducting qubits such as transmons) for processing information. Physical qubits cannot be implemented by the human mind or by a person with a pen and paper. Furthermore, a quantum circuit can be a sequence of quantum gates that can be executed on a quantum computer. Neither the human mind nor a person with a pen and paper can insert quantum gates (e.g., controlled Pauli operators) into a Clifford circuit, nor can it execute quantum gates on physical qubits. Therefore, a computerized tool capable of detecting errors in a Clifford circuit by implementing controlled Pauli checks inserted into the Clifford circuit such that its own backpropagation satisfies some threshold criterion is inherently computerized and cannot be implemented in any practical, operational, or rational way without a computer.

[0042] In various cases, one or more embodiments described herein may integrate the teachings described herein into practical applications. As mentioned above, existing techniques for facilitating single-error mitigation utilize two-sided Pauli checks. Similarly, as mentioned above, the inventors were aware that two-sided Pauli checks suffer from various technical problems.

[0043] Firstly, the inventors recognized that two-face Pauli checks require an undesirable trade-off between hardware complexity and circuit depth. Indeed, two-face Pauli checks typically take the form of an all-to-all qubit coupling topology. An all-to-all qubit coupling topology means that each check qubit is physically coupled to each data qubit, and as a result, a two-qubit entanglement gate can be executed between each of the unique check-data qubit pairs. Unfortunately, physically constructing or fabricating an all-to-all qubit coupling topology is not a trivial task: such construction or fabrication involves complex resonator layouts and an increased risk of quantum crosstalk or interference. In other words, all-to-all coupling topologies can be considered difficult, cumbersome, or expensive hardware architectures. Here, two-face Pauli checks can be implemented on topologies that are less complex than all-to-all qubit coupling topologies (e.g., on linear nearest neighbor topologies which may be considered easier to build), however such implementations require the inclusion of a very large number of (e.g., tens, hundreds, or thousands) of SWAP gates. Such a large number of SWAP gates can be seen as dramatically increasing circuit depth and, consequently, the computational overhead associated with two-sided Pauli checks.

[0044] Secondly, the inventors recognized that the error reduction execution showed that there was room for improvement in the two-sided Pauli check. Specifically, the inventors recognized that it would be beneficial to improve the post-select rate achievable by the two-sided Pauli check and to reduce the logic error rate achievable by the two-sided Pauli check.

[0045] Accordingly, the inventors have devised various embodiments described herein that can be considered to solve, address, or otherwise improve upon the technical problems plaguing two-sided Pauli checks. In particular, the various embodiments described herein may include detecting errors in Clifford circuits by implementing what the inventors call generalized Pauli checks. As described herein, generalized Pauli checks are, or otherwise include, one or more controlled weighted 1-Pauli operators inserted inside a Clifford circuit such that the multiplicative product of the backpropagation of one or more controlled weighted 1-Pauli operators satisfies some criterion (e.g., being equal to the identity operator; being equal to the backpropagation of some randomly inserted Pauli operator; being in a group of stabilizers in the Clifford circuit). Generalized Pauli checks can function or serve the same purpose as two-sided Pauli checks but without sacrificing circuit depth to reduce hardware complexity. Indeed, generalized Pauli checks do not require any special or specific qubit coupling topology (e.g., an all-to-all coupling topology). Instead, a valid generalized Pauli check can be identified for any given topology without relying on interleaved SWAP gates (e.g., by analyzing a stacked array of Boolean encodings of the backpropagation of candidate Pauli operators). Thus, generalized Pauli checks can be considered to have significantly fewer hardware constraints than two-face Pauli checks. In addition, experiments conducted by the inventors show that generalized Pauli checks can achieve higher post-select rates and lower logic error rates than two-face Pauli checks. In other words, the inventors have experimentally verified that the generalized Pauli checks described herein can exhibit significantly better error mitigation performance than two-face Pauli checks. Thus, such embodiments can be considered to result in a quantifiable performance improvement in the field of quantum error mitigation. For example, single-error detection using generalized Pauli checks may exhibit a higher level of accuracy or reliability compared to existing techniques (or achieve a comparable level of accuracy with fewer checks).As another example, single-shot error detection using generalized Pauli checks may consume fewer computational resources compared to existing techniques (e.g., it may require fewer quantum gate executions). Yet another example is that single-shot error detection using generalized Pauli checks may relax hardware architecture requirements or otherwise reduce the cost of controlled Not (CNOT) compared to existing techniques. These are concrete and tangible technical improvements or effects in the field of quantum circuits. For at least these reasons, the various embodiments described herein certainly constitute useful and practical applications of computers.

[0046] It should be understood that the figures and disclosures herein illustrate non-limiting examples of various embodiments. Furthermore, it should be noted that the figures are not necessarily drawn to scale.

[0047] Figure 1 illustrates a block diagram of an exemplary and non-limiting system 100 that can facilitate error mitigation of a Clifford circuit by generalized Pauli check according to one or more embodiments described herein. As shown, the Pauli check system 102 may be electronically integrated with a quantum computer 104 and a Clifford circuit 110 via any preferred wired or wireless electronic connection.

[0048] In various embodiments, the quantum computer 104 may be any suitable quantum computing device or quantum computing hardware. In various embodiments, the quantum computer 104 may comprise a set of data qubits 106. In various embodiments, the set of data qubits 106 may comprise n qubits: data qubit 106(1) to data qubit 106(n) for any suitable positive integer n. In various embodiments, the quantum computer 104 may comprise a set of check qubits 108. In various embodiments, the set of check qubits 108 may comprise m qubits: check qubit 108(1) to check qubit 108(m) for any suitable positive integer m. In various embodiments, any of the sets of data qubits 106 or any of the sets of check qubits 108 may exhibit any suitable structure or architecture. As an unrestricted example, any of such qubits may exhibit a superconducting qubit architecture (for example, such a qubit may be constructed from any number of suitable Josephson junctions shunted by any number of suitable planar capacitor pads). As another unrestricted example, any of such qubits may exhibit a quantum dot architecture. As yet another unrestricted example, any of such qubits may exhibit a spin qubit architecture. In various embodiments, different qubits of a set of data qubits 106 or a set of check qubits 108 may exhibit the same or different structures or architectures as one another.Although not explicitly shown in Figure 1, the quantum computer 104 may be equipped with, or otherwise associated with, any suitable hardware or software (e.g., a real-time controller implemented within the field-programmable gate array of the quantum computer 104), which may be used to initialize any set of data qubits 106 or any set of check qubits 108, or to perform any suitable quantum operations (e.g., quantum gates, qubit measurements, qubit idling) on ​​the set of data qubits 106 or the set of check qubits 108.

[0049] In various embodiments, the Clifford circuit 110 can be any suitable sequence of Clifford gates (e.g., Hadamard gates (H), phase gates (S), or CNOT gates) that can be executed in parallel or series on the set of data qubits 106. Thus, in various cases, the Clifford circuit 110 is an n-qubit Clifford circuit (e.g., a Clifford circuit that can operate on n qubits, an n-th order tensor product; 2 n ×2 n It can be considered as a matrix. In some cases, the Clifford circuit 110 can be a Clifford layer in a larger, non-Clifford quantum circuit.

[0050] In various cases, it may be desirable to use single-shot error mitigation to execute the Clifford circuit 110 on a set of data qubits 106. As described herein, the Pauli check system 102 can facilitate such execution and single-shot error mitigation.

[0051] In various embodiments, the Pauli-check system 102 may include a processor 112 (e.g., a computer processing unit, a microprocessor) and a non-temporary computer-readable memory 114 operably connected to or coupled to the processor 112. The memory 114 may store computer-executable instructions that, when executed by the processor 112, cause the processor 112 or other components of the Pauli-check system 102 (e.g., an access component 116, a detection component 118) to perform one or more operations. In various embodiments, the memory 114 may store computer-executable components (e.g., an access component 116, a detection component 118), and the processor 112 may execute the computer-executable components.

[0052] In various embodiments, the Pauli-Czek system 102 may include an access component 116. In various embodiments, the access component 116 may electronically access the quantum computer 104 in any preferred manner, and as a result, the Pauli-Czek system 102 may initialize, electronically start (e.g., power on), electronically stop (e.g., power off), or otherwise electronically control the quantum computer 104. Furthermore, in various cases, the access component 116 may electronically receive, acquire, obtain, import, or otherwise access the Clifford circuit 110 from any preferred data structure or any preferred computing device. In any case, the access component 116 may electronically access the quantum computer 104 or the Clifford circuit 110 (e.g., send or receive data or program instructions to or from them), and as a result, other components of the Pauli-Czek system 102 may electronically interact with the quantum computer 104 or the Clifford circuit 110.

[0053] In various embodiments, the Pauli check system 102 may include a detection component 118. In various cases, the detection component 118 may electronically execute the Clifford circuit 110 on a set of data qubits 106. In some cases, as described herein, the detection component 118 may electronically detect errors associated with such execution by utilizing a set of generalized Pauli checks inserted throughout the Clifford circuit 110 and controlled by a set of check qubits 108, respectively.

[0054] It should be noted that in various cases, the access component 116 and the detection component 118 may be considered collectively as one or more software components 115 of the Pauli Check system 102. In various embodiments, for the sake of simplicity of description and illustration, it should be understood that in this specification, one or more software components 115 are primarily described as comprising two components (e.g., the access component 116 and the detection component 118). However, one or more software components 115 are not limited to being implemented as precisely such two components in every embodiment. Indeed, in some embodiments, the functions described herein for such two components may be combined in any preferred manner so as to be implemented in or by fewer than two components (for example, in some cases, a single component may perform all the functions described herein with respect to the access component 116 and the detection component 118). In other embodiments, the functions of such two components described herein may instead be distributed, separated, divided, or subdivided in any preferred manner so as to be implemented in or by more than two components (for example, two or more components may facilitate a function that can be performed by the access component 116; two or more components may facilitate a function that can be performed by the detection component 118).

[0055] Figure 2 illustrates a block diagram of an exemplary and non-limiting system 200, which includes a set of generalized Pauli checks and errors that may facilitate error mitigation of Clifford circuits by generalized Pauli checks, according to one or more embodiments described herein. As shown, system 200 may in some cases comprise the same components as system 100 and further comprise a set of generalized Pauli checks 202 and errors 204.

[0056] In various embodiments, each set of generalized Pauli checks 202 may correspond to a set of check qubits 108 (e.g., in a one-to-one manner). Thus, since a set of check qubits 108 may have m qubits, a set of generalized Pauli checks 202 may have m Pauli checks: from the first generalized Pauli check to the mth generalized Pauli check. In various embodiments, each set of generalized Pauli checks 202 may have one or more non-identical Pauli operators of weight 1, operating on a set of data qubits 106, controlled by each set of check qubits 108, and inserted inside or otherwise into the Clifford circuit 110 by a detection component 118.

[0057] As a non-restrictive example, the first generalized Pauli check in the set of generalized Pauli checks 202 may be one or more n-qubit Pauli operators, each of which may be a tensor product between a non-identical 1-qubit Pauli gate (e.g., a 2x2 Pauli X gate, a 2x2 Pauli Y gate, or a 2x2 Pauli Z gate) and a total of (n-1) 1-qubit identity gates (e.g., (n-1) copies or instantiations of a 2x2 identity gate), where the 1-qubit Pauli gate can operate on any of the set of data qubits 106, and the 1-qubit Pauli gate may be controlled by a check qubit 108(1). Note that which particular one of the set of data qubits 106 the non-identical 1-qubit Pauli gate is configured to act on may indicate where the non-identical 1-qubit Pauli gate lies within the tensor product.

[0058] As another non-restrictive example, the mth generalized Pauli check in the set of generalized Pauli checks 202 can be one or more n-qubit Pauli operators, or otherwise contain them, each of which may be a tensor product between a non-identical 1-qubit Pauli gate and a total of (n-1) 1-qubit identity gates, the 1-qubit Pauli gate may operate on any of the set of data qubits 106, and the 1-qubit Pauli gate may be controlled by a check qubit 108(m). Just as above, which particular one of the set of data qubits 106 the non-identical 1-qubit Pauli gate is configured to operate on may indicate where the non-identical 1-qubit Pauli gate lies within the tensor product.

[0059] In either case, the detection component 118 may insert any non-identical Pauli operator of weight 1 that constitutes a given generalized Pauli check of the set of generalized Pauli checks 202 inside the Clifford circuit 110 such that the multiplicative product of the backpropagation of the non-identical Pauli operators of weight 1 satisfies any preferred error mitigation criterion.

[0060] In various embodiments, the detection component 118 may electronically execute a set of generalized Pauli checks 202 and the Clifford circuit 110 on the quantum computer 104, and the resulting measured state of the set of check qubits 108 can indicate, communicate, or otherwise represent whether an n-qubit Pauli error associated with the Clifford circuit 110 has been detected. In various cases, such an error may be referred to as error 204. In various embodiments, the detection component 118 may repeatedly execute the Clifford circuit 110 and the set of generalized Pauli checks 202 until no more errors 204 are detected. Various non-limiting embodiments are described with respect to Figures 3 to 6.

[0061] Figure 3 illustrates an exemplary and non-limiting block diagram 300 relating to a generalized Pauliczek according to one or more embodiments described herein.

[0062] In various embodiments, a generalized Pauli check 302 may be any one of the set of generalized Pauli checks 202. In various embodiments, as shown, a generalized Pauli check 302 may have, possess, or otherwise be constructed from a set of Pauli operators 304. In various cases, the set of Pauli operators 304 may include k operators: Pauli operator 304(1) to Pauli operator 304(k) for any preferred positive integer k. In various cases, each of the set of Pauli operators 304 may be a non-identical Pauli operator of weight 1, configured to operate on any of the set of data qubits 106 and controlled by a single, common check qubit 108.

[0063] As a non-restrictive example, assume that the generalized Pauli check 302 is controlled by a check qubit 108(j) for any suitable positive integer 1 ≤ j ≤ m. In such a case, the Pauli operator 304(1) is formed by the tensor product of any 2 × 2 non-identical Pauli gates and n-1 instantiations of the 2 × 2 identity gate. n ×2 n It can be a matrix (for example, a first n-qubit matrix). More specifically, assume that the Pauli operator 304(1) is configured to operate on data qubits 106(i) for any suitable positive integer 1 ≤ i ≤ n. In such a case, the Pauli operator 304(1) is:

number

Number

[0064] Note that different sets of Pauli operators 304 may operate on the same or different sets of data qubits 106. Similarly, note that different sets of Pauli operators 304 may operate at the same or different circuit timesteps. Indeed, in some cases, any set of Pauli operators 304 may be configured to run simultaneously or in parallel with each other, or any set of Pauli operators 304 may be configured to run sequentially or in series with each other. Note that any two sets of Pauli operators 304 configured to run sequentially or in series with each other may, in some cases, not be separated by the quantum gates of the Clifford circuit 110, or in other cases, be separated by one or more quantum gates of the Clifford circuit 110. That is, any two Pauli operators configured to run at different circuit timesteps may be considered chronologically consecutive (e.g., one runs before the other), even though the two Pauli operators may not be configured to run at immediately adjacent timesteps. Additionally, it should be understood or otherwise recognized that no two of the Pauli operators 304 can be configured to perform their respective non-identity operations on the same data qubits simultaneously. That is, if any two or more of the Pauli operators 304 are configured to perform their respective non-identity operations on the same data qubits as each other, then those two or more of the Pauli operators 304 can be considered configured to run at different circuit timesteps (e.g., not simultaneously). Conversely, if two or more of the Pauli operators 304 are configured to perform their respective non-identity operations simultaneously or in parallel with each other, then those two or more of the Pauli operators 304 can be considered configured to perform their respective non-identity operations on different data qubits.

[0065] In various embodiments, the detection component 118 can electronically insert or position a set of Pauli operators 304 inside or within the Clifford circuit 110 such that the multiplicative product of the backpropagation of the set of Pauli operators 304 satisfies any preferred error mitigation criterion (for example, the set of Pauli operators 304 can be scattered throughout the Clifford circuit 110). More specifically, P n i However, for any suitable positive integer 1 ≤ i ≤ k, this represents the i-th of the set of Pauli operators 304 (where the superscript n is P n i This can be expressed as an n-qubit Pauli operator, in contrast to a 1-qubit Pauli gate. Furthermore, C before However, P n i Let C represent all the quantum gates of the Clifford circuit 110, which is configured to be executed before C. after However, P n i Let P represent all the quantum gates of the Clifford circuit 110 that are configured to be executed after P. n i If configured to run at the same circuit time step (but on different data qubits), note that the circuit time step will be divided or subdivided into two new circuit time steps, and one of these two new circuit time steps may occur immediately before the other. Therefore, P n i The quantum gate may be assigned to one of the two new circuit timesteps, and the quantum gate may be assigned to the other of the two new circuit timesteps, and accordingly, the quantum gate may be assigned to C as appropriate. before or C after It may be considered part of the same. In any case, the detection component 118 moves the Clifford circuit 110 to the starting position, start, or forward P as shown below. n i The backpropagation of can be calculated:

number

number

[0066] The disclosure herein primarily describes various embodiments in which the detection component 118 propagates Pauli operators backward to the start, beginning, or forward position of the Clifford circuit 110, but these are merely non-limiting examples. In other embodiments, the detection component 118 may instead propagate Pauli operators to any other time step of the Clifford circuit 110 (e.g., to the end of the Clifford circuit 110, to any intermediate time step within the Clifford circuit 110). Various embodiments may function as intended or described, as long as the detection component 118 propagates different Pauli operators to the same circuit time step as each other.

[0067] In various cases, the detection component 118 can compute the respective backpropagation for each of the set of Pauli operators 304 (C before and C after Note that this can differ for different sets of Pauli operators 304, thereby resulting in multiple backpropagations. In various cases, if the multiplication product of these multiple backpropagations satisfies any suitable error mitigation criterion, the set of Pauli operators 304 can be considered to form a valid generalized Pauli check. In other words, Π ki=1 B(P n i If the error mitigation criteria are met, the generalized Pauli check 302 may be considered capable of appropriately or effectively detecting errors during the execution of the Clifford circuit 110.

[0068] In some embodiments, the error mitigation criterion may be equal to the n-qubit identity operator. That is, the generalized Paulič 302 is Π k i=1 B(P n i )=I n If this is the case, it can be considered that errors can be appropriately or effectively detected during the execution of the Clifford circuit 110, where I n is 2 n ×2 n It is the identity matrix.

[0069] In other embodiments, the error mitigation criterion may instead be equal to the backpropagation of one or more other Pauli operators randomly inserted into the Clifford circuit 110 by the detection component 118. In particular, assume that for any preferred positive integer q, the detection component 118 randomly inserts a total of q non-identical n-qubit Pauli operators of weight 1 into the Clifford circuit 110 (for example, the detection component 118 may randomly select which data qubits and on which circuit timestep the q randomly inserted Pauli operators operate). Note that such q randomly inserted Pauli operators are separate from the Pauli operators that constitute the set of generalized Pauli checks 202. In such a case, the generalized Pauli checks 302 are Π k i=1 B(P n i )=Π q j=1 B(P n random j If ) then it can be considered that errors can be appropriately or effectively detected during the execution of the Clifford circuit 110, where Π q j=1 B(P n random j) represents the multiplication product of the backpropagation of q randomly inserted Pauli operators. In other words, Π k i=1 B(P n i )≠I n Even in such cases, the generalized Paulicheck 302 can be effective or otherwise effective.

[0070] In yet another embodiment, the error mitigation criterion may instead be belonging to or being present in a group of stabilizers of the Clifford circuit 110 (for example, belonging to or being present in a mathematical group of unitary transforms that leave the quantum states associated with the Clifford circuit 110 unchanged). Specifically, assume that the Clifford circuit 110 has a group of stabilizers represented by S. In such a case, the generalized Paulicheck 302 is Π k i=1 B(P n i If )∈S, it can be considered that errors can be appropriately or effectively detected during the execution of the Clifford circuit 110. Again, this is because Π k i=1 B(P n i )≠I n Even in such cases, this demonstrates that generalized Paulicheck 302 can be effective or otherwise effective.

[0071] In some embodiments, the error mitigation criterion may involve both a group of stabilizers associated with the Clifford circuit 110 and arbitrary non-identical n-qubit Pauli operators of weight 1 randomly inserted into the Clifford circuit 110. In particular, the detection component 118 again assumes that a total of q non-identical n-qubit Pauli operators of weight 1 are randomly inserted into the Clifford circuit 110 (again, such q operators are separate from those that constitute the set of generalized Pauli checks 202), and also assumes that the Clifford circuit 110 has a group of stabilizers indicated by S. In such a case, the generalized Pauli check 302 is (Π q j=1 B(Pn random j ))(Π k i=1 B(P n i If ))∈S, it can be considered that errors can be appropriately or effectively detected during the execution of the Clifford circuit 110. Again, this is because Π k i=1 B(P n i )≠I n Even in such cases, this demonstrates that generalized Paulicheck 302 can be effective or otherwise effective.

[0072] In either case, if the product of the backpropagation of the set of Pauli operators 304 satisfies the error mitigation criteria, the generalized Pauli check 302 can function as a suitable or appropriate check for the Clifford circuit 110.

[0073] In various embodiments, each set of generalized Pauli checks 202 can be constructed or designed similarly to generalized Pauli checks 302. That is, each set of generalized Pauli checks 202 may consist of one or more n-qubit Pauli operators of weight 1, which are inserted into or throughout the Clifford circuit 110 such that the product of the backpropagation of the one or more n-qubit Pauli operators of weight 1 satisfies the error mitigation criterion. Note that different sets of generalized Pauli checks 202 may consist of the same or different numbers, types, or configurations of n-qubit Pauli operators of weight 1.

[0074] In various embodiments, the detection component 118 can electronically execute a set of Clifford circuits 110 and generalized Pauli checks 202 on the quantum computer 104. That is, the detection component 118 can initialize the state of a set of data qubits 106 and a set of check qubits 108 in any preferred manner, and can operate on the initialized state according to quantum operations specified or otherwise required by the set of Clifford circuits 110 and generalized Pauli checks 202. After such execution, the detection component 118 can electronically execute the respective quantum readout or measurement operations on each of the set of data qubits 106 and each of the set of check qubits 108.

[0075] If all read-out or measured states of the set of check qubits 108 indicate that no error occurred during such execution (for example, if each of the set of check qubits 108 is in the |0> state after execution of the set of Clifford circuit 110 and generalized Pauli check 202), then the detection component 118 can conclude that the read-out or measured states of the set of data qubits 106 are reliable. Thus, the detection component 118 can take any suitable subsequent electronic action with respect to the read-out or measured states of the set of data qubits 106 (for example, electronically transmit or share the read-out or measured states of the set of data qubits 106 to any other suitable computing device; electronically render the read-out or measured states of the set of data qubits 106 on any suitable computer screen or monitor associated with the quantum computer 104).

[0076] On the other hand, if the read-out or measured state of any of the set of check qubits 108 indicates that an error occurred during such execution (for example, if at least one of the set of check qubits 108 is in the |1> state after the execution of the Clifford circuit 110 and the generalized Pauli check 202 set), then the detection component 118 may conclude that the read-out or measured state of the set of data qubits 106 is unreliable. Thus, the detection component 118 may reinitialize the sets of data qubits 106 and the sets of check qubits 108, and re-execute the Clifford circuit 110 and the generalized Pauli check 202 set until all of the set of check qubits 108 no longer indicate an error. In other words, the detection component 118 may post-select a set of check qubits 108 that all indicate that an error did not occur during the execution of the Clifford circuit 110.

[0077] Figures 4 to 6 illustrate exemplary and non-limiting schematics 400, 500, and 600 relating to a generalized PauliCzech 302 according to one or more embodiments described herein.

[0078] In the non-restrictive examples in Figures 4-6, the set of data qubits 106 has a total of four data qubits, as indicated by the abbreviated notation (e.g., "D1" represents the first data qubit in the set of data qubits 106; "D2" represents the second data qubit in the set of data qubits 106). Similarly, in the non-restrictive examples in Figures 4-6, the set of check qubits 108 has a total of one check qubit, as indicated by the abbreviated notation (e.g., "C1" represents the first and only check qubit in the set of check qubits 108).

[0079] Although not explicitly shown in Figures 4 to 6, the detection component 118 may electronically initialize the set of data qubits 106 and the set of check qubits 108 in any preferred manner. As a non-limiting example, the detection component 118 may initialize each of the set of data qubits 106 and each of the set of check qubits 108 to |0>.

[0080] First, consider Figure 4. As shown, the Clifford circuit 110 can operate on a set of data qubits 106. It should be understood, or otherwise recognized, that quantum circuit diagrams are read from left to right. Therefore, after the Clifford circuit 110 is executed, the resulting quantum state of the set of data qubits 106 can be read out or measured, as indicated by symbol 402.

[0081] Now, consider Figure 5. In various embodiments, the Clifford circuit 110 can be considered as a sequence of any preferred or desired number of smaller or shorter subcircuits. In the non-restrictive example of Figure 5, the Clifford circuit 110 is decomposed into a sequence of four subcircuits: a first subcircuit indicated by "A1"; a second subcircuit indicated by "A2"; a third subcircuit indicated by "A3"; and a fourth subcircuit indicated by "A4". As a non-restrictive example, assume that the Clifford circuit 110 is a sequence having a total of h n-qubit operators for any preferred positive integer h. In such cases, for any suitable positive integers h1, h2, h3, and h4, A1 can be considered as a subcircuit formed by the first consecutive h1 of the total h n-qubit operators, A2 as a subcircuit formed by any consecutive h2 of the total h n-qubit operators following A1, A3 as a subcircuit formed by any consecutive h3 of the total h n-qubit operators following A2, and A4 as a subcircuit formed by the last consecutive h4 of the total h n-qubit operators, where h1+h2+h3+h4=h. Thus, in linear algebraic notation, the Clifford circuit 110 can be considered equal to A4A3A2A1. Note that A1, A2, A3, and A4 do not need to satisfy any special restrictions or constraints other than that their matrix multiplication product A4A3A2A1 is equal to the Clifford circuit 110.

[0082] Next, consider Figure 6 illustrating an exemplary and non-limiting embodiment of the set of Pauli operators 304 and thus the generalized Pauli check 302, controlled by C1. In the non-limiting example of Figure 6, the set of Pauli operators 304 has a total of three operators, i.e., k=3 in circuit diagram 600. Specifically, the first Pauli operator of the set of Pauli operators 304 is designated by "P1" and is located at the circuit time step between A1 and A2. Furthermore, the second Pauli operator of the set of Pauli operators 304 is designated by "P2" and is located at the circuit time step between A2 and A3. Finally, the third Pauli operator of the set of Pauli operators 304 is designated by "P3" and is located at the circuit time step between A3 and A4. Each of these three Pauli operators can be considered an n-qubit operator obtained by the tensor product between each of the three copies of the 1-qubit non-identical Pauli gate and the 1-qubit identity gate. In particular, P1 is illustrated as having a 1-qubit identity gate operating on D1; a 1-qubit identity gate operating on D2; a non-identical 1-qubit Pauli gate operating on D3; and a 1-qubit identity gate operating on D4. Furthermore, P2 is illustrated as having a non-identical 1-qubit Pauli gate operating on D1; a 1-qubit identity gate operating on D2; a 1-qubit identity gate operating on D3; and a 1-qubit identity gate operating on D4. Moreover, P3 is illustrated as having a 1-qubit identity gate acting on D1; a 1-qubit non-identical Pauli gate acting on D2; a 1-qubit identity gate acting on D3; and a 1-qubit identity gate acting on D4. Note how all three sets of P1, P2, and P3 are controlled by C1 (for example, having C1 as a source qubit).

[0083] Here, for the set of Pauli operators 304 and thus the generalized Pauli check 302 to function as described herein, they can be selected such that the product of their backwards propagation to the start position or forward of the Clifford circuit 110 meets the error reduction criteria. The symbol 608 can be considered to indicate the start position or forward of the Clifford circuit 110. Using the backwards propagation formulation described above, the backwards propagation of P1 is

Number

Number

Number

Number

Number

Number

number

[0084] In various embodiments, as indicated by reference numeral 602, the Hadamard gate may be applied to C1 before the start or forward position of the Clifford circuit 110 (e.g., upstream). Conversely, as indicated by reference numeral 604, the Hadamard gate may be applied to C1 following the end or rear of the Clifford circuit 110 (e.g., downstream). In various cases, such a Hadamard gate can be considered to be transforming C1 into an X basis for measurement. It should be understood that any such Hadamard gate may be accompanied by a phase gate as appropriate or as desired (e.g., to take phase into account or to ignore phase). After the execution of the set of Pauli operators 304 (and any Hadamard or phase gates, where applicable), the resulting quantum state of C1 can be read out or measured as indicated by reference numeral 606. Assume that C1 is initialized to the |0> state. In such a case, if the read or measured state of C1 is |0>, this can be interpreted as meaning that no error occurred (or an undetected error occurred) during the execution of the Clifford circuit 110, and therefore the read or measured states of D1, D2, D3, and D4 can be trusted. Thus, the detection component 118 can share or display the read or measured states of D1, D2, D3, and D4. In contrast, if the read or measured state of C1 is |1>, this can be interpreted as meaning that an error occurred during the execution of the Clifford circuit 110, and therefore the read or measured states of D1, D2, D3, and D4 cannot be trusted. Thus, the detection component 118 can reinitialize the states of C1, D1, D2, D3, and D4 and re-execute the Clifford circuit 110 and the set of Pauli operators 304. The detection component 118 can repeat such actions until the state of C1 after execution is |0>.

[0085] Figure 7 illustrates an exemplary and non-limiting block diagram of a system 700, including several candidate locations, which may facilitate error mitigation for Clifford circuits by generalized Pauli checks, according to one or more embodiments described herein. As shown, system 700 may in some cases comprise the same components as system 200 and may further comprise several candidate locations 702.

[0086] In various embodiments, the access component 116 may, in any preferred manner, electronically receive, acquire, import, retrieve, or otherwise electronically access a plurality of candidate locations 702 from any preferred electronic database or data structure. As a non-limiting example, the plurality of candidate locations 702 may be electronic data provided to the access component 116 by a user or technician associated with the quantum computer 104. Indeed, such a user or technician may provide, create, select, or indicate the plurality of candidate locations 702 by interacting with any preferred human-computer interface device such as a keyboard, keypad, touchscreen, joystick, or voice control system. In any case, the detection component 118 may electronically determine or identify a set of generalized Pauli checks 202 based on the plurality of candidate locations 702. In other words, the detection component 118 can utilize multiple candidate positions 702 to determine where in the Clifford circuit 110 which weight 1 n-qubit non-identical Pauli operator should be inserted so that its backpropagation satisfies the error mitigation criterion. Various non-restrictive embodiments are described with respect to Figure 8.

[0087] Figure 8 illustrates an exemplary and non-limiting block diagram 800 showing how a set of generalized Pauli checks 202 may be obtained or identified with respect to the Clifford circuit 110, given a plurality of candidate positions 702, according to one or more embodiments described herein.

[0088] In various embodiments, the plurality of candidate positions 702 may comprise l positions: candidate position 702(1) candidate position 702(l) for any preferred positive integer l>1. In various embodiments, each of the plurality of candidate positions 702 may be any preferred electronic data (e.g., one or more scalars, one or more vectors, one or more matrices, one or more tensors, one or more strings, or any preferred combination thereof) which can represent or otherwise represent each qubit-timestep tuple in the Clifford circuit 110 that is considered or designated as a preferred or acceptable location for the insertion of an n-qubit non-identical Pauli operator of weight 1. As an unrestrictive example, candidate position 702(1) may be a first scalar, vector, matrix, tensor, or string that identifies a first circuit time step of the Clifford circuit 110, in which any suitable n-qubit non-identical Pauli operator of weight 1 may be potentially or possible to be inserted with respect to the first of the set of data qubits 106. As another unrestrictive example, candidate position 702(l) may be an i-th scalar, vector, matrix, tensor, or string that identifies the i-th circuit time step of the Clifford circuit 110, in which any suitable n-qubit non-identical Pauli operator of weight 1 may be potentially or possible to be inserted with respect to the i-th of the set of data qubits 106. Note that different of the above candidate positions 702 may represent the same or different qubits, or the same or different circuit time steps. However, in various cases, no two of the above candidate positions 702 can represent the same qubit and the same circuit time step as each other.

[0089] Here, in various embodiments, the positions 702 of the multiple candidates can be considered to correspond to multiple sets of candidate Pauli operators 802, each of which represents all conceivable n-qubit non-identical Pauli operators of weight 1 that can be inserted into or positioned at each of the positions 702 of the multiple candidates.

[0090] As a non-restrictive example, candidate position 702(1) may correspond to a set of candidate Pauli operators 802(1). Thus, the set of candidate Pauli operators 802(1) can be considered as a set of all conceivable n-qubit non-identical Pauli operators of weight 1 that can be inserted into or positioned at candidate position 702(1). More specifically, the set of candidate Pauli operators 802(1) may contain three candidate Pauli operators. The first candidate Pauli operator in the set of candidate Pauli operators 802(1) may be a 2x2 Pauli X gate applied to any of the set of data qubits 106 indicated by candidate position 702(1); and an n-qubit matrix obtained by the tensor product between n-1 copies of the 2x2 identity matrix applied to the rest of the set of data qubits 106. A second candidate Pauli operator in the set of candidate Pauli operators 802(1) could be an n-qubit matrix obtained by the tensor product of a 2x2 Pauli Y gate applied to any of the set of data qubits 106 indicated by candidate position 702(1) and n-1 copies of a 2x2 identity matrix applied to the rest of the set of data qubits 106. A third candidate Pauli operator in the set of candidate Pauli operators 802(1) could be an n-qubit matrix obtained by the tensor product of a 2x2 Pauli Z gate applied to any of the set of data qubits 106 indicated by candidate position 702(1) and n-1 copies of a 2x2 identity matrix applied to the rest of the set of data qubits 106.

[0091] As another non-restrictive example, candidate position 702(l) may correspond to a set of candidate Pauli operators 802(l). Thus, the set of candidate Pauli operators 802(l) can be considered as a set of all conceivable n-qubit non-identical Pauli operators of weight 1 that can be inserted into or positioned at candidate position 702(l). More specifically, the set of candidate Pauli operators 802(l) may contain three candidate Pauli operators. The first candidate Pauli operator in the set of candidate Pauli operators 802(l) may be a 2x2 Pauli X gate applied to any of the set of data qubits 106 indicated by candidate position 702(l); and an n-qubit matrix obtained by the tensor product between n-1 copies of the 2x2 identity matrix applied to the rest of the set of data qubits 106. A second candidate Pauli operator in the set of candidate Pauli operators 802(l) could be an n-qubit matrix obtained by the tensor product of a 2x2 Pauli Y gate applied to any of the set of data qubits 106 indicated by candidate position 702(l) and n-1 copies of a 2x2 identity matrix applied to the rest of the set of data qubits 106. A third candidate Pauli operator in the set of candidate Pauli operators 802(l) could be an n-qubit matrix obtained by the tensor product of a 2x2 Pauli Z gate applied to any of the set of data qubits 106 indicated by candidate position 702(l) and n-1 copies of a 2x2 identity matrix applied to the rest of the set of data qubits 106.

[0092] In various embodiments, the detection component 118 may electronically convert the backpropagation of each candidate Pauli operator in the set of multiple candidate Pauli operators 802 into its respective Boolean encoding (e.g., its respective bitstring representation), thereby resulting in multiple sets of Boolean encodings 804. As an unrestricted example, the detection component 118 may electronically compute the backpropagation for each of the set of candidate Pauli operators 802(1) and convert the backpropagation into a set of Boolean encodings 804(1). In other words, a set of Boolean encodings 804(1) may contain or possess three distinct bitstrings, each representing the backpropagation of three distinct candidate Pauli operators contained within the set of candidate Pauli operators 802(1). As another unrestricted example, the detection component 118 may electronically compute the backpropagation for each of the set of candidate Pauli operators 802(l) and convert the backpropagation into a set of Boolean encodings 804(l). That is, a set of Boolean encodings 804(l) can contain or possess three distinct bit strings, each of which represents the backpropagation of each of the three distinct candidate Pauli operators contained within the set of candidate Pauli operators 802(l).

[0093] In various cases, the detection component 118 may electronically stack multiple sets of Boolean encodings 804 on top of each other. In various cases, such a stack may result in a stacked array 806. Thus, the stacked array 806 can be considered as a stack or tower of bit strings having a total height of 3l (for example, there may be a total of l candidate positions, each of which may be associated with three conceivable or candidate n-qubit non-identical Pauli operators with Pauli weight 1). In other words, each row of the stacked array 806 can be considered as representing, in binary format, the backpropagation of each candidate Pauli operator from multiple sets of candidate Pauli operators 802. In some embodiments, the detection component 118 may electronically shuffle or otherwise randomly organize the rows of the stacked array 806.

[0094] In various embodiments, the detection component 118 may electronically analyze the stacked array 806 using any suitable linear algebra or other mathematical technique. In various cases, the final result of such analysis may be the identification or determination of a set of generalized Pauli checks 202. In various cases, how the detection component 118 analyzes the stacked array 806 may depend on error mitigation criteria.

[0095] As a non-restrictive example, suppose the error mitigation criterion is that the backpropagation product is equal to the identity operator (up to the global phase). In such a case, the detection component 118 may compute the zero space of the stacked array 806, which can be considered to represent a set of generalized Pauli checks 202. More specifically, the computation of the zero space of the stacked array 806 can be considered to be determining which specific combinations of rows in the stacked array result in a bit string that sums up to all zeros. Each of the identified combinations of rows can be considered to represent each of the candidate Pauli operators identified within a set of candidate Pauli operators 802, and each of the identified combinations of candidate Pauli operators can be considered to be each of the set of generalized Pauli checks 202.

[0096] As another non-restrictive example, the error mitigation criterion assumes that the product of the backpropagations is equal to the product of the backpropagations of q random Pauli operators similarly inserted into the Clifford circuit 110 by the detection component 118. In such a case, the detection component 118 may apply any suitable syndrome decoding technique or heuristic search algorithm, whether greedy or non-greedy, to the stacked array 806. Some non-restrictive examples may include any suitable technique, including syndrome computation, parity check matrices, or the Berlekamp-Massey algorithm. In any case, the application of such a syndrome decoding technique or heuristic search algorithm can be considered as determining which particular combination of rows in the stacked array, when summed, matches a bit string that represents the product of the backpropagations of q randomly inserted Pauli operators. Each of the identified combinations in a row can be considered to represent each combination of candidate Pauli operators identified within a set of candidate Pauli operators 802, and each of the identified combinations of candidate Pauli operators can be considered to represent each of the set of generalized Pauli checks 202.

[0097] As yet another non-restrictive example, suppose the error mitigation criterion is that the backpropagation product is an element of the stabilizer group of the Clifford circuit 110. In such a case, the detection component 118 may apply any suitable syndrome decoding technique or heuristic search algorithm, whether greedy or non-greedy, to the stacked array 806, where the application of such a syndrome decoding technique or heuristic search algorithm can be considered as determining which particular combination of rows in the stacked array, when summed, matches any bit string known to represent an element of the stabilizer group. Each of the identified combinations of rows can be considered to represent each of the candidate Pauli operators identified in a set of candidate Pauli operators 802, and each of the identified combinations of candidate Pauli operators can be considered to represent each of the generalized Pauli checks 202.

[0098] In some cases, the analysis of a stacked array 806 can be formulated as a linear algebra optimization problem. As a non-restrictive example, such a formulation is: min x,y |x| ∋xF = q + yS This can be given by, where x represents the selection range of candidate Pauli operators having the weights to be minimized, where the Boolean matrix F represents the Boolean encoding of the backpropagation of the candidate Pauli operators, where q represents one or more randomly inserted Pauli operators implemented as a combination of candidate Pauli operators being backpropagated, where y represents the combination of stabilizers, and where the Boolean matrix S represents the set of stabilizers for the Clifford circuit 110 at any time step in which the Pauli operators are being backpropagated. In some cases, the dependence on y can be eliminated by finding the zero space Null of S. In such cases, the above formulation becomes: min x |x|∋xFNull=qNull It can be simplified to this.

[0099] Figure 9 shows a flowchart of an exemplary and non-limiting computer implementation method 900 that can facilitate error mitigation of Clifford circuits by generalized Pauli checks, according to one or more embodiments described herein.

[0100] In various embodiments, operation 902 may include a device (e.g., via 116) operably coupled to a processor (e.g., 112) accessing a Clifford circuit (e.g., 110) running on a quantum computer (e.g., 104).

[0101] In various embodiments, operation 904 may include the device (e.g., via 116) accessing an electronic indication of a qubit-timestep tuple in a Clifford circuit that is acceptable or designated as a candidate location (e.g., 702) for Pauli insertion.

[0102] In various cases, operation 906 may involve the device (e.g., via 118) computing backpropagation over all possible non-identical n-qubit Pauli qubits of weight 1 (e.g., 802) that may be inserted at each candidate position.

[0103] In various cases, operation 908 may include a device (e.g., via 118) converting the backpropagation to its respective Boolean encoding (e.g., 804).

[0104] In various embodiments, operation 910 may include the device (e.g., via 118) stacking the Boolean encoding into an array (e.g., 806). In some cases, this may include randomly shuffling the rows of the array.

[0105] In various cases, operation 912 may include applying zero-space computation or syndrome decoding techniques to a device (e.g., via 118) and array to determine which possible combinations of non-identical n-qubit Pauli with weight 1, inserted at candidate positions in the Clifford circuit, constitute a valid generalized Pauli check (e.g., 202) with respect to the Clifford circuit.

[0106] The various embodiments described herein may be seen as promoting a new type of Pauli check (referred to herein as a generalized Pauli check) relating to Clifford circuits that do not have the strict hardware constraints of a two-face Pauli check. Indeed, a generalized Pauli check does not require the implementation of any particular coupling topology, whereas a two-face Pauli check requires an all-to-all coupling topology (or a massive SWAP gate if an all-to-all coupling topology is not available). In other words, regardless of the coupling topology implemented on the quantum computer 104, a valid generalized Pauli check can always be identified, given a Clifford circuit 110 and a set of candidate positions 702. In particular, a user or technician associated with the quantum computer 104 can make multiple candidate positions 702 identify or include only data qubits that are physically coupled to at least one check qubit. Equivalently, the set of check qubits 106 can be selected from any qubits of the quantum computer 104 that are unused by the Clifford circuit 110 and coupled to at least one of the set of data qubits 106. Therefore, a valid generalized Pauli check can be found for any topology exhibited by the quantum computer 104. Furthermore, the circuit depth of the Clifford circuit 110 can even be preserved in some situations, such as when a user or technician allows a set of candidate positions 702 to identify only the "holes" within the Clifford circuit 110. Non-limiting aspects are described with respect to Figures 10-11.

[0107] Figures 10 and 11 illustrate exemplary and non-limiting circuit diagrams 1000 and 1100, illustrating how the generalized Pauli check may be effective even for qubit topologies with limited coupling, according to one or more embodiments described herein.

[0108] First, consider Figure 10. In the non-restrictive example of Figure 10, a 7-qubit Clifford circuit is shown consisting of 10 timesteps of a CNOT gate (e.g., operating on a total of 7 data qubits, D1-D7). In Figure 10, abbreviated notation is used to indicate circuit timesteps (e.g., "T1" indicates the first timestep of the 7-qubit Clifford circuit; "T2" indicates the second timestep of the 7-qubit Clifford circuit; "T3" indicates the third timestep of the 7-qubit Clifford circuit). Note the various visual holes present in circuit diagram 1000 (e.g., qubit-timestep tuples to which quantum gates do not apply). In the non-restrictive example, there are five holes on D1: the first hole at T2; the second hole at T4; the third hole at T6; the fourth hole at T8; and T 10 The fifth hole in T1. As another non-restrictive example, there are five holes on D7: the first hole in T1; the second hole in T3; the third hole in T5; the fourth hole in T7; and the fifth hole in T9.

[0109] Now consider Figure 11. In the non-restrictive example of Figure 11, there is only a single check qubit, indicated as C1. Assume that C1 is coupled only to D1 and not to any other data qubits. In such a situation, a two-faced Pauli check cannot be implemented without a huge number of interleaved SWAP gates, which would significantly increase the circuit depth of the Clifford circuit. In contrast, a valid generalized Pauli check can be found even though C1 is coupled only to D1. Indeed, as shown in schematic 1100, a valid generalized Pauli check filling the five holes of D1 is identified and inserted within the Clifford circuit: a CNOT gate controlled by C1 and inserted at T2; a CNOT gate controlled by C1 and inserted at T4; a CNOT gate controlled by C1 and inserted at T6; a Pauli Y gate controlled by C1 and inserted at T8; and a T 10 A Pauli Z gate is inserted into it. That is, a two-sided Pauli check cannot be implemented with respect to the Clifford circuit shown without significant cost in terms of circuit depth, but a valid generalized Pauli check can nevertheless be implemented in this particular non-limiting example without even increasing the circuit depth at all. Note that, as shown, Hadamard gates and phase gates can be applied to C1 for the purpose of measurement basis, as mentioned above.

[0110] Up to this point, various embodiments have been described that include the Pauli operator of generalized Pauli checks, each controlled by a set of check qubits 108 and targeting each of the sets of data qubits 106. Indeed, in various embodiments, the set of data qubits 106 could be any qubits of the quantum computer 104 utilized by the Clifford circuit 110, and the set of check qubits 108 could be any qubits of the quantum computer 104 that are not utilized by the Clifford circuit 110 and are physically coupled to at least one of the sets of data qubits 106. However, these are merely non-limiting examples. In some cases, one or more of the sets of check qubits 108 do not need to be physically coupled to any of the sets of data qubits 106, but nevertheless, one or more of the sets of check qubits 108 can function or play a role as a suitable or sufficient source for each of the sets of generalized Pauli checks 202. In various embodiments, this can be achieved by daisy-chaining the check qubits together. In other words, this can be achieved by having one generalized Pauli check Pauli operator target or otherwise operate on a check qubit that controls some other generalized Pauli check Pauli operator. Non-limiting embodiments are described with respect to Figures 12-14.

[0111] Figures 12–14 illustrate illustrative and non-limiting circuit diagrams 1200, 1300, and 1400, showing how daisy-chained check qubits may be involved in a generalized Pauli check according to one or more embodiments described herein.

[0112] First, consider Figure 12. As shown, circuit diagram 1200 may be similar to circuit diagram 400, except that the set of check qubits 108 may have two qubits instead of one: C1 and C2. Assume that C2 is coupled only to C1 and not to any of D1, D2, D3, or D4.

[0113] Next, let us consider Figure 13. As shown, circuit diagram 1300 can be similar to circuit diagram 500, again with two check qubits instead of one.

[0114] Now, let's consider Figure 14. In various embodiments, circuit diagram 1400 shows an unrestricted example of two generalized Pauli checks inserted within the Clifford circuit 110: generalized Pauli check 1402 and generalized Pauli check 1404. As shown, generalized Pauli check 1402 may be controlled by C1, while generalized Pauli check 1404 may be controlled by C2. In the unrestricted example of Figure 14, generalized Pauli check 1402 consists of two Pauli operators: a first Pauli operator indicated by "P1" and another Pauli operator indicated by "P3". In contrast, in the unrestricted example of Figure 14, generalized Pauli check 1404 consists of only one Pauli operator indicated by "P2". Specifically, P1 could be the tensor product obtained between a 2x2 non-identical Pauli gate targeting D4 and 2x2 identity gates on each of D1, D2, and D3. Additionally, P3 could be the tensor product obtained between a 2x2 non-identical Pauli gate targeting D1 and 2x2 identity gates on each of D2, D3, and D4. In contrast, since C2 is coupled only to C1 in this unrestricted example, P2 could be the tensor product obtained between a 2x2 non-identical Pauli gate targeting C1 and 2x2 identity gates on each of D1, D2, D3, and D4. That is, P1 and P3 can be 4-qubit operators, but P2 can instead be a 5-qubit operator. In other words, from the perspective of C2, C1 can be considered a fifth or additional data qubit.

[0115] Here, from the above considerations of backpropagation, the generalized Pauli check 1402 is:

Number

Number

[0116] More generally, whenever a new check qubit is daisy-chained in this manner, the total data qubit count from the perspective of that new check qubit can be considered incremented (for example, that new check qubit may target another check qubit, and therefore that new check qubit may: all the qubits treated as data qubits by that other check qubit; and that other check qubit itself may be treated as a data qubit). Daisy-chaining in this way is another concrete example of how a generalized Pauli check can be considered to have significantly relaxed hardware constraints compared to a two-faced Pauli check.

[0117] Figures 15-16 illustrate the results of exemplary and non-limiting experiments using one or more embodiments described herein. In particular, the inventors have conducted various experiments relating to the various embodiments described herein. Some of these experiments involved implementing various sets of generalized Pauli checks on randomly generated 20-qubit Clifford circuits performed on a linear nearest-neighbor coupling topology (e.g., n=20). Such experiments treated a set of state-of-the-art two-sided Pauli checks for the above randomly generated Clifford circuits as a baseline. Some of the results from the above experiments are shown in Figures 15-16.

[0118] Figure 15 shows graph 1500 of the post-select rate as a function of the number of Pauli checks (e.g., as a function of m). Reference numeral 1502 shows the result presented by the two-sided Pauli check criterion. Reference numeral 1504 shows the result presented by the generalized Pauli check, each limited or restricted so as to consist of two Pauli operators (e.g., k=2). Reference numeral 1506 shows the result presented by the generalized Pauli check, each limited or restricted so as to consist of 10 Pauli operators (e.g., k=10). Reference numeral 1508 shows the result presented by the generalized Pauli check, each limited or restricted so as to consist of 20 Pauli operators (e.g., k=20). As shown, all embodiments of the generalized Pauli check exhibited significantly higher post-select rates for all values ​​of m compared to the two-sided Pauli check criterion.

[0119] Figure 16 shows graph 1600 of the logic error rate as a function of the number of Pauli checks (e.g., as a function of m). Reference numeral 1602 shows the result presented by the two-sided Pauli check criterion. Reference numeral 1604 shows the result presented by a generalized Pauli check, each limited or restricted to consist of two Pauli operators (e.g., k=2). Reference numeral 1606 shows the result presented by a generalized Pauli check, each limited or restricted to consist of ten Pauli operators (e.g., k=10). Reference numeral 1608 shows the result presented by a generalized Pauli check, each limited or restricted to consist of twenty Pauli operators (e.g., k=20). As shown, all embodiments of the generalized Pauli check exhibited a lower logic error rate than the two-sided Pauli check criterion for m>30. Furthermore, as shown, the generalized Pauli check with a larger number of constructor Pauli operators exhibited a significantly lower logical error rate than the two-sided Pauli check criterion for m > 10.

[0120] The results of these experiments demonstrate that the generalized Pauli check described herein can achieve quantifiablely better error reduction compared to the two-face Pauli check. Similar results were experimentally obtained for a random 20-qubit Clifford circuit implemented on a caterpillar topology (for example, where the caterpillar body constitutes the data qubits and the caterpillar legs constitute the check qubits).

[0121] Figure 17 illustrates a flowchart of an exemplary and non-limiting computer implementation method 1700 that facilitates error mitigation for Clifford circuits by generalized Pauli check, according to one or more embodiments described herein. In various cases, the Pauli check system 102 may facilitate the computer implementation method 1700.

[0122] In various embodiments, operation 1702 may include a device (e.g., via 116) operably coupled to a processor (e.g., 112) executing a Clifford circuit (e.g., 110) on a set of data qubits (e.g., 106).

[0123] In various embodiments, operation 1704 may include a device (e.g., 118) detecting an error (e.g., 204) in the execution of a Clifford circuit by measuring a set of check qubits (e.g., 108) that control a set of Pauli operators inserted into the Clifford circuit (e.g., 202, configured such that 304 constitutes 302), wherein the product of the backpropagation of the set of Pauli operators satisfies an error mitigation criterion.

[0124] Although not explicitly shown in Figure 17, the device may identify a set of Pauli operators to be inserted into the Clifford circuit based on the following: the device (e.g., via 118) computes the backpropagation of each candidate Pauli operator (e.g., 804) associated with a candidate position (e.g., 802) in the Clifford circuit, thereby yielding backpropagation of multiple candidates; the device (e.g., via 118) stacks the Boolean encodings (e.g., 804) of the above multiple candidate backpropagations, thereby yielding a stacked array (e.g., 806); and the device (e.g., via 118) computes the zero space of the stacked array.

[0125] Although not explicitly shown in Figure 17, the device can compute the backpropagation of the set of Pauli operators in the starting layer of the Clifford circuit.

[0126] Although not explicitly shown in Figure 17, the error mitigation criteria here may be: the product is equal to the identity operator up to the global phase; the product is equal to the backpropagation of randomly inserted Pauli operators in the Clifford circuit; or the product is in the set of stabilizers associated with the Clifford circuit.

[0127] Although not explicitly shown in Figure 17, the Clifford circuit may be executed on a quantum computer (e.g., 10⁴), and the device may further comprise selecting one or more qubits of the quantum computer that are unused by the Clifford circuit as a set of check qubits.

[0128] Although not explicitly shown in Figure 17, the first check qubit in the set of check qubits (e.g., C1 in Figure 14) may be the target of the second check qubit in the set of check qubits (e.g., C2 in Figure 14).

[0129] Figure 18 and the following discussion are intended to provide a concise and general description of a preferred computing environment 1800 in which one or more embodiments described herein may be implemented. For example, various aspects of this disclosure are described by explanatory text, flowcharts, block diagrams of computer systems, or block diagrams of machine logic contained within computer program product (CPP) embodiments. With respect to any flowchart, depending on the technology involved, operations may be performed in a different order than those shown in a given flowchart. For example, again depending on the technology involved, two operations shown in consecutive blocks of a flowchart may be performed in reverse order, as a single integrated stage, simultaneously, or with at least partial time overlap.

[0130] Computer program product embodiment ("CPP embodiment" or "CPP") is a term used in this disclosure to describe any set of one or more storage devices collectively comprising machine-readable code corresponding to instructions or data for performing computer operations specified in a given CPP claim, and also referred to as "mediums." A "storage device" is any tangible device capable of holding and storing instructions for use by a computer processor. Computer-readable storage media may be, but are not limited to, electronic storage media, magnetic storage media, optical storage media, electromagnetic storage media, semiconductor storage media, mechanical storage media, or any preferred combination thereof. Some known types of storage devices, including these media, include diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random-access memory (SRAM), compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanically encoded devices (such as pits / lands formed on the main surface of a punch card or disk), or any suitable combination of the foregoing. Computer-readable storage media themselves should not be interpreted as storage of transient signals, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides, optical pulses passing through optical fiber cables, or electrical signals transmitted through wires or other transmission media, as the term is used in this disclosure.As those skilled in the art will understand, data is typically moved at several intermittent points during the normal operation of a storage device, such as during access, defragmentation, or garbage collection; however, data is not transient while it is stored, and therefore the storage device is not transient.

[0131] The computing environment 1800 includes an example of an environment for executing at least a portion of computer code involved in performing the method of the invention, such as the generalized Paulicheck code 1880. In addition to block 1880, the computing environment 1800 includes, for example, a computer 1801, a wide area network (WAN) 1802, an end user device (EUD) 1803, a remote server 1804, a public cloud 1805, and a private cloud 1806. In this embodiment, the computer 1801 includes a processor set 1810 (including a processing circuit configuration 1820 and a cache 1821), a communication fabric 1811, volatile memory 1812, persistent storage 1813 (including an operating system 1822 and blocks 1880 as identified above), a peripheral device set 1814 (including a user interface (UI) device set 1823, storage 1824, and an Internet of Things (IoT) sensor set 1825), and a network module 1815. The remote server 1804 includes a remote database 1830. The public cloud 1805 includes a gateway 1840, a cloud orchestration module 1841, a host physical machine set 1842, a virtual machine set 1843, and a container set 1844.

[0132] Computer 1801 may take the form of a desktop computer, laptop computer, tablet computer, smartphone, smartwatch, or other wearable computer, mainframe computer, quantum computer, or any other form of computer or mobile device, currently known or to be developed in the future, capable of running programs, accessing networks, or querying databases such as remote database 1830. As is well understood in the field of computer technology, and depending on the technology, the execution of a computer implementation method may be distributed among multiple computers or across multiple locations. On the other hand, in this presentation concerning the computing environment 1800, in order to keep the presentation as concise as possible, the detailed considerations focus on a single computer, specifically computer 1801. Computer 1801 may be located in the cloud, although it is not shown in Figure 18. On the other hand, computer 1801 is not required to be in the cloud, except to any extent that can be definitively shown.

[0133] The processor set 1810 includes one or more computer processors of any type currently known or to be developed in the future. The processing circuit configuration 1820 may be distributed across multiple packages, for example, multiple interconnected integrated circuit chips. The processing circuit configuration 1820 may implement multiple processor threads or multiple processor cores. The cache 1821 is memory located within the processor chip package and is typically used for data or code that should be available for high-speed access by threads or cores running on the processor set 1810. The cache memory is typically organized into multiple levels depending on its relative proximity to the processing circuit configuration. Alternatively, some or all of the cache for the processor set may be located "off-chip". In some computing environments, the processor set 1810 may operate with qubits and be designed to perform quantum computing.

[0134] Computer-readable program instructions are typically loaded onto computer 1801, causing the processor set 1810 of computer 1801 to execute a series of operational steps, thereby realizing a computer implementation method. As a result, the instructions thus executed instantiate the method (collectively referred to as the "Method of Invention") as specified in the flowchart or description of the computer implementation method contained herein. These computer-readable program instructions are stored in various types of computer-readable storage media, such as cache 1821 and other storage media discussed below. The program instructions and associated data are accessed by the processor set 1810 to control and direct the execution of the Method of Invention. In the computing environment 1800, at least some of the instructions for executing the Method of Invention may be stored in block 1880 in persistent storage 1813.

[0135] The communication fabric 1811 is a signal conduction path that enables various components of the computer 1801 to communicate with one another. Typically, this fabric is made up of switches and conductive paths, such as buses, bridges, physical input / output ports, and similar components. Other types of signal communication paths may be used, such as fiber optic communication paths or wireless communication paths.

[0136] Volatile memory 1812 is any type of volatile memory currently known or to be developed in the future. Examples include dynamic random-access memory (RAM) or static RAM. Volatile memory typically features random access, but this is not required unless explicitly stated. In computer 1801, volatile memory 1812 is located in a single package and is internal to computer 1801; however, alternatively or additionally, volatile memory can be distributed across multiple packages or located externally to computer 1801.

[0137] Persistent storage 1813 is any form of non-volatile storage for a computer, currently known or to be developed in the future. Non-volatility of this storage means that the stored data is maintained regardless of whether power is supplied to computer 1801 or directly to persistent storage 1813. Persistent storage 1813 may be read-only memory (ROM), but typically at least a portion of the persistent storage allows for writing, deleting, and rewriting of data. Some well-known forms of persistent storage include magnetic disks and solid-state storage devices. Operating system 1822 can take multiple forms, including various known proprietary operating systems or open-source portable operating system interface (CSI) types employing a kernel. The code contained in block 1880 typically includes at least a portion of computer code involved in performing the method of the present invention.

[0138] The peripheral device set 1814 includes a set of peripheral devices for computer 1801. Data communication connections between the peripheral devices and other components of computer 1801 can be implemented in various ways, including Bluetooth® connections, Near-Field Communication (NFC) connections, connections made by cables (such as universal serial bus (USB) type cables), insert-type connections (e.g., secure digital (SD) cards), connections made through local area communication networks, and even connections made through wide area networks such as the Internet. In various embodiments, the UI device set 1823 may include components such as a display screen, speaker, microphone, wearable devices (such as goggles and smartwatches), keyboard, mouse, printer, touchpad, game controller, and haptic devices. Storage 1824 is external storage such as an external hard drive, or insertable storage such as an SD card. Storage 1824 may be persistent or volatile. In some embodiments, storage 1824 may take the form of a quantum computing storage device for storing data in the form of qubits. In embodiments where computer 1801 is required to have a large amount of storage (for example, when computer 1801 locally stores and manages a large database), in this case, this storage may be provided by peripheral storage devices designed to store large amounts of data, such as a storage area network (SAN) shared by multiple geographically distributed computers. The IoT sensor set 1825 consists of sensors that can be used in Internet of Things applications. For example, one sensor may be a thermometer and another may be a motion detector.

[0139] The network module 1815 is a collection of computer software, hardware, and firmware that enables computer 1801 to communicate with other computers via the WAN 1802. The network module 1815 may include hardware such as a modem or Wi-Fi® signal transceiver, software for packetizing or depacketizing data for transmission over a communication network, or web browser software for transmitting data over the internet. In some embodiments, the network control and network forwarding functions of the network module 1815 are performed on the same physical hardware device. In other embodiments (e.g., embodiments utilizing software-defined networking (SDN)), the control and forwarding functions of the network module 1815 are performed on physically separate devices (resulting in the control function managing multiple different network hardware devices). Computer-readable program instructions for performing the method of the present invention can typically be downloaded from an external computer or external storage device to computer 1801 through a network adapter card or network interface included in the network module 1815.

[0140] WAN1802 is any wide area network (e.g., the Internet) that can transmit computer data over non-local distances using any currently known or future-developed technology for transmitting computer data. In some embodiments, a WAN may be replaced or complemented by a local area network (LAN), such as a Wi-Fi® network, which is designed to transmit data between devices located within a local area. A WAN or LAN typically includes computer hardware, such as copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and edge servers.

[0141] The end-user device (EUD) 1803 is any computer system used and controlled by an end-user (e.g., a customer of the company operating computer 1801) and can take any of the forms considered above in relation to computer 1801. Typically, EUD 1803 receives useful and valuable data from the operation of computer 1801. For example, in a hypothetical case where computer 1801 is designed to provide recommendations to an end-user, these recommendations would typically be communicated from the network module 1815 of computer 1801 to EUD 1803 via WAN 1802. In this way, EUD 1803 can display or otherwise present the recommendations to the end-user. In some embodiments, EUD 1803 may be a client device, such as a thin client, a heavy client, a mainframe computer, or a desktop computer.

[0142] The remote server 1804 is any computer system that provides at least some data or functionality to computer 1801. The remote server 1804 may be controlled and used by the same entity that operates computer 1801. The remote server 1804 represents a machine that collects and stores useful and valuable data for use by other computers, such as computer 1801. For example, in a hypothetical case where computer 1801 is designed and programmed to provide recommendations based on historical data, this historical data may be provided to computer 1801 from the remote database 1830 of the remote server 1804.

[0143] Public Cloud 1805 is any computer system available for use by multiple entities, providing on-demand availability of computer system resources or other computing capabilities, particularly data storage (cloud storage) and computing power, without direct, active management by scale. Direct and active management of Public Cloud 1805's computing resources is performed by the computer hardware or software of Cloud Orchestration Module 1841. The computing resources provided by Public Cloud 1805 are typically implemented by virtual computing environments running on various computers that make up the host physical machine set 1842, which is the population of physical computers within or available to Public Cloud 1805. Virtual computing environments (VCEs) typically take the form of virtual machines from the virtual machine set 1843 or containers from the container set 1844. These VCEs may be stored as images and may be transferred either as images or after instantiation of the VCEs, among and between hosts of various physical machines. The cloud orchestration module 1841 manages image transfer and storage, deploys new VCE instances, and manages active instances of VCE deployments. The gateway 1840 is a collection of computer software, hardware, and firmware that enables the public cloud 1805 to communicate over the WAN 1802.

[0144] Here, some further explanation of virtualized computing environments (VCEs) is provided. A VCE can be stored as an "image." From this image, a new active instance of the VCE can be instantiated. Two well-known types of VCEs are virtual machines and containers. A container is a VCE that uses operating system-level virtualization. This refers to an operating system feature where the kernel allows for the existence of multiple isolated user-space instances called containers. These isolated user-space instances typically behave like actual computers in terms of the programs running within them. Computer programs running on a normal operating system can utilize all the resources of that computer, including connected devices, files and folders, network shares, CPU power, and quantifiable hardware capabilities. However, programs running inside a container can only use the contents of the container and the devices allocated to the container, which is a known feature of containerization.

[0145] Private Cloud 1806 is similar to Public Cloud 1805, except that its computing resources are available for use by a single enterprise only. While Private Cloud 1806 is shown as being in communication with WAN 1802, in other embodiments, a private cloud may be completely isolated from the internet and accessible only through a local / private network. A hybrid cloud is a combination of multiple clouds of different types (e.g., private, community, or public cloud types), often implemented by different vendors. Each of the multiple clouds remains a separate discrete entity, but the larger hybrid cloud architecture is coupled by standardization or proprietary technologies that enable orchestration, management, or data / application portability between the multiple configured clouds. In this embodiment, both Public Cloud 1805 and Private Cloud 1806 are part of a larger hybrid cloud.

[0146] The embodiments described herein may cover one or more systems, methods, apparatus, or computer program products at any possible level of technical detail of integration. A computer program product may include a computer-readable storage medium (or more mediums) having computer-readable program instructions for causing a processor to execute aspects of one or more embodiments described herein. The computer-readable storage medium may be a tangible device capable of holding and storing instructions for use by an instruction execution device. The computer-readable storage medium may, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a superconducting storage device, or any preferred combination of those described above. A non-exclusive list of more specific examples of computer-readable storage media is below: portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital multipurpose disks (DVDs), memory sticks, floppy disks, mechanically encoded devices such as punched cards or grooved structures on which instructions are recorded, or any suitable combination of the foregoing. Computer-readable storage media themselves, as used herein, should not be construed as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses passing through optical fiber cables), or transient signals such as electrical signals transmitted through wires.

[0147] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to each computing / processing device, or they may be downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, or a wireless network. The network may include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, or edge servers. A network adapter card or network interface within each computing / processing device receives computer-readable program instructions from the network and transfers the computer-readable program instructions for storage in a computer-readable storage medium within each computing / processing device. Computer-readable program instructions for performing the operation of one or more embodiments described herein may be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for integrated circuit configurations, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk®, C++, or similar, or procedural programming languages ​​such as the C programming language or similar programming languages. Computer-readable program instructions may run entirely on a computer, partially on a computer, as a standalone software package, partially on a computer, partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or wide area network (WAN), or the connection may be made to an external computer (for example, via the Internet using an Internet service provider).In one or more embodiments, to perform an aspect of one or more embodiments described herein, an electronic circuit configuration including, for example, a programmable logic circuit configuration, a field-programmable gate array (FPGA), or a programmable logic array (PLA) may execute computer-readable program instructions by personalizing the electronic circuit configuration using state information of computer-readable program instructions.

[0148] Aspects of one or more embodiments described herein are described with reference to flowcharts or block diagrams of methods, apparatus (systems), and computer program products according to one or more embodiments described herein. It will be understood that each block in a flowchart or block diagram, and combinations of blocks in a flowchart or block diagram, can be implemented by computer-readable program instructions. These computer-readable program instructions may be provided to a processor of a general-purpose computer, a dedicated computer, or other programmable data processing device to create a machine, and as a result, instructions executed via the processor of the computer or other programmable data processing device may produce means for implementing the functions / actions specified in one or more blocks of a flowchart or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that can instruct a computer, a programmable data processing device, or other device to function in a particular manner, and as a result, the computer-readable storage medium storing the instructions may include a product containing instructions that can implement the functions / actions specified in one or more blocks of a flowchart or block diagram. Furthermore, computer-readable program instructions can be loaded onto a computer, other programmable data processing device, or other device to perform a series of actions on the computer, other programmable device, or other device, thereby creating a computer implementation process. As a result, the instructions executed on the computer, other programmable device, or other device implement the functions / actions specified in a block or multiple blocks of a flowchart or block diagram.

[0149] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, or operation of a possible implementation of a system, a computer implementable method, or a computer program product according to one or more embodiments described herein. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In one or more alternative implementations, the functions described in a block may occur in an order different from that shown in the figure. For example, two consecutively shown blocks may be executed substantially simultaneously, depending on the functionality involved, or the blocks may, in some cases, be executed in reverse order. In addition, it should be noted that each block in a block diagram or flowchart, or a combination of blocks in a block diagram or flowchart, may be implemented by a dedicated hardware-based system capable of performing a specified function or operation or one or more combinations of dedicated hardware or computer instructions.

[0150] While the subject matter is described above in the general context of computer executable instructions for computer program products running on a computer or multiple computers, those skilled in the art will recognize that one or more embodiments of this specification may also be implemented at least partially in parallel with one or more other program modules. Generally, a program module includes routines, programs, components, or data structures that perform a particular task or implement a particular abstract data type. Furthermore, the computer implementation methods described above may be practiced with single-processor or multi-processor computer systems, minicomputing devices, mainframe computers, and other computer system configurations including computers, handheld computing devices (e.g., PDAs®, telephones), or microprocessor-based or programmable consumer or industrial electronic equipment. The embodiments shown may be implemented in a distributed computing environment where tasks are performed by remote processing devices connected via a communication network. However, one or more embodiments, if not all, of the one or more embodiments described herein may be implemented on a standalone computer. In a distributed computing environment, program modules may reside in both local and remote memory storage devices.

[0151] Where used herein, terms such as “component,” “system,” “platform,” or “interface” may refer to or include computer-related entities or entities relating to operating machines having one or more inherent functionalities. Entities described herein may be hardware, a combination of hardware and software, software, or running software. For example, a component may be, but is not limited to, a process running on a processor, a processor, an object, an executable file, a thread of execution, a program, or a computer. Exemplarily, an application running on a server and the server itself may both be components. One or more components may reside in a process or thread of execution, and components may be localized in one computer or distributed among two or more computers. In another example, each component may run from various computer-readable media containing various data structures. Components may communicate via local or remote processes, for example, according to signals containing one or more data packets (e.g., data from a local system, another component in a distributed system, or a component interacting with other systems via signals over a network such as the Internet). As another example, a component may be a device having inherent functionality provided by mechanical parts operated by an electrical or electronic circuit configuration operated by a software or firmware application executed by a processor. In such a case, the processor may be inside or outside the device and may execute at least part of the software or firmware application. As yet another example, a component may be a device that provides inherent functionality through electronic components without using mechanical parts, and such electronic components may include a processor or other means for executing software or firmware that gives at least part of the functionality of the electronic components.In one embodiment, the component may emulate an electronic component via a virtual machine, for example, in a cloud computing system.

[0152] In addition, the term “or” is intended to mean an inclusive “or,” not an exclusive “or.” That is, unless otherwise specified or the context makes clear, “X uses A or B” is intended to mean either of the natural inclusive substitutions. That is, “X uses A or B” is satisfied under any of the above cases: X uses A; X uses B; or X uses both A and B. Where used herein, the terms “and / or” are intended to have the same meaning as “or.” Furthermore, the articles “a” and “an” used herein and in the accompanying drawings should generally be interpreted as “one or more,” unless otherwise specified or the context makes it clear that they refer to a singular form. Where used herein, the terms “example” or “exemplary” are used to mean an example, case, or illustration. To avoid doubt, the subject matter described herein is not limited to such examples. In addition, any embodiment or design described herein as “example” and / or “exemplary” should not necessarily be construed as being preferable or advantageous to other embodiments or designs, nor is it intended to exclude equivalent exemplary structures and techniques known to those skilled in the art.

[0153] The disclosure herein describes non-limiting examples of various embodiments. For ease of description or explanation, various parts of the disclosure herein use the terms “each,” “every,” or “all” when considering various embodiments. Such use of the terms “each,” “every,” or “all” is non-limiting. In other words, where the disclosure herein provides a description that applies to “each,” “every,” or “all” of any particular object or component, it should be understood that this is a non-limiting example of various embodiments, and it should be further understood that in various other embodiments, such a description may apply to fewer than “each,” “every,” or “all” of that particular object or component.

[0154] The term “processor,” as used herein, can refer to substantially any computing unit or device, including, but not limited to, a single-core processor; a single processor with software multithreading capability; a multi-core processor; a multi-core processor with software multithreading capability; a multi-core processor with hardware multithreading technology; a parallel platform; or a parallel platform with distributed shared memory. Furthermore, a processor can refer to an integrated circuit, an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a field-programmable gate array (FPGA), a programmable logic controller (PLC), a complex-programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Furthermore, a processor may utilize nanoscale architectures, such as molecular and quantum dot-based transistors, switches, or gates, to optimize space utilization or enhance the performance of associated equipment, but is not limited to these. A processor may be implemented as a combination of computing units.

[0155] In this specification, terms such as “storage,” “data storage,” “data storage,” “database,” and substantially any other information storage component relating to the operation and functionality of a component are used to refer to “memory” or “memory component” entities embodied in a component containing memory. Memory or memory components described herein may be either volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory may include, but not limit, read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or non-volatile random-access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory may include RAM that can operate as, for example, external cache memory. As examples, not limitations, RAM may be available in many forms, including synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data-rate SDRAM (DDR SDRAM), extended SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), or Rambus dynamic RAM (RDRAM). Furthermore, the memory components described herein in relation to systems or computer implementations are intended to include, but are not limited to, these or any other suitable types of memory.

[0156] The above descriptions include only examples of systems and computer implementations. Naturally, it is not possible to describe every conceivable combination of components or computer implementations for the purpose of describing one or more embodiments, but those skilled in the art will recognize that many further combinations or substitutions of one or more embodiments are possible. Furthermore, to the extent that the terms “includes,” “has,” “possesses,” and similar terms are used in the detailed description, claims, appendices, or drawings, such terms are intended to be comprehensive in the same manner as the term “comprising,” just as “comprising” is interpreted as a transitional clause in a claim when used.

[0157] While descriptions of various embodiments have been presented for illustrative purposes, they are not intended to be exhaustive or to limit the scope to the embodiments described herein. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the embodiments described. The terminology used herein has been selected to best describe the principles, practical applications, or technical improvements to the technologies available on the market, or to enable other those skilled in the art to understand the embodiments described herein.

Claims

1. A processor, wherein the processor includes: Procedure for running a Clifford circuit on a set of data qubits; and A procedure for detecting an error in the execution of the Clifford circuit by measuring a set of check qubits that control a set of Pauli operators inserted into the Clifford circuit, wherein the product of the backpropagation of the set of Pauli operators satisfies an error mitigation criterion. A processor that facilitates operations having the ability to execute computer executable instructions stored in non-temporary computer-readable memory. A system equipped with these features.

2. The aforementioned processor is: Calculate the backpropagation of each candidate with respect to the Pauli operator associated with the candidate's position in the Clifford circuit, thereby resulting in the backpropagation of multiple candidates; Stacking the Boolean encodings of the backpropagation of the aforementioned multiple candidates, thereby yielding a stacked array; and Calculating the zero space of the stacked array. The system according to claim 1, which identifies the set of Pauli operators to be inserted into the Clifford circuit based on the following.

3. The system according to claim 1, wherein the processor calculates the backpropagation of the set of Pauli operators in the starting layer of the Clifford circuit.

4. The system according to claim 1, wherein the error mitigation criterion is that the product is equal to the identity operator up to the global phase.

5. The system according to any one of claims 1 to 4, wherein the error mitigation criterion is that the product is equal to the backpropagation of randomly inserted Pauli operators in the Clifford circuit.

6. The system according to any one of claims 1 to 4, wherein the error mitigation criterion is that the product is present in the set of stabilizers associated with the Clifford circuit.

7. The Clifford circuit is executed on a quantum computer, and the operation is as follows: A procedure for selecting one or more unused qubits of the quantum computer as the set of check qubits using the Clifford circuit. The system according to any one of claims 1 to 4, further comprising:

8. The system according to any one of claims 1 to 4, wherein the first check qubit of the set of check qubits is the target of the second check qubit of the set of check qubits.

9. The step in which a device operablely coupled to a processor executes a Clifford circuit on a set of data qubits; and The device detects an error in the execution of the Clifford circuit by measuring a set of check qubits that control a set of Pauli operators inserted into the Clifford circuit, wherein the product of the backpropagation of the set of Pauli operators satisfies the error mitigation criterion. A computer implementation method comprising the above.

10. The aforementioned device is: The device calculates the backpropagation of each candidate Pauli operator associated with the candidate's position in the Clifford circuit, thereby resulting in the backpropagation of multiple candidates; The device stacks the Boolean encodings of the backpropagation of the plurality of candidates, thereby resulting in a stacked array; and The device computes the zero space of the stacked array. A computer implementation method according to claim 9, which identifies the set of Pauli operators to be inserted into the Clifford circuit based on the above.

11. The computer implementation method according to claim 9, wherein the device calculates the backpropagation of the set of Pauli operators in the starting layer of the Clifford circuit.

12. The computer implementation method according to claim 9, wherein the error mitigation criterion is that the product is equal to the identity operator up to the global phase.

13. The computer implementation method according to claim 9, wherein the error mitigation criterion is that the product is equal to the backpropagation of randomly inserted Pauli operators in the Clifford circuit.

14. The computer implementation method according to claim 9, wherein the error mitigation criterion is that the product is present in the set of stabilizers associated with the Clifford circuit.

15. The aforementioned Clifford circuit was executed on a quantum computer: The device selects one or more unused qubits of the quantum computer as the set of check qubits by the Clifford circuit. The computer implementation method according to claim 9, further comprising the above.

16. The computer implementation method according to any one of claims 9 to 15, wherein the first check qubit of the set of check qubits is the target of the second check qubit of the set of check qubits.

17. A computer program for facilitating error reduction in Clifford circuits by generalized Pauli checks, wherein the computer program comprises program instructions, and the program instructions are transmitted to a processor: Run the Clifford circuit on a set of data qubits; Errors in the execution of the Clifford circuit are detected by measuring a set of check qubits that control a set of Pauli operators inserted into the Clifford circuit, where the product of the backpropagation of the set of Pauli operators satisfies the error mitigation criterion. A computer program that is executable by the aforementioned processor.

18. The aforementioned processor is: Calculate the backpropagation of each candidate with respect to the Pauli operator associated with the candidate's position in the Clifford circuit, thereby resulting in the backpropagation of multiple candidates; Stacking the Boolean encodings of the backpropagation of the aforementioned multiple candidates, thereby yielding a stacked array; and Calculating the zero space of the stacked array. A computer program according to claim 17, which identifies the set of Pauli operators to be inserted into the Clifford circuit based on the above.

19. The computer program according to claim 17, wherein the processor calculates the backpropagation of the set of Pauli operators in the starting layer of the Clifford circuit.

20. The error mitigation criterion is that the product is equal to the identity operator up to the global phase, according to any one of claims 17 to 19.

Images