Lamp generator and imaging apparatus including the same

Abstract

Generate HDR images with simplified hardware. [Solution] An image sensing device 100 according to one embodiment of the present invention may include a lamp generator 130 that generates a lamp signal Vramp, a cap divider 142 that adjusts the voltage level range of a pixel signal PS to a first voltage level range value and outputs a first adjusted pixel signal PS_D in a first analog gain mode, or adjusts the voltage level range of a pixel signal PS to a second voltage level range value and outputs a second adjusted pixel signal PS_D in a second analog gain mode, and a signal controller 175 that controls the lamp generator 130 so that the waveform of the lamp signal Vramp has a first slope in the first analog gain mode and the second analog gain mode.

Description

Technical Field

[0001] The present invention relates to a lamp generator for generating a high dynamic range (HDR) image and an imaging device including the same.

Background Art

[0002] An image sensing device is a device that captures an optical image by using the property of a light-sensitive semiconductor material that reacts to light. With the development of industries such as automobiles, medicine, computers, and communications, there is an increasing demand for high-performance image sensing devices in various fields such as smartphones, digital cameras, game devices, Internet of Things, robots, security cameras, and medical micro cameras.

[0003] Recently, there has been an increasing interest in HDR images in order to provide high-quality images, and various techniques for obtaining HDR images have been developed. Among them, a technique for varying an analog gain that converts an electrical signal indicating the intensity of incident light into digital data can contribute to obtaining an HDR image, but there is a problem that a large amount of resources are required for hardware implementation to realize this.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The technical idea of the present invention can provide a lamp generation circuit capable of generating an HDR image with relatively simplified hardware, an image sensing device including the same, and an operation method thereof.

[0005] The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0006] An image sensing device according to one embodiment of the present invention may include: a lamp generator that generates a lamp signal; a cap divider that adjusts the voltage level range of a pixel signal to a first voltage level range value in a first analog gain mode and outputs a first adjusted pixel signal, or adjusts the voltage level range of a pixel signal to a second voltage level range value and outputs a second adjusted pixel signal in a second analog gain mode; and a signal controller that controls the lamp generator so that the waveform of the lamp signal has a first slope in the first analog gain mode and the second analog gain mode.

[0007] An image sensing device according to another embodiment of the present invention may include: a pixel array that generates a pixel signal; a signal controller that generates a lamp control signal and a switch control signal based on an analog gain mode corresponding to illuminance; a cap divider that adjusts the voltage level range of the pixel signal to a first voltage level range value based on the switch control signal and outputs it as a first adjusted pixel signal, or adjusts the voltage level range of the pixel signal to a second voltage level range value and outputs it as a second adjusted pixel signal; a lamp generator that adjusts the slope of the lamp signal based on the lamp control signal; and a comparator that compares the first adjusted pixel signal or the second adjusted pixel signal with the lamp signal and generates comparison data. [Effects of the Invention]

[0008] According to the embodiments disclosed herein, in low-light environments, the signal-to-noise ratio (SNR) can be improved by compressing not only the lamp signal but also the voltage level range of the pixel signal.

[0009] Furthermore, according to the embodiments of this disclosure, the circuit area and power consumption required to implement a lamp generator that uses multiple analog gains can be reduced.

[0010] In addition, a variety of other effects may be conveyed, either directly or indirectly, through this document. [Brief explanation of the drawing]

[0011] [Figure 1] This is a block diagram showing an imaging apparatus according to one embodiment of the present disclosure. [Figure 2] Figure 1 is a circuit diagram showing one embodiment of pixels included in the pixel array. [Figure 3] This figure shows an ADC according to one embodiment of the present disclosure. [Figure 4] This is a circuit diagram showing one embodiment of the capacitor divider included in the ADC shown in Figure 3. [Figure 5] This is a circuit diagram showing another embodiment of the cap divider included in the ADC of Figure 3. [Figure 6] This timing diagram illustrates how the voltage level of the adjustment pixel signal changes depending on the opening and closing of the first switch shown in Figure 5. [Figure 7a] These timing diagrams illustrate the voltage levels of the adjustment pixel signal and adjustment lamp signal, which vary depending on the signals shown in Figures 2 to 4. [Figure 7b] These timing diagrams illustrate the voltage levels of the adjustment pixel signal and adjustment lamp signal, which vary depending on the signals shown in Figures 2 to 4. [Figure 7c] These timing diagrams illustrate the voltage levels of the adjustment pixel signal and adjustment lamp signal, which vary depending on the signals shown in Figures 2 to 4. [Modes for carrying out the invention]

[0012] Various embodiments will be described below with reference to the attached drawings. However, this disclosure should be understood not to be limited to any particular embodiment, but to include various modifications, equivalents, and / or alternatives of the embodiments. Embodiments of this disclosure can provide a variety of effects that can be recognized directly or indirectly through this disclosure.

[0013] Figure 1 is a block diagram showing an imaging apparatus according to one embodiment of the present disclosure.

[0014] Referring to Figure 1, the imaging device (10) can refer to devices such as a digital still camera for capturing still images or a digital video camera for capturing moving images. For example, the imaging device 10 may be embodied in a digital single-lens reflex camera (DSLR), a mirrorless camera, or a smartphone, but is not limited to these. The imaging device 10 may be a concept that includes devices capable of capturing a subject, including an image sensor, and generating an image.

[0015] The imaging device 10 may include an image sensing device 100 and an image signal processor (hereinafter referred to as "ISP") 200.

[0016] In one example, the image sensing device 100 may be a CIS (Complementary Metal Oxide Semiconductor Image Sensor) that converts incident light into electrical signals. The image sensing device 100 may include a pixel array 110, a row driver 120, a ramp generator 130, an analog-to-digital converter (ADC) 140, an output buffer 150, a column driver 160, and a timing controller 170. Here, the configurations of the image sensing device 100 are merely illustrative, and at least some of the configurations may be added or omitted as needed.

[0017] The pixel array 110 may include multiple pixels arranged in multiple rows and multiple columns. In one embodiment, the multiple pixels may be arranged in a two-dimensional pixel array including rows and columns. In another embodiment, the multiple unit image pixels may be arranged in a three-dimensional pixel array. The multiple pixels can convert optical signals into electrical signals on a pixel-by-pixel or pixel-group basis to output a pixel signal PS. Pixels within a pixel group in the pixel array 110 may share at least one internal circuit. The pixel array 110 can receive a drive signal RDRV from the low driver 120, which includes a low selection signal, a pixel reset signal, and a transmission signal. The drive signal RDRV may activate the corresponding pixels in the pixel array 110 to perform operations corresponding to the low selection signal, the pixel reset signal, and the transmission signal.

[0018] The load driver 120 can activate the pixel array 110 to perform a specific operation on the pixels included in the corresponding row based on the instructions and / or control signal CON supplied by the timing controller 170. In one embodiment, the load driver 120 can select at least one pixel arranged in at least one row of the pixel array 110. The load driver 120 can generate a row selection signal to select at least one row among the plurality of rows.

[0019] The load driver 120 can sequentially enable a pixel reset signal and a transmission signal for the pixels corresponding to the selected at least one row. Thereby, the analog reference signal and the video signal generated from each of the pixels of the selected row may be sequentially transmitted to the ADC 140. Here, the reference signal is an electrical signal generated in a state where the sensing node (e.g., floating diffusion region) of the pixel is reset and provided to the ADC 140, and the video signal may be an electrical signal generated in a state where the photoelectric charge generated by the pixel is accumulated in the sensing node and provided to the ADC 140. The reference signal indicating the pixel-specific reset noise and the video signal indicating the intensity of the incident light may be collectively referred to as the pixel signal PS.

[0020] The ramp generator 130 can generate a ramp signal Vramp required for the analog-to-digital conversion operation of the ADC 140 by the ramp control signal RCON applied from the timing controller 170 and supply it to the ADC 140. The ramp generator 130 can control the slope of the ramp signal Vrmp based on the ramp control signal RCON. The ramp generator 130 can also be referred to as a ramp generation circuit.

[0021] According to one embodiment, the CMOS image sensor can use Correlated Double Sampling (CDS) to remove unwanted offset values of pixels, such as fixed pattern noise, by resampling the pixel signal PS twice to remove the difference between two samples. As an example, correlated double sampling can remove unwanted offset values by comparing the pixel output voltages obtained before and after the photoelectric charge generated by the incident light is accumulated in the sensing node, so that the pixel output voltage based solely on the incident light can be measured.

[0022] The ADC 140 can sequentially sample, hold, and convert the reference signal and the video signal provided from each of the plurality of column lines from the pixel array 110 into ADC data ADC_OUT by the control signal ADC_CON applied from the timing controller 170, and output the ADC data ADC_OUT. In one embodiment, the ADC 140 may be implemented as a ramp-compare type ADC using the ramp signal Vramp of the ramp generator 130.

[0023] According to one embodiment, the ADC data ADC_OUT (which may correspond to the image data IDATA) generated by the ADC 140 may correspond to at least two different sensitivities. Here, the sensitivity can mean the increase amount of the image data IDATA (or the increase amount of the response) with respect to the increase amount of the intensity of the incident light. That is, the higher the sensitivity, the larger the increase amount of the image data IDATA with respect to the increase amount of the intensity of the incident light, and the lower the sensitivity, the smaller the increase amount of the image data IDATA with respect to the increase amount of the intensity of the incident light. The sensitivity in the present disclosure may be determined by the analog gain in the analog gain mode AGM. The analog gain can mean the ratio of the voltage level of the pixel signal PS in analog form, which changes according to the intensity of the incident light, to the magnitude of the image data IDATA.

[0024] The ADC140 may include a capacitor divider 142. The capacitor divider 142 may include a configuration for performing correlated double sampling (CDS) operation. For example, the capacitor divider 142 may include a capacitor and / or switch that can adjust the voltage level range of the ramp signal Vramp received from the ramp generator 130 and the voltage level range of the pixel signal PS received from the pixels of the pixel array 110. Here, the voltage level range can mean the difference between the minimum voltage level and the maximum voltage level. A detailed configuration of the capacitor divider 142 will be described later in Figures 4 and 5.

[0025] The output buffer 150 can temporarily hold and output the ADC data ADC_OUT for each column provided by the ADC 140. The output buffer 150 can temporarily store the ADC data ADC_OUT output from the ADC 140 based on the output control signal OCON applied from the timing controller 170. The output buffer 150 can operate as an interface to compensate for differences in transmission (or processing) speeds between the image sensing device 100 and other devices connected to it.

[0026] The column driver 160 can select a column in the output buffer 150 based on the column control signal CCON applied from the timing controller 170, and control the output buffer 150 so that the image data IDATA temporarily stored in the selected column of the output buffer 150 is output sequentially. The column driver 160 can receive an address signal from the timing controller 170, and by generating a column selection signal based on the address signal and selecting a column in the output buffer 150, the column driver 160 can control the output buffer 150 so that the image data IDATA is output externally from the selected column.

[0027] The timing controller 170 can control at least one of the following: the low driver 120, the ramp generator 130, the ADC 140, the output buffer 150, and the column driver 160.

[0028] The timing controller 170 can provide at least one of the following: a low driver 120, a ramp generator 130, an ADC 140, an output buffer 150, and a column driver 160, which can provide a clock signal required for the operation of each component of the image sensing device 100, a control signal for timing control, and an address signal for selecting a low or column.

[0029] For example, the timing controller 170 can generate a control signal CON for controlling the low driver 120. The timing controller 170 can generate a ramp control signal RCON for controlling the ramp generator 130. The timing controller 170 can generate a control signal ADC_CON for controlling the ADC 140. The timing controller 170 can generate an output control signal OCON for controlling the output buffer 150. The timing controller 170 can generate a column control signal CCON for controlling the column driver 160.

[0030] In one embodiment, the timing controller 170 may include a logic control circuit, a phase lock loop (PLL) circuit, a timing control circuit, and a communication interface circuit.

[0031] The timing controller 170 may include a signal controller 175. The signal controller 175 can receive input information from the ISP 200 regarding the analog gain mode AGM. In one example, the signal controller 175 can generate a switch control signal SC_S for controlling the cap divider 142 based on the analog gain mode AGM. The signal controller 175 can also control a ramp control signal RCON based on the analog gain mode AGM.

[0032] For example, the signal controller 175 can generate a switch control signal SC_S to control the switches included in the cap divider 142 so that they open or close. The signal controller 175 can also control the ramp control signal RCON so that the slope of the ramp signal Vrmp is controlled.

[0033] According to another embodiment, the signal controller 175 can generate a switch control signal SC_S to control the transistors included in the cap divider 142 so that they are turned on or turned off.

[0034] In this disclosure, the signal controller 175 is shown as being located inside the timing controller 170, but the signal controller 175 may be located outside the timing controller 170 or included in the ISP 200, and the location of the signal controller 175 is not limited to this.

[0035] If the signal controller 175 is located outside the timing controller 170, the signal controller 175 can transmit control signals to the timing controller 170. The timing controller 170 can then generate a switch control signal SC_S to control the cap divider 142 based on the transmitted control signals. A detailed explanation of the operation of the signal controller 175 will be provided later in Figures 3 and 4.

[0036] ISP200 can perform video signal processing on image data IDATA received from the image sensing device 100. ISP200 can perform video signal processing on image data IDATA to reduce noise and improve image quality, including interpolation, synthesis, gamma correction, color filter array interpolation, color matrix, color correction, color enhancement, and lens distortion correction. Furthermore, ISP200 can compress the image data generated by the video signal processing for image quality improvement to produce a video file, or repair image data from the video file. The video compression format may be lossless or lossy. Examples of compression formats include JPEG (Joint Photographic Experts Group) or JPEG2000 for still images. For moving images, a video file may be generated by compressing multiple frames according to the MPEG (Moving Picture Experts Group) standard. The video file may be generated according to the Exif (Exchangeable image file format) standard, for example.

[0037] ISP200 can generate an HDR image by combining at least two images with different sensitivities. For example, image sensing device 100 can output a reduced image generated by a low analog gain with relatively low sensitivity and a high-sensitivity image generated by a high analog gain with relatively high sensitivity, and ISP200 can generate an HDR image by combining the reduced image and the high-sensitivity image. Here, reduced sensitivity and high sensitivity are relative concepts, and image sensing device 100 can generate n (where n is an integer of 2 or more) or more video data IDATA with different sensitivities, and ISP200 can generate an HDR image using these.

[0038] The analog gain mode AGM for providing analog gain information to the image sensing device 100 may be set in the ISP 200. For example, if the illuminance environment corresponds to low illuminance, the ISP 200 can determine and provide an analog gain mode AGM with a high gain value to the image sensing device 100. On the other hand, if the illuminance environment corresponds to high illuminance, the ISP 200 can determine and provide an analog gain mode AGM with a low gain value to the image sensing device 100.

[0039] In this disclosure, setting the analog gain mode AGM in the ISP200 in response to the illumination environment was described as an example. However, this disclosure is not limited to this, and the analog gain mode may be determined by the signal controller 175 upon receiving illumination information input from the ISP200, or by an AP (application processor, not shown) included in the imaging device 10.

[0040] The ISP200 or AP (not shown) can determine a first analog gain mode in response to a first illuminance environment and a second analog gain mode in response to a second illuminance environment. The ISP200 or AP (not shown) can transmit information regarding the determined analog gain modes to the image sensing device 100. For example, the ISP200 or AP (not shown) can transmit information regarding the determined analog gain modes to a signal controller 175 included in the timing controller 170.

[0041] The ISP200 can transmit image data after image processing is complete to a host device (not shown). The host device (not shown) may be a processor (e.g., an application processor) that processes the image-processed image data IDATA received from the ISP200, a memory (e.g., non-volatile memory) that stores the image data, or a display device (e.g., an LCD (liquid crystal display)) that visually outputs the image data. The ISP200 can also transmit control signals to the image sensing device 100 to control its operation (operation status, operation timing, operation mode, etc.).

[0042] Figure 2 is a circuit diagram showing one embodiment of the pixels included in the pixel array of Figure 1.

[0043] Referring to Figure 2, pixel PX may be any one of several pixels included in the pixel array 110. Although Figure 2 describes a single pixel PX, other pixels may have substantially the same structure and operation as pixel PX.

[0044] Pixel PX may include a photoelectric element PD, a transmission transistor TX, a reset transistor RX, a floating diffusion region FD, a pixel capacitor Cpx, a source follower transistor SF, and a selection transistor SX. In Figure 2, pixel PX is exemplified as including one photoelectric element PD, but in other embodiments it may be a shared pixel having multiple photoelectric elements. In this case, multiple transmission transistors may be provided corresponding to the multiple photoelectric elements.

[0045] A photoelectric conversion element (PD) can generate and store photocharge corresponding to the intensity of incident light. For example, the photoelectric conversion element (PD) may be implemented as a photodiode, phototransistor, photogate, pinned photodiode, or a combination thereof.

[0046] When the photoelectric conversion element PD is embodied as a photodiode, it may be a region doped with an impurity of a second conductivity type (e.g., N-type) within a substrate having a first conductivity type (e.g., P-type).

[0047] The transmission transistor TX may be connected between the photoelectric conversion element PD and the floating diffusion region FD. The transmission transistor TX may be turned on or turned off in response to the transmission signal TG, and when the transmission transistor TX is turned on by the logic high-level transmission signal TG, it can transfer the photocharge accumulated in the photoelectric conversion element PD to the floating diffusion region FD.

[0048] The reset transistor RX is connected between the power supply terminal VDD and the floating diffusion region FD, and in response to a logic high-level pixel reset signal RG, it can reset the voltage of the floating diffusion region FD to the voltage of the power supply terminal VDD.

[0049] The floating diffusion region FD can accumulate photocharge transferred from the transmission transistor TX. The floating diffusion region FD may be connected to a pixel capacitor Cpx connected to the ground terminal. For example, the floating diffusion region FD may be a region doped with an impurity of a second conductivity type (e.g., N-type) within a substrate having a first conductivity type (e.g., P-type), and the substrate and the impurity-doped region may be modeled as a pixel capacitor Cpx, which is a junction capacitor. The floating diffusion region FD may be referred to as a sensing node.

[0050] In this disclosure, a logic high level may mean a voltage level required to activate (e.g., turn on) the element in question (e.g., a transistor), and a logic low level may mean a voltage level required to deactivate (e.g., turn off) the element in question (e.g., a transistor).

[0051] Although Figure 2 describes an embodiment in which the floating diffusion region FD has one capacitance, the floating diffusion region FD can have two or more capacitances. For example, the floating diffusion region FD can have two types of capacitances by being connected to a DCG (dual conversion gain) transistor to selectively provide additional capacitance.

[0052] The source follower transistor SF is connected between the power supply terminal VDD and the selection transistor SX, and can amplify the change in the electrical potential of the floating diffusion region FD, which receives the photocharge stored in the photoelectric conversion element PD, and transmit it to the selection transistor SX.

[0053] The selection transistor SX is connected between the source follower transistor SF and the output signal line, and can be turned on by the selection control signal SEL to output the electrical signal transmitted from the source follower transistor SF as the pixel signal PS.

[0054] Figure 3 is a diagram showing an ADC according to one embodiment of the present disclosure.

[0055] Referring to Figure 3, the ADC 140 can receive a ramp signal Vrmp from the ramp generator 130 and a pixel signal PS from the pixel PX, and generate and output ADC data ADC_OUT based on the ramp signal Vrmp and the pixel signal PS.

[0056] The ADC140 may include a cap divider 142, a comparator 144, and a counter 146.

[0057] The cap divider 142 can receive a ramp signal Vrmp and output an adjustment ramp signal Vrmp_D. For example, the cap divider 142 can receive a ramp signal Vrmp having a first voltage level range and output an adjustment ramp signal Vrmp_D having a second voltage level range. As another example, the cap divider 142 can receive a pixel signal PS and output an adjustment pixel signal PS_D. For example, the cap divider 142 can receive a pixel signal PS having a first voltage level range and output an adjustment pixel signal PS_D having a second voltage level range.

[0058] The ramp signal Vrmp and the pixel signal PS may be converted to an adjustment ramp signal Vrmp_D and an adjustment pixel signal PS_D via a cap divider 142. The cap divider 142 can transmit the adjustment ramp signal Vrmp_D and the adjustment pixel signal PS_D to a comparator 144. The cap divider 142 can adjust the voltage level of the received pixel signal PS by controlling at least one component included in the cap divider 142 based on a switch control signal SC_S. For example, the pixel signal PS with an adjusted voltage level may correspond to the adjustment pixel signal PS_D. For instance, the cap divider 142 can open or close at least one switch included in the cap divider 142 based on a switch control signal SC_S.

[0059] The comparator 144 compares the adjustment ramp signal Vrmp_D and the adjustment pixel signal PS_D, and generates comparison data CMP_OUT according to the comparison result, which it then transmits to the counter 146. If the adjustment ramp signal Vrmp_D is greater than the adjustment pixel signal PS_D, the comparator 144 can generate logic high-level comparison data CMP_OUT. If the adjustment ramp signal Vrmp_D is less than the adjustment pixel signal PS_D, the comparator 144 can generate logic low-level comparison data CMP_OUT. In other words, the comparison data CMP_OUT can indicate the magnitude relationship between the adjustment ramp signal Vrmp_D and the adjustment pixel signal PS_D.

[0060] The counter 146 can be activated in response to the counter enable signal CNT_EN, and the activated counter 146 can perform counting in response to the logic high-level comparison data CMP_OUT and output the counting result to the ADC data ADC_OUT. Here, the counter enable signal CNT_EN can be included in the aforementioned control signal ADC_CON.

[0061] Referring to Figure 1, the signal controller 175 can cause the waveform of the ramp signal Vrmp to have a first slope in a first analog gain mode set based on the analog gain mode AGM. The signal controller 175 can also cause the voltage level range of the adjustment pixel signal PS_D to have a first range value in the first analog gain mode. In this disclosure, analog gain can mean the ratio of the voltage level of the analog form pixel signal PS, which varies with the intensity of incident light, to the magnitude of the image data IDATA. For example, the second analog gain mode can have an analog gain value greater than or equal to that of the first analog gain mode, and an analog gain value less than or equal to that of the third analog gain mode.

[0062] In the first analog gain mode, set based on the analog gain mode AGM, the ramp generator 130 can generate a ramp signal Vrmp, which includes a waveform of a first reference slope, based on the ramp control signal RCON received from the signal controller 175. At this time, the cap divider 142 can receive the ramp signal Vrmp and output an adjustment ramp signal Vrmp_D, which includes a waveform of a first slope. In the first analog gain mode, the cap divider 142 can generate an adjustment pixel signal PS_D, whose voltage level range is a first range value, based on the switch control signal SC_S received from the signal controller 175.

[0063] In the second analog gain mode, which is set based on the analog gain mode AGM, the ramp generator 130 can generate a ramp signal Vrmp, which includes a waveform of the first reference slope, based on the ramp control signal RCON received from the signal controller 175. At this time, the cap divider 142 can receive the ramp signal Vrmp and output an adjustment ramp signal Vrmp_D, which includes a waveform of the first slope. In the second analog gain mode, the cap divider 142 can generate an adjustment pixel signal PS_D, whose voltage level range is a second range value, based on the switch control signal SC_S received from the signal controller 175.

[0064] In a third analog gain mode set based on the analog gain mode AGM, the ramp generator 130 can generate a ramp signal Vrmp including a waveform of a second reference slope based on the ramp control signal RCON received from the signal controller 175. At this time, the cap divider 142 can receive the ramp signal Vrmp and output an adjustment ramp signal Vrmp_D including a waveform of a second slope. In the third analog gain mode, the cap divider 142 can generate an adjustment pixel signal PS_D whose voltage level range is a second range value based on the switch control signal SC_S received from the signal controller 175. In one example, the first slope may correspond to a value that is greater in absolute value than or equal to the second slope. In one example, the second range value may correspond to a value that is greater in absolute value than or equal to the first range value.

[0065] The signal controller 175 can control the cap divider 142 and lamp generator 130 in a first illuminance environment using a first analog gain mode, and in a second illuminance environment using a second analog gain mode. In one example, the first illuminance environment may correspond to a higher illuminance than the second illuminance environment.

[0066] The imaging device 10 can sense the external illumination environment or the intensity of incident light and determine a suitable analog gain. For example, the ISP 200 can determine a high analog gain value when the external environment is dark and a low analog gain value when the external environment is bright. The ISP 200 can adjust the signal controller 175 by transmitting information about the analog gain mode AGM to the signal controller 175 based on the determined analog gain. For example, based on the analog gain mode AGM received from the ISP 200, the signal controller 175 can generate a signal corresponding to the first analog gain mode, the second analog gain mode, or the third analog gain mode.

[0067] Figure 4 is a circuit diagram showing one embodiment of the capacitance divider included in the ADC of Figure 3.

[0068] Referring to Figure 4, the cap divider 142_1 may include a pixel line PL, a ramp line RL, a first capacitor C1, a second capacitor C2, a third capacitor C3, a first parasitic capacitor Cp1, a second parasitic capacitor Cp2, a first switch SW1, an adjustment pixel line DPL, and an adjustment ramp line DRL.

[0069] The pixel line PL can receive the pixel signal PS transmitted from the first node N1. The pixel line PL can receive the pixel signal PS and transmit it to the first capacitor C1. Referring together with Figure 3, the pixel line PL can correspond to the line connecting the pixel PX and the capacitor divider 142_1.

[0070] The ramp line RL can receive the ramp signal Vrmp transmitted from the second node N2. The ramp line RL can receive the ramp signal Vrmp and transmit it to the third capacitor C3. Referring together with Figure 3, the ramp line RL can correspond to the line connecting the ramp generator 130 and the capacitor divider 142_1.

[0071] The first capacitor C1 can receive the pixel signal PS. The third node N3 may be connected to a second capacitor C2 via a first switch SW1. For example, the third node N3 may be connected to a first parasitic capacitor Cp1.

[0072] The third capacitor C3 can receive the ramp signal Vrmp. The fourth node N4 may be connected to a second parasitic capacitor Cp2.

[0073] The first switch SW1 can be opened or closed by the first switch control signal SC_S1. Referring to Figure 1, the first switch control signal SC_S1 may be generated by the signal controller 175 and transmitted to the first switch SW1.

[0074] When the first switch SW1 receives a first switch control signal SC_S1 at the first logic level, the first switch SW1 can be closed, and when the first switch SW1 receives a first switch control signal SC_S1 at the second logic level, the first switch SW1 can be opened.

[0075] Referring to Figure 3, the adjustment pixel line DPL can transmit the adjustment pixel signal PS_D to the fifth node N5. The pixel signal PS may be converted to the adjustment pixel signal PS_D via the cap divider 142_1, and the adjustment pixel line DPL can transmit the adjustment pixel signal PS_D to the comparator 144 connected to the fifth node N5.

[0076] Referring to Figure 3, the adjustment ramp line DRL can transmit the adjustment ramp signal Vrmp_D to the sixth node N6. The ramp signal Vrmp may be converted to the adjustment ramp signal Vrmp_D via the cap divider 142_1, and the adjustment ramp line DRL can transmit the adjustment ramp signal Vrmp_D to the comparator 144 connected to the sixth node N6.

[0077] Referring to Figure 3, the signal controller 175 can generate a first switch control signal SC_S1 of a first logic level in the first analog gain mode. The signal controller 175 can also generate a ramp control signal RCON in the first analog gain mode that controls the ramp generator 130 to generate a ramp signal Vrmp containing a waveform of a first slope.

[0078] The signal controller 175 can generate a first switch control signal SC_S1 of the second logic level in the second analog gain mode. The signal controller 175 can generate a ramp control signal RCON in the second analog gain mode that controls the ramp generator 130 to generate a ramp signal Vrmp containing a first slope waveform.

[0079] The signal controller 175 can generate a first switch control signal SC_S1 of the second logic level in the third analog gain mode. The signal controller 175 can also generate a ramp control signal RCON in the third analog gain mode that controls the ramp generator 130 to generate a ramp signal Vrmp that includes a waveform of the second slope. For example, the second slope may be a gentler slope than the first slope.

[0080] In the first analog gain mode, the first switch SW1 can be closed by the first switch control signal SC_S1, in which case the voltage level range of the pixel signal PS may be compressed. The pixel signal PS may be output to an adjusted pixel signal PS_D, whose voltage level range has been adjusted, via a cap divider 142_1.

[0081] In the first analog gain mode, if the voltage level range of the pixel signal PS is twice the voltage level range of the ramp signal Vrmp, the formula for matching the voltage level range of the tuned pixel signal PS_D with the voltage level range of the tuned ramp signal Vrmp_D can satisfy the following difference. In this case, PS can correspond to the peak-to-peak voltage level [vpp] of the pixel signal PS, and Vrmp can correspond to the peak-to-peak voltage level of the ramp signal Vrmp.

[0082] Furthermore, PS_D can correspond to the peak-to-peak voltage level of the adjustment pixel signal PS_D, and Vrmp_D can correspond to the peak-to-peak voltage level [vpp] of the adjustment ramp signal Vrmp_D. C1, C2, and C3 can correspond to the capacitance levels F of the first capacitor C1, the second capacitor C2, and the third capacitor C3, respectively. Cp can correspond to the capacitance levels F of the first parasitic capacitor Cp1 and the second parasitic capacitor Cp2. In this formula, we assume that C1 = C3.

[0083]

number

[0084]

number

[0085]

number

[0086]

number

[0087]

number

[0088] In the first analog gain mode, the voltage level range of the pixel signal PS may be twice the voltage level range of the ramp signal Vrmp. Furthermore, the voltage level ranges of the adjustment pixel signal PS_D and the adjustment ramp signal Vrmp_D may be set to match each other. In this case, [Equation 1] and [Equation 2] must be satisfied.

[0089] In the first analog gain mode, when the first switch SW1 is closed by the first switch control signal SC_S1, the second capacitor C2 and the first parasitic capacitor Cp1 may be connected in parallel between the ground terminal and the third node N3.

[0090] The pixel signal PS may be converted into an adjusted pixel signal PS_D by adjusting its voltage level range through capacitance distribution based on the coupling relationship of a first capacitor C1, a second capacitor C2, and / or a first parasitic capacitor Cp1. For example, the voltage level range of the pixel signal PS may be compressed to the voltage level range of the adjusted pixel signal PS_D. The relationship between the voltage level range of the pixel signal PS and the voltage level range of the adjusted pixel signal PS_D can satisfy [Equation 3]. The equation provided herein only indicates a tendency, and the voltage level range of the pixel signal PS or the adjusted pixel signal PS_D is not limited thereto.

[0091] In the first analog gain mode, the third capacitor C3 and the second parasitic capacitor Cp2 may be connected in series between the second node N2 and the ground terminal. The ramp signal Vrmp may be converted into an adjusted ramp signal Vrmp_D by adjusting the voltage level range through capacitance distribution based on the connection relationship of the third capacitor C3 and / or the second parasitic capacitor Cp2. The relationship between the voltage level range of the ramp signal Vrmp and the voltage level range of the adjusted ramp signal Vrmp_D can satisfy [Equation 4]. The equation provided herein only indicates a tendency, and the voltage level range of the ramp signal Vrmp or the adjusted ramp signal Vrmp_D is not limited thereto.

[0092] Substituting [Equation 3] and [Equation 4] into [Equation 2] and applying [Equation 1], we can obtain [Equation 5]. For example, in the first analog gain mode, we can assume that the voltage level range of the pixel signal PS is 1 [vpp], the voltage level range of the ramp signal Vrmp is 0.5 [vpp], C1=C3=200 [fF], and Cp=20 [fF]. In this case, referring to [Equation 5], the capacitance level of the second capacitor C2 for matching the voltage level range of the adjustment pixel signal PS_D and the voltage level range of the adjustment ramp signal Vrmp_D can be 220 [fF]. In this case, referring to [Equation 3], the voltage level range of the adjustment pixel signal PS_D can be 0.4545 [vpp]. Also, referring to [Equation 4], the voltage level range of the adjustment ramp signal Vrmp_D can be 0.4545 [vpp].

[0093] The voltage level range of the pixel signal PS must be within the input range of the comparator 144. For example, the comparator 144 can generate valid ADC data ADC_OUT for a pixel signal PS within the input range. When the first switch SW1 is closed by the first switch control signal SC_S1, the voltage level range of the pixel signal PS may be compressed through capacitance distribution by the coupling relationship of the first capacitor C1, the second capacitor C2, and the first parasitic capacitor Cp1, etc. The cap divider 142 can compress the voltage level range of the pixel signal PS to generate an adjusted pixel signal PS_D. Based on the adjusted pixel signal PS_D, the comparator 144 can generate valid ADC data ADC_OUT even for a pixel signal PS having a wide range of voltage levels. That is, the imaging device 10 can obtain a high dynamic range (HDR) image using the cap divider 142.

[0094] Referring together with Figure 1, the signal controller 175 can control the ramp generator 130 and / or the cap divider 142 by analog gain mode AGM to reduce noise generated during the process of compressing the pixel signal PS. In this disclosure, noise is assumed to refer to noise that means the degree to which the intensity of incident light incident on the image sensing device 100 does not match the voltage level of the corresponding pixel signal PS, and noise generated in the circuits within the imaging device 10, etc.

[0095] According to one embodiment, noise may be mitigated when the waveform of the ramp signal Vrmp has a sharp slope. In one example, when only the voltage level range of the pixel signal PS is compressed without compressing the ramp signal Vrmp, the signal-to-noise ratio (SNR) may be maintained or improved compared to when both the ramp signal Vrmp and the pixel signal PS are compressed simultaneously.

[0096] In the first analog gain mode, the signal controller 175 can cancel out noise generated by the compression of the voltage level range of the pixel signal PS, which reduces the input signal, by matching it with a ramp signal Vrmp having a waveform with a relatively steep slope (first slope). In the second analog gain mode, the signal controller 175 can ensure that the voltage level range of the pixel signal PS is not compressed, and that the ramp signal Vrmp has a waveform with a first slope.

[0097] The signal controller 175 can cause the ramp signal Vrmp to have a waveform with a first slope in the first analog gain mode and the second analog gain mode. By causing the ramp signal Vrmp to have a waveform with a common first slope in the first analog gain mode and the second analog gain mode, the signal controller 175 can eliminate the need for components to change the slope of the ramp signal Vrmp (e.g., a ramp signal control switch) or save the physical size and / or power consumption of the image sensing device 100.

[0098] The signal controller 175 can close the first switch SW1 of the cap divider 142_1 in the first analog gain mode, and open the first switch SW1 of the cap divider 142_1 in the second analog gain mode.

[0099] Figure 5 is a schematic diagram showing another embodiment of the cap divider included in the ADC of Figure 3.

[0100] Referring to Figure 5, the cap divider 142_2 may include a pixel line PL, a ramp line RL, a first capacitor C1, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a first parasitic capacitor Cp1, a second parasitic capacitor Cp2, a first switch SW1, a second switch SW2, a shared line SL, an adjustment pixel line DPL, and an adjustment ramp line DRL.

[0101] The pixel line PL can receive the pixel signal PS transmitted from the first node N1. The pixel line PL can receive the pixel signal PS and transmit it to the first capacitor C1. Referring together with Figure 3, the pixel line PL can correspond to the line connecting the pixel PX and the capacitor divider 142_2.

[0102] The ramp line RL can receive the ramp signal Vrmp transmitted from the second node N2. In one example, the ramp line RL can receive the ramp signal Vrmp and transmit it to the third capacitor C3. Referring together with Figure 3, the ramp line RL can correspond to the line connecting the ramp generator 130 and the capacitor divider 142_2.

[0103] The first capacitor C1 can receive the pixel signal PS. The third node N3 may be connected to a fourth capacitor C4 via a first switch SW1. In one example, the third node N3 may be connected to a first parasitic capacitor Cp1.

[0104] The third capacitor C3 can receive the ramp signal Vrmp. The fifth capacitor C5 may be connected between the shared line SL and the ground terminal. In one example, the fourth node N4 may have a second parasitic capacitor Cp2 connected to it.

[0105] The first switch SW1 can be opened or closed by the first switch control signal SC_S1. Referring to Figure 1, the first switch control signal SC_S1 may be generated by the signal controller 175 and transmitted to the first switch SW1.

[0106] If the first switch SW1 receives a first switch control signal SC_S1 at the first logic level, the first switch SW1 can be closed, and if the first switch SW1 receives a first switch control signal SC_S1 at the second logic level, the first switch SW1 can be opened.

[0107] The second switch SW2 can receive the second switch control signal SC_S2. Referring to Figure 1, the second switch control signal SC_S2 may be generated by the signal controller 175 and transmitted to the second switch SW2.

[0108] The shared line SL can connect the node connecting the first switch SW1 and the fourth capacitor C4 to the node connecting the second switch SW2 and the fifth capacitor C5. The second switching control signal SC_S2 may set the second switch SW2 to always be open. When the second switch SW2 is open, the fourth capacitor C4 and the fifth capacitor C5 may be connected in parallel between the node connecting the first switch SW1 and the fourth capacitor C4 and the ground terminal.

[0109] For example, the sum of the capacitances of the fourth capacitor C4 and the fifth capacitor C5 may be the same as the value of the capacitance of the second capacitor C2 in Figure 4 described above. The first capacitor C1, the first switch SW1, and the fourth capacitor C4 connected to node ND3 have a symmetrical structure with the third capacitor C3, the second switch SW2, and the fifth capacitor C5 connected to node ND4, so that noise can be canceled out at nodes N3 and N4. As a result, the second switch SW2 is set to always be open, and the voltage level of the adjustment pixel signal PS_D can be changed by opening and closing the first switch SW1 in accordance with the capacitances of the first capacitor C1, the fourth capacitor C4, and the fifth capacitor C5 connected to the fourth capacitor C4 via a shared line SL. In this disclosure, the sum of the capacitances of the fourth capacitor C4 and the fifth capacitor C5 is set to be the same as the value of the second capacitor C2, but this disclosure is not limited to this, and the capacitances of the fourth capacitor C4 and the fifth capacitor C5 may be different from each other, and the ratio of the capacitances of the fourth capacitor C4 and the fifth capacitor C5 can be changed considerably.

[0110] Referring to Figure 3, the adjustment pixel line DPL can transmit the adjustment pixel signal PS_D to the fifth node N5. The pixel signal PS may be converted to the adjustment pixel signal PS_D via the cap divider 142_2, and the adjustment pixel line DPL can transmit the adjustment pixel signal PS_D to the comparator 144 connected to the fifth node N5.

[0111] Referring to Figure 3, the adjustment ramp line DRL can transmit the adjustment ramp signal Vrmp_D to the sixth node N6. The ramp signal Vrmp may be converted to the adjustment ramp signal Vrmp_D via the cap divider 142_2, and the adjustment ramp line DRL can transmit the adjustment ramp signal Vrmp_D to the comparator 144 connected to the sixth node N6.

[0112] Referring to Figure 3, the signal controller 175 can generate a first switch control signal SC_S1 at a first logic level in the first analog gain mode. The signal controller 175 can also generate a second switch control signal SC_S2 at a second logic level in the first analog gain mode. The signal controller 175 can also generate a ramp control signal RCON in the first analog gain mode that controls the ramp generator 130 to generate a ramp signal Vrmp containing a waveform of a first slope.

[0113] The signal controller 175 can generate a first switch control signal SC_S1 at a second logic level in the second analog gain mode. The signal controller 175 can also generate a second switch control signal SC_S2 at a second logic level in the second analog gain mode. The signal controller 175 can also generate a ramp control signal RCON in the second analog gain mode, which controls the ramp generator 130 to generate a ramp signal Vrmp containing a first slope waveform.

[0114] The signal controller 175 can generate a first switch control signal SC_S1 at a second logic level in the third analog gain mode. The signal controller 175 can also generate a second switch control signal SC_S2 at a second logic level in the third analog gain mode. The signal controller 175 can also generate a ramp control signal RCON in the third analog gain mode, which controls the ramp generator 130 to generate a ramp signal Vrmp containing a second slope waveform.

[0115] In the first analog gain mode, the first switch SW1 can be closed by the first switch control signal SC_S1, and the second switch SW2 can be opened by the second switch control signal SC_S2. In this case, the voltage level range of the pixel signal PS can be compressed. The pixel signal PS can be output as an adjusted pixel signal PS_D with an adjusted voltage level range via the cap divider 142_1.

[0116] In the first analog gain mode, if the voltage level range of the pixel signal PS is twice the voltage level range of the ramp signal Vrmp, the formula for matching the voltage level range of the tuned pixel signal PS_D with the voltage level range of the tuned ramp signal Vrmp_D can satisfy the following difference. In this case, PS can correspond to the peak-to-peak voltage level [vpp] of the pixel signal PS, and Vrmp can correspond to the peak-to-peak voltage level of the ramp signal Vrmp.

[0117] Furthermore, PS_D can correspond to the peak-to-peak voltage level of the adjustment pixel signal PS_D, and Vrmp_D can correspond to the peak-to-peak voltage level [vpp] of the adjustment ramp signal Vrmp_D. C1, C4, C3, and C5 can correspond to the capacitance levels F of the first capacitor C1, the fourth capacitor C4, the third capacitor C3, and the fifth capacitor C5, respectively. Cp can correspond to the capacitance levels F of the first parasitic capacitor Cp1 and the second parasitic capacitor Cp2. In this formula, we assume that C1=C3 and C4=C5.

[0118]

number

[0119]

number

[0120]

number

[0121]

number

[0122]

number

[0123] In the first analog gain mode, the voltage level range of the pixel signal PS may be twice the voltage level range of the ramp signal Vrmp. Furthermore, the voltage level ranges of the adjustment pixel signal PS_D and the adjustment ramp signal Vrmp_D may be set to match each other. In this case, equations 6 and 7 must be satisfied.

[0124] In the first analog gain mode, when the first switch SW1 is closed by the first switch control signal SC_S1, the fourth capacitor C4 and the first parasitic capacitor Cp1 may be connected in parallel between the ground terminal and the third node N3. Also, since the second switch SW2 is open, the fourth capacitor C4 and the fifth capacitor C5 may be connected in parallel between the node connecting the first switch SW1 and the fourth capacitor C4 and the ground terminal. That is, the fourth capacitor C4, the third capacitor C3, and the first parasitic capacitor Cp1 may be connected in parallel between the ground terminal and the third node N3.

[0125] The pixel signal PS may be converted into an adjusted pixel signal PS_D by adjusting its voltage level range through capacitance distribution based on the coupling relationship of the first capacitor C1, the fourth capacitor C4, the fifth capacitor C5, and / or the first parasitic capacitor Cp1. For example, the voltage level range of the pixel signal PS may be compressed to the voltage level range of the adjusted pixel signal PS_D. The relationship between the voltage level range of the pixel signal PS and the voltage level range of the adjusted pixel signal PS_D can be satisfied by [Equation 8]. The equation provided herein only indicates a tendency, and the voltage level range of the pixel signal PS or the adjusted pixel signal PS_D is not limited thereto.

[0126] In the first analog gain mode, the third capacitor C3 and the second parasitic capacitor Cp2 may be connected in series between the second node N2 and the ground terminal. For example, the ramp signal Vrmp may be converted into an adjusted ramp signal Vrmp_D by adjusting the voltage level range through capacitance distribution based on the connection relationship between the third capacitor C3 and / or the second parasitic capacitor Cp2. The relationship between the voltage level range of the ramp signal Vrmp and the voltage level range of the adjusted ramp signal Vrmp_D can satisfy [Equation 9]. The equation provided herein only indicates a tendency, and the voltage level range of the ramp signal Vrmp or the adjusted ramp signal Vrmp_D is not limited thereto.

[0127] Substituting [Equation 8] and [Equation 9] into [Equation 7] and applying [Equation 6], we can obtain [Equation 10]. For example, in the first analog gain mode, we can assume that the voltage level range of the pixel signal PS is 1 [vpp], the voltage level range of the ramp signal Vrmp is 0.5 [vpp], C1=C3=200 [fF], and Cp=20 [fF]. In this case, referring to [Equation 10], the capacitance level of the fourth capacitor C4 for matching the voltage level range of the adjustment pixel signal PS_D and the voltage level range of the adjustment ramp signal Vrmp_D can be 110 [fF]. In this case, referring to [Equation 8], the voltage level range of the adjustment pixel signal PS_D can be 0.4545 [vpp]. Also, referring to [Equation 9], the voltage level range of the adjustment ramp signal Vrmp_D can be 0.4545 [vpp].

[0128] The capacitor divider 142_2 minimizes external noise response by symmetrically arranging the pixel line PL, ramp line RL, first capacitor C1, fourth capacitor C4, third capacitor C3, fifth capacitor C5, first parasitic capacitor Cp1, second parasitic capacitor Cp2, first switch SW1, second switch SW2, and shared line SL.

[0129] Figure 6 is a timing diagram illustrating the voltage level of the adjustment pixel signal, which changes as the first switch shown in Figure 5 is opened or closed.

[0130] Referring to Figures 2 to 4 and Figure 6, based on the first switch control signal SC_S1 being a logic high level H, when the first switch SW1 is closed, the voltage level range of the adjustment pixel signal PS_D can correspond to the adjustment range D_on. Based on the first switch control signal SC_S1 being a logic low level L, when the first switch SW1 is open, the voltage level range of the adjustment pixel signal PS_D can correspond to the reference range D_off.

[0131] The voltage level range of the pixel signal PS may be greater than or equal to the reference range D_off. This is because the voltage level range of the pixel signal PS may be reduced by capacitance distribution due to the coupling relationship of the first capacitor C1, the second capacitor C2, and / or the first parasitic capacitor Cp1, and the pixel signal PS with the reduced voltage level range may be output as the adjusted pixel signal PS_D.

[0132] Based on the fact that the second switch control signal SC_S2 is at a logic low level L, while the second switch SW2 is open, the voltage level range of the adjustment ramp signal Vrmp_D can fall within the reference ramp range R_off. In one example, while the first switch SW1 is open or closed, the second switch SW2 may be set to be open. For example, in the first and second analog gain modes, the second switch SW2 may always be set to be open, and therefore the voltage level range of the adjustment ramp signal Vrmp_D can be maintained within the reference ramp range R_off.

[0133] The pixel reset signal RG, transmission signal TG, and selection control signal SEL, which affect the voltage level of the adjustment pixel signal PS_D, will be explained later in Figures 7a to 7c.

[0134] Figures 7a to 7c are timing diagrams illustrating the voltage levels of the adjustment pixel signal and adjustment ramp signal, which vary depending on the signals shown in Figures 2 to 4.

[0135] Referring to Figures 2 to 4 and Figure 7a, in the first analog gain mode, the operation in which the adjustment pixel signal PS_D is converted to image data IDATA may occur during the readout section RO. For example, the readout section RO may correspond to the section in which the ADC140 receives the pixel signal PS from the source follower transistor SF based on the logic high-level H selection control signal SEL.

[0136] The pixel signal PS may be converted to an adjusted pixel signal PS_D by passing through the cap divider 142, and the adjusted pixel signal PS_D may be divided into a reference signal and a video signal. The readout section RO may correspond to the section in which the reference signal and video signal are converted to digital values.

[0137] The first analog gain mode may be a mode in which the increase in response (or image data) due to an increase in the intensity of incident light corresponds to the first gain value. For example, the first gain value of the first analog gain mode may be the same as or lower than the second gain value of the second analog gain mode and the third gain value of the third analog gain mode.

[0138] The readout section RO may be divided into a reset section RST and a signal section SIG. The reset section RST may be the section in which the reference signal is converted to analog-to-digital (AD), and the signal section SIG may be the section in which the video signal is converted to analog-to-digital (AD).

[0139] In the reset section RST, the pixel reset signal RG temporarily has a logic high level H, which may cause a pixel signal PS corresponding to the voltage of the reset floating diffusion region FD to be output from the pixel PX. The pixel signal PS corresponding to the voltage of the reset floating diffusion region FD may pass through the cap divider 142 and be converted into an adjusted pixel signal PS_D.

[0140] The comparison data CMP_OUT may have a logic high level H in the interval where the adjustment ramp signal Vrmp_D is greater than the adjustment pixel signal PS_D, and a logic low level L in the interval where the adjustment ramp signal Vrmp_D is less than the adjustment pixel signal PS_D.

[0141] The counter enable signal CNT_EN may have a logic high level H in the interval where the adjustment ramp signal Vrmp_D has a first slope L1 with a negative slope. The counter 146 may be activated in response to the counter enable signal CNT_EN having a logic high level H.

[0142] The activated counter 146 can perform counting during intervals where the comparison data CMP_OUT is at logic high level H, and output the counting result to the ADC data ADC_OUT. The value obtained by A / D conversion of the reference signal can correspond to the value counted by counter 146 during the reset data counting interval RDC.

[0143] In the signal section SIG, the transmission signal TG temporarily has a logic high level H, which may cause a pixel signal PS corresponding to the voltage of the floating diffusion region FD where the photocharge generated at pixel PX is accumulated to be output from pixel PX. The voltage level of the pixel signal PS may decrease in proportion to the amount of photocharge accumulated in the floating diffusion region FD.

[0144] The pixel signal PS with a reduced voltage level may be converted to an adjustment pixel signal PS_D with a reduced voltage level by passing through the cap divider 142. The adjustment pixel signal PS_D in the signal section SIG may have a voltage level that is lower by a first range value D1 than the adjustment pixel signal PS_D in the reset section RST.

[0145] After the signal section SIG is started and a predetermined time has elapsed, the lamp generator 130 can output a lamp output signal Vrmp having a first slope L1 which is a negative slope. Here, the first slope L1 of the lamp output signal Vrmp may be the same as the first slope L1 of the lamp output signal Vrmp in the reset section RST.

[0146] The comparison data CMP_OUT may have a logic high level H in the interval where the adjustment ramp signal Vrmp_D is greater than the adjustment pixel signal PS_D, and a logic low level L in the interval where the adjustment ramp signal Vrmp_D is less than the adjustment pixel signal PS_D.

[0147] The counter enable signal CNT_EN may have a logic high level H in the interval where the adjustment ramp signal Vrmp_D has a first slope L1 with a negative slope. The counter 146 may be activated in response to the counter enable signal CNT_EN having a logic high level H.

[0148] The activated counter 146 can perform counting during intervals where the comparison data CMP_OUT is at logic high level H, and output the counting result to the ADC data ADC_OUT. The value obtained by A / D conversion of the video signal can correspond to the value counted by counter 146 during the pixel data counting interval PDC.

[0149] In the first analog gain mode, the value corresponding to the voltage difference between the video signal and the reference signal (i.e., the signal component from which reset noise has been removed) may be obtained by subtracting the value obtained by AD conversion of the reference signal from the value obtained by AD conversion of the video signal.

[0150] Referring to Figures 2 to 4 and Figure 7b, in the second analog gain mode, the operation in which the adjustment pixel signal PS_D is converted to image data may occur during the readout section RO. The readout section RO may correspond to the section in which the ADC140 receives the pixel signal PS from the source follower transistor SF based on the logic high-level H selection control signal SEL.

[0151] The pixel signal PS may be converted to an adjusted pixel signal PS_D by passing through the cap divider 142, and the adjusted pixel signal PS_D may be divided into a reference signal and a video signal. The readout section RO may correspond to the section in which the reference signal and video signal are converted to digital values.

[0152] The second analog gain mode may be a mode in which the increase in response (or image data) due to an increase in the intensity of incident light corresponds to the second gain value. For example, the second gain value of the second analog gain mode may be greater than or equal to the first gain value of the first analog gain mode. The second gain value of the second analog gain mode may be equal to or lower than the third gain value of the third analog gain mode.

[0153] The readout section RO may be divided into a reset section RST and a signal section SIG. For example, the reset section RST may be the section where the reference signal is converted to analog-to-digital (AD), and the signal section SIG may be the section where the video signal is converted to analog-to-digital (AD).

[0154] In the reset section RST, the pixel reset signal RG temporarily has a logic high level H, which may cause a pixel signal PS corresponding to the voltage of the reset floating diffusion region FD to be output from the pixel PX. The pixel signal PS corresponding to the voltage of the reset floating diffusion region FD may pass through the cap divider 142 and be converted into an adjusted pixel signal PS_D.

[0155] The comparison data CMP_OUT may have a logic high level H in the interval where the adjustment ramp signal Vrmp_D is greater than the adjustment pixel signal PS_D, and a logic low level L in the interval where the adjustment ramp signal Vrmp_D is less than the adjustment pixel signal PS_D.

[0156] The counter enable signal CNT_EN may have a logic high level H in the interval where the adjustment ramp signal Vrmp_D has a first slope L1 with a negative slope. The counter 146 may be activated in response to the counter enable signal CNT_EN having a logic high level H.

[0157] The activated counter 146 can perform counting during intervals where the comparison data CMP_OUT is at logic high level H, and output the counting result to the ADC data ADC_OUT. The value obtained by A / D conversion of the reference signal can correspond to the value counted by counter 146 during the reset data counting interval RDC.

[0158] In the signal section SIG, the transmission signal TG temporarily has a logic high level H, which may cause a pixel signal PS corresponding to the voltage of the floating diffusion region FD where the photocharge generated at pixel PX is accumulated to be output from pixel PX. The voltage level of the pixel signal PS may decrease in proportion to the amount of photocharge accumulated in the floating diffusion region FD.

[0159] The pixel signal PS with a reduced voltage level may be converted to an adjustment pixel signal PS_D with a reduced voltage level by passing through the cap divider 142. The adjustment pixel signal PS_D in signal section SIG may have a voltage level that is lower by a second range value D2 than the adjustment pixel signal PS_D in reset section RST.

[0160] After the signal section SIG is started and a predetermined time has elapsed, the lamp generator 130 can output a lamp output signal Vrmp having a first slope L1 which is a negative slope. Here, the first slope L1 of the lamp output signal Vrmp may be the same as the first slope L1 of the lamp output signal Vrmp in the reset section RST.

[0161] The comparison data CMP_OUT may have a logic high level H in the interval where the adjustment ramp signal Vrmp_D is greater than the adjustment pixel signal PS_D, and a logic low level L in the interval where the adjustment ramp signal Vrmp_D is less than the adjustment pixel signal PS_D.

[0162] The counter enable signal CNT_EN may have a logic high level H in the interval where the adjustment ramp signal Vrmp_D has a first slope L1 with a negative slope. The counter 146 may be activated in response to the counter enable signal CNT_EN having a logic high level H.

[0163] The activated counter 146 can count the intervals in which the comparison data CMP_OUT is at a logic high level (H) and output the counting result to the ADC data ADC_OUT. The value obtained by A / D conversion of the video signal can correspond to the value counted by the counter 146 during the pixel data counting interval PDC. The pixel data counting interval PDC in the second analog gain mode may be greater than the pixel data counting interval PDC in the first analog gain mode.

[0164] In the second analog gain mode, the value corresponding to the voltage difference between the video signal and the reference signal (i.e., the signal component from which reset noise has been removed) may be obtained by subtracting the value obtained by AD conversion of the reference signal from the value obtained by AD conversion of the video signal.

[0165] Referring to Figures 2 to 4 and Figure 7c, in the third analog gain mode, the operation in which the adjustment pixel signal PS_D is converted to image data may occur during the readout section RO. The readout section RO may correspond to the section in which the ADC140 receives the pixel signal PS from the source follower transistor SF based on the logic high-level H selection control signal SEL.

[0166] The pixel signal PS may be converted to an adjusted pixel signal PS_D by passing through the cap divider 142, and the adjusted pixel signal PS_D may be divided into a reference signal and a video signal. The readout section RO may correspond to the section in which the reference signal and video signal are converted to digital values.

[0167] The third analog gain mode may be a mode in which the increase in response (or image data) due to an increase in the intensity of incident light corresponds to the third gain value. The third gain value of the third analog gain mode may be the same as or greater than the first gain value of the first analog gain mode and the second gain value of the second analog gain mode.

[0168] The readout section RO may be divided into a reset section RST and a signal section SIG. The reset section RST may be the section in which the reference signal is converted to analog-to-digital (AD), and the signal section SIG may be the section in which the video signal is converted to analog-to-digital (AD).

[0169] In the reset section RST, the pixel reset signal RG temporarily has a logic high level H, which may cause a pixel signal PS corresponding to the voltage of the reset floating diffusion region FD to be output from the pixel PX. The pixel signal PS corresponding to the voltage of the reset floating diffusion region FD may pass through the cap divider 142 and be converted into an adjusted pixel signal PS_D.

[0170] The comparison data CMP_OUT may have a logic high level H in the interval where the adjustment ramp signal Vrmp_D is greater than the adjustment pixel signal PS_D, and a logic low level L in the interval where the adjustment ramp signal Vrmp_D is less than the adjustment pixel signal PS_D.

[0171] The counter enable signal CNT_EN may have a logic high level H in the interval where the adjustment ramp signal Vrmp_D has a second slope L2 with a negative slope. The counter 146 may be activated in response to the counter enable signal CNT_EN having a logic high level H.

[0172] The activated counter 146 can perform counting during intervals where the comparison data CMP_OUT is at logic high level H, and output the counting result to the ADC data ADC_OUT. The value obtained by A / D conversion of the reference signal can correspond to the value counted by counter 146 during the reset data counting interval RDC.

[0173] In the signal section SIG, the transmission signal TG temporarily has a logic high level H, which may cause a pixel signal PS corresponding to the voltage of the floating diffusion region FD where the photocharge generated at pixel PX is accumulated to be output from pixel PX. The voltage level of the pixel signal PS may decrease in proportion to the amount of photocharge accumulated in the floating diffusion region FD.

[0174] The pixel signal PS with a reduced voltage level may be converted to an adjustment pixel signal PS_D with a reduced voltage level by passing through the cap divider 142. The adjustment pixel signal PS_D in the signal section SIG may have a voltage level that is lower by a second range value D2 than the adjustment pixel signal PS_D in the reset section RST.

[0175] After the signal section SIG is started and a predetermined time has elapsed, the lamp generator 130 can output a lamp output signal Vrmp having a second slope L2 which is a negative slope. Here, the second slope L2 of the lamp output signal Vrmp may be the same as the second slope L2 of the lamp output signal Vrmp in the reset section RST.

[0176] The comparison data CMP_OUT may have a logic high level H in the interval where the adjustment ramp signal Vrmp_D is greater than the adjustment pixel signal PS_D, and a logic low level L in the interval where the adjustment ramp signal Vrmp_D is less than the adjustment pixel signal PS_D.

[0177] The counter enable signal CNT_EN may have a logic high level H in the interval where the adjustment ramp signal Vrmp_D has a second slope L2 with a negative slope. The counter 146 may be activated in response to the counter enable signal CNT_EN having a logic high level H.

[0178] The activated counter 146 can count the intervals in which the comparison data CMP_OUT is at logic high level H and output the counting result to the ADC data ADC_OUT. The value obtained by A / D conversion of the video signal can correspond to the value counted by the counter 146 during the pixel data counting interval PDC. The pixel data counting interval PDC in the third analog gain mode may be larger than the pixel data counting interval PDC in the second analog gain mode.

[0179] In the first analog gain mode, the value corresponding to the voltage difference between the video signal and the reference signal (i.e., the signal component from which reset noise has been removed) may be obtained by subtracting the value obtained by AD conversion of the reference signal from the value obtained by AD conversion of the video signal. [Explanation of symbols]

[0180] 10 Imaging equipment 100 Image Sensing Devices 110 pixel array 120 Low Driver 130 Lamp generator 142. Cap divider 144 comparator 146 counter 150 Output buffer 150 output buffer 160 Column Driver 170 Timing controller 175 Signal Controller

Claims

1. A lamp generator that produces lamp signals; A cap divider that, in a first analog gain mode, adjusts the voltage level range of a pixel signal to a first voltage level range value and outputs a first adjusted pixel signal, or in a second analog gain mode, adjusts the voltage level range of the pixel signal to a second voltage level range value and outputs a second adjusted pixel signal; and An image sensing device including a signal controller that controls the lamp generator such that the waveform of the lamp signal has a first slope in the first analog gain mode and the second analog gain mode.

2. The aforementioned cap divider is, A first capacitor connected between a first node and a second node to which the pixel signal is applied; A second capacitor connected to the ground terminal; and The image sensing apparatus according to claim 1, further comprising a first switch connected between the second node and the second capacitor, the switching operation of which is controlled by a first switch control signal.

3. The aforementioned signal controller is The first switch control signal is generated based on the first analog gain mode or the second analog gain mode. The image sensing device according to claim 2, wherein the first switch is controlled to open or close based on the first switch control signal.

4. The aforementioned signal controller is The image sensing apparatus according to claim 2, wherein the first switch is controlled to close in the first analog gain mode and the first switch is controlled to open in the second analog gain mode.

5. The aforementioned cap divider is, The image sensing apparatus according to claim 2, wherein the voltage level range of the pixel signal is adjusted by capacitance distribution through the linkage of the first capacitor, the second capacitor, and the first parasitic capacitor generated at the second node.

6. The aforementioned cap divider is, The image sensing apparatus according to claim 2, further comprising a third capacitor connected to a third node to which the lamp signal is applied.

7. The aforementioned cap divider is, The image sensing device according to claim 6, wherein the voltage level range of the lamp signal is adjusted by capacitance distribution through the connection of the third capacitor and the second parasitic capacitor generated at the third node.

8. The aforementioned cap divider is, A first capacitor connected between a first node and a second node to which the pixel signal is applied; A fourth capacitor connected to the ground terminal; A first switch connected between the second node and the fourth capacitor, the switching operation of which is controlled by a first switch control signal; A third capacitor connected between the third node and the fourth node to which the aforementioned ramp signal is applied; A fifth capacitor connected to the aforementioned grounding terminal; A second switch connected between the fourth node and the fifth capacitor, the switching operation of which is controlled by a second switch control signal; and The image sensing apparatus according to claim 1, further comprising a shared line connecting the fourth capacitor and the fifth capacitor.

9. The aforementioned cap divider is The image sensing apparatus according to claim 8, wherein the voltage level range of the pixel signal is adjusted by capacitance distribution through the linking of the first capacitor, the fourth capacitor, the fifth capacitor, and the first parasitic capacitor generated at the second node.

10. The aforementioned cap divider is, The image sensing device according to claim 8, wherein the voltage level range of the ramp signal is adjusted by capacitance distribution through the connection of the third capacitor and the second parasitic capacitor generated at the fourth node.

11. The image sensing device according to claim 1, wherein the second voltage level range value is greater than the first voltage level range value.

12. The first analog gain mode corresponds to a first illuminance environment, The second analog gain mode corresponds to a second illumination environment. The image sensing device according to claim 1, wherein the illuminance corresponding to the first illuminance environment is higher than the illuminance corresponding to the second illuminance environment.

13. The aforementioned cap divider is, In the third analog gain mode, the voltage level range of the pixel signal is adjusted to the second voltage level range value and the second adjusted pixel signal is output. The aforementioned signal controller is The image sensing apparatus according to claim 1, wherein in the third analog gain mode, the lamp generator is controlled so that the waveform of the lamp signal has a second slope.

14. The image sensing device according to claim 13, wherein the second incline is a gentler incline than the first incline.

15. A comparator that compares the first adjustment pixel signal or the second adjustment pixel signal with the ramp signal to generate comparison data; and The image sensing apparatus according to claim 1, further comprising a counter for counting the comparison data based on a counter enable signal.

16. A pixel array that generates pixel signals; A signal controller that generates lamp control signals and switch control signals based on analog gain modes corresponding to illuminance; A cap divider that adjusts the voltage level range of the pixel signal to a first voltage level range value based on the switch control signal and outputs it as a first adjusted pixel signal, or adjusts the voltage level range of the pixel signal to a second voltage level range value and outputs it as a second adjusted pixel signal; A lamp generator that adjusts the slope of the lamp signal based on the aforementioned lamp control signal; and An image sensing device including a comparator that compares the first adjustment pixel signal or the second adjustment pixel signal with the lamp signal to generate comparison data.

17. The aforementioned cap divider is, A first capacitor connected between a first node and a second node to which the pixel signal is applied; Second capacitor connected to the ground terminal; A first switch connected between the second node and the second capacitor, the switching operation of which is controlled by a first switch control signal; and The image sensing apparatus according to claim 16, further comprising a third capacitor connected to a third node to which the lamp signal is applied.

18. The aforementioned cap divider is, The image sensing apparatus according to claim 17, wherein the voltage level range of the pixel signal is adjusted by capacitance distribution through the connection of the first capacitor, the second capacitor, and the first parasitic capacitor generated at the second node.

19. The aforementioned cap divider is, A first capacitor connected between a first node and a second node to which the pixel signal is applied; A fourth capacitor connected to the ground terminal; A first switch connected between the second node and the fourth capacitor, the switching operation of which is controlled by a first switch control signal; A third capacitor connected between the third node and the fourth node to which the aforementioned ramp signal is applied; A fifth capacitor connected to the aforementioned grounding terminal; A second switch connected between the fourth node and the fifth capacitor, the switching operation of which is controlled by a second switch control signal; and The image sensing apparatus according to claim 16, further comprising a shared line connecting the fourth capacitor and the fifth capacitor.

20. The aforementioned cap divider is The image sensing apparatus according to claim 19, wherein the voltage level range of the pixel signal is adjusted by capacitance distribution through the linkage of the first capacitor, the fourth capacitor, the fifth capacitor, and the first parasitic capacitor generated at the second node.

Images