System and method for estimating symbol timing in a received data frame

Abstract

The present invention provides a method and circuit for estimating symbol timings within one or more received data frames of a given nominal envelope signal. [Solution] The circuit includes an envelope detector and a symbol timing estimator. The envelope detector generates an envelope detection output 212 of the received data frame 20. The envelope detection output has amplitude ripple related to the symbol timing in the received data frame. The symbol timing estimator receives the envelope detection output and generates a symbol timing estimate output 216 based on the amplitude ripple.

Description

[Technical Field]

[0001]

[0001] (Cross-reference of related applications) This application claims the interests of U.S. Provisional Patent Application No. 63 / 707,520, filed on 15 October 2024, and U.S. Patent Application No. 18 / 964,068, filed on 29 November 2024, the entire contents of both U.S. Provisional Patent Application No. 63 / 707,520 and U.S. Patent Application No. 18 / 964,068 are incorporated herein by reference.

[0002]

[0002] (Field) This subject relates to a system and method for estimating symbol timing in a received data frame, and more particularly to a system and method for estimating symbol timing in a received data frame of a certain nominal envelope signal. [Background technology]

[0003]

[0003] Wireless communication involves transmitting and receiving data using radio frequency (RF) signals. The transmitter generates a data frame for transmission by assigning data to blocks of modulation symbols. A symbol refers to any suitable representation of information. For example, in some applications, a symbol may correspond to a single bit. In some applications, a symbol may correspond to a sequence of chips. Any suitable modulation scheme may be used to assign data to modulation symbols. Some non-exclusive examples of modulation schemes include phase shift keying (PSK) and frequency shift keying (FSK).

[0004]

[0004] Symbol timing estimation can generally refer to the estimation of symbol frequencies and / or symbol phases within a data frame. For example, symbol timing estimation may include detecting the start time and duration of a symbol. Symbol timing estimation may be required in many communication applications. For example, a receiver may use symbol timing estimation to demodulate a received signal and reconstruct transmitted data. As another example, a backscatter tag may use symbol timing estimation to assist in generating a backscatter signal containing encoded backscatter tag data. [Overview of the Initiative]

[0005]

[0005] The following introduction is provided to introduce the reader to the following more detailed explanation. The introduction is not intended to limit or define any claimed or unclaimed invention. One or more inventions may be any combination or partial combination of elements or process steps disclosed in any part of this document, including its claims and drawings.

[0006]

[0006] In one broad embodiment, a circuit is provided for estimating symbol timings in one or more received data frames of a certain nominal envelope signal. The circuit may include an envelope detector and a symbol timing estimator. The envelope detector may be configured to produce an envelope detection output of a received data frame, the envelope detection output having an amplitude ripple related to the symbol timings in the received data frame. The symbol timing estimator may be configured to receive the envelope detection output and produce a symbol timing estimate output based on the amplitude ripple.

[0007]

[0007] In some embodiments, the circuit may be included in a backscatter tag configured to generate a clock signal based on the symbol timing estimation output and to use the clock signal during backscattering of the received data frame.

[0008]

[0008] In some embodiments, the backscatter tag may be configured to initiate backscattering at the K-th symbol of at least one received data frame. The backscatter tag may include a symbol count block configured to count the occurrences of symbols 1 to K-1 in at least one received data frame and to generate a symbol count block output to indicate the start of the K-th symbol in at least one received data frame.

[0009]

[0009] In some embodiments, the symbol count block may include a selector and a symbol counter. The selector may be configured to generate a selector output for selecting between a local reference clock signal and a restore clock signal based on an input switching control signal. The symbol counter may be configured to receive the selector output and generate a symbol count block output.

[0010]

[0010] In some embodiments, the symbol timing estimator may include a bandpass filter configured to receive the envelope detection output.

[0011]

[0011] In some embodiments, the center frequency of the bandpass filter may be equal to the reference symbol frequency of the received data frame.

[0012]

[0012] In some embodiments, the center frequency of the bandpass filter may be equal to the harmonic of the reference symbol frequency of the received data frame.

[0013]

[0013] In some embodiments, the circuit may further include a frequency downconverter configured to generate a frequency downconverted output of a certain nominal envelope signal and to provide the frequency downconverted output to an envelope detector to generate an envelope detection output.

[0014] In some embodiments, the frequency down-conversion output may include an intermediate frequency signal or a complex baseband I / Q (in-phase / quadrature) signal.

[0015]

[0015] In some embodiments, the symbol timing estimator is a phase-locked loop (PLL) configured to receive an envelope detection output, and the PLL may include a phase detector, a loop filter, and a voltage-controlled oscillator (VCO).

[0016]

[0016] In some embodiments, the symbol timing estimator may further include a band-pass filter configured to receive an envelope detection output, and the PLL may be configured to receive a band-pass filter output from the band-pass filter.

[0017]

[0017] In some embodiments, the VCO control voltage may be determined for the first frame of the received data frame to lock the PLL frequency to the target frequency of the envelope detection output, and the determined VCO control voltage may be applied to the VCO during one or more subsequent frames to keep the PLL frequency locked to the target frequency.

[0018]

[0018] In some embodiments, the PLL may further include a delay circuit configured to provide a plurality of delayed versions of the VCO output.

[0019]

[0019] In some embodiments, the PLL may be further configured to use the phase detector output to select one of the plurality of delayed versions of the VCO output, and the selected version of the VCO output provides the phase alignment closest to the symbol timing.

[0020] In some embodiments, the symbol timing estimator includes a first bandpass filter, a second bandpass filter, a frequency divider, and a phase resolver. The first bandpass filter may be configured to receive an envelope detection output, and the first bandpass filter has a center frequency equal to the reference symbol frequency of the received data frame. The second bandpass filter may be configured to receive an envelope detection output, and the second bandpass filter has a center frequency equal to a higher harmonic of the reference symbol frequency of the received data frame. The frequency divider may be configured to generate a plurality of frequency division outputs based on the output from the second bandpass filter, and each of the plurality of frequency division outputs has the same frequency equal to the symbol frequency detected in the output from the second bandpass filter and a different phase compared to other frequency division outputs. The phase resolver may be configured to generate a symbol timing estimation output by selecting the frequency division output having the highest phase correlation with the output from the first bandpass filter.

[0021]

[0021] In some embodiments, the symbol timing estimator includes a first bandpass filter, a second bandpass filter, a PLL, a frequency divider, and a phase resolver. The first bandpass filter may be configured to receive an envelope detection output, and the first bandpass filter has a center frequency equal to the reference symbol frequency of the received data frame. The second bandpass filter may be configured to receive an envelope detection output, and the second bandpass filter has a center frequency equal to the higher harmonic of the reference symbol frequency of the received data frame. The PLL may be configured to receive the output from the second bandpass filter, and the VCO center frequency of the PLL is equal to the higher harmonic of the reference symbol frequency. The frequency divider may be configured to generate a plurality of frequency division outputs based on the output from the PLL, each of which has the same frequency equal to the symbol frequency detected in the output from the PLL, and a different phase compared to the other frequency division outputs. The phase resolver may be configured to generate a symbol timing estimate output by selecting the frequency division output that has the highest phase correlation with the output from the first bandpass filter.

[0022]

[0022] In some embodiments, the symbol timing estimator may include a Fast Fourier Transform (FFT) block or a Discrete Fourier Transform (DFT) block configured to receive an envelope detection output and generate a complex frequency domain output to extract the amplitude, frequency, and phase of one or more frequency components having the maximum amplitude.

[0023]

[0023] In some embodiments, the symbol timing estimator may further include an additional processing block configured to receive a complex frequency domain output and extract timing information from the amplitude, frequency, and / or phase of one or more frequency components having the maximum amplitude.

[0024]

[0024] In some embodiments, the additional processing block is an interpolation block configured to identify the maximum peak amplitude among one or more frequency components having the maximum amplitude.

[0025]

[0025] In some embodiments, a certain nominal envelope signal is a filtered phase-modulated signal.

[0026]

[0026] In some embodiments, the backscatter tag is further configured to identify the start of a received data frame in response to the envelope detection output satisfying a threshold condition.

[0027]

[0027] In another broader embodiment, a method is provided for estimating symbol timings in one or more received data frames of a certain nominal envelope signal. The method includes the steps of: generating an envelope detection output of a received data frame, wherein the envelope detection output has amplitude ripples related to symbol timings in the received data frame; and generating a symbol timing estimation output based on the amplitude ripples in the envelope detection output.

[0028]

[0028] In some embodiments, the method may further include the steps of generating a clock signal based on the symbol timing estimation output by the backscatter tag, and encoding the backscatter tag data using the clock signal during backscattering of the received data frame.

[0029]

[0029] In some embodiments, the step of generating a symbol timing estimate output may include filtering the envelope detection output using a bandpass filter, wherein the center frequency of the bandpass filter is equal to i) the reference symbol frequency of the received data frame, or ii) a harmonic of the reference symbol frequency of the received data frame.

[0030]

[0030] In some embodiments, the method may further include the steps of generating a frequency downconverted output of a certain nominal envelope signal and providing the frequency downconverted output to an envelope detector to generate an envelope detection output.

[0031]

[0031] In some embodiments, the step of generating a symbol timing estimation output may include the step of applying the envelope detection output to a phase-locked loop (PLL).

[0032]

[0032] In some embodiments, the step of generating a symbol timing estimate output may include the steps of determining a voltage-controlled oscillator (VCO) control voltage for the first frame of the received data frame to lock the PLL frequency to a target frequency of the envelope detection output, and keeping the determined VCO control voltage constant for one or more subsequent frames to keep the PLL frequency locked to the target frequency.

[0033]

[0033] Other features and advantages of this application will become apparent from the following detailed description. However, it should be understood that the detailed description and specific examples illustrate embodiments of this application, but are given only as examples, and the claims should not be limited by these embodiments, but rather the broadest interpretation consistent with the description as a whole should be given. [Brief explanation of the drawing]

[0034]

[0034] To better understand the embodiments described herein and to more clearly illustrate how they may be carried out, the accompanying drawings, by their very nature, show at least one exemplary embodiment.

[0035] [Figure 1A]

[0035] Figure 1A shows a sequence of symbols in a data frame received by a backscatter tag in an exemplary backscatter communication system. [Figure 1B]

[0035] Figure 1B shows a sequence of symbols in a data frame received by a backscatter tag in an exemplary backscatter communication system.

[0036] [Figure 2]

[0036] Figure 2 is a block diagram of a circuit for estimating symbol timing in a received signal according to an exemplary embodiment.

[0037] [Figure 3]

[0037] Figure 3 shows a timing diagram relating to an exemplary received data frame and the corresponding envelope detection output generated by the envelope detector of the circuit in Figure 2.

[0038] [Figure 4]

[0038] Figure 4 is a frequency spectrum plot of the envelope detection output in Figure 3.

[0039] [Figure 5]

[0039] Figure 5 is a block diagram of a circuit for estimating symbol timing in a received signal, according to another exemplary embodiment.

[0040] [Figure 6A]

[0040] Figure 6A is a frequency spectrum plot of the absolute value of the envelope of an exemplary input signal to the circuit in Figure 2 (or Figure 5).

[0041] [Figure 6B]

[0041] Figure 6B is a frequency spectrum plot of the squared value of the envelope of the exemplary input signal in Figure 6A.

[0042] [Figure 7]

[0042] Figure 7 is a schematic diagram of a backscatter communication system including a backscatter tag that includes the circuit shown in Figure 2 (or Figure 5).

[0043] [Figure 8]

[0043] Figure 8 is a block diagram of a circuit for estimating symbol timing in a received signal, according to another exemplary embodiment.

[0044] [Figure 9]

[0044] Figure 9 is a block diagram of a circuit for estimating symbol timing in a received signal, according to another exemplary embodiment.

[0045] [Figure 10]

[0045] Figure 10 is a block diagram of the frequency divider and phase resolver of the circuit of Figure 9 according to an exemplary embodiment.

[0046] [Figure 11]

[0046] Figure 11 is a block diagram of the frequency divider and phase resolver correlator of Figure 10 according to an exemplary embodiment.

[0047] [Figure 12]

[0047] Figure 12 is a block diagram of a circuit for estimating symbol timing in a received signal, according to another exemplary embodiment.

[0048] [Figure 13]

[0048] Figure 13 is a block diagram of the phase-locked loop of the circuit in Figure 12 according to an exemplary embodiment.

[0049] [Figure 14]

[0049] Figure 14 is a block diagram of the voltage-controlled oscillator and delay circuit of the phase-locked loop shown in Figure 13, according to an exemplary embodiment.

[0050] [Figure 15]

[0050] Figure 15 is a timing diagram showing an exemplary sequence of frames received by the backscatter tag of the backscatter communication system in Figure 7.

[0051] [Figure 16]

[0051] Figure 16 is a block diagram of a circuit for estimating symbol timing in a received signal, according to another exemplary embodiment.

[0052] [Figure 17]

[0052] Figure 17 is a block diagram of a circuit for estimating symbol timing in a received signal, according to another exemplary embodiment.

[0053] [Figure 18A]

[0053] Figure 18A is a block diagram of a circuit for estimating symbol timing in a received signal, according to another exemplary embodiment.

[0054] [Figure 18B]

[0054] Figure 18B is a block diagram of a circuit for estimating symbol timing in a received signal, according to another exemplary embodiment.

[0055] [Figure 18C]

[0055] Figure 18C is a block diagram of a circuit for estimating symbol timing in a received signal, according to another exemplary embodiment.

[0056] [Figure 19]

[0056] Figure 19 shows a process flow of an exemplary embodiment of a method for estimating symbol timing in a received data frame of a certain nominal envelope signal.

[0057] [Figure 20]

[0057] Figure 20 is a block diagram of the symbol count block of the backscatter tag of Figure 7, according to an exemplary embodiment. [Modes for carrying out the invention]

[0058]

[0058] Further aspects and features of the exemplary embodiments described herein will become apparent from the following description in conjunction with the accompanying drawings.

[0059]

[0059] For the sake of simplicity and clarity of the examples, it will be understood that, where appropriate, reference numerals may be repeated between drawings to indicate corresponding or similar elements or steps. In addition, numerous specific details are provided to give a complete understanding of the exemplary embodiments described herein. However, it will be understood by those skilled in the art that the embodiments described herein can be carried out without these specific details. In other examples, well-known methods, procedures, and components are not described in detail so as not to obscure the embodiments described herein. Furthermore, this description should not be considered to limit the scope of the embodiments described herein in any way, but rather to simply describe embodiments of the various embodiments described herein.

[0060]

[0060] Unless otherwise specified, the terms “an embodiment,” “embodiment,” “embodiments,” “the embodiment,” “the embodiments,” “one or more embodiments,” “some embodiments,” and “one embodiment” mean “one or more (but not all) embodiments of the present invention.”

[0061]

[0061] The terms “including,” “comprising,” and their variations mean “including, but not limited to,” unless otherwise specified. The list of items does not imply that any or all of the items are mutually exclusive unless otherwise specified. The terms “a,” “an,” and “the” mean “one or more,” unless otherwise specified.

[0062]

[0062] As used herein and in the claims, two or more parts are said to be “joined,” “connected,” “attached,” or “fixed,” insofar as the connection is made, if the parts are joined directly or indirectly (i.e., through one or more intermediate parts) or work together. As used herein and in the claims, two or more parts are said to be “directly joined,” “directly connected,” “directly attached,” or “directly fixed,” if the parts are joined in physical contact with each other. As used herein, two or more parts are said to be “firmly joined,” “firmly connected,” “firmly attached,” or “firmly fixed,” if the parts are joined so that they move as one while maintaining a certain orientation relative to each other. None of the terms “joined,” “connected,” “attached,” and “fixed” distinguish how two or more parts are joined to each other.

[0063]

[0063] When used herein, terms of degree such as “substantially,” “about,” and “approximately” should be noted to mean a reasonable degree of deviation from the modified term so as not to significantly alter the final result. These terms of degree should be interpreted as including a deviation from the modified term, unless the deviation negates the meaning of the term that the degree term modifies.

[0064]

[0064] In addition, as used herein, the term “and / or” is intended to be comprehensive or inclusive. That is, “X and / or Y” is intended to mean, for example, X or Y or both of them. As a further example, “X, Y, and / or Z” is intended to mean X or Y or Z or any combination thereof.

[0065]

[0065] The receiver may use an envelope detector to estimate the symbol timing in the received data frame. The envelope detector can enable lower power receiver operation compared to other designs. However, the envelope detector cannot accurately estimate the symbol timing of a constant envelope signal (e.g., a phase-modulated signal or a frequency-modulated signal). For example, the envelope detector may attempt to estimate the symbol timing using the rising edge at the beginning of the received data frame. This generally requires high bandwidth and high accuracy (and correspondingly high power consumption) and cannot provide accurate symbol timing estimation for low received signal levels. Furthermore, the symbol timing can only be estimated at the beginning of the received data frame (rising edge), and estimation errors can accumulate across multiple symbols in the received data frame.

[0066]

[0066] On the other hand, in many applications, communication signals are filtered at the transmitter and / or receiver. The filtering process can generate amplitude ripple related to symbol timing (in other respects within a constant envelope signal). Such filtered signals are referred to herein as “constant nominal envelope” signals. Amplitude ripple introduced during the filtering process can increase the peak-to-average power ratio (PAPR) of the filtered signal. In some examples, the PAPR ratio of a constant nominal envelope signal may be in the range of 0 to 6 dB. For example, an unfiltered constant envelope signal (e.g., an unfiltered binary phase shift keying (BPSK) signal or an unfiltered quadrature phase shift keying (QPSK) signal) may have a PAPR of 0 dB. Non-constant amplitude resulting from a filtering process (e.g., using a root-raised-cosine (RRC) filter) can increase the PAPR by approximately 0.5–3 dB (based on the filter characteristics and RRC roll-off coefficient). As another example, an unfiltered higher-order modulated signal (e.g., 16-QAM) may have a higher PAPR than an unfiltered signal, while a filtered constant nominal envelope signal may have a PAPR of approximately 4–6 dB. In other examples, a constant nominal envelope signal may have different PAPRs based on, for example, the PAPR of the unfiltered signal and coefficients including a particular embodiment of the filtering process (e.g., the roll-off coefficient of a raised-cosine filter).

[0067]

[0067] Filters may be placed in the transmitter and / or receiver. In some embodiments, the transmitter may filter the modulated signal before transmission (for example, to meet frequency spectrum regulatory requirements). Filters may be used to control the spectral mask of the radiation, including bandpass filters for reducing harmonics and other spurious in-band and out-of-band transmissions. In some applications, the transmitter filters may include one or more of surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, LC filters, and ceramic filters. In some applications, the transmitter may perform digital filtering to achieve a sharp transition bandwidth. Digital filtering may be further combined with RC filters to remove harmonics associated with the conversion between digital and analog signals. In other applications, the transmitter filters may include any other suitable filters. In some embodiments, the transmitter antenna and / or receiver antenna may include filters that result in a constant nominal envelope signal with amplitude ripple. In some embodiments, the receiver may include band-limiting and channel-limiting filters that result in a constant nominal envelope signal with amplitude ripple. In some embodiments, filters may be specifically added to generate amplitude ripple that can be used for symbol timing estimation using the disclosed systems and methods.

[0068]

[0068] For simplicity and ease of explanation, this specification describes many exemplary embodiments with reference to digital phase-modulated signals such as 1 Mb / s Direct-Sequence Spread Spectrum (DSSS) of Differential Binary Phase Shift Keying (DBPSK) 802.11. However, the embodiments disclosed are not limited to such signals and can be implemented for any suitable constant nominal envelope signal.

[0069]

[0069] The disclosed system and method use an envelope detector to detect amplitude ripple in a received data frame of a constant nominal envelope signal. The detected amplitude ripple can indicate symbol timing in the received data frame. The ability to use an envelope detector for symbol timing estimation enables the disclosed system and method to provide low-power or ultra-low-power operation.

[0070]

[0070] Furthermore, the amplitude ripple detected is not limited to the beginning of the received data frame (which would cause accuracy and power issues associated with rising edge detection as described above in this specification). Instead, amplitude ripple detection can be performed over the duration of the received data frame (for example, each phase transition of a phase-shifted modulation (PSK) signal may be associated with a dip in the amplitude waveform). This allows for symbol timing estimation at multiple points in time within the received data frame and avoids the error accumulation problems associated with relying entirely on rising edge detection at the beginning of the received data frame (as described above in this specification).

[0071]

[0071] By using an envelope detector capable of detecting amplitude ripple occurring over the duration of a received data frame, the disclosed system and method can enable low-power operation while providing high-precision symbol timing estimation. The disclosed system and method can enable ultra-low-power wireless operation, for example, in ambient-powered IoT device applications.

[0072]

[0072] The disclosed systems and methods can enable improvements in the operational efficiency of backscatter communication systems. Backscatter communication has attracted interest in applications such as embedded sensors, wearables, and smart home sensing due to its ability to provide low-power connectivity to these sensors. Such applications have strict power constraints. Embedded sensors, for example, must last for several years, and more traditional smart home monitoring applications can benefit from sensors and actuators that can last for several years. The disclosed systems and methods can enable backscatter communication systems to meet connectivity requirements while consuming low power, such as by collecting energy or being powered by a battery that can last for several years.

[0073]

[0073] The backscatter tags in a backscatter communication system may apply different methods to manipulate the transmission signal (to encode the backscatter tag data) and to generate the backscatter signal. Backscatter communication systems and methods may include, for example, the systems and methods described in U.S. Patent No. 10,338,205 by Zhang et al., filed on 14 August 2017 and issued on 2 July 2019; U.S. Patent No. 11,483,836 by Zhang et al., filed on 25 April 2019 and issued on 25 October 2022; and U.S. Patent Application Publication No. 2023 / 0244883 by Nielsen et al., filed on 27 January 2023, all of which are incorporated herein by reference in their entirety.

[0074]

[0074] Next, refer to Figures 1A and 1B. Figures 1A and 1B show a sequence of symbols 18 in a data frame received by a backscatter tag in a backscatter communication system. The sequence of symbols includes symbols 24a and 24b used to encode the backscatter tag data during backscattering, and symbols 28a-28c (for example, symbols 28a-28c may include transmit unit data) that are intended to remain unchanged during backscattering.

[0075]

[0075] In the example shown in Figure 1A, the symbol timing estimation in the backscatter tag is sufficiently accurate. The backscatter tag modifies only symbols 24a and 24b to encode the backscatter tag data, leaving symbols 28a to 28c unchanged.

[0076]

[0076] In the example shown in Figure 1B, the symbol timing estimation in the backscatter tag is not sufficiently accurate. The backscatter tag modifies symbols 28b, 24a, and 24b to encode the backscatter tag data. As a result of the inaccurate symbol timing estimation, the backscatter tag modifies symbol 28a, which was intended not to be modified during backscattering. This can lead to errors when decoding the backscatter tag data and / or loss of unintentionally modified transmit unit data.

[0077]

[0077] To compensate for inaccurate symbol timing estimation, many backscatter communication systems assign multiple consecutive symbols (e.g., 2 to 4 consecutive symbols) of the received data frame to encode a single symbol of backscatter tag data. This can reduce errors when decoding backscatter tag data and reduce unintended loss of transmit unit data. However, this technique reduces the operational efficiency of the backscatter communication system because it requires the use of multiple symbols of the received data frame to encode each symbol of the backscatter tag data.

[0078]

[0078] The disclosed systems and methods can enable accurate symbol timing estimation such that only a single symbol of the transmitted data frame is required to encode one symbol of the backscattered tag data. This can reduce the errors and unintended loss of transmitted unit data associated with decoding the backscattered tag data as described above, while also enabling high operational efficiency of the backscattered communication system.

[0079]

[0079] Furthermore, preserving the frame check sequence of received data frames during backscatter communication may require that only a single symbol of the transmitted data frame be used to encode one symbol of the backscatter tag data. By providing accurate symbol timing estimation, the disclosed systems and methods can enable the use of only a single symbol of the transmitted data frame to encode one symbol of the backscatter tag data, thereby enabling the preservation of the frame check sequence during backscatter communication. Systems and methods for preserving the frame check sequence during backscatter communication may include, for example, the systems and methods described in U.S. Patent No. 11,962,412 by Kezys et al., filed on 18 December 2023 and issued on 16 April 2024, which is incorporated herein by reference in its entirety.

[0080]

[0080] Next, refer to Figure 2, a block diagram of circuit 200a for estimating symbol timing in the received signal. In the illustrated exemplary embodiment, circuit 200a includes an envelope detector 204 and a symbol timing estimator 208.

[0081]

[0081] The received signal may be any constant nominal envelope signal, for example, a filtered phase-modulated signal. The received signal may include a plurality of data frames 20, and the circuit 200a can estimate the symbol timing within the received data frames 20.

[0082]

[0082] The envelope detector 204 may have any suitable design for generating an envelope detection output 212 of the received data frame 20. As described above herein, a constant nominal envelope signal may include amplitude ripples indicating symbol timing in the received data frame 20. The envelope detection output 212 generated by the envelope detector 204 may include corresponding amplitude changes related to symbol timing in the received data frame 20.

[0083]

[0083] Next, we refer to Figure 3, which shows the timing diagrams 304-316 related to the exemplary received data frame and the corresponding envelope detection output generated by the envelope detector.

[0084]

[0084] Timing diagram 304 shows the bit phase transitions of the two-phase shift modulation (BPSK) waveform associated with the transmitted data. The BPSK waveform shows the bit duration 320(T) for each data bit being transmitted. b ) may have.

[0085]

[0085] Timing diagram 308 shows the phase transitions of an exemplary spreading code "1011000" for generating a spread spectral modulation signal. Each chip of the spreading code has a chip duration of 324(T c ) may have. In the illustrated example, spread spectral modulation utilizes 7 chips per bit. In other examples, any other suitable number of chips per bit may be used.

[0086]

[0086] Timing diagram 312 shows the phase transitions of the spread spectrum modulated signal generated based on the BPSK waveform and the "1011000" spread code. The generated spread spectrum modulated signal may be filtered and transmitted by the transmitting unit. The filtering operation may introduce amplitude ripple into the envelope of the transmitted spread spectrum modulated signal. Each dip in the amplitude waveform may correspond to a phase transition of the spread spectrum modulated signal.

[0087]

[0087] The transmitted signal may be received by an envelope detector (e.g., envelope detector 204 shown in Figure 2). Timing Figure 316 shows an exemplary envelope detection output generated by the envelope detector. The envelope detection output may include amplitude ripple. The amplitude ripple waveform may include a number of amplitude dips 328a to 328d related to the phase transition of the spread spectrally modulated signal. As seen in Figure 3, there may be a delay between the occurrence of the modulation phase bit transition (timing Figure 312) and the corresponding amplitude dips (timing Figure 316) due to the group delay response of the filter used to filter the spread spectrally modulated signal. In some applications, an offset value may be used in combination with estimated symbol timing, which includes adjustment for the delay.

[0088]

[0088] Next, refer to Figure 4, which shows the frequency spectrum plot 404 of the envelope detection output. The frequency spectrum plot 404 shows the bit frequency f b (1 / T b ), f b The higher harmonics and the chip frequency f c (1 / T c This shows multiple spectral peaks 408a to 408g corresponding to ). The noise floor may be due to the random nature of the transmitted data. As will be described in more detail herein, the symbol timing estimator 208 (shown in Figure 2) can be used to isolate and extract any suitable spectral peak signal. For example, the symbol timing estimator is 3 / T b The system may include a filter that can be used to separate and extract signals associated with the spectral peak 408c of a frequency.

[0089]

[0089] In some embodiments, the symbol timing estimation circuit may include a frequency downconverter. Next, refer to Figure 5, a block diagram of circuit 200b for estimating symbol timing in a received signal. The received signal may be any constant nominal envelope signal and may include a plurality of data frames 20. Circuit 200b can generate a symbol timing estimation output 216 indicating the symbol timing in the received data frames 20.

[0090]

[0090] In the illustrated exemplary embodiment, the circuit 200b includes a frequency downconverter 504, an envelope detector 204, and a symbol timing estimator 208. The frequency downconverter 504 generates a frequency downconverted output 508 of the received signal and can provide the frequency downconverted output 508 to the envelope detector 204.

[0091]

[0091] The frequency downconverter 504 may be configured to perform any appropriate frequency downconversion. For example, the frequency downconverter 504 may downconvert the received RF signal to an intermediate frequency (IF) signal or a baseband frequency signal. Frequency downconversion may allow for improved filtering of adjacent channel noise. The frequency downconverter 504 can provide the envelope detector 204 with a frequency downconverted and optionally filtered output 508. The envelope detector 204 can generate an envelope detection output 212 which includes amplitude ripple indicating symbol timing in the received data frame 20, as described above herein.

[0092]

[0092] The envelope detector 204 (shown in Figures 2 and 5) may use any suitable technique to generate the envelope detection output 212. For example, the envelope detection output may be based on the absolute or squared value of the input signal envelope. The input signal may be, for example, an RF signal (in the circuit 200a shown in Figure 2) or a down-converted signal (in the circuit 200b shown in Figure 5).

[0093]

[0093] Next, refer to Figures 6A and 6B. Figure 6A is an absolute value frequency spectrum plot 604 of an exemplary input signal envelope having a bit frequency (fb) of 1 MHz. Figure 6B is a square value frequency spectrum plot 612 of an exemplary input signal envelope. Both frequency spectrum plots 604 and 612 show multiple spectral peaks 608 at harmonic frequencies of 1 MHz bit frequency (fb) (for clarity in Figures 6A and 6B, not all observed peaks are numbered). A symbol timing estimator may be used to isolate and extract the signal associated with any suitable spectral peak 608 and estimate the symbol timing.

[0094]

[0094] Referring back to Figure 5, in some embodiments, circuit 200b may perform complex downconversion, and the envelope detection output may be generated using the sum of the squares of the common-mode (I) and quadrature (Q) values.

[0095]

[0095] In some embodiments, the envelope detector 204 may use logarithms to generate the envelope detection output. Using logarithms to generate the envelope detection output may allow for compression of the dynamic range of the signal. For example, the envelope detection output may be generated using the logarithm of the absolute value of the envelope, the logarithm of the squared value of the envelope, or the logarithm of the sum of the squares of the I and Q values.

[0096]

[0096] Next, referring to both Figures 2 and 5, the symbol timing estimator 208 can be configured to receive an envelope detection output 212 from the envelope detector 204. The symbol timing estimator 208 may have any suitable design for generating a symbol timing estimate output 216 based on the amplitude ripple contained in the envelope detection output 212.

[0097]

[0097] The symbol timing estimation output 216 may include any suitable waveform depending on the intended use of the symbol timing estimation output. For example, the symbol timing estimation output 216 may include a sinusoidal signal. In some embodiments, the sinusoidal signal may be thresholded (e.g., using a data slicer) to generate a square wave that can be used as a clock signal.

[0098]

[0098] Next, refer to Figure 7, which is a schematic diagram of a backscatter communication system 704 including a transmitting unit 708, a receiving unit 712, and a backscatter tag 716. The transmitting unit 708 may be configured to transmit a signal including one or more transmit data frames 720. The transmit signal may be an IEEE 802.11 compliant WLAN signal, and the transmit data frame 720 may be an IEEE 802.11 compliant WLAN data frame. The receiving unit 712 may be any suitable device configured to receive a transmit signal.

[0099]

[0099] The backscatter tag 716 may be any suitable device that operates to intercept the transmitted data frame 720. In particular, the backscatter tag 716 may be configured to manipulate the intercepted frame to encode backscatter tag data. The backscatter tag 716 may backscatter the transmitted signal to form a backscatter signal that includes one or more backscatter data frames 724. The backscatter data frames 724 may include backscatter tag data. The backscatter tag 716 may be configured such that the backscatter signal is an 802.11b compliant Wi-Fi signal and the backscatter data frames 724 are 802.11b compliant Wi-Fi data frames.

[0100]

[0100] In the illustrated embodiment, the backscatter tag 716 includes a circuit 200 (e.g., circuit 200a (shown in Figure 2) or circuit 200b (shown in Figure 5)) for estimating the symbol timing in the data frame 720. The backscatter tag 716 may generate a clock signal based on the symbol timing estimation output from the circuit 200. In some embodiments, the symbol timing estimation output from the circuit 200 may be used directly as a clock signal for encoding the backscatter data. In some embodiments, the symbol timing estimation output from the circuit 200 may be processed to satisfy clock signal requirements (e.g., waveform type, waveform amplitude, waveform duty cycle). The backscatter tag 716 can use the generated clock signal to modify the symbols in the data frame 720 (to encode the backscatter tag data) and generate a backscatter data frame 724.

[0101]

[0101] The circuit 200 can enable sufficiently accurate symbol timing estimation so that the backscatter tag 716 can be configured to encode each symbol of the backscatter tag data by changing only a single symbol of the data frame 720. As described above in this specification, this can improve the operational efficiency of the backscatter tag 716 and allow the saving of the frame check sequence to be performed.

[0102]

[0102] Next, refer to FIG. 8, which is a block diagram of a circuit 200c for symbol timing estimation in the received data frame 20. The circuit 200c includes an envelope detector 204 and a symbol timing estimator 208.

[0103]

[0103] In the illustrated exemplary embodiment, the symbol timing estimator 208 includes a bandpass filter 804 configured to receive an envelope detection output 212 from the envelope detector 204. The bandpass filter 804 can separate and extract a signal related to an appropriate spectral peak from the envelope detection output 212 and generate a bandpass filter output. The bandpass filter 804 can select a spectral peak of the envelope detection output 212 corresponding to the center frequency of the bandpass filter 804 and attenuate other spectral peaks. In some embodiments, the circuit 200c may directly provide the bandpass filter output from the bandpass filter 804 as a symbol timing estimation output 216. In other embodiments, the circuit 200c may further process the bandpass filter output (e.g., using a PLL to improve the signal-to-noise ratio, as described below in this specification) to generate the symbol timing estimation output 216.

[0104]

(0104)

[0105]

[0105] In some embodiments, the center frequency of the bandpass filter 804 may be equal to a higher harmonic of the reference symbol frequency. Based on the signal characteristics of the received data frame, a particular higher harmonic spectral peak in the envelope detection output may have a better signal-to-noise ratio compared to other spectral peaks (including the fundamental spectral peak). The center frequency of the bandpass filter 804 may be configured to select a higher harmonic spectral peak that has a better signal-to-noise ratio. For example, the bandpass filter 804 may have a center frequency equal to three times the reference bit frequency in order to select the spectral peak 408c shown in frequency spectrum plot 404 of Figure 4 (and attenuate other spectral peaks, including the spectral peak 408a).

[0106]

[0106] The bandpass filter 804 detects higher harmonic spectral peaks (e.g., 3 / T). s In an exemplary embodiment configured to select the symbol frequency (1 / T), the frequency of the bandpass filter output signal is the symbol frequency (1 / T). s The frequency division may be divided to produce a symbol timing estimate output having a frequency equal to (1 / T). However, frequency division can introduce phase ambiguity into the frequency-divided output. For example, the bandpass filter 804 may be configured to select the Mth harmonic spectral peak, and the frequency divider may be used to divide the frequency of the bandpass filter output signal by M. The frequency divider can produce M outputs, each output having a symbol frequency (1 / T). s It has a frequency equal to ) and an associated phase ambiguity of 360 / M degrees. In some embodiments, a phase resolver may be used to resolve the phase ambiguity associated with frequency division.

[0107]

[0107] Next, we refer to Figure 9, which is a block diagram of circuit 200d for symbol timing estimation in the received data frame 20. Circuit 200d includes an envelope detector 204 and a symbol timing estimator 208. In the illustrated exemplary embodiment, the symbol timing estimator 208 includes a first bandpass filter 804a, a second bandpass filter 804b, a frequency divider and a phase resolver 904.

[0108]

[0108] The first bandpass filter 804a may be configured to receive the envelope detection output 212 (from the envelope detector 204) and generate the first bandpass filter output 908. The first bandpass filter 804a uses a reference symbol frequency f s (1 / T s It may have a center frequency equal to ). The first bandpass filter 804a can separate and extract the signal (from the envelope detection output 212) associated with the spectral peak corresponding to the symbol frequency.

[0109]

[0109] The second bandpass filter 804b may be configured to receive the envelope detection output 212 (from the envelope detector 204) and generate the second bandpass filter output 912. The second bandpass filter 804b uses a reference symbol frequency f s (1 / T s The second bandpass filter 804b may have a center frequency equal to the higher harmonic of the symbol frequency (e.g., 2f). s 3F s , 4f s Signals (from the envelope detection output 212) associated with spectral peaks corresponding to (etc.) can be separated and extracted. Higher harmonics may be selected, for example, to extract spectral peak signals with a higher signal-to-noise ratio.

[0110]

[0110] The frequency divider and phase resolver 904 may be configured to receive the first bandpass filter output 908 and the second bandpass filter output 912. The frequency divider and phase resolver 904 may have any suitable design to divide the frequency of the second bandpass filter output 912 (corresponding to the higher harmonics of the symbol frequency) into the fundamental frequency of the symbol frequency and to eliminate the phase ambiguity associated with frequency division.

[0111]

[0111] Next, refer to Figure 10, a block diagram of an exemplary embodiment of a frequency divider and phase resolver 904 which may be used in combination with a second bandpass filter having a center frequency equal to the M harmonic of the reference symbol frequency. In the illustrated exemplary embodiment, M=3, but the design of the frequency divider and phase resolver 904 can be modified to implement other values ​​of M.

[0112]

[0112] The frequency divider and phase resolver 904 may include an M-division counter 1004, a correlator 1008, a selector 1012, and a multiplexer 1016. Optionally, the frequency divider and phase resolver 904 may include slicers 1020a and 1020b. The slicer 1020 may operate to convert the sinusoidal signals of the first bandpass filter output 908 and the second bandpass filter output 912 into digital signals (e.g., binary 0 / 1 signals) suitable for processing by the other components of the frequency divider and phase resolver 904.

[0113]

[0113] Any suitable design may be used to implement the M-split counter 1004. In some embodiments, the M-split counter 1004 may include a Johnson counter. The M-split counter 1004 may be configured to receive a second bandpass filter output 912 (related to the M-harmonic spectral peak of the envelope detection output) and generate M frequency-split outputs having different phases. In the illustrated example, the M-split counter 1004 generates three frequency-split outputs 1024a, 1024b, and 1024c, each frequency-split output 1024 having the same frequency equal to the symbol frequency extracted in the second bandpass filter output 912. Each frequency-split output 1024 may include a phase ambiguity of 360 / M degrees (120 degrees in the illustrated example).

[0114]

[0114] The frequency divider and phase resolver 904 can resolve the phase ambiguity by inputting the first bandpass filter output 908 and each frequency division output 1024 (three frequency division outputs 1024a to 1024c in the illustrated example) into the correlator 1008. The correlator 1008 can have any suitable design to generate M outputs 1028 (three outputs 1028a to 1028c in the illustrated example) that show the phase correlation between the first bandpass filter output 908 and each frequency division output 1024. For example, correlator output 1028a can show the phase correlation between the first bandpass filter output 908 and the frequency division output 1024a.

[0115]

[0115] Next, refer to Figure 11, a block diagram of an exemplary embodiment of the correlator 1008 implemented for M=3. In other embodiments, the design of the correlator 1008 may be modified for other values ​​of M. In the illustrated exemplary embodiment, the correlator 1008 can exhibit a phase correlation between a first bandpass filter output 908 (corresponding to the fundamental symbol frequency) and three frequency division outputs 1024a to 1024c (each having the same fundamental symbol frequency but different phases).

[0116]

[0116] The correlator 1008 may include M multipliers 1104 (three multipliers 1104a to 1104c in the illustrated example) and M integrators and dumps 1108 (three integrators and dumps 1108a to 1108c in the illustrated example). As shown in Figure 11, each multiplier 1104 may multiply the frequency division output 1024 by the first bandpass filter output 908 (for example, multiplier 1104b may multiply the frequency division output 1024b by the first bandpass filter output 908). The output of each multiplier 1104 may be applied to the corresponding integrator and dump 1108, which is dumped for each period of the fundamental symbol frequency. In the illustrated example, the outputs of multipliers 1104a to 1104c are applied to integrators and dumps 1108a to 1108c, respectively. The frequency-divided output 1024 that has the highest phase correlation with the first bandpass filter output 908 can yield the highest output 1028 value from the corresponding integration and dump 1108. For example, the output 1028c from integration and dump 1108c may have the highest value indicating that the frequency-divided output 1024c has the highest phase correlation with the first bandpass filter output 908.

[0117]

[0117] Referring back to Figure 10, the selector 1012 may have any suitable design for selecting the correlator output 1028 that exhibits the highest phase correlation. The output 1032 from the selector 1012 may indicate which of the frequency division outputs 1024 has the highest phase correlation with the first bandpass filter output 908. For example, output 1028c may have a higher value compared to outputs 1028a and 1028b. The selector 1012 may select output 1028c as indicating that the frequency division output 1024c is closest to the first bandpass filter output 908 in terms of phase. The selector 1012 may provide the selector output 1032 to the multiplexer 1016 to select the corresponding frequency division output 1024c that is closest in phase to the first bandpass filter output 908, for the purpose of enabling the elimination of phase ambiguity.

[0118]

[0118] Circuit 200d (Figure 9) may directly provide the output from the multiplexer 1016 as the symbol timing estimate output 216. Optionally, circuit 200d may further process the output from the multiplexer 1016 to generate the symbol timing estimate output 216 (for example, to improve the signal-to-noise ratio).

[0119]

[0119] Next, refer to Figure 12, which is a block diagram of circuit 200e for symbol timing estimation in the received data frame 20. Circuit 200e includes an envelope detector 204 and a symbol timing estimator 208.

[0120]

[0120] In the illustrated exemplary embodiment, the symbol timing estimator 208 includes a phase-locked loop (PLL) 1204 configured to receive an envelope detection output 212 from an envelope detector 204. The PLL 1204 may include a phase detector (PD) 1208, a loop filter 1212, and a voltage-controlled oscillator (VCO) 1216. The PLL 1204 can function as a narrowband filter that isolates and extracts appropriate spectral peak signals from the envelope detection output 212 to generate a PLL output. The PLL 1204 may be configured to lock to any appropriate spectral peak of the envelope detection output 212 (e.g., related to the fundamental or higher harmonics of the symbol frequency). The circuit 200e may directly provide the PLL output from the PLL 1204 as a symbol timing estimator output 216. Optionally, the circuit 200e may further process the PLL output to generate the symbol timing estimator output 216.

[0121]

[0121] Next, we refer to Figure 13, a block diagram of an exemplary embodiment of the PLL 1204. In the illustrated exemplary embodiment, the PLL 1204 includes a PD 1208, a loop filter 1212, and a VCO and delay circuit 1304.

[0122]

[0122] The PD1208 can generate a phase detector output 1320 that is proportional to the phase difference between the PLL reference input (e.g., envelope detection output 212) and the VCO and delay circuit output 1328. Any suitable design may be used to implement the PD1208. In some embodiments, the PD1208 may include a digital phase frequency detector. In other embodiments, a different design (e.g., a mixer / multiplier) may be used.

[0123]

[0123] The loop filter 1212 may be configured to receive the phase detector output 1320 and generate a filtered signal 1324. The filtered signal 1324 may be used to apply the VCO control voltage to the VCO. Optionally, the PLL 1204 may include a reference suppression low-pass filter (LPF) 1308. The reference suppression LPF 1308 may further filter the signal 1324 before it is used to apply the VCO control voltage.

[0124]

[0124] The VCO and delay circuit 1304 may include any suitable voltage-controlled oscillator (e.g., a sinusoidal VCO). The VCO may be designed to have a center frequency corresponding to the target frequency of the spectral peak included in the envelope detection output 212. For example, the center frequency of the VCO may be equal to the fundamental or higher harmonic of the reference symbol frequency. In embodiments including a VCO having a center frequency equal to the higher harmonic of the reference symbol frequency, a frequency divider and a phase resolver may be used as described above herein with reference to Figures 9 to 11. The PLL 1204 can operate to determine a VCO control voltage that matches / locks the frequency of the VCO to the frequency of the PLL reference signal (corresponding to the spectral peak target frequency).

[0125]

[0125] In some embodiments, the loop filter 1212 may be implemented as a selectable bandwidth loop filter. Reducing the bandwidth can improve the signal-to-noise performance of the PLL 1204, but increases the amount of time required for the PLL 1204 to achieve frequency lock / matching. A bandwidth gear shift mechanism may be used to dynamically and continuously reduce the bandwidth of the PLL from an initial higher bandwidth value (allowing faster initial frequency lock) to a reduced bandwidth value (allowing higher signal-to-noise performance).

[0126]

[0126] PLL 1204 may first perform frequency acquisition to lock the frequency of the VCO to the frequency of the PLL reference signal. Then, PLL 1204 may perform phase acquisition to match the phase of the frequency-locked VCO and delay circuit output 1328 to the phase of the PLL reference signal. Next, refer to Figure 14, a block diagram of an exemplary embodiment of the VCO and delay circuit 1304. In the illustrated exemplary embodiment, the VCO and delay circuit 1304 includes a VCO 1404, a delay circuit 1408, a sample / hold (S / H) block 1412, a switch 1416, and a quantizer 1420.

[0127]

[0127] The VCO 1404 may include any suitable voltage-controlled oscillator as described above in this specification with reference to Figure 13. The delay circuit 1408 provides n delayed versions of the VCO output 1436 and may have any suitable design to allow selection of any one of the n delayed versions. For example, the delay circuit 1408 may include n-tap delay lines, each tap corresponding to a delay of (1 / n*period of the VCO output 1436). Any suitable value for n may be used. In some embodiments, the delay circuit 1408 may include 50-tap delay lines. In some embodiments, the delay circuit 1408 may include more than 50 taps. A larger number of delay versions "n" allows for higher granularity of phase matching. In some embodiments, the delay circuit 1408 may include fewer than 50 taps. A smaller number of delay versions "n" can reduce circuit cost / complexity. Any suitable design may be used to implement the switch 1416. For example, switch 1416 may include a single-pole single-throw (SPST) switch.

[0128]

[0128] The control input 1424 can control the frequency and phase acquisition operation of the PLL 1204. For example, during the initial frequency acquisition operation of the PLL 1204, the delay circuit may be set to any appropriate delay value (e.g., an intermediate delay value). Furthermore, the control input 1424 can control the sample / hold (S / H) block 1412 so that the filtered signal 1324 from the loop filter can apply the VCO control voltage 1428 to the VCO 1404. The VCO control voltage 1428 is determined during the initial frequency acquisition to match the frequency of the VCO output 1436 to the frequency of the PLL reference signal (corresponding to the spectral peak target frequency).

[0129]

[0129] After frequency acquisition is complete, the control input 1424 may control the sample / hold (S / H) block 1412 to hold the VCO control voltage 1428 at the determined control voltage value (maintain frequency lock) while phase acquisition is being performed. The control input 1424 may control the switch 1416 to apply the phase detector output 1320 to the quantizer 1420. The phase detector output 1320 can indicate the phase difference between the frequency-locked VCO output and the PLL reference signal. The quantizer 1420 may be configured to use the phase difference value to select the corresponding delayed version of the VCO output that is closest to matching the phase of the PLL reference signal.

[0130]

[0130] In some examples, the time required to acquire the frequency and phase can be shorter than the duration of the data frame, with the desired accuracy. In such examples, the PLL1204 can perform frequency and phase acquisition for each received data frame. In other examples, the total time required to acquire the frequency and phase can be longer than the duration of the data frame, with the desired accuracy. For example, a narrower bandwidth of the loop filter can enable higher accuracy frequency acquisition, but requires a longer duration to achieve frequency lock / matching. In such examples, frequency acquisition may be performed on the first data frame, and phase acquisition of the frequency-locked output may be performed on subsequent data frames.

[0131]

[0131] Next, refer to Figures 7 and 15. Figure 15 is a timing diagram showing an exemplary sequence of frames 1504 and 1508 received by the backscatter tag 716. The transmitting unit 708 may transmit frames 1504 and 1508 ad hoc using carrier sense multiple access (CSMA) without centralized control, i.e., the interframe space (IFS) length 1512 can be random. Thus, the symbol frequencies may be equal in frames 1504 and 1508, but the symbol phase of frame 1508 may not have a predetermined / known relationship with respect to the symbol phase of frame 1504.

[0132]

[0132] The circuit 200 can enable the backscatter tag 716 to perform symbol frequency acquisition during frame 1504 (for example, using the PLL 1204 shown in Figures 12 and 13). Since the symbol frequency has already been acquired, the circuit 200 may then perform only phase acquisition for frame 1508. For example, the VCO control voltage of the PLL 1204 may be determined during frame 1504 to lock the frequency, and the VCO control voltage may be kept constant for the duration of the IFS length 1512 and frame 1508.

[0133]

[0133] In some embodiments, the backscatter tag 716 may be configured to encode the backscatter tag data using symbols starting from the K-th symbol in the received data frame. The backscatter tag 716 can count / track the number of symbols in frame 1508 while phase acquisition is being performed. High-precision phase determination may not be required to count the number of symbols, and therefore the backscatter tag 716 may track / count the number of symbols in frame 1508 while phase acquisition is being performed. Phase acquisition may only need to be completed before the start of the K-th symbol (this may be changed as described above herein, and accurate symbol phase determination with respect to this can improve backscatter performance).

[0134]

[0134] With respect to frame 1508, circuit 200 can enable fast phase acquisition to generate a clock signal for encoding backscatter tag data in a timely manner (before the start of the Kth symbol of frame 1508). Circuit 200 can enable fast phase acquisition by i) performing frequency acquisition during frame 1504, and ii) during frame 1508, by directly using the phase detector output (e.g., without passing through a loop filter) to select the closest phase-matched output from multiple delayed versions of the frequency-locked VCO output.

[0135]

[0135] In some embodiments, the symbol timing estimator may include a combination of a bandpass filter and a PLL. For example, the bandpass filter may be used for the initial extraction of a desired spectral peak signal from the envelope detection output. The PLL may be applied to the bandpass filter output to generate the symbol timing estimate output (for example, to further improve the signal-to-noise ratio of the extracted signal).

[0136]

[0136] Next, we refer to Figure 16, a block diagram of circuit 200f for symbol timing estimation in the received data frame 20. Circuit 200f includes an envelope detector 204 and a symbol timing estimator 208. In the illustrated exemplary embodiment, the symbol timing estimator 208 includes a first bandpass filter 804a, a second bandpass filter 804b, a frequency divider and phase resolver 904, and a PLL 1204.

[0137]

[0137] Optionally, circuit 200f includes a frequency downconverter 504. The frequency downconverter 504 can receive a signal including the data frame 20 and generate a frequency downconverted output provided to the envelope detector 204. In some embodiments, the frequency downconverted output from the frequency downconverter 504 may include a real intermediate frequency signal. In some embodiments, the frequency downconverted output from the frequency downconverter 504 may include a complex baseband I / Q (in-phase / quadrature) signal. If circuit 200f does not include the frequency downconverter 504, the received data frame 20 may be input directly to the envelope detector 204.

[0138]

[0138] The first bandpass filter 804a has a reference symbol frequency f s (1 / T s The first bandpass filter 804a may have a center frequency equal to ). The first bandpass filter 804a may be configured to receive the envelope detection output from the envelope detector 204 and extract the spectral peak signal (from the envelope detection output) corresponding to the symbol frequency.

[0139]

[0139] The second bandpass filter 804b has a reference symbol frequency f s (1 / T s The second bandpass filter 804b may have a center frequency equal to the higher harmonics of the symbol frequency. The second bandpass filter 804b may be configured to receive the envelope detection output from the envelope detector 204 and extract the spectral peak signal corresponding to the higher harmonics of the symbol frequency.

[0140]

[0140] The frequency divider and phase resolver 904 may be configured to receive the first bandpass filter output 908 and the second bandpass filter output 912. The frequency divider and phase resolver 904 may be configured to divide the frequency of the second bandpass filter output into fundamentals of the symbol frequency and to resolve the phase ambiguity associated with frequency division (by selecting the frequency division output that has the highest phase correlation with the first bandpass filter output).

[0141]

[0141] The signal-to-noise ratio of the extracted signal may be further improved by applying the outputs of the frequency divider and phase resolver 904 to the PLL 1204. The VCO center frequency of the PLL 1204 may be equal to the fundamental frequency of the reference symbol frequency. The PLL 1204 may be configured to perform frequency and phase acquisition and generate a symbol timing estimation output 216, as described above in this specification.

[0142]

[0142] Optionally, circuit 200f may include slicer 1312 for thresholding the PLL output to generate a square wave that can be used as a clock signal. If circuit 200f does not include slicer 1312, the PLL output may be provided directly to an external circuit.

[0143]

[0143] Next, refer to Figure 17, a block diagram of the circuit 200g for symbol timing estimation in the received data frame 20. The circuit 200g includes an envelope detector 204 and a symbol timing estimator 208. In the illustrated exemplary embodiment, the symbol timing estimator 208 includes a first bandpass filter 804a, a second bandpass filter 804b, a PLL 1204, and a frequency divider and phase resolver 904.

[0144]

[0144] Optionally, circuit 200g includes a frequency downconverter 504. The frequency downconverter 504 can receive a signal including a data frame 20 and generate a frequency downconverted output that is provided to the envelope detector 204. If circuit 200g does not include the frequency downconverter 504, the received data frame 20 may be input directly to the envelope detector 204.

[0145]

[0145] The first bandpass filter 804a has a reference symbol frequency f s (1 / T s The first bandpass filter 804a may have a center frequency equal to ). The first bandpass filter 804a may be configured to receive the envelope detection output from the envelope detector 204 and to extract a spectral peak signal corresponding to the symbol frequency from the envelope detection output.

[0146]

[0146] The second bandpass filter 804b has a reference symbol frequency f s (1 / T s The second bandpass filter 804b may have a center frequency equal to the higher harmonics of the symbol frequency. The second bandpass filter 804b may be configured to receive the envelope detection output from the envelope detector 204 and extract the spectral peak signal corresponding to the higher harmonics of the symbol frequency.

[0147]

[0147] The signal-to-noise ratio of the extracted spectral peaks included in the output of the second bandpass filter may be further improved by applying the output of the second bandpass filter 804b to the PLL 1204. The VCO center frequency of the PLL 1204 may be equal to the center frequency of the second bandpass filter 804b (a higher harmonic of the reference symbol frequency). The PLL 1204 can effectively function as a filter with a narrower bandwidth compared to the second bandpass filter 804b, thereby improving the signal-to-noise ratio of the extracted spectral peak signal.

[0148]

[0148] The frequency divider and phase resolver 904 may be configured to receive the PLL output. The frequency divider and phase resolver 904 may be configured to divide the frequency of the PLL output into fundamental waves of symbol frequencies and resolve the phase ambiguity associated with frequency division (by selecting the frequency division output that has the highest phase correlation with the first bandpass filter output).

[0149]

[0149] Optionally, circuit 200g may include slicer 1312 for thresholding the outputs of the frequency divider and phase resolver to generate a square wave that can be used as a clock signal. If circuit 200g does not include slicer 1312, the outputs from the frequency divider and phase resolver 904 may be provided directly to an external circuit.

[0150]

[0150] Next, refer to Figure 18A, which is a block diagram of circuit 200h for symbol timing estimation in the received data frame 20. Circuit 200h includes an envelope detector 204 and a symbol timing estimator 208.

[0151]

[0151] In the illustrated exemplary embodiment, the envelope detector 204 directly receives the data frame 20. In some embodiments, the circuit 200h may further include a frequency downconverter 504. As described above in this specification, the frequency downconverter 504 can generate a frequency downconverted output of the received signal and provide the frequency downconverted output (e.g., an IF or baseband frequency signal) to the envelope detector 204. Optionally, the frequency downconverter 504 may provide the envelope detector 204 with a filtered frequency downconverted output.

[0152]

[0152] In the illustrated exemplary embodiment, the symbol timing estimator 208 includes a Fourier transform block 1804a.

[0153]

[0153] The Fourier transform block 1804a can enable the symbol timing estimator 208 to extract symbol timing, frequency, and phase information by directly sampling the envelope detection output 212. The Fourier transform can be applied to the envelope detection output 212 without requiring a bandpass filter or PLL to first extract the target spectral peak signal from the envelope detection output 212.

[0154]

[0154] In some embodiments, the Fourier transform block 1804a may apply a Fast Fourier Transform (FFT) to the envelope detection output 212. Next, refer to Figure 18B, a block diagram of the circuit 200h for symbol timing estimation in the received data frame 20. In the illustrated exemplary embodiment, the symbol timing estimator 208 includes an FFT block 1804b.

[0155]

[0155] The FFT block 1804b may apply an FFT to the envelope detection output 212. Optionally, the symbol timing estimator 208 may further include an interpolator 1808. The FFT output is a complex representation of the frequency components of the envelope detection output. The complex output can be used to calculate the amplitude, frequency, and phase of any frequency component. Samples of the time-domain signal applied to the FFT input can be represented as a sequence of discrete samples. x[n]=x(0),x(1),x(2),…,x(N-1) Here, x[n] is the nth discrete-time sample of the time-domain signal. • N is the total number of samples. x[n] can be a real number or a complex number. The output of the FFT block is defined as follows:

number

[0156]

[0156] The phase (or angle) of X[k] generates a phase output between ±π / 2 radians.

[0157]

[0157] The phase θ is relative to the start of the FFT window time. The exact time at which backscattering begins can be extracted from the phase of the 1 MHz frequency component or other frequency components of the envelope detection output 212. The atan2(b / a) function can be used to obtain angles covering ±π radians.

[0158]

[0158] In some embodiments, the sampling rate of the FFT may be at least twice the Nyquist bandwidth of the signal being analyzed. Higher sampling rates can provide greater amplitude and phase resolution in the FFT output, but at the expense of increased complexity.

[0159]

[0159] In some cases, the required frequency / phase resolution may be greater than the resolution that the FFT can provide. In some embodiments, the symbol timing estimator 208 may include an interpolator 1808 which can enable additional processing of adjacent FFT outputs by applying a precise interpolation algorithm. The interpolation algorithm may be designed to output corresponding frequencies and phases which can be used to identify the magnitude of peaks in frequency components and provide more accurate phase and timing estimates compared to the output from the FFT block 1804. In other embodiments, padding may be used with the FFT to locate the magnitude peaks of the FFT with a higher frequency resolution compared to the output from the FFT block 1804.

[0160]

[0160] In some embodiments, the Fourier transform block 1804a in Figure 18A may apply a discrete Fourier transform (DFT) to the envelope detection output 212. Next, we refer to Figure 18C, a block diagram of the circuit 200h for symbol timing estimation in the received data frame 20. In the illustrated exemplary embodiment, the symbol timing estimator 208 includes a DFT block 1804c and a maximum value selector 1812. The DFT block 1804c may apply a DFT to the envelope detection output 212.

[0161]

[0161] The DFT can be used instead of the FFT to provide higher resolution of frequency and phase at known frequencies. For example, if the first harmonic from the envelope detection output 212 is selected and filtered (e.g., using a BPF), it may not be necessary to compute all frequency components (e.g., as in the case of the FFT). The DFT block 1804c may apply the DFT to the acquired time-domain signal and transform the sample x(n) into the frequency domain. The DFT can generate a set of complex values, each corresponding to a particular frequency bin and representing the amplitude and phase of the signal at that frequency. The maximum value selector 1812 may be used to select the frequency bin with the largest amplitude.

number

number

[0162]

[0162] The symbol timing estimation output 216 from block 1804 / interpolator 1808 / maximum value selector 1812 may include amplitude, phase, and frequency information relating to the time-domain signal from the envelope detector 204. In some embodiments, this information can be used to generate a timestamp for synchronizing the backscatter of received data symbols, for example, as described herein with reference to operation 1930 of method 1900.

[0163]

[0163] Next, we refer to Figure 19, which is a process flow of an exemplary embodiment of Method 1900 for estimating symbol timing in a received data frame of a constant nominal envelope signal. The constant nominal envelope signal can be, for example, a filtered phase-modulated signal.

[0164]

[0164] Method 1900 may be carried out by, for example, any of the circuits for estimating symbol timing described herein. For example, Method 1900 may be carried out by circuits 200a to 200h shown in Figures 2, 5, 8, 9, 12, 16, 17, and 18, respectively, and in this specification, the components shown in Figures 2, 5, 8, 9, 12, 16, 17, and 18A to 18C will be referred to together.

[0165]

[0165] In operation 1910 of method 1900, the envelope detector 204 generates an envelope detection output for one or more received data frames. The envelope detection output may have amplitude ripple related to the symbol timing in the received data frame.

[0166]

[0166] In operation 1920 of method 1900, the symbol timing estimator 208 generates a symbol timing estimate output based on the amplitude ripple in the envelope detection output. In some examples, the symbol timing estimate output may be generated based on a combination of received data frames. For example, circuit 200 may use a PLL for frequency acquisition in the first frame and then use a lock frequency for phase acquisition in one or more subsequent frames.

[0167]

[0167] In some exemplary embodiments, method 1900 may include operation 1930, in which a clock signal is generated based on the symbol timing estimation output. The clock signal may be generated, for example, by a backscatter tag (e.g., a backscatter tag 716 shown in Figure 7) to encode the backscatter tag data into a received data frame.

[0168]

[0168] As an example, the backscatter tag 716 may be configured to encode the backscatter tag data using symbols starting from the K-th symbol in the received data frame. High-precision symbol timing estimation may not be required for the initial count of symbols 1 to K-1 in the received data frame. The backscatter tag may use a local reference clock signal (e.g., an onboard crystal oscillator clock signal divided to have a frequency approximately the same as the symbol frequency) for the initial count of symbols 1 to K-1.

[0169]

[0169] The exact relationship between the frequency and phase of the local reference clock signal and the symbol timing frequency and phase may not be known. However, the duration corresponding to the count of the initial symbols (using the local reference clock) can provide the symbol timing estimator 208 with enough time to generate a symbol timing estimate output. For example, as described above in this specification, this can provide enough time for the frequency and phase locking operation of the PLL to complete. After the symbol timing estimate output is generated, the backscatter tag 716 can switch from using the local reference clock signal to using the symbol timing estimate output, which provides a more accurate estimate of the symbol timing frequency and phase. This can enable high-precision synchronization between the start of the K-th symbol in the received data frame and the start of backscattering. In some embodiments, the time required for the symbol timing estimator 208 to generate a high-precision symbol timing estimate output may be longer than the duration of symbols 1 to K-1. In such cases, the backscatter tag may start symbol timing estimation using the initial N-1 frames and then start backscattering for the N-th frame (for example, as described above in this specification with reference to Figure 15).

[0170]

[0170] The symbol count in the Nth frame can be started by an envelope detector output exceeding a threshold that indicates the Nth frame has been received. Another method may include, for example, the use of a Receive Signal Strength Indicator (RSSI) exceeding a threshold.

[0171]

[0171] Next, we refer further to Figure 20, which is a block diagram of an exemplary symbol count block 2004 of a backscatter tag. The symbol count block 2004 may include a selector 2008 and a symbol counter 2012. The output 2036 of the selector 2008 may be provided to the symbol counter 2012. The selector 2008 may receive a switching control signal 2032, a local reference clock signal 2016, and a restore clock signal 2020.

[0172]

[0172] The restored clock signal 2020 may be received from the symbol timing estimator 208, which provides high-precision symbol timing estimation. However, at the start of the Nth frame, for example due to the rise time of the filter and noise, the restored clock signal 2020 may not have sufficient accuracy.

[0173]

[0173] The switching control signal 2032 can control which of the two input clock signals is provided at output 2036 of the selector 2008. During the initial period 2024, the selector 2008 may provide a local reference clock signal 2016 at output 2036. During the initial period 2024, the local reference clock signal 2016 may provide a more stable clock signal compared to the restore clock signal 2020. Output 2040 of the symbol counter 2012 may be incremented each time the local reference clock signal goes high.

[0174]

[0174] In response to a sufficiently accurate recovery clock signal 2020 becoming available (at a time before the start of symbol K in the received data frame), the switching control signal 2032 may control the selector 2008 to switch output 2036 from the local reference clock signal 2016 to the recovery clock signal 2020. After the switch, the symbol counter 2012 may continue counting symbols in the received data frame until it reaches the Kth symbol, and may produce output 2040 indicating the start of the Kth symbol. The recovery clock signal 2020 can enable high-precision synchronization between the start of the Kth symbol in the received data frame and the start of backscattering. Output 2040 of the symbol counter 2012 may include a strobe generated to indicate the exact time when backscattering of the received data frame must begin.

[0175]

[0175] While the above description provides examples of embodiments, it will be understood that some features and / or functions of the described embodiments can be modified without departing from the spirit and principles of operation of the described embodiments. Accordingly, it will be understood by those skilled in the art that what is described above is intended to illustrate the invention and is not limiting, and that other modifications and changes can be made without departing from the scope of the invention as defined in the appended claims. The claims should not be limited by preferred embodiments and examples, and should be given the broadest interpretation that is consistent with the description as a whole. [Explanation of Symbols]

[0176] 18…Sequence, 20…Received Data Frame, 24a…Symbol 3, 24b…Symbol 4, 28a…Symbol 1, 28b…Symbol 2, 28c…Symbol 5, 200…Circuit, 200a…Circuit, 200b…Circuit, 200c…Circuit, 200d…Circuit, 200e…Circuit, 200f…Circuit, 200g…Circuit, 200h…Circuit, 204…Envelope Detector, 208…Symbol Timing Estimator, 212…Envelope Detection Output, 216…Symbol Timing Estimation Output, 304…Timing Diagram, 308…Timing Diagram, 312…Timing Diagram, 316…Timing Figure, 320...bit duration, 324...chip duration, 328...amplitude dip, 404...frequency spectrum plot, 408...spectral peak, 504...frequency downconverter, 508...frequency downconvert output, 604...frequency spectrum plot, 608...spectral peak, 612...frequency spectrum plot, 704...backscatter communication system, 708...transmitting unit, 712...receiving unit, 716...backscatter tag, 720...transmitted data frame, 724...backscattered data frame, 804...bandpass filter, 804a...first band 804b…Second bandpass filter, 904…Frequency divider and phase resolver, 908…First bandpass filter output, 912…Second bandpass filter output, 1004…M-division counter, 1008…Corrector, 1012…Selector, 1016…Multiplexer, 1020a…Slicer, 1020b…Slicer, 1024a…Frequency division output, 1024b…Frequency division output, 1024c…Frequency division output, 1028a…Corrector output, 1028b…Corrector output, 1028c…Corrector output, 1032…Selector output, 1104a…Multiplier, 11 04b…Multiplier, 1104c…Multiplier, 1108a…Integrator and dump, 1108b…Integrator and dump, 1108c…Integrator and dump, 1204…Phase-locked loop, 1208…Phase detector, 1212…Loop filter, 1216…Voltage-controlled oscillator, 1304…VCO and delay circuit, 1308…Reference suppression LPF, 1312…Slicer, 1320…Phase detector output, 1324…Filtered signal, 1328…VCO and delay circuit output, 1404…VCO, 1408…Delay circuit, 1412…Sample / hold block, 1416…Switch,1420...Quantizer, 1424...Control Input, 1428...VCO Control Voltage, 1436...VCO Output, 1436...Output, 1504...Frame, 1508...Frame, 1512...Interframe Space Length, 1804a...Fourier Transform Block, 1804b...Fast Fourier Transform Block, 1804c...Discrete Fourier Transform Block, 1808...Interpolator, 1812...Maximum Value Selector, 2004...Symbol Count Block, 2008...Selector, 2012...Symbol Counter, 2016...Local Reference Clock Signal, 2020...Restore Clock Signal, 2024...Initial Period, 2032...Switching Control Signal, 2036...Selector Output, 2040...Symbol Counter Output

Claims

1. A circuit for estimating the symbol timing in one or more received data frames of a certain nominal envelope signal, wherein the circuit is An envelope detector configured to generate an envelope detection output of the received data frame, wherein the envelope detection output has an amplitude ripple related to the symbol timing in the received data frame. A symbol timing estimator configured to receive the envelope detection output and generate a symbol timing estimation output based on the amplitude ripple, A circuit equipped with the following features.

2. The aforementioned circuit, A clock signal is generated based on the symbol timing estimation output. The clock signal is used during the backscattering of the received data frame. The circuit according to claim 1, included in a backscatter tag configured as such.

3. The backscatter tag is configured to initiate the backscattering at the K-th symbol of at least one received data frame. The aforementioned backscatter tag, The occurrence of symbols 1 to K-1 in at least one received data frame is counted. This indicates the start of the K-th symbol within the at least one received data frame. The circuit according to claim 2, comprising a symbol count block configured to generate a symbol count block output.

4. The aforementioned symbol count block, A selector configured to generate a selector output for selecting between a local reference clock signal and a restore clock signal based on an input switching control signal, A symbol counter configured to receive the selector output and generate the symbol count block output, The circuit according to claim 3, comprising:

5. The circuit according to claim 1, wherein the symbol timing estimator includes a bandpass filter configured to receive the envelope detection output.

6. The circuit according to claim 5, wherein the center frequency of the bandpass filter is equal to the reference symbol frequency of the received data frame.

7. The circuit according to claim 5, wherein the center frequency of the bandpass filter is equal to a harmonic of the reference symbol frequency of the received data frame.

8. The circuit according to claim 1, further comprising a frequency downconverter configured to generate a frequency downconverted output of the constant nominal envelope signal, and to provide the frequency downconverted output to the envelope detector to generate the envelope detection output.

9. The circuit according to claim 8, wherein the frequency down-converted output includes a real intermediate frequency signal or a complex baseband I / Q (common-mode / quadrature) signal.

10. The circuit according to claim 1, wherein the symbol timing estimator comprises a phase-locked loop (PLL) configured to receive the envelope detection output, and the PLL includes a phase detector, a loop filter, and a voltage-controlled oscillator (VCO).

11. The circuit according to claim 10, wherein the symbol timing estimator further comprises a bandpass filter configured to receive the envelope detection output, and the PLL is configured to receive the bandpass filter output from the bandpass filter.

12. The circuit according to claim 10, wherein a VCO control voltage is determined for the first frame of the received data frame to lock the PLL frequency to the target frequency of the envelope detection output, and the determined VCO control voltage is applied to the VCO in one or more subsequent frames to keep the PLL frequency locked to the target frequency.

13. The circuit according to claim 10, further comprising a delay circuit configured to provide multiple delayed versions of the VCO output, wherein the PLL is further configured to provide multiple delayed versions of the VCO output.

14. The circuit according to claim 13, wherein the PLL is further configured to use a phase detector output to select one of the plurality of delayed versions of the VCO output, the selected version of the VCO output provides the closest phase matching to the symbol timing.

15. The symbol timing estimator, A first bandpass filter configured to receive the envelope detection output, wherein the first bandpass filter has a center frequency equal to the reference symbol frequency of the received data frame, A second bandpass filter configured to receive the envelope detection output, wherein the second bandpass filter has a center frequency equal to the higher harmonic of the reference symbol frequency of the received data frame, A frequency divider configured to generate a plurality of frequency division outputs based on the output from the second bandpass filter, wherein each of the plurality of frequency division outputs has the same frequency as the symbol frequency detected in the output from the second bandpass filter, and has a different phase compared to the other frequency division outputs. A phase resolver configured to generate the symbol timing estimation output by selecting the frequency division output which has the highest phase correlation with the output from the first bandpass filter, The circuit according to claim 1, comprising:

16. The symbol timing estimator, A first bandpass filter configured to receive the envelope detection output, wherein the first bandpass filter has a center frequency equal to the reference symbol frequency of the received data frame, A second bandpass filter configured to receive the envelope detection output, wherein the second bandpass filter has a center frequency equal to the higher harmonic of the reference symbol frequency of the received data frame, A PLL configured to receive the output from the second bandpass filter, wherein the VCO center frequency of the PLL is equal to the higher harmonic of the reference symbol frequency, A frequency divider configured to generate a plurality of frequency division outputs based on the output from the PLL, wherein each of the plurality of frequency division outputs has the same frequency as the symbol frequency detected in the output from the PLL, and a different phase compared to the other frequency division outputs. A phase resolver configured to generate the symbol timing estimation output by selecting the frequency division output which has the highest phase correlation with the output from the first bandpass filter, The circuit according to claim 1, comprising:

17. The circuit according to claim 1, wherein the symbol timing estimator comprises a fast Fourier transform (FFT) block or a discrete Fourier transform (DFT) block configured to receive the envelope detection output and generate a complex frequency domain output to extract the amplitude, frequency, and phase of one or more frequency components having the maximum amplitude.

18. The circuit according to claim 17, further comprising an additional processing block configured to receive the complex frequency domain output and extract timing information from the amplitude, frequency, and / or phase of one or more frequency components having the maximum amplitude.

19. The circuit according to claim 18, wherein the additional processing block is an interpolation block configured to identify the maximum peak amplitude among the one or more frequency components having the maximum amplitude.

20. The circuit according to claim 1, wherein the constant nominal envelope signal is a filtered phase-modulated signal.

21. The circuit according to claim 3, wherein the backscatter tag is further configured to identify the start of the received data frame in response to the envelope detection output satisfying a threshold condition.

22. A method for estimating symbol timings in one or more received data frames of a certain nominal envelope signal, wherein the method is A step of generating an envelope detection output of the received data frame, wherein the envelope detection output has an amplitude ripple related to the symbol timing in the received data frame. A step of generating a symbol timing estimation output based on the amplitude ripple in the envelope detection output. Methods that include...

23. The steps include generating a clock signal based on the symbol timing estimation output using backscatter tags, The steps include: encoding backscattered tag data using the clock signal during backscattering of the received data frame; The method according to claim 22, further comprising:

24. The step of generating the symbol timing estimation output is, A step of filtering the envelope detection output using a bandpass filter, wherein the center frequency of the bandpass filter is equal to i) the reference symbol frequency of the received data frame, or ii) a harmonic of the reference symbol frequency of the received data frame. The method according to claim 22, including the method described in claim 22.

25. The steps include generating a frequency down-converted output of the aforementioned constant nominal envelope signal, The steps include providing the frequency down-converted output to the envelope detector to generate the envelope detection output, and The method according to claim 22, further comprising:

26. The method according to claim 22, wherein the step of generating the symbol timing estimation output includes the step of applying the envelope detection output to a phase-locked loop (PLL).

27. The step of generating the symbol timing estimation output is, The process involves determining the voltage-controlled oscillator (VCO) control voltage of the first frame of the received data frame and locking the PLL frequency to the target frequency of the envelope detection output, A step of keeping the determined VCO control voltage constant during one or more subsequent frames, thereby keeping the PLL frequency locked to the target frequency. The method according to claim 26, including the method described in claim 26.

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