Photodetector and electronic equipment

Abstract

To provide an optical detection device and electronic equipment capable of achieving pixel miniaturization. [Solution] An embodiment of the photodetector of the present disclosure includes a first substrate including a first semiconductor layer having a photoelectric conversion unit and a charge holding unit; a second substrate including a second semiconductor layer having a readout circuit and a wiring layer on a second surface opposite to the first surface facing the first semiconductor layer, which outputs a pixel signal based on the charge output from the pixel; a through-wiring that penetrates the second semiconductor layer and electrically connects the charge holding unit and the readout circuit; a first transistor that constitutes the readout circuit and is electrically connected to the charge holding unit via the through-wiring; a first wiring provided in the wiring layer that electrically connects the through-wiring and a first gate electrode; a second wiring provided in the same layer as the first wiring and electrically connected to a terminal whose voltage does not change in conjunction with a change in the voltage of the charge holding unit; and a third wiring provided in the same layer as the first and second wirings and disposed between the first and second wirings, which is electrically connected to a first source region.

Description

Technical Field

[0001] The present disclosure relates to a photodetector and an electronic device having a plurality of semiconductor layers stacked on one another.

Background Art

[0002] For example, in Non-Patent Document 1, a three-layer stacked image sensor with improved FD conversion gain due to the mirror effect caused by reducing the capacitance of through-wiring (DCNT) penetrating a wafer has been reported.

Prior Art Documents

Non-Patent Documents

[0003]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, miniaturization of pixels is required in a photodetector.

[0005] It is desirable to provide light detection devices and electronic equipment that can achieve pixel miniaturization. [Means for solving the problem]

[0006] A photodetector according to one embodiment of the present disclosure includes a first substrate including a first semiconductor layer having a photoelectric conversion unit and a charge holding unit for temporarily holding the charge transferred from the photoelectric conversion unit, provided for each pixel; a second substrate including a wiring layer provided on the second surface side of the second semiconductor layer, having a first surface facing the first semiconductor layer and a second surface opposite to the first surface, and having a readout circuit on the second surface side that outputs a pixel signal based on the charge output from the pixel; a through-wiring that penetrates the second semiconductor layer and electrically connects the charge holding unit and the readout circuit; and a component constituting the readout circuit that is electrically connected to the charge holding unit via the through-wiring. The first transistor has a first gate electrode, a first channel region provided on the second surface of the second semiconductor layer opposite the first gate electrode, a first source region and a first drain region provided on the second surface of the second semiconductor layer with the first channel region in between, and a first wiring provided in the wiring layer that electrically connects the through wiring to the first gate electrode, a second wiring provided in the same layer as the first wiring and electrically connected to a terminal whose voltage does not change in conjunction with changes in the voltage of the charge holding part, and a third wiring provided in the same layer as the first and second wirings and disposed between the first and second wirings, which is electrically connected to the first source region.

[0007] An electronic device according to one embodiment of the present disclosure is equipped with the light detection device according to the above embodiment as a light detection device.

[0008] In a photodetector and electronic device according to one embodiment of the present disclosure, a first substrate including a first semiconductor layer having a photoelectric conversion unit and a charge holding unit, and a second substrate including a second semiconductor layer having a readout circuit and a semiconductor layer provided on the second surface side of the second semiconductor layer opposite to the first surface facing the first semiconductor layer, are arranged opposite each other, and the charge holding unit and the readout circuit are electrically connected by through-wiring that penetrates the second semiconductor layer. The readout circuit includes a first transistor. The wiring layer includes a first wire that electrically connects the through-wiring to the gate electrode (first gate electrode) of the first transistor, a second wire electrically connected to a terminal whose voltage does not change in conjunction with the voltage change of the charge holding unit, and a third wire electrically connected to the source region (first source region) of the first transistor. These first, second, and third wires are provided on the same layer, and the third wire is arranged between the first and second wires. This reduces the capacitance of the through-wiring. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a block diagram showing an example of the functional configuration of a photodetector according to one embodiment of the present disclosure. [Figure 2] Figure 2 is a schematic plan view showing the general configuration of the photodetector shown in Figure 1. [Figure 3] Figure 3 is a schematic diagram showing the cross-sectional configuration along the line A-A' shown in Figure 2. [Figure 4] Figure 4 is the equivalent circuit diagram of the pixel sharing unit shown in Figure 1. [Figure 5] Figure 5 is a schematic cross-sectional diagram showing an example of a specific configuration of the photodetector shown in Figure 3. [Figure 6A] Figure 6A is a schematic diagram showing an example of the planar configuration of the main part of the first substrate shown in Figure 5. [Figure 6B] Figure 6B is a schematic diagram showing the planar configuration of the pad portion along with the main parts of the first substrate shown in Figure 6A. [Figure 7] Figure 7 is a schematic diagram showing an example of the planar configuration of the second substrate shown in Figure 5. [Figure 8]FIG. 8 is a schematic cross-sectional view corresponding to the line I-I' shown in FIG. 7. [Figure 9] FIG. 9 is a schematic diagram showing another example of the planar configuration of the second substrate shown in FIG. 5. [Figure 10] FIG. 10 is a schematic diagram showing another example of the planar configuration of the second substrate shown in FIG. 5. [Figure 11] FIG. 11 is a schematic diagram showing another example of the planar configuration of the second substrate shown in FIG. 5. [Figure 12] FIG. 12 is a plan schematic diagram showing an example of the layout of the bonding electrodes on the bonding surface between the first substrate and the second substrate. [Figure 13] FIG. 13 is a schematic diagram for explaining the path of an input signal or the like to the photodetection device shown in FIG. 3. [Figure 14] FIG. 14 is a schematic diagram for explaining the signal path of the pixel signal of the photodetection device shown in FIG. 3. [Figure 15A] FIG. 15A is a schematic diagram showing an example of the planar configuration of the second substrate constituting the photodetection device according to a modification of the present disclosure. [Figure 15B] FIG. 15B is a schematic diagram showing another example of the planar configuration of the second substrate constituting the photodetection device according to a modification of the present disclosure. [Figure 15C] FIG. 15C is a schematic diagram showing another example of the planar configuration of the second substrate constituting the photodetection device according to a modification of the present disclosure. [Figure 16] FIG. 16 is a plan schematic diagram showing an example of the layout of the bonding electrodes on the bonding surface between the first substrate and the second substrate. [Figure 17] FIG. 17 is a block diagram showing a configuration example of an electronic device having the photodetection device shown in FIG. 1. [Figure 18A] FIG. 18A is a schematic diagram showing an example of the overall configuration of a photodetection system using the photodetection device shown in FIG. 1 and the like. [Figure 18B] FIG. 18B is a diagram showing an example of the circuit configuration of the photodetection system shown in FIG. 18A. [Figure 19] FIG. 19 is a diagram showing an example of a schematic configuration of an endoscopic surgery system. [Figure 20] FIG. 20 is a block diagram showing an example of the functional configuration of the camera head and the CCU. [Figure 21] FIG. 21 is a block diagram showing an example of the schematic configuration of the vehicle control system. [Figure 22] FIG. 22 is an explanatory diagram showing an example of the installation positions of the out-vehicle information detection unit and the imaging unit.

Mode for Carrying Out the Invention

[0010] Hereinafter, embodiments for implementing the present disclosure will be described in detail with reference to the drawings. The description will be made in the following order. 1. Embodiment (Example of a photodetector that discharges a wiring connected to the source region of an amplification transistor between a wiring connecting a through-wiring and the gate electrode of the amplification transistor and a wiring connected to the gate electrode of other transistors) 2. Modified Example (Another example of the configuration of the photodetector) 3. Application Example 4. Application Example

[0011] <1. Embodiment> A photodetector (photodetector 1) according to an embodiment of the present disclosure is used, for example, as a CMOS (Complementary Metal Oxide Semiconductor) image sensor or the like used in electronic devices such as digital still cameras and video cameras.

[0012] The photodetector 1 of this embodiment has a first substrate 100 including a semiconductor layer 100S having a photodiode PD and a floating diffusion FD, and a second substrate 200 including a semiconductor layer 200S having a pixel circuit 210 and a wiring layer 200T-2 provided on the front surface 200S1 side opposite to the surface of the semiconductor layer 200S facing the semiconductor layer 100S (back surface 200S2). The floating diffusion FD and the pixel circuit 210 are electrically connected by through wiring 120E that penetrates the semiconductor layer 200S. The pixel circuit 210 is configured to include, for example, an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FDG. The wiring layer 200T-2 includes wiring FD-AMPgL which electrically connects the through-wiring 120E to the gate of the amplification transistor AMP, wiring electrically connected to terminals whose voltage does not change in conjunction with the voltage change of the floating diffusion FD (for example, wiring SELgL, RSTgL, FDGgL which are electrically connected to the gates of transistors other than the amplification transistor AMP), and wiring AMPsL which is electrically connected to the source of the amplification transistor AMP. These wirings FD-AMPgL, SELgL, RSTgL, FDGgL, and AMPsL are provided on the same layer, and wiring AMPsL is arranged between wiring FD-AMPgL and wiring SELgL, RSTgL, FDGgL.

[0013] Here, the photodiode PD corresponds to a specific example of the "photoelectric conversion unit" as one embodiment of the present disclosure. The floating diffusion FD corresponds to a specific example of the "charge holding unit" as one embodiment of the present disclosure. The first substrate 100 corresponds to a specific example of the "first substrate" as one embodiment of the present disclosure, and the semiconductor layer 100S corresponds to a specific example of the "first semiconductor layer" as one embodiment of the present disclosure. The second substrate 200 corresponds to a specific example of the "second substrate" as one embodiment of the present disclosure, and the semiconductor layer 200S corresponds to a specific example of the "second semiconductor layer" as one embodiment of the present disclosure. The through-wiring 120E corresponds to a specific example of the "through-wiring" as one embodiment of the present disclosure. The pixel circuit 210 corresponds to a specific example of the "readout circuit" as one embodiment of the present disclosure. The amplification transistor AMP corresponds to a specific example of the "first transistor" as one embodiment of the present disclosure. Wiring FD-AMPgL corresponds to one specific example of the "first wiring" as one embodiment of the present disclosure, wiring SELgL,RSTgL,FDGgL corresponds to one specific example of the "second wiring" as one embodiment of the present disclosure, and wiring AMPsL corresponds to one specific example of the "third wiring" as one embodiment of the present disclosure.

[0014] [Functional Configuration of the Photodetector] Figure 1 is a block diagram showing an example of the functional configuration of a photodetector (photodetector 1).

[0015] The light detection device 1 in Figure 1 includes, for example, an input unit 510A, a row drive unit 520, a timing control unit 530, a pixel array unit 540, a column signal processing unit 550, an image signal processing unit 560, and an output unit 510B.

[0016] In the pixel array section 540, pixels 541 are repeatedly arranged in an array. More specifically, a pixel sharing unit 539 containing multiple pixels serves as the repeating unit, and these are repeatedly arranged in an array consisting of row and column directions. For convenience, in this specification, the row direction may be referred to as the H direction, and the column direction orthogonal to the row direction as the V direction. In the example in Figure 1, one pixel sharing unit 539 contains eight pixels (pixels 541A to 541H). Each of the pixels 541A to 541H has a photodiode PD (illustrated in Figure 5, etc., described later). The pixel sharing unit 539 is a unit that shares one pixel circuit (pixel circuit 210 in Figure 4, described later). In other words, there is one pixel circuit (pixel circuit 210 described later) for every eight pixels (pixels 541A to 541H). By operating this pixel circuit in a time-division multiplexing manner, the pixel signals of each of the pixels 541A to 541H are read out sequentially. Pixels 541A to 541H are arranged, for example, in a 2x4 grid. The pixel array section 540 is provided with multiple row drive signal lines 542 and multiple vertical signal lines (column read lines) 543, along with the pixels 541A to 541H. The row drive signal lines 542 drive the pixels 541 included in each of the multiple pixel sharing units 539 arranged in the row direction in the pixel array section 540. They drive each pixel in the pixel sharing unit 539 that is arranged in the row direction. As will be explained in detail later with reference to Figure 4, the pixel sharing unit 539 is provided with multiple transistors. Multiple row drive signal lines 542 are connected to one pixel sharing unit 539 in order to drive each of these multiple transistors. The pixel sharing unit 539 is connected to the vertical signal lines (column read lines) 543. Pixel signals are read from each of the pixels 541A to 541H included in the pixel sharing unit 539 via the vertical signal lines (column read lines) 543.

[0017] The row drive unit 520 includes, for example, a row address control unit that determines the position of a row for driving pixels, in other words, a row decoder unit, and a row drive circuit unit that generates signals for driving pixels 541A to 541H.

[0018] The timing control unit 530 supplies timing control signals to the row drive unit 520 and the column signal processing unit 550 based on the reference clock signal and timing control signal input to the device.

[0019] The column signal processing unit 550 includes, for example, a load circuit section connected to the vertical signal line 543 and forming a source follower circuit with the pixels 541A to 541H (pixel sharing unit 539). The column signal processing unit 550 may also have an amplification circuit section that amplifies the signal read out from the pixel sharing unit 539 via the vertical signal line 543. The column signal processing unit 550 may also have a noise processing unit. In the noise processing unit, for example, the noise level of the system is removed from the signal read out from the pixel sharing unit 539 as a result of photoelectric conversion.

[0020] The column signal processing unit 550 includes, for example, an analog-to-digital converter (ADC). In the analog-to-digital converter, the signal read from the pixel sharing unit 539 or the noise-processed analog signal is converted into a digital signal. The ADC includes, for example, a comparator unit and a counter unit. In the comparator unit, the analog signal to be converted is compared with a reference signal to be compared with it. In the counter unit, the time until the comparison result in the comparator unit is reversed is measured. The column signal processing unit 550 may also include a horizontal scanning circuit unit that controls scanning of the readout column.

[0021] The image signal processing unit 560 is a circuit that performs various signal processing on the data obtained as a result of photoelectric conversion, in other words, the data obtained as a result of the imaging operation in the photodetector 1. The image signal processing unit 560 includes, for example, an image signal processing circuit unit and a data holding unit. The image signal processing unit 560 may also include a processor unit.

[0022] One example of signal processing performed in the image signal processing unit 560 is tone curve correction processing, which increases the tonal range of the AD-converted imaging data if it is data of a dark subject, and decreases the tonal range if it is data of a bright subject. In this case, it is desirable to store in advance the characteristic data of the tone curve on which the tonal range of the imaging data will be corrected in the data storage unit of the image signal processing unit 560.

[0023] The input unit 510A is for inputting, for example, the above-mentioned reference clock signal, timing control signal, and characteristic data from outside the device to the photodetector 1. The timing control signal is, for example, a vertical synchronization signal and a horizontal synchronization signal. The characteristic data is, for example, stored in the data holding unit of the image signal processing unit 560. The input unit 510A includes, for example, an input terminal 511, an input circuit unit 512, an input amplitude changing unit 513, an input data conversion circuit unit 514, and a power supply unit (not shown).

[0024] Input terminal 511 is an external terminal for inputting data. Input circuit section 512 is for taking the signal input to input terminal 511 into the photodetector 1. Input amplitude changing section 513 changes the amplitude of the signal taken in by input circuit section 512 to an amplitude that is easy to use inside the photodetector 1. Input data conversion circuit section 514 changes the order of the data sequence of the input data. Input data conversion circuit section 514 is composed of, for example, a serial-to-parallel conversion circuit. In this serial-to-parallel conversion circuit, the serial signal received as input data is converted into a parallel signal. Note that in input section 510A, the input amplitude changing section 513 and the input data conversion circuit section 514 may be omitted. Power supply section supplies power set to various voltages required inside the photodetector 1, based on the power supply supplied to the photodetector 1 from the outside.

[0025] When the light detection device 1 is connected to an external memory device, the input unit 510A may be provided with a memory interface circuit for receiving data from the external memory device. The external memory device may be, for example, flash memory, SRAM, or DRAM.

[0026] The output unit 510B outputs image data to the outside of the device. This image data includes, for example, image data captured by the light detection device 1 and image data processed by the image signal processing unit 560. The output unit 510B includes, for example, an output data conversion circuit unit 515, an output amplitude changing unit 516, an output circuit unit 517, and an output terminal 518.

[0027] The output data conversion circuit 515 is configured, for example, by a parallel-to-serial conversion circuit, which converts the parallel signal used inside the photodetector 1 into a serial signal. The output amplitude modification unit 516 modifies the amplitude of the signal used inside the photodetector 1. The modified amplitude signal is made easier to use by external devices connected outside the photodetector 1. The output circuit 517 is a circuit that outputs data from inside the photodetector 1 to outside the device, and the output circuit 517 drives the wiring outside the photodetector 1 connected to the output terminal 518. At the output terminal 518, data is output from the photodetector 1 to outside the device. In the output unit 510B, the output data conversion circuit 515 and the output amplitude modification unit 516 may be omitted.

[0028] When the light detection device 1 is connected to an external memory device, the output unit 510B may be provided with a memory interface circuit for outputting data to the external memory device. The external memory device may be, for example, flash memory, SRAM, or DRAM.

[0029] [Outline configuration of the photodetector] Figures 2 and 3 show an example of the schematic configuration of the photodetector 1. The photodetector 1 comprises three substrates (first substrate 100, second substrate 200, and third substrate 300). Figure 2 schematically shows the planar configuration of each of the first substrate 100, second substrate 200, and third substrate 300, while Figure 3 schematically shows the cross-sectional configuration of the first substrate 100, second substrate 200, and third substrate 300 stacked on top of each other. Figure 3 corresponds to the cross-sectional configuration along the line A-A' shown in Figure 2. The photodetector 1 is a three-dimensional photodetector constructed by bonding together three substrates (first substrate 100, second substrate 200, and third substrate 300). The first substrate 100 includes a semiconductor layer 100S and a wiring layer 100T. The second substrate 200 includes a semiconductor layer 200S and a wiring layer 200T. The third substrate 300 includes a semiconductor layer 300S and a wiring layer 300T. Here, for convenience, the wiring contained in each of the first substrate 100, the second substrate 200, and the third substrate 300, along with the interlayer insulating film surrounding it, are referred to as the wiring layers (100T, 200T, 300T) provided on each substrate (first substrate 100, second substrate 200, and third substrate 300). The first substrate 100, the second substrate 200, and the third substrate 300 are stacked in this order, and are arranged in the order of semiconductor layer 100S, wiring layer 100T, semiconductor layer 200S, wiring layer 200T, wiring layer 300T, and semiconductor layer 300S along the stacking direction. The specific configurations of the first substrate 100, the second substrate 200, and the third substrate 300 will be described later. The arrows shown in Figure 3 indicate the direction of incidence of light L to the photodetector 1. In this specification, for convenience, the light incidence side of the photodetector 1 may be referred to as "bottom," "lower side," or "downward" in the following cross-sectional diagrams, and the side opposite to the light incidence side may be referred to as "top," "upper side," or "upward." Also, in this specification, for convenience, with respect to a substrate having a semiconductor layer and a wiring layer, the side with the wiring layer may be referred to as the front surface, and the side with the semiconductor layer may be referred to as the back surface. However, the description in this specification is not limited to the above terminology. The photodetector 1 is, for example, a back-illuminated photodetector in which light is incident from the back surface of a first substrate 100 having a photodiode.

[0030] The pixel array section 540 and the pixel sharing unit 539 included in the pixel array section 540 are both constructed using both the first substrate 100 and the second substrate 200. The first substrate 100 is provided with a plurality of pixels 541A to 541H of the pixel sharing unit 539. Each of these pixels 541 has a photodiode (photodiode PD described later) and a transfer transistor (transfer transistor TR described later). The second substrate 200 is provided with a pixel circuit (pixel circuit 210 described later) of the pixel sharing unit 539. The pixel circuit reads out the pixel signal transferred from the photodiode of each of the pixels 541A to 541H via the transfer transistor, or resets the photodiode. In addition to such a pixel circuit, the second substrate 200 has a plurality of row drive signal lines 542 extending in the row direction and a plurality of vertical signal lines 543 extending in the column direction. The second substrate 200 further has power lines 544 (power lines VDD described later) extending in the row direction. The third substrate 300 includes, for example, an input unit 510A, a row drive unit 520, a timing control unit 530, a column signal processing unit 550, an image signal processing unit 560, and an output unit 510B. The row drive unit 520 is provided, for example, in a region that partially overlaps the pixel array unit 540 in the stacking direction of the first substrate 100, the second substrate 200, and the third substrate 300 (hereinafter simply referred to as the stacking direction). More specifically, the row drive unit 520 is provided in a region that overlaps near the edge of the pixel array unit 540 in the H direction in the stacking direction. The column signal processing unit 550 is provided, for example, in a region that partially overlaps the pixel array unit 540 in the stacking direction. More specifically, the column signal processing unit 550 is provided in a region that overlaps near the edge of the pixel array unit 540 in the V direction in the stacking direction. Although not shown in the diagram, the input section 510A and the output section 510B may be located on a part other than the third substrate 300, for example, on the second substrate 200. Alternatively, the input section 510A and the output section 510B may be provided on the back side (light incident surface) of the first substrate 100. The pixel circuit provided on the second substrate 200 may also be referred to as a pixel transistor circuit, pixel transistor group, pixel transistor, pixel readout circuit, or readout circuit.In this specification, the term "pixel circuit" is used.

[0031] The first substrate 100 and the second substrate 200 are electrically connected, for example, via a plurality of contact portions, as will be described in detail later. The second substrate 200 and the third substrate 300 are electrically connected, for example, via contact portions 201, 202, 301, and 302. Contact portions 201 and 202 are provided on the second substrate 200, and contact portions 301 and 302 are provided on the third substrate 300. Contact portion 201 of the second substrate 200 is in contact with contact portion 301 of the third substrate 300, and contact portion 202 of the second substrate 200 is in contact with contact portion 302 of the third substrate 300. The second substrate 200 has a contact region 201R provided with a plurality of contact portions 201, and a contact region 202R provided with a plurality of contact portions 202. The third substrate 300 has a contact region 301R provided with a plurality of contact portions 301 and a contact region 302R provided with a plurality of contact portions 302. The contact regions 201R and 301R are provided between the pixel array portion 540 and the row drive portion 520 in the stacking direction, as shown in Figure 3, for example. In other words, the contact regions 201R and 301R are provided in the region where the row drive portion 520 (third substrate 300) and the pixel array portion 540 (second substrate 200) overlap in the stacking direction, or in a nearby region. The contact regions 201R and 301R are provided, for example, at the ends in the H direction of such a region. In the third substrate 300, for example, the contact region 301R is provided at a position that overlaps with a part of the row drive portion 520, specifically the end of the row drive portion 520 in the H direction. Contact sections 201 and 301 connect, for example, a row drive unit 520 provided on the third substrate 300 to a row drive signal line 542 provided on the second substrate 200. Contact sections 201 and 301 may also connect, for example, an input unit 510A provided on the third substrate 300 to a power line 544 and a reference potential line (reference potential line VSS described later). Contact regions 202R and 302R are provided between the pixel array unit 540 and the column signal processing unit 550 in the stacking direction. In other words, contact regions 202R and 302R are provided, for example, in the region where the column signal processing unit 550 (third substrate 300) and the pixel array unit 540 (second substrate 200) overlap in the stacking direction, or in a nearby region.Contact areas 202R and 302R are located, for example, at the V-direction ends of such areas. On the third substrate 300, for example, contact area 301R is provided at a position overlapping with a part of the column signal processing unit 550, specifically the V-direction end of the column signal processing unit 550. Contact areas 202 and 302 are for connecting, for example, the pixel signals (signals corresponding to the amount of charge generated as a result of photoelectric conversion by the photodiode) output from each of the multiple pixel sharing units 539 of the pixel array unit 540 to the column signal processing unit 550 provided on the third substrate 300. The pixel signals are sent from the second substrate 200 to the third substrate 300.

[0032] Figure 3 is an example of a cross-sectional view of the photodetector 1, as described above. The first substrate 100, the second substrate 200, and the third substrate 300 are electrically connected via wiring layers 100T, 200T, and 300T. For example, the photodetector 1 has an electrical connection section that electrically connects the second substrate 200 and the third substrate 300. Specifically, contact sections 201, 202, 301, and 302 are formed with electrodes made of a conductive material. The conductive material is made of a metallic material such as copper (Cu), aluminum (Al), or gold (Au). The contact regions 201R, 202R, 301R, and 302R electrically connect the second substrate 200 and the third substrate 300 by directly joining wirings formed as electrodes, for example, enabling signal input and / or output between the second substrate 200 and the third substrate 300.

[0033] The electrical connection portion that electrically connects the second substrate 200 and the third substrate 300 can be provided at any desired location. For example, as described in Figure 3 as contact regions 201R, 202R, 301R, and 302R, it may be provided in a region that overlaps with the pixel array portion 540 in the stacking direction. Alternatively, the electrical connection portion may be provided in a region that does not overlap with the pixel array portion 540 in the stacking direction. Specifically, it may be provided in a region that overlaps with the peripheral portion located outside the pixel array portion 540 in the stacking direction.

[0034] The first substrate 100 and the second substrate 200 are provided with, for example, connection holes H1 and H2. The connection holes H1 and H2 penetrate the first substrate 100 and the second substrate 200. The connection holes H1 and H2 are located outside the pixel array section 540 (or the portion overlapping the pixel array section 540). For example, connection hole H1 is located outside the pixel array section 540 in the H direction, and connection hole H2 is located outside the pixel array section 540 in the V direction. For example, connection hole H1 reaches the input section 510A provided on the third substrate 300, and connection hole H2 reaches the output section 510B provided on the third substrate 300. The connection holes H1 and H2 may be cavities, or they may contain conductive material in at least part of them. For example, there is a configuration in which bonding wires are connected to electrodes formed as the input section 510A and / or the output section 510B. Alternatively, there is a configuration in which electrodes formed as input section 510A and / or output section 510B are connected to conductive material provided in connection holes H1 and H2. The conductive material provided in connection holes H1 and H2 may be embedded in part or all of the connection holes H1 and H2, or the conductive material may be formed on the side walls of the connection holes H1 and H2.

[0035] In Figure 3, the input section 510A and output section 510B are provided on the third board 300, but the structure is not limited to this. For example, the input section 510A and / or output section 510B can be provided on the second board 200 by sending the signals from the third board 300 to the second board 200 via wiring layers 200T and 300T. Similarly, the input section 510A and / or output section 510B can be provided on the first board 100 by sending the signals from the second board 200 to the first board 100 via wiring layers 100T and 200T.

[0036] Figure 4 is an equivalent circuit diagram showing an example of the configuration of a pixel sharing unit 539. The pixel sharing unit 539 includes a plurality of pixels 541 (in Figure 4, eight pixels 541A to 541H are represented), one pixel circuit 210 connected to these multiple pixels 541, and a vertical signal line 543 connected to the pixel circuit 210. The pixel circuit 210 includes, for example, four transistors, specifically an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FDG. As described above, the pixel sharing unit 539 operates the one pixel circuit 210 in a time-division manner, thereby sequentially outputting the pixel signals of each of the eight pixels 541 (pixels 541A to 541H) included in the pixel sharing unit 539 to the vertical signal line 543. In a configuration where multiple pixels 541 are connected to a single pixel circuit 210, and the pixel signals of these multiple pixels 541 are output by the single pixel circuit 210 in a time-division manner, this is referred to as "multiple pixels 541 sharing a single pixel circuit 210."

[0037] Pixels 541A to 541H share common components. To distinguish the components of pixels 541A to 541H from one another, the following identification numbers are added to the end of the code of the component of pixel 541A: identification number 1; identification number 2; identification number 3; identification number 4; identification number 541E; identification number 541F; identification number 6; identification number 7; and identification number 8. If it is not necessary to distinguish the components of pixels 541A to 541H from one another, the identification number at the end of the code of the component of pixel 541A to 541H is omitted.

[0038] Pixels 541A to 541H each have, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion FD electrically connected to the transfer transistor TR. In the photodiode PD (PD1 to PD8), the cathode is electrically connected to the source of the transfer transistor TR, and the anode is electrically connected to a reference potential line (e.g., ground GND). The photodiode PD converts incident light into electricity and generates a charge corresponding to the amount of light received. The transfer transistors TR (transfer transistors TR1 to TR8) are, for example, N-type MOS (Metal Oxide Semiconductor) transistors. The drain of the transfer transistor TR is electrically connected to the floating diffusion FD, and the gate of the transfer transistor TR is electrically connected to a drive signal line. This drive signal line is part of a plurality of row drive signal lines 542 (see Figure 1) connected to one pixel sharing unit 539. The transfer transistor TR transfers the charge generated in the photodiode PD to the floating diffusion FD. Floating Diffusion FDs (Floating Diffusion FD1 to FD8) are n-type diffusion layer regions formed within a p-type semiconductor layer. Floating Diffusion FDs are charge-holding means that temporarily hold the charge transferred from the photodiode PD, and are also charge-voltage conversion means that generate a voltage corresponding to the amount of charge due to the capacitance Cfd of the Floating Diffusion FD.

[0039] The eight floating diffusion transistors (Floating Diffusion FD1 to FD8) contained in the pixel sharing unit 539 are electrically connected to each other, as well as to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG. The drain of the FD conversion gain switching transistor FDG is connected to the source of the reset transistor RST, and the gate of the FD conversion gain switching transistor FDG is connected to a drive signal line. This drive signal line is part of a plurality of row drive signal lines 542 connected to the pixel sharing unit 539. The drain of the reset transistor RST is connected to the power line VDD, and the gate of the reset transistor RST is connected to a drive signal line. This drive signal line is part of a plurality of row drive signal lines 542 connected to the pixel sharing unit 539. The gate of the amplification transistor AMP is connected to the floating diffusion transistor FD, the drain of the amplification transistor AMP is connected to the power line VDD, and the source of the amplification transistor AMP is connected to the drain of the selection transistor SEL. The source of the selection transistor SEL is connected to the vertical signal line 543, and the gate of the selection transistor SEL is connected to a drive signal line. This drive signal line is part of a group of row drive signal lines 542 connected to a single pixel sharing unit 539.

[0040] When the transfer transistor TR is turned ON, it transfers the charge from the photodiode PD to the floating diffusion FD. The gate of the transfer transistor TR (transfer gate TG) includes, for example, a so-called vertical electrode and extends from the surface of the semiconductor layer (semiconductor layer 100S in Figure 5) to a depth that reaches the photodiode PD, as shown in Figure 5 below. The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned ON, it resets the potential of the floating diffusion FD to the potential of the power line VDD. The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 210. The amplification transistor AMP generates a signal with a voltage corresponding to the level of charge held in the floating diffusion FD as the pixel signal. The amplification transistor AMP is connected to the vertical signal line 543 via the selection transistor SEL. In the column signal processing unit 550, this amplification transistor AMP forms a source follower together with the load circuit section connected to the vertical signal line 543. When the selector transistor SEL is turned ON, the amplifying transistor AMP outputs the voltage across the floating diffusion FD to the column signal processing unit 550 via the vertical signal line 543. The reset transistor RST, the amplifying transistor AMP, and the selector transistor SEL are, for example, N-type MOS transistors. The feedback capacitance Cfb is the capacitance between the floating diffusion FD and the source of the amplifying transistor AMP. When operating in source follower mode, the feedback capacitance Cfb is significantly reduced to about 1 / 10 of its value when not operating in source follower mode (for example, in common-source mode) due to the positive feedback effect (Miller effect).

[0041] The FD conversion gain switching transistor FDG is used to change the gain of charge-to-voltage conversion in a floating diffusion FD. Generally, when shooting in dark places, the pixel signal is small. Based on Q=CV, when performing charge-to-voltage conversion, if the capacitance of the floating diffusion FD (capacitance Cfd) is large, the voltage V when converted by the amplification transistor AMP will be small. On the other hand, in bright places, the pixel signal is large, so if the capacitance Cfd is not large enough, the floating diffusion FD will not be able to accept the charge of the photodiode PD. Furthermore, the capacitance Cfd needs to be large so that the voltage V when converted by the amplification transistor AMP does not become too large (in other words, to keep it small). Considering these points, when the FD conversion gain switching transistor FDG is turned on, the gate capacitance of the FD conversion gain switching transistor FDG increases, so the overall capacitance Cfd increases. On the other hand, when the FD conversion gain switching transistor FDG is turned off, the overall capacitance Cfd decreases. In this way, by switching the FD conversion gain switching transistor FDG on and off, the capacitance Cfd can be varied and the conversion efficiency can be switched. The FD conversion gain switching transistor (FDG) is, for example, an N-type MOS transistor.

[0042] It is also possible to omit the FD conversion gain switching transistor FDG. In this case, for example, the pixel circuit 210 is composed of three transistors, such as an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST. The pixel circuit 210 has at least one of the pixel transistors, such as an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FDG.

[0043] The selection transistor SEL may be located between the power line VDD and the amplification transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically connected to the drain of the amplification transistor AMP, and the gate of the selection transistor SEL is electrically connected to the row drive signal line 542. The source of the amplification transistor AMP (the output terminal of the pixel circuit 210) is electrically connected to the vertical signal line 543, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST. Although not shown in the figures, the number of pixels 541 sharing one pixel circuit 210 may be other than eight. For example, two or four pixels 541 may share one pixel circuit 210.

[0044] [Specific configuration of the photodetector] Figure 5 schematically shows an example of a specific cross-sectional configuration of the photodetector 1. Note that Figure 5 is a schematic representation to make the positional relationships of the components easier to understand, and may differ from the actual cross-section. The photodetector 1 is, for example, a back-illuminated photodetector. The photodetector 1 has three substrates, namely a first substrate 100, a second substrate 200, and a third substrate 300, stacked in this order from the light incident side. The photodetector 1 further has a light-receiving lens 401 on the light incident side (back side) of the first substrate 100. A color filter layer (not shown) may be provided between the light-receiving lens 401 and the first substrate 100. The photodetector 1 has a pixel array section 540 in which a plurality of pixels 541 are repeatedly arranged in an array as described above, and a peripheral section 540B arranged around the pixel array section 540. The light-receiving lens 401 is provided for each of the plurality of pixels 541, for example.

[0045] The first substrate 100 has a semiconductor layer 100S and a wiring layer 100T. The semiconductor layer 100S has a pair of opposing surfaces (front surface 100S1 and back surface 100S2), and the wiring layer 100T is provided on the front surface 100S1 side. The back surface 100S2 of the semiconductor layer 100S is a light-receiving surface, and a light-receiving lens 401 is arranged on the back surface 100S2 side for each pixel 541. Between the semiconductor layer 100S and the light-receiving lens 401, an insulating film 111 and a fixed charge film 112 are provided in order from the light-receiving lens 401 side. The first substrate 100 is provided with a photodiode PD, a floating diffusion FD, a VSS contact region 118, and a transfer transistor TR. The photodiode PD, floating diffusion FD, VSS contact region 118, and transfer transistor TR are provided for each pixel 541.

[0046] The semiconductor layer 100S is composed of, for example, a silicon substrate. The semiconductor layer 100S has, for example, a p-well layer 115 in a part of the surface 100S1 and its vicinity, and an n-type semiconductor region 114 in the remaining region (a region deeper than the p-well layer 115). For example, this n-type semiconductor region 114 and the p-well layer 115 constitute a pn-junction type photodiode PD. The p-well layer 115 is a p-type semiconductor region.

[0047] Floating diffusion FD and VSS contact regions 118 are provided spaced apart from each other near the surface 100S1 of the semiconductor layer 100S.

[0048] Floating diffusion FD and VSS contact regions 118 are provided spaced apart from each other near the surface 100S1 of the semiconductor layer 100S.

[0049] The floating diffusion FD is composed of an n-type semiconductor region provided within the p-well layer 115. The floating diffusion FD is connected from the first substrate 100 to the second substrate 200 by electrical means. For example, the floating diffusion FD is electrically connected to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG via a through-wiring 120E that penetrates the semiconductor layer 200S constituting the second substrate 200.

[0050] The VSS contact region 118 is an area electrically connected to the reference potential line VSS and is composed of a p-type semiconductor region provided within the p-well layer 115. The VSS contact region 118 is connected to the pad portion 121 via, for example, a connecting via 121C, and to the junction electrode 125 exposed on the surface of the junction surface 124S of the first substrate 100 via wiring 121D, etc. The junction electrode 125 electrically connected to the VSS contact region 118 is bonded to the junction electrode 215 exposed on the junction surface 221S of the second substrate 200 with the first substrate 100. The VSS contact region 118 may also be connected to the ground potential or a fixed potential via, for example, through wiring that penetrates the semiconductor layer 200S constituting the second substrate 200. This supplies the reference potential to the semiconductor layer 100S.

[0051] The transfer transistor TR is provided on the surface 100S1 side of the semiconductor layer 100S. The transfer transistor TR has a transfer gate TG. The transfer gate TG includes, for example, a horizontal portion TGb facing the surface of the semiconductor layer 100S and a vertical portion TGa provided within the semiconductor layer 100S. The vertical portion TGa extends in the thickness direction of the semiconductor layer 100S. One end of the vertical portion TGa is in contact with the horizontal portion TGb, and the other end is provided within the n-type semiconductor region 114. By configuring the transfer transistor TR as such a vertical transistor, the occurrence of pixel signal transfer failures becomes less likely, and the readout efficiency of the pixel signal can be improved.

[0052] As described above, the transfer gate TG is electrically connected to the drive signal line. The transfer gate TG and the drive signal line are electrically connected, for example, via a through-wiring 122E that penetrates the semiconductor layer 200S constituting the second substrate 200. The through-wiring 122E is provided in the peripheral portion 540B. The transfer gate TG is connected, for example, to the through-wiring 122E provided in the peripheral portion 540B via a wiring layer W11 and junction electrodes 125B and 215B routed from the pixel array portion 540 to the peripheral portion 540B. By providing the through-wiring 122E in the peripheral portion 540B in this way, the area of ​​the insulating region 213 for inserting the through-wiring 122E in the second substrate 200 can be reduced. Therefore, the area of ​​the semiconductor layer 200S on which the pixel circuit 210 is formed can be increased, contributing to improved image quality through noise reduction and the like.

[0053] The transfer transistor TR may be composed of a planar transistor. In this case, for example, a transfer gate TG is provided on the surface of the semiconductor layer 100S. For example, the side surface of the transfer gate TG is covered by a sidewall SW. The sidewall SW contains, for example, silicon nitride (SiN). A gate insulating film is provided between the semiconductor layer 100S and the transfer gate TG.

[0054] The semiconductor layer 100S is further provided with a pixel separation region 117, a first pinning region 113, and a second pinning region 116.

[0055] The pixel separation section 117 separates adjacent pixels 541 from each other and is formed extending between the front surface 100S1 and the back surface 100S2 of the semiconductor layer 100S. The pixel separation section 117 is provided, for example, in a grid pattern to partition adjacent pixels 541 from each other, as shown in Figures 6A and 6B. The pixel separation section 117 electrically and optically separates pixels 541A to 541H from each other. The pixel separation section 117 includes, for example, a light-shielding film 117A and an insulating film 117B. For example, tungsten (W) is used for the light-shielding film 117A. The insulating film 117B is provided between the light-shielding film 117A and the p-well layer 115 or n-type semiconductor region 114. The insulating film 117B is made of, for example, silicon oxide (SiO). The pixel isolation portion 117 has, for example, an FTI (Full Trench Isolation) structure and penetrates the semiconductor layer 100S. Although not shown, the pixel isolation portion 117 is not limited to an FTI structure that penetrates the semiconductor layer 100S. For example, it may have a DTI (Deep Trench Isolation) structure that does not penetrate the semiconductor layer 100S.

[0056] The first pinning region 113 is located near the back surface 100S2 of the semiconductor layer 100S and is positioned between the n-type semiconductor region 114 and the fixed charge film 112. The second pinning region 116 is located on the side surface of the pixel separation portion 117, specifically between the pixel separation portion 117 and the p-well layer 115 or the n-type semiconductor region 114. The first pinning region 113 and the second pinning region 116 are composed of, for example, p-type semiconductor regions.

[0057] A fixed charge film 112 having a negative fixed charge is provided between the semiconductor layer 100S and the insulating film 111. The electric field induced by the fixed charge film 112 forms a first pinning region 113 of the hole storage layer at the interface on the back surface 100S2 side of the semiconductor layer 100S, which is the light-receiving surface. This suppresses the generation of dark current caused by the interface state on the light-receiving surface side of the semiconductor layer 100S. The fixed charge film 112 is formed, for example, by an insulating film having a negative fixed charge. Examples of materials for this insulating film having a negative fixed charge include hafnium oxide (HfO2). x ), zirconium oxide (ZrO x ), aluminum oxide (AlO x ), titanium dioxide (TiO x ) or tantalum oxide (TaO x ) are some examples.

[0058] A light-shielding film 117A is provided between the fixed charge film 112 and the insulating film 111. The light-shielding film 117A may be provided continuously with the light-shielding film 117A that constitutes the pixel separation portion 117. This light-shielding film 117A between the fixed charge film 112 and the insulating film 111 is selectively provided, for example, at a position in the semiconductor layer 100S facing the pixel separation portion 117. The insulating film 111 is provided so as to cover this light-shielding film 117A. The insulating film 111 is formed of, for example, a single layer film made of one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON), or a multilayer film made of two or more of these.

[0059] The light-receiving lens 401 faces the semiconductor layer 100S, for example, with a fixed charge film 112 and an insulating film 111 in between. The light-receiving lens 401 is provided, for example, for each pixel 541, at a position facing the photodiode PD.

[0060] The wiring layer 100T has, from the semiconductor layer 100S side, an interlayer insulating film 119, pad portions 120, 121, a passivation film 123, and an interlayer insulating film 124 in this order. Within the interlayer insulating film 124, for example, the wiring layer W11 and junction electrodes 125 (125B) are provided from the semiconductor layer 100S side, and these are insulated from each other by the interlayer insulating film 124. The interlayer insulating film 124 forms a junction surface 124S with the second substrate 200, and the junction electrodes 125 (125B) are exposed on the junction surface 124S. Within the interlayer insulating film 124, vias V1 are further provided as connection parts that connect the wiring 120D, 121D and junction electrodes 125 (125B) extending in the thickness direction (Z-axis direction) of the interlayer insulating film 124 to the wiring layer W11.

[0061] The interlayer insulating films 119, 124 and the passivation film 123 are formed from a single layer film made of one of the following materials: silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON), or from a multilayer film made of two or more of these materials. The pad portions 120, 121 are formed from, for example, polysilicon (PolySi), more specifically, doped polysilicon with added impurities. It is preferable that the pad portions 120, 121 are formed from highly heat-resistant conductive materials such as polysilicon, tungsten (W), titanium (Ti), and titanium nitride (TiN). This makes it possible to form the pixel circuit 210 after bonding the semiconductor layer 200S of the second substrate 200 to the first substrate 100. The pad portions 120, 121 may also be formed from metallic materials such as tantalum nitride (TaN), aluminum (Al), and copper (Cu). The wiring 120D, through-wiring 120E, wiring layer W11, and junction electrodes 125 (125B) are formed using, for example, aluminum (Al), copper (Cu), tungsten (W), polysilicon (Poly-Si), etc.

[0062] Figure 6A schematically shows an example of the planar configuration of pixels 541 on the first substrate 100. As described above, the first substrate 100 is provided with a photodiode PD, a floating diffusion FD, a VSS contact area 118, and a transfer transistor TR for each pixel 541. Figure 6A shows the planar configuration of the photodiode PD, floating diffusion FD, VSS contact area 118, and transfer transistor TR in a pixel sharing unit 539, which consists of eight pixels 541A to 541H arranged in 2 rows and 4 columns. Note that multiple pixel sharing units 539 that are repeatedly arranged in the pixel array section 540 have substantially the same configuration as each other.

[0063] The floating diffusions FD1 to FD8, provided for each of the pixels 541A to 541H, are arranged in a 2x2 grid for pixels 541A to 541D in the upper part of the pixel sharing unit 539, and for each of the pixels 541E to 541H in the lower part of the pixel sharing unit 539, and are located close to each other approximately in the center of each pixel. The floating diffusions FD1 to FD4 and floating diffusions FD5 to FD8, which are located close to each other within the pixel sharing unit 539, are electrically connected to each other via the pad portion 120.

[0064] The VSS contact areas 118 provided for each of the pixels 541A to 541H are located at the other end of each pixel, while the floating diffusion FD is located at one end of each pixel in the V direction. For example, within the pixel sharing unit 539, the VSS contact areas 118 provided for each of the pixels 541C to 541F, which are arranged in a 2x2 grid in the center of the pixel sharing unit 539, are close to each other approximately in the center of the 2x2 grid of pixels 541C to 541F. The VSS contact areas 118 provided for pixels 541A, 541B and pixels 541G, 541H are close to each other with the VSS contact areas 118 provided for each of the other pixels constituting other pixel sharing units 539 adjacent to each other in the V direction. These VSS contact areas 118 of each pixel, which are located close to each other, are electrically connected to each other via a pad portion 121.

[0065] The transfer gates TGTG1 to TG8 provided for each of the pixels 541A to 541H are, for example, provided to surround the floating diffusion gates FD1 to FD4 and floating diffusion gates FD5 to FD8, which are located close to each other in the approximate center of pixels 541A to 541D and pixels 541D to 541H, which are arranged in a 2x2 configuration on the upper and lower sides of the pixel sharing unit 539.

[0066] Figure 6B schematically shows an example of the planar configuration of the pad portions 120 and 121, along with the planar configuration of the pixels 541 on the first substrate 100 shown in Figure 6A. The pad portions 120 and 121 are each provided in selective regions on the interlayer insulating film 119.

[0067] The pad portion 120 is for connecting floating diffusions FD1-FD4 and floating diffusions FD5-FD8, which are located close to each other approximately in the center of pixels 541A-541D and pixels 541D-541H, which are arranged in a 2x2 configuration on the upper and lower sides of the pixel sharing unit 539. One pad portion 120 is located on the upper and lower sides of the pixel sharing unit 539, straddling the pixel separation portion 117 and overlapping at least a portion of each of the floating diffusions FD1-FD4 and floating diffusions FD5-FD8. These two pad portions 120 and the floating diffusions FD1-FD4 and floating diffusions FD5-FD8 located below them are electrically connected by connection vias 120C provided in the interlayer insulating film 119. A connection via 120C is provided for each of the pixels 541A-541H. For example, by embedding a portion of the pad portion 120 in the connection via 120C, the two pad portions 120 are electrically connected to the floating diffusions FD1-FD4 and FD5-FD8, respectively.

[0068] Furthermore, the two pad portions 120 located within the pixel sharing unit 539 are electrically connected to each other via a wiring layer W11 extending in the X-axis direction and through-wirings 120E connected to each, as shown in Figure 6B. This wiring layer W11 extending in the X-axis direction is connected to a junction electrode 125 via a via V1, and is further electrically connected to a pixel circuit 210 provided for each pixel sharing unit 539 via a junction electrode 215, through-wirings 120E, a first wiring layer W21, and via V2, which will be described later.

[0069] The pad portion 121 is for connecting multiple VSS contact regions 118 that are located close to each other. The pad portion 121 straddles the pixel separation portion 117 and is arranged to overlap at least a portion of each of the four adjacent VSS contact regions 118. For example, the pad portion 121 is located between adjacent pad portions 120 in the V direction. In other words, the pad portions 120 and pad portions 121 are arranged alternately in the V direction. The pad portion 121 and the four VSS contact regions 118 located below it are electrically connected by connection vias 121C provided in the interlayer insulating film 119. Connection vias 121C are provided for each of the pixels 541A to 541H. For example, by embedding a portion of the pad portion 121 in the connection via 121C, the pad portion 121 and the four VSS contact regions 118 located below it are electrically connected.

[0070] In this way, by providing the pad portion 120, the amount of wiring connecting each floating diffusion FD to the pixel circuit 210 can be reduced throughout the entire chip. Similarly, by providing the pad portion 121, the amount of wiring supplying potential to each VSS contact area 118 can be reduced throughout the entire chip. This makes it possible to reduce the overall chip area, suppress electrical interference between wirings in miniaturized pixels, and / or reduce costs by reducing the number of components.

[0071] The pad portions 120 and 121 may, for example, be in direct contact with the semiconductor layer 100S. Specifically, the pad portions 120 and 121 may be configured to be directly connected to at least a portion of each of the floating diffusion FD and / or VSS contact regions 118.

[0072] The layout of the floating diffusion FD1 to FD8 and VSS contact area 118 provided for each of the pixels 541A to 541H, as well as the pad portions 120 and 121 provided in close proximity to each other, is not limited to this, and each can be provided in any desired position.

[0073] The second substrate 200 has a semiconductor layer 200S and wiring layers 200T-1 and 200T-2. The semiconductor layer 200S has a pair of opposing surfaces (front surface 200S1 and back surface 200S2), with wiring layer 200T-1 on the back surface 200S2 side and wiring layer 200T-2 on the front surface 200S1 side. The front surface 200S1 of the semiconductor layer 100S is the element formation surface. In the photodetector 1, the first substrate 100 and the second substrate 200 are stacked by electrode bonding such that the front surface 100S1 of the semiconductor layer 100S and the back surface 200S2 of the semiconductor layer 200S face each other. In other words, the first substrate 100 and the second substrate 200 are bonded so that the front surface of the first substrate 100 and the back surface of the second substrate 200 face each other. This bonding method is called face-to-back bonding. The first substrate 100 and the second substrate 200 may be joined to each other by a so-called hybrid junction. That is, electrodes exposed on the junction surface 124S of the first substrate 100 (junction electrodes 125 (125B)) and electrodes exposed on the junction surface 221S of the second substrate 200 (junction electrodes 215 (215B)) are joined, and the interlayer insulating film 124 forming the junction surface 124S and the interlayer insulating film 221 forming the junction surface 221S are joined. When both junction electrodes 125 (125B) and junction electrodes 215 (215B) are made of copper (Cu), the joining of junction electrodes 125 (125B) and junction electrodes 215 (215B) is sometimes called a Cu-Cu junction. The second substrate 200 is provided with a pixel circuit 210 and through-wirings 120E, 122E. The through-wirings 120E and 122E each penetrate the semiconductor layer 200S.

[0074] The semiconductor layer 200S is composed of, for example, a silicon substrate. The semiconductor layer 200S has well regions 211 in the thickness direction. The well regions 211 are, for example, p-type semiconductor regions.

[0075] The semiconductor layer 200S is further provided with an insulating region 213 and an element isolation region 214.

[0076] The insulating region 213 is a region for providing multiple through-wirings 120E, 122E for electrically connecting the first substrate 100 and the second substrate 200, insulated from the semiconductor layer 200S. The insulating region 213 has approximately the same thickness as the semiconductor layer 200S and divides the semiconductor layer 200S into multiple sections. The through-wirings 120E, 122E are arranged in this insulating region 213. The insulating region 213 is formed of, for example, silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON).

[0077] The element isolation region 214 isolates the multiple transistors constituting the pixel circuit 210 according to the layout of the pixel circuit 210. The element isolation region 214 is provided on the surface 200S1 side of the semiconductor layer 200S. The element isolation region 214 has an STI (Shallow Trench Isolation) structure. A well region 211 extends below the element isolation region 214 (deep within the semiconductor layer 200S). In the element isolation region 214, the semiconductor layer 200S is recessed in the thickness direction, and an insulating film is embedded in this recess. This insulating film is formed from, for example, silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON).

[0078] As described above, the through-wirings 120E and 122E are positioned in the insulating region 213 and penetrate the insulating region 213 in the thickness direction. The upper ends of the through-wirings 120E and 122E are connected to the wiring of the wiring layer 200T-2 (first wiring layer W21, second wiring layer W22, third wiring layer W23, fourth wiring layer W24). The through-wirings 120E and 122E are provided penetrating the insulating region 213 and the interlayer insulating film 221, and their lower ends are connected to the bonding electrodes 215 (215B) provided on the bonding surface 221S of the wiring layer 200T-1 which is bonded to the first substrate 100.

[0079] The through-wiring 120E is for electrically connecting the floating diffusion FD provided on the first substrate 100 and the pixel circuit 210 provided on the second substrate 200. More specifically, the through-wiring 120E is one of the connection means for electrically connecting the floating diffusion FD1 to FD8 provided on the pixel sharing unit 539 on the first substrate 100 and the pixel circuit 210, one of which is provided for each pixel sharing unit 539 on the second substrate 200. The floating diffusion FD1 to FD8 and the pixel circuit 210 are connected in order from the first substrate 100 side via connection via 120C, pad portion 120, wiring 120D, wiring layer W11, via V1, bonding electrodes 125, 215, through-wiring 120E, first wiring layer W21, and via V2. As a result, the pixel signals of each of the pixels 541A to 541H constituting the pixel sharing unit 539 are read out.

[0080] The through-hole wiring 122E is for electrically connecting the gate (transfer gate TG) of the transfer transistor TR provided on the first substrate 100 to the drive signal line provided on the second substrate 200. The through-hole wiring 122E is located in the peripheral area 540B. The transfer gate TG and the drive signal line are connected in order from the first substrate 100 side via wiring 122D, wiring layer W11, via V1, junction electrodes 124B, 215B and the first wiring layer W21, etc. This ensures that a drive signal is sent to each of the transfer transistors TR provided for each pixel 541.

[0081] Figure 7 schematically shows an example of a planar layout of each pixel circuit 210 provided on the second substrate 200 for each pixel sharing unit 539. Figure 8 schematically shows an example of a cross-sectional configuration of the second substrate 200 corresponding to the I-I' line shown in Figure 7. For example, in each pixel circuit 210, of the eight pixels 541 arranged in 2 rows x 4 columns within the pixel sharing unit 539, an amplification transistor AMP is provided in the upper 4 pixel 541 region arranged in 2 rows x 2 columns, and a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FDG are provided around a through-wiring 120E located in the center of the lower 4 pixel 541 region arranged in 2 rows x 2 columns. An n-well region 212 is provided in the semiconductor layer 200S surrounding the through-wiring 120E. The n-well region 212 has an annular portion 212A surrounding the through-wiring 120E and a protruding portion 212B that protrudes from the annular portion 212A in the in-plane direction of the semiconductor layer 200S.

[0082] An amplifying transistor AMP, for example, includes a substantially circular (octagonal in Figure 7) gate AMPg with an opening H in the center, a channel AMPc provided on the surface 200S1 of the semiconductor layer 200S facing the gate AMPg, source AMPs provided on the surface 200S1 of the semiconductor layer 200S surrounding the gate AMPg, adjacent to the channel AMPc, and a drain AMPd provided on the surface 200S1 of the semiconductor layer 200S inside the opening H of the gate AMPg, adjacent to the channel AMPc.

[0083] In an amplifying transistor (AMP), the width of the channel AMPc on the drain AMPd side is narrower than the width of the channel AMPc on the source AMPs side. Therefore, the gate-drain capacitance Cgd of the amplifying transistor AMP becomes smaller, improving the FD conversion efficiency. On the other hand, the gate-source capacitance Cgs of the amplifying transistor AMP becomes larger, but since the gate-source capacitance Cgs of the amplifying transistor AMP becomes the feedback capacitance Cfb, the increase in FD capacitance is reduced by the Miller effect.

[0084] The selection transistor SEL, reset transistor RST, and FD conversion gain switching transistor FDG are arranged around the through-wiring 120E as described above. It is preferable that the selection transistor SEL, reset transistor RST, and FD conversion gain switching transistor FDG are arranged to surround the through-wiring 120E. For example, as shown in Figure 7, it is preferable that the selection transistor SEL is arranged in a curved or bent line shape in a plan view, with the channel SELc in between and the source SELs and drain SELd surrounding the through-wiring 120E. Similarly, it is preferable that the reset transistor RST and FD conversion gain switching transistor FDG are arranged in a curved or bent line shape in a plan view, with the channel RSTc and FDGc in between and the source RSTs, FDGs and drain RSTd, FDGd, respectively, surrounding the through-wiring 120E. This allows for the formation of larger pixel transistors compared to when the selection transistor SEL, reset transistor RST, and FD conversion gain switching transistor FDG are arranged in a straight line, which can contribute to improved image quality through noise reduction and other means.

[0085] As described above, the n-well region 212 is provided so as to surround the through-wiring 120E and forms part of the feedback capacitance Cfb. By providing the n-well region 212 around the through-wiring 120E, the capacitance between the through-wiring 120E and the well region 211 of the semiconductor layer 200S to which the reference potential is applied is reduced. This reduces the FD capacitance and improves the conversion efficiency. Note that the n-well region 212 may be omitted. For example, the capacitance between the through-wiring 120E and the well region 211 of the semiconductor layer 200S can also be reduced by increasing the width of the insulating region 213 between the through-wiring 120E and the semiconductor layer 200S.

[0086] An element isolation region 214 is provided between the n-well region 212 surrounding the through-wiring 120E and the selection transistor SEL, reset transistor RST, and FD conversion gain switching transistor FDG. The gates SELg, RSTg, and FDGg of the selection transistor SEL, reset transistor RST, and FD conversion gain switching transistor FDG extend onto the element isolation region 214 embedded in the n-well region 212, as shown in Figure 8, for example. In this way, by arranging the transistors and the n-well region 212 in the semiconductor layer 200S in the stacking direction (Z-axis direction), both the transistors and the n-well region 212 can be arranged in the semiconductor layer 200S while securing the required width of the n-well region 212 and the area occupied by the transistors. Furthermore, the pixel size can be reduced by arranging the transistors and the n-well region 212 in the Z-axis direction. Furthermore, as shown in Figure 8, for example, since an element isolation region 214 exists between the gates that overlap in the Z-axis direction (e.g., gate SELg) and the n-well region 212, the gate potential and the n-well potential do not affect each other.

[0087] The source AMPs of the amplification transistor AMP are connected to wiring AMPsL, which form a feedback capacitance between the floating diffusion FD shown in Figure 4 and the source AMPs of the amplification transistor AMP. The wiring AMPsL extends to surround the gate AMPg of the substantially circular amplification transistor AMP, as shown in Figure 7, for example, and is connected to the source AMPs of the amplification transistor AMP at multiple points. The wiring AMPsL further extends between the annular portion 212A surrounding the through-wiring 120E and the selection transistor SEL, reset transistor RST, and FD conversion gain switching transistor FDG, which are arranged to surround the through-wiring 120E, and is connected to the n-well contact region 216 provided in the protruding portion 212B of the n-well region 212.

[0088] Near the surface 200S1 of the semiconductor layer 200S, a VSS contact region 218 connected to a reference potential line VSS is further provided. The VSS contact region 218 is composed of, for example, a p-type semiconductor region. It is preferable to place the VSS contact region 218 near, for example, the amplification transistor AMP, the selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG. This makes it possible to suppress characteristic fluctuations of the selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG due to changes in the potential of the n-well region 212 surrounding the through-wiring 120E.

[0089] Figures 9 to 11 schematically represent other examples of the planar layout of each pixel circuit 210 provided on the second substrate 200 for each pixel sharing unit 539. The amplification transistor AMP, selection transistor SEL, reset transistor RST, and FD conversion gain switching transistor FDG that constitute the pixel circuit 210 are not limited to the layout shown in Figure 7. For example, Figure 7 shows an example in which the channels, sources, and drains of the selection transistor SEL, reset transistor RST, and FD conversion gain switching transistor FDG are arranged in a curved or bent line in a planar view, surrounding the through-wiring 120E, but is not limited to this. The channels, sources, and drains of the selection transistor SEL, reset transistor RST, and FD conversion gain switching transistor FDG may also be arranged in a straight line, for example, as shown in Figure 9. Furthermore, Figure 7 shows an example in which amplification transistors AMP are arranged in four pixel 541 regions arranged in a 2x2 grid at the top, and selection transistors SEL, reset transistors RST, and FD conversion gain switching transistors FDG are arranged around a through-wiring 120E located in the center of four pixel 541 regions arranged in a 2x2 grid at the bottom, but the configuration is not limited to this. For example, as shown in Figure 10, among the eight pixels 541 arranged in a 2x4 grid within the pixel sharing unit 539, selection transistors SEL, reset transistors RST, and FD conversion gain switching transistors FDG may be arranged in four pixel 541 regions arranged in a 2x2 grid at the top, and four amplification transistors AMP may be arranged around a through-wiring 120E located in the center of four pixel 541 regions arranged in a 2x2 grid at the bottom. In this configuration, amplification transistors AMP are arranged in close proximity between adjacent pixel sharing units 539. Therefore, it is preferable to provide multiple contacts, or linear contacts, that are electrically connected to the VSS contact region 218, on the drain DMPd of adjacent amplification transistors AMP, as shown in Figure 10. This reduces crosstalk between adjacent pixel sharing units 539.Furthermore, while Figure 7 and others show an example in which the amplification transistor AMP, selection transistor SEL, reset transistor RST, and FD conversion gain switching transistor FDG are arranged in the upper and lower parts of the eight pixels 541 arranged in a 2x4 grid within the pixel sharing unit 539, the arrangement is not limited to this. For example, as shown in Figure 11, the reset transistor RST and FD conversion gain switching transistor FDG may be arranged in the upper part of the four pixel 541 region arranged in a 2x2 grid within the eight pixels 541 arranged in a 2x4 grid within the pixel sharing unit 539, while the two amplification transistors AMP and selection transistor SEL may be arranged around the through-wiring 120E located in the center of the four pixel 541 region arranged in a 2x2 grid within the lower part.

[0090] The wiring layer 200T-1 has an interlayer insulating film 221 and a bonding electrode 215 (215B). The interlayer insulating film 221 forms a bonding surface 221S with the first substrate 100, and the bonding electrode 215 (215B) is exposed on the bonding surface 221S.

[0091] Figure 12 schematically shows an example of a planar layout (B) of the bonding electrodes 125 and 215 when the second substrate 200 has a planar configuration (A) as shown in Figure 7. The bonding electrodes 125 and 215 are positioned directly beneath the through-wiring 120E, as shown in Figure 12, for example.

[0092] The wiring layer 200T-2 has a passivation film 222 and an interlayer insulating film 223 from the semiconductor layer 200S side. The passivation film 222 is in contact with, for example, the surface 200S1 of the semiconductor layer 200S and covers the entire surface 200S1 of the semiconductor layer 200S. The passivation film 222 covers the gates of the amplification transistor AMP, the selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG. Multiple wiring layers are provided within the interlayer insulating film 223. For example, within the interlayer insulating film 223, a first wiring layer W21, a second wiring layer W22, a third wiring layer W23, and a fourth wiring layer W24 are provided from the semiconductor layer 200S side, and these are insulated from each other by the interlayer insulating film 223. The interlayer insulating film 223 forms a bonding surface with the third substrate 300, and 201 and 202 are exposed at the bonding surface. The contact portions 201 and 202 are provided, for example, in the peripheral portion 540B. The contact portions 201 and 202 may be provided in a position that overlaps the pixel array portion 540 in a plan view. Multiple connection portions are provided within the interlayer insulating film 223 that connect the first wiring layer W21, the second wiring layer W22, the third wiring layer W23 or the fourth wiring layer W24 with the layers below them.

[0093] The first wiring layer W21 includes, in addition to the wiring FD-AMPgL that electrically connects the through-wiring 120E to the gate of the amplification transistor AMP, wiring SELgL that is electrically connected to the gate SELg of the selection transistor SEL, RSTgL that is electrically connected to the gate RSTg of the reset transistor RST, and FDGgL that is electrically connected to the gate FDGg of the FD conversion gain switching transistor FDG, as well as wiring AMPsL that is electrically connected to the source of the amplification transistor AMP, as shown in Figures 7,9~11. Wiring AMPsL is disposed in at least a portion of the space between wiring FD-AMPgL and wiring SELgL,RSTgL, and FDGgL. More specifically, it is preferable that wiring AMPsL is disposed such that the spacing between it and wiring FD-AMPgL is wider than the spacing between it and any of the wirings SELgL,RSTgL, and FDGgL. This reduces FD capacitance and improves conversion efficiency.

[0094] The interlayer insulating films 221, 223 and the passivation film 222 are formed from a single layer made of one of the following materials: silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON), or from a multilayer film made of two or more of these materials. The gates of the amplification transistor AMP, the selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG, the first wiring layer W21, the second wiring layer W22, the third wiring layer W23, the fourth wiring layer W24, the junction electrodes 215 (, 215B), and the contact portions 201, 202 are formed using materials such as aluminum (Al), copper (Cu), tungsten (W), and polysilicon (Poly-Si).

[0095] The third substrate 300 has a semiconductor layer 300S and a wiring layer 300T. The semiconductor layer 300S has a pair of opposing surfaces, and the wiring layer 300T is provided on one of these surfaces (front surfaces). In the photodetector 1, the second substrate 200 and the third substrate 300 are laminated by electrode bonding so that the surface 200S1 of the semiconductor layer 200S and the surface of the semiconductor layer 300S face each other. In other words, the second substrate 200 and the third substrate 300 are bonded so that the surface of the second substrate 200 and the surface of the third substrate 300 face each other. This bonding method is called face-to-face bonding. The second substrate 200 and the third substrate 300 may also be bonded to each other by so-called hybrid bonding. Specifically, electrodes (contact portions 201, 202) exposed on the bonding surface of the second substrate 200 and electrodes (contact portions 301, 302) exposed on the bonding surface of the third substrate 300 are bonded together, and the interlayer insulating film 223 forming the bonding surface of the second substrate 200 and the interlayer insulating film 311 forming the bonding surface of the third substrate 300 are bonded together. When both contact portions 201, 202 and contact portions 301, 302 are made of copper (Cu), the bonding between contact portions 201, 202 and contact portions 301, 302 is sometimes called a Cu-Cu bond.

[0096] The semiconductor layer 300S is made of, for example, a silicon substrate. Circuits are provided on the surface side of the semiconductor layer 300S. Specifically, at least a portion of the following are provided on the surface side of the semiconductor layer 300S: the input unit 510A, the row drive unit 520, the timing control unit 530, the column signal processing unit 550, the image signal processing unit 560, and the output unit 510B.

[0097] The wiring layer 300T has, for example, an interlayer insulating film 311. Within the interlayer insulating film 311 are multiple wiring layers and contact portions 301 and 302. The interlayer insulating film 311 forms a bonding surface with the second substrate 200, and the contact portions 301 and 302 are exposed on this bonding surface. The contact portions 301 and 302 are electrically connected to at least one of the following, formed on the semiconductor layer 300S: an input portion 510A, a row drive portion 520, a timing control portion 530, a column signal processing portion 550, an image signal processing portion 560, and an output portion 510B.

[0098] The interlayer insulating film 311 is formed from a single layer made of one of the following materials: silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON), or from a multilayer film made of two or more of these materials. The wiring layer and contact portions 301 and 302 provided within the interlayer insulating film 311 are formed from materials such as aluminum (Al), copper (Cu), tungsten (W), and polysilicon (Poly-Si).

[0099] In the light detection device 1, for example, the external terminal TA is connected to the input unit 510A via the connection hole H1, and the external terminal TB is connected to the output unit 510B via the connection hole H2.

[0100] Figure 5 shows an example in which peripheral circuits are provided on the peripheral portion 540B of the second substrate 200. These peripheral circuits may include a part of the row drive unit 520 or a part of the column signal processing unit 550, etc. Alternatively, as shown in Figure 3, peripheral circuits may not be placed on the peripheral portion 540B of the second substrate 200, and connection holes H1 and H2 may be placed near the pixel array unit 540.

[0101] [Operation of the light detection device] Next, the operation of the photodetector 1 will be explained using Figures 13 and 14. Figures 13 and 14 are the same as Figure 3 with arrows added to represent the paths of each signal. Figure 13 shows the paths of the input signal input to the photodetector 1 from the outside, and the power supply potential and reference potential, represented by arrows. Figure 14 shows the signal path of the pixel signal output from the photodetector 1 to the outside, represented by arrows. For example, the input signal (e.g., pixel clock and synchronization signal) input to the photodetector 1 via the input unit 510A is transmitted to the row drive unit 520 of the third substrate 300, where a row drive signal is generated. This row drive signal is sent to the second substrate 200 via the contact units 301 and 201. Furthermore, this row drive signal reaches each of the pixel sharing units 539 of the pixel array unit 540 via the row drive signal line 542 in the wiring layer 200T. Of the row drive signals that reach the pixel sharing unit 539 on the second substrate 200, drive signals other than the transfer gate TG are input to the pixel circuit 210, driving each transistor included in the pixel circuit 210. The drive signal for the transfer gate TG is input to the transfer gates TG1, TG2, TG3, TG4, TG5, TG6, TG7, TG8 on the first substrate 100 via the through wiring 122E, driving pixels 541A to 541H. In addition, the power supply potential and reference potential supplied from outside the photodetector 1 to the input section 510A (input terminal 511) of the third substrate 300 are sent to the second substrate 200 via the contact sections 301 and 201, and supplied to each pixel circuit 210 of the pixel sharing unit 539 via the wiring in the wiring layer 200T. The reference potential is further supplied to pixels 541A to 541H of the first substrate 100 via through-wiring 121E, junction electrodes 125, 215, and wiring 121D. Meanwhile, the pixel signals photoelectrically converted by pixels 541A to 541H of the first substrate 100 are sent to the pixel circuit 210 of the second substrate 200 for each pixel sharing unit 539 via wiring 120D, junction electrodes 125, 215, and through-wiring 120E. Pixel signals based on these pixel signals are sent from the pixel circuit 210 to the third substrate 300 via vertical signal lines 543 and contact sections 202, 302. These pixel signals are processed by the column signal processing unit 550 and image signal processing unit 560 of the third substrate 300, and then output to the outside via the output unit 510B.

[0102] [Effects / Effects] In the photodetector 1 of this embodiment, as described above, a first substrate 100 including a semiconductor layer 100S having a photodiode PD and a floating diffusion FD, and a second substrate 200 including a semiconductor layer 200S having a pixel circuit 210 and a wiring layer 200T-2 provided on the front surface 200S1 side opposite to the surface of the semiconductor layer 200S facing the semiconductor layer 100S (back surface 200S2), are arranged opposite each other, and the floating diffusion FD and the pixel circuit 210 are electrically connected by through-wiring 120E that penetrates the semiconductor layer 200S. The wiring layer 200T-2 includes wiring FD-AMPgL that electrically connects the through-wiring 120E to the gate of the amplification transistor AMP, wiring electrically connected to terminals whose voltage does not change in conjunction with the voltage change of the floating diffusion FD (for example, wiring SELgL, RSTgL, FDGgL that are electrically connected to the gates of transistors other than the amplification transistor AMP), and wiring AMPsL that is electrically connected to the source of the amplification transistor AMP. These wirings, FD-AMPgL, and the wirings electrically connected to terminals whose voltage does not change in conjunction with the voltage changes of the floating diffusion FD, as well as the wiring AMPsL, are provided on the same layer, and the wiring AMPsL is positioned between the wiring FD-AMPgL and the wiring electrically connected to terminals whose voltage does not change in conjunction with the voltage changes of the floating diffusion FD. This reduces the capacity (FD capacity) of the through-wiring 120E. This will be explained below.

[0103] In recent years, development has progressed on three-layer stacked image sensors in which photodiodes and floating diffusion are located on the top wafer, pixel transistors on the middle wafer, and analog and logic circuits on the bottom wafer. In such stacked image sensors, challenges to pixel miniaturization include a decrease in conversion efficiency due to the high capacitance ratio of through-wiring in the FD capacitance, and an increase in noise due to the reduction in the area of ​​pixel transistors.

[0104] In contrast, in this embodiment, as described above, the FD capacitance is reduced by arranging wiring FDsL, which is electrically connected to the source of the amplification transistor AMP, between wiring FD-AMPgL, which electrically connects the through-wiring 120E that penetrates the semiconductor layer 200S and is provided in the same layer, and the gate of the amplification transistor AMP, and wiring SELgL, RSTgL, FDGgL, which is electrically connected to terminals whose voltage does not change in conjunction with changes in the voltage of the floating diffusion FD (for example, wiring SELgL, RSTgL, FDGgL that is electrically connected to the gates of transistors other than the amplification transistor AMP), and wiring AMPsL, which is electrically connected to the source of the amplification transistor AMP. This improves the conversion efficiency.

[0105] As a result of the above, the optical detection device 1 of this embodiment makes it possible to achieve pixel miniaturization.

[0106] Modifications of this disclosure are described below. In the following modifications, components common to the above embodiments are denoted by the same reference numerals.

[0107] <2. Variant> Figures 15A to 15C schematically show examples of the planar configuration of the second substrate 200 that constitutes the photodetector (photodetector 2A to 2C) according to a modified example of the present disclosure. The photodetector 2, like the photodetector 1 of the above embodiment, is used, for example, as a CMOS (Metal Oxide Semiconductor) image sensor used in electronic devices such as digital still cameras and video cameras.

[0108] In the above embodiment, an example was shown in which the pixel sharing unit 539, which is repeatedly arranged in an array in the pixel array section 540, consists of eight pixels 541A to 541H arranged in 2 rows x 4 columns, but it is not limited to this. In this modified example, the photodetector 2 has a pixel sharing unit 539 consisting of four pixels 541 arranged in 2 rows x 2 columns, which is repeatedly arranged in an array in the pixel array section 540.

[0109] In the photodetector 2, a through-wiring 120E is positioned in the center of four pixels 541 arranged in a 2x2 grid within a pixel sharing unit 539. Of the four transistors constituting the pixel circuit 210, the amplification transistors AMP have, for example, a roughly semicircular or fan-shaped planar form and are arranged one above the through-wiring 120E. The other transistors, selection transistors SEL1 and SEL2, reset transistor RST, and FD conversion gain switching transistor FDG, are arranged separately to the left and right of the through-wiring 120E. Wiring FD-AMPgL, which electrically connects the through-wiring 120E to the gate of the amplification transistor AMP, and wiring AMPsL, which is electrically connected to the source of the amplification transistor AMP, are arranged between a portion of the wiring electrically connected to a terminal whose voltage does not change in conjunction with the voltage change of the floating diffusion FD. For example, in the photodetector 2A shown in Figure 15A and the photodetector 2B shown in Figure 15B, wiring AMPsL is arranged between wiring FD-AMPgL and wiring SEL2gL. In the photodetector 2C shown in Figure 15C, wiring AMPsL is arranged between wiring FD-AMPgL, wiring RSTgL, and wiring FDGgL. Except for this point, the photodetector 2 has substantially the same configuration as the photodetector 1 of the above embodiment.

[0110] Figure 16 schematically shows an example of a planar layout (B) of the bonding electrodes 125 and 215 when the second substrate 200 has a planar configuration (A) as shown in Figure 15A. The bonding electrodes 125 and 215 are positioned directly beneath the through-wiring 120E, similar to the embodiment described above.

[0111] Even with this configuration, the photodetectors 2A to 2C of this modified example can achieve the same effects as the photodetector 1 of the above embodiment.

[0112] <3. Application Examples> (Application Example 1) The above-mentioned light detection device 1 can be applied to any type of electronic device equipped with imaging capabilities, such as camera systems like digital still cameras and video cameras, or mobile phones with imaging functions. Figure 17 shows a schematic configuration of the electronic device 1000.

[0113] The electronic device 1000 includes, for example, a lens group 1001, a light detection device 1, a DSP (Digital Signal Processor) circuit 1002, a frame memory 1003, a display unit 1004, a recording unit 1005, an operation unit 1006, and a power supply unit 1007, all of which are interconnected via a bus line 1008.

[0114] The lens group 1001 captures incident light (image light) from the subject and forms an image on the imaging surface of the light detection device 1. The light detection device 1 converts the amount of incident light formed on the imaging surface by the lens group 1001 into an electrical signal on a pixel-by-pixel basis and supplies it as a pixel signal to the DSP circuit 1002.

[0115] The DSP circuit 1002 is a signal processing circuit that processes signals supplied from the photodetector 1. The DSP circuit 1002 outputs image data obtained by processing the signals from the photodetector 1. The frame memory 1003 temporarily holds the image data processed by the DSP circuit 1002 in frame units.

[0116] The display unit 1004 consists of a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and records the image data of moving or still images captured by the light detection device 1 onto a recording medium such as a semiconductor memory or a hard disk.

[0117] The operation unit 1006 outputs operation signals for various functions of the electronic device 1000 in accordance with user operations. The power supply unit 1007 appropriately supplies various power sources to the DSP circuit 1002, frame memory 1003, display unit 1004, recording unit 1005, and operation unit 1006.

[0118] (Application Example 2) Figure 18A schematically shows an example of the overall configuration of a photodetection system 2000 equipped with a photodetector 1. Figure 18B shows an example of the circuit configuration of the photodetection system 2000. The photodetection system 2000 includes a light-emitting device 2001 as a light source that emits infrared light L2, and a photodetector 2002 as a light-receiving unit having a photoelectric conversion element. The photodetector 1 described above can be used as the photodetector 2002. The photodetection system 2000 may further include a system control unit 2003, a light source drive unit 2004, a sensor control unit 2005, a light source side optical system 2006, and a camera side optical system 2007.

[0119] The photodetector 2002 can detect light L1 and light L2. Light L1 is light reflected from ambient light from the outside by the subject (object to be measured) 2100 (Figure 18A). Light L2 is light that has been emitted by the light-emitting device 2001 and then reflected by the subject 2100. Light L1 is, for example, visible light, and light L2 is, for example, infrared light. Light L1 is detectable in the photoelectric conversion unit of the photodetector 2002, and light L2 is detectable in the photoelectric conversion region of the photodetector 2002. Image information of the subject 2100 can be obtained from light L1, and distance information between the subject 2100 and the photodetector system 2000 can be obtained from light L2. The photodetector system 2000 can be mounted on, for example, electronic devices such as smartphones or mobile devices such as cars. The light-emitting device 2001 can be, for example, a semiconductor laser, a surface-emitting semiconductor laser, or a vertical-cavity surface-emitting laser (VCSEL). The detection method for light L2 emitted from the light-emitting device 2001 by the photodetector 2002 can, for example, be the iTOF method, but is not limited to this. In the iTOF method, the photoelectric conversion unit can measure the distance to the subject 2100 by, for example, the time-of-flight (TOF). The detection method for light L2 emitted from the light-emitting device 2001 by the photodetector 2002 can also be, for example, the structured light method or the stereo vision method. For example, in the structured light method, the distance between the photodetector 2000 and the subject 2100 can be measured by projecting a predetermined pattern of light onto the subject 2100 and analyzing the degree of distortion of the pattern. In the stereo vision method, for example, the distance between the photodetector 2000 and the subject can be measured by using two or more cameras to acquire two or more images of the subject 2100 from two or more different viewpoints. The light-emitting device 2001 and the photodetector 2002 can be synchronized and controlled by the system control unit 2003.

[0120] <4. Application Examples> (Examples of application to endoscopic surgical systems) The technology described herein (the Technology) can be applied to a variety of products. For example, the Technology described herein may be applied to an endoscopic surgical system.

[0121] Figure 19 shows an example of a schematic configuration of an endoscopic surgical system to which the technology described herein (the technology) may be applied.

[0122] Figure 19 illustrates a surgeon (physician) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgical system 11000. As shown in the figure, the endoscopic surgical system 11000 consists of an endoscope 11100, other surgical instruments 11110 such as an insufflation tube 11111 and an energy treatment device 11112, a support arm device 11120 for supporting the endoscope 11100, and a cart 11200 equipped with various devices for endoscopic surgery.

[0123] The endoscope 11100 consists of a barrel 11101, the tip of which is inserted into the body cavity of the patient 11132 for a predetermined length, and a camera head 11102 connected to the base end of the barrel 11101. In the illustrated example, the endoscope 11100 is shown as a so-called rigid endoscope having a rigid barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible endoscope having a flexible barrel.

[0124] An opening into which an objective lens is fitted is provided at the tip of the endoscope tube 11101. A light source device 11203 is connected to the endoscope 11100, and the light generated by the light source device 11203 is guided to the tip of the endoscope tube by a light guide extending inside the endoscope tube 11101, and is irradiated through the objective lens towards the object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a straight-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0125] The camera head 11102 contains an optical system and an image sensor. Reflected light from the object being observed (observation light) is focused onto the image sensor by the optical system. The image sensor converts the observation light into electrical signals, generating an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. This image signal is transmitted as RAW data to the camera control unit (CCU) 11201.

[0126] The CCU11201 consists of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and other components, and comprehensively controls the operation of the endoscope 11100 and the display device 11202. Furthermore, the CCU11201 receives image signals from the camera head 11102 and performs various image processing operations on these image signals, such as development processing (demosaic processing), to display the image based on those image signals.

[0127] The display device 11202 displays an image based on an image signal that has been processed by the CCU 11201, under control from the CCU 11201.

[0128] The light source device 11203 consists of a light source such as an LED (light-emitting diode) and supplies illumination light to the endoscope 11100 when photographing the surgical area, etc.

[0129] The input device 11204 is an input interface for the endoscopic surgical system 11000. The user can input various information and instructions to the endoscopic surgical system 11000 via the input device 11204. For example, the user can input instructions to change the imaging conditions (type of light, magnification, focal length, etc.) of the endoscope 11100.

[0130] The treatment instrument control device 11205 controls the drive of the energy treatment instrument 11112 for purposes such as tissue cauterization, incision, or vascular sealing. The insufflation device 11206 delivers gas into the patient's body cavity via the insufflation tube 11111 to inflate the body cavity of the patient 11132 for the purpose of securing a field of view by the endoscope 11100 and securing the operator's working space. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various formats such as text, images, or graphs.

[0131] The light source device 11203, which supplies illumination light to the endoscope 11100 when photographing the surgical area, can be configured as a white light source consisting of, for example, an LED, a laser light source, or a combination thereof. When the white light source is configured as a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so the white balance of the captured image can be adjusted in the light source device 11203. In this case, it is also possible to time-divisionally capture images corresponding to each of the RGB light sources by irradiating the observation target with laser light from each RGB laser light source and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter on the image sensor.

[0132] Furthermore, the light source device 11203 may be controlled to change the intensity of the light it outputs at predetermined time intervals. By controlling the drive of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity, images can be acquired in time-division order, and these images can be combined to generate high dynamic range images without so-called black crushing and white clipping.

[0133] Furthermore, the light source device 11203 may be configured to supply light in a predetermined wavelength range corresponding to special light observation. In special light observation, for example, so-called narrow-band imaging is performed, in which a predetermined tissue such as blood vessels on the surface of the mucosa is imaged with high contrast by irradiating with narrow-band light compared to the irradiation light used in normal observation (i.e., white light), utilizing the wavelength dependence of light absorption in body tissue. Alternatively, fluorescence observation may be performed in special light observation, in which an image is obtained from fluorescence generated by irradiation with excitation light. In fluorescence observation, fluorescence can be obtained by irradiating body tissue with excitation light and observing the fluorescence from the body tissue (autofluorescence observation), or by locally injecting a reagent such as indocyanine green (ICG) into body tissue and irradiating the body tissue with excitation light corresponding to the fluorescence wavelength of the reagent to obtain a fluorescence image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0134] Figure 20 is a block diagram showing an example of the functional configuration of the camera head 11102 and CCU 11201 shown in Figure 19.

[0135] The camera head 11102 includes a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with one another.

[0136] The lens unit 11401 is an optical system provided at the connection point with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and then incident on the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses, including a zoom lens and a focus lens.

[0137] The imaging unit 11402 may consist of one image sensor (a so-called single-chip system) or multiple image sensors (a so-called multi-chip system). If the imaging unit 11402 is configured as a multi-chip system, for example, each image sensor may generate image signals corresponding to RGB, and these signals may be combined to obtain a color image. Alternatively, the imaging unit 11402 may be configured to have a pair of image sensors for acquiring image signals for the right eye and left eye, respectively, corresponding to 3D (dimensional) display. By performing 3D display, the surgeon 11131 can more accurately grasp the depth of the biological tissue in the surgical area. In addition, if the imaging unit 11402 is configured as a multi-chip system, multiple lens units 11401 may be provided corresponding to each image sensor.

[0138] Furthermore, the imaging unit 11402 does not necessarily have to be located in the camera head 11102. For example, the imaging unit 11402 may be located inside the lens barrel 11101, directly behind the objective lens.

[0139] The drive unit 11403 is composed of actuators and, under control from the camera head control unit 11405, moves the zoom lens and focus lens of the lens unit 11401 along the optical axis by a predetermined distance. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted as appropriate.

[0140] The communication unit 11404 consists of communication devices for sending and receiving various types of information with the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 as RAW data to the CCU 11201 via the transmission cable 11400.

[0141] Furthermore, the communication unit 11404 receives control signals from the CCU 11201 to control the drive of the camera head 11102 and supplies them to the camera head control unit 11405. These control signals include information regarding imaging conditions, such as information to specify the frame rate of the captured image, information to specify the exposure value at the time of imaging, and / or information to specify the magnification and focus of the captured image.

[0142] The imaging conditions such as frame rate, exposure value, magnification, and focus may be specified by the user as appropriate, or they may be automatically set by the control unit 11413 of the CCU11201 based on the acquired image signal. In the latter case, the endoscope 11100 will be equipped with so-called AE (Auto Exposure), AF (Auto Focus), and AWB (Auto White Balance) functions.

[0143] The camera head control unit 11405 controls the drive of the camera head 11102 based on the control signal received from the CCU 11201 via the communication unit 11404.

[0144] The communication unit 11411 consists of a communication device for sending and receiving various types of information with the camera head 11102. The communication unit 11411 receives image signals transmitted from the camera head 11102 via the transmission cable 11400.

[0145] Furthermore, the communication unit 11411 transmits control signals to the camera head 11102 to control the driving of the camera head 11102. Image signals and control signals can be transmitted via telecommunications, optical communications, etc.

[0146] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data transmitted from the camera head 11102.

[0147] The control unit 11413 performs various controls related to imaging the surgical area, etc., by the endoscope 11100, and the display of the images obtained from imaging the surgical area, etc. For example, the control unit 11413 generates control signals to control the driving of the camera head 11102.

[0148] Furthermore, the control unit 11413 displays the captured image showing the surgical area on the display device 11202 based on the image signal processed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical instruments such as forceps, specific biological sites, bleeding, mist when using the energy treatment device 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When the control unit 11413 displays the captured image on the display device 11202, it may use the recognition results to superimpose various surgical support information onto the image of the surgical area. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced, and the surgeon 11131 can proceed with the surgery with confidence.

[0149] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable compatible with electrical signal communication, an optical fiber compatible with optical communication, or a composite cable thereof.

[0150] In the illustrated example, communication was performed via a wired connection using the transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may be performed wirelessly.

[0151] The above describes an example of an endoscopic surgical system to which the technology described herein may be applied. The technology described herein can be applied to the imaging unit 11402 of the configuration described above. By applying the technology described herein to the imaging unit 11402, the detection accuracy is improved.

[0152] While an endoscopic surgical system has been described here as an example, the technology described herein may also be applied to other systems, such as microsurgical systems.

[0153] (Examples of applications to mobile devices) The technology disclosed herein can be applied to a variety of products. For example, the technology disclosed herein may be implemented as a device mounted on any type of mobile vehicle, such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, robots, construction machinery, or agricultural machinery (tractors).

[0154] Figure 21 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0155] The vehicle control system 12000 comprises multiple electronic control units connected via a communication network 12001. In the example shown in Figure 21, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0156] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0157] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0158] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0159] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0160] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0161] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking system based on information from inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0162] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0163] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0164] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 21, the output devices include an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0165] Figure 22 shows an example of the installation position of the imaging unit 12031.

[0166] In Figure 22, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0167] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0168] Figure 22 shows an example of the imaging range of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0169] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0170] For example, the microcomputer 12051, based on distance information obtained from imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to vehicle 12100). In particular, it can extract the nearest object on the vehicle 12100's path that is traveling in approximately the same direction as vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, where the vehicle drives autonomously without driver intervention, can be performed.

[0171] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, heavy vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0172] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0173] The above describes an example of a mobile object control system to which the technology of this disclosure may be applied. The technology of this disclosure can be applied to the imaging unit 12031 of the configuration described above. Specifically, the light detection device according to the above embodiment and its modified example 1 can be applied to the imaging unit 12031. By applying the technology of this disclosure to the imaging unit 12031, high-resolution images with low noise can be obtained, so that high-precision control using the captured images can be performed in the mobile object control system.

[0174] The present disclosure has been described above with reference to embodiments, their modifications, application examples, and application examples. However, the present disclosure is not limited to the above embodiments, and various modifications are possible. The effects described herein are merely illustrative. The effects of the present disclosure are not limited to those described herein. The present disclosure may have effects other than those described herein.

[0175] Furthermore, for example, this disclosure can take the following configuration. In an optical detection device having the following configuration, the capacitance of the through-wiring (FD capacitance) is reduced, and pixel miniaturization becomes possible. (1) A first substrate including a first semiconductor layer having a photoelectric conversion unit provided for each pixel and a charge holding unit that temporarily holds the charge transferred from the photoelectric conversion unit, A second semiconductor layer having a first surface facing the first semiconductor layer and a second surface opposite to the first surface, and having a readout circuit on the second surface side that outputs a pixel signal based on the charge output from the pixel, and a second substrate including a wiring layer provided on the second surface side of the second semiconductor layer, A through-wiring penetrates the second semiconductor layer and electrically connects the charge holding unit and the readout circuit, The readout circuit comprises a first transistor having a first gate electrode electrically connected to the charge holding portion via the through-wiring, a first channel region provided on the second surface of the second semiconductor layer facing the first gate electrode, and a first source region and a first drain region provided on the second surface of the second semiconductor layer with the first channel region in between. A first wiring provided in the wiring layer that electrically connects the through-wiring and the first gate electrode, a second wiring provided in the same layer as the first wiring and electrically connected to a terminal whose voltage does not change in conjunction with the voltage change of the charge holding part, and a third wiring provided in the same layer as the first and second wirings and disposed between the first and second wirings, which is electrically connected to the first source region. A light detection device equipped with this device. (2) The photodetector according to (1), wherein the distance between the first wiring and the third wiring is wider than the distance between the second wiring and the third wiring. (3) The photodetector according to (1) or (2), wherein the width of the first channel region adjacent to the first drain region is narrower than the width of the first channel region adjacent to the first source region. (4) The photodetector according to (3), wherein the first gate electrode has a planar shape that is approximately circular, approximately semicircular, or approximately fan-shaped, with an opening approximately in the center of the circle. (5) It includes a second transistor that, together with the first transistor, constitutes the readout circuit, The second transistor has a second gate electrode, a second channel region provided on the second surface of the second semiconductor layer facing the second gate electrode, a second source region and a second drain region provided on the second surface of the second semiconductor layer with the second channel region in between. The photodetector according to any one of (1) to (4), wherein the second channel region, the second source region, and the second drain region are arranged in a curved or bent linear manner relative to each other in a plan view. (6) It includes a second transistor that, together with the first transistor, constitutes the readout circuit, The second transistor has a second gate electrode, a second channel region provided on the second surface of the second semiconductor layer facing the second gate electrode, a second source region and a second drain region provided on the second surface of the second semiconductor layer with the second channel region in between. The photodetector according to any one of (1) to (5), wherein the second semiconductor layer has at least on the second surface and its vicinity a well layer of a first conductivity type on which the first transistor and the second transistor are formed, and an annular well layer of a second conductivity type different from the first conductivity type surrounding the through wiring. (7) The photodetector according to (6), wherein the second conductive well layer has an annular portion surrounding the through wiring and a protruding portion projecting from the annular portion in the in-plane direction of the second semiconductor layer. (8) A second contact portion is formed on the aforementioned protruding portion. The photodetector according to (7), wherein the third wiring is electrically connected to the second contact portion. (9) The second semiconductor layer further has a first contact portion for applying a voltage to the first conductivity type well layer, The photodetector according to any one of (6) to (8), wherein the first contact portion is located near the first transistor and the second transistor. (10) The second semiconductor layer is embedded in the second surface and further has an element isolation region that spans the second conductivity type well layer and the first conductivity type well layer. The photodetector according to any one of (6) to (9), wherein a portion of the second gate electrode extends, in a plan view, from the second channel region to the element isolation region embedded in the well layer of the second conductivity type. (11) The second semiconductor layer has a third contact portion that is connected to a power line, The photodetector according to any one of (1) to (10), wherein the third contact portion is located between adjacent first transistors. (12) The photodetector according to (11), wherein one or more contact wires are connected to the third contact portion. (13) The photodetector according to (11) or (12), wherein a contact wiring having a planar shape in which one of the first and second directions, which are mutually orthogonal in a plan view, is longer than the other, is connected to the third contact portion. (14) It includes a second transistor that, together with the first transistor, constitutes the readout circuit, The readout circuit includes an amplification transistor, a reset transistor, a selection transistor, and an FD conversion gain switching transistor. The first transistor is the amplification transistor, The photodetector according to any one of (1) to (13), wherein the second transistor is the reset transistor, the selection transistor, and the FD conversion gain switching transistor. (15) The photodetector according to (14), wherein the terminals are the gate electrode, source electrode and drain electrode of the reset transistor, the gate electrode and drain electrode of the selection transistor, and the gate electrode, source electrode and drain electrode of the FD conversion gain switching transistor. (16) The first substrate and the second substrate each have one or more bonding electrodes on their respective bonding surfaces. The photodetector according to any one of (1) to (15), wherein the first substrate and the second substrate are electrically connected by bonding of the one or more bonding electrodes. (17) The third substrate further includes a control circuit that controls the driving of the aforementioned pixels and the readout circuit, The photodetector according to any one of (1) to (16), wherein the first substrate, the second substrate, and the third substrate are stacked in this order. (18) Equipped with a light detection device, The aforementioned light detection device is A first substrate including a first semiconductor layer having a photoelectric conversion unit provided for each pixel and a charge holding unit that temporarily holds the charge transferred from the photoelectric conversion unit, A second semiconductor layer having a first surface facing the first semiconductor layer and a second surface opposite to the first surface, and having a readout circuit on the second surface side that outputs a pixel signal based on the charge output from the pixel, and a second substrate including a wiring layer provided on the second surface side of the second semiconductor layer, A through-wiring penetrates the second semiconductor layer and electrically connects the charge holding unit and the readout circuit, The readout circuit comprises a first transistor having a first gate electrode electrically connected to the charge holding portion via the through-wiring, a first channel region provided on the second surface of the second semiconductor layer facing the first gate electrode, and a first source region and a first drain region provided on the second surface of the second semiconductor layer with the first channel region in between. A first wiring provided in the wiring layer that electrically connects the through-wiring and the first gate electrode, a second wiring provided in the same layer as the first wiring and electrically connected to a terminal whose voltage does not change in conjunction with the voltage change of the charge holding part, and a third wiring provided in the same layer as the first and second wirings and disposed between the first and second wirings, which is electrically connected to the first source region. A powerful electronic device. [Explanation of Symbols]

[0176] 1,2A,2B,2C...Photodetector, 100...First substrate, 100S,200S,300S...Semiconductor layer, 100T,200T,300T...Wiring layer, 111...Insulating film, 112...Fixed charge film, 113...First pinning region, 114...n-type semiconductor region, 115...p-well layer, 116...Second pinning region, 117...Pixel separation region, 117A...Light-shielding film, 117B...Insulating film, 118,218...VSS contact region, 119,123,221,223...Interlayer insulating film, 120,121...Pad region, 120D,121D...Wiring, 120E,121E,TGV...Through-hole wiring, 123,222...Passivation film, 200...Second substrate ,201,202,301,302...Contact area, 211...p-well area, 212...n-well area, 213...Insulation area, 214...Element isolation area, 300...Third substrate, 401...Light receiving lens, 539...Pixel sharing unit, 540...Pixel array area, 541A,541B,541C,541D...Pixel, 542...Row drive signal line, 543...Vertical signal line, 1000...Electronic equipment, TR...Transfer transistor, TG...Transfer gate, RST...Reset transistor, AMP...Amplifying transistor, SEL...Selection transistor, FDG...FD transfer transistor, PD...Photodiode, FD...Floating diffusion.

Claims

1. A first substrate including a first semiconductor layer having a photoelectric conversion unit provided for each pixel and a charge holding unit that temporarily holds the charge transferred from the photoelectric conversion unit, A second semiconductor layer having a first surface facing the first semiconductor layer and a second surface opposite to the first surface, and having a readout circuit on the second surface side that outputs a pixel signal based on the charge output from the pixel, and a second substrate including a wiring layer provided on the second surface side of the second semiconductor layer, A through-wiring penetrates the second semiconductor layer and electrically connects the charge holding portion and the readout circuit, The readout circuit comprises a first transistor having a first gate electrode electrically connected to the charge holding portion via the through-wiring, a first channel region provided on the second surface of the second semiconductor layer facing the first gate electrode, and a first source region and a first drain region provided on the second surface of the second semiconductor layer with the first channel region in between. A first wiring provided in the wiring layer that electrically connects the through wiring and the first gate electrode, a second wiring provided in the same layer as the first wiring and electrically connected to a terminal whose voltage does not change in conjunction with the voltage change of the charge holding part, and a third wiring provided in the same layer as the first and second wirings and disposed between the first and second wirings, which is electrically connected to the first source region. A light detection device equipped with this device.

2. The photodetector according to claim 1, wherein the distance between the first wiring and the third wiring is wider than the distance between the second wiring and the third wiring.

3. The photodetector according to claim 1, wherein the width of the first channel region adjacent to the first drain region is narrower than the width of the first channel region adjacent to the first source region.

4. The photodetector according to claim 3, wherein the first gate electrode has a planar shape that is substantially circular, substantially semicircular, or substantially fan-shaped, with an opening in substantially the center of the circle.

5. It includes a second transistor that, together with the first transistor, constitutes the readout circuit, The second transistor has a second gate electrode, a second channel region provided on the second surface of the second semiconductor layer facing the second gate electrode, a second source region and a second drain region provided on the second surface of the second semiconductor layer with the second channel region in between. The photodetector according to claim 1, wherein the second channel region, the second source region, and the second drain region are arranged in a curved or bent linear manner relative to each other in a plan view.

6. It includes a second transistor that, together with the first transistor, constitutes the readout circuit, The second transistor has a second gate electrode, a second channel region provided on the second surface of the second semiconductor layer facing the second gate electrode, a second source region and a second drain region provided on the second surface of the second semiconductor layer with the second channel region in between. The photodetector according to claim 1, wherein the second semiconductor layer has, at least on the second surface and its vicinity, a well layer of a first conductivity type on which the first transistor and the second transistor are formed, and an annular well layer of a second conductivity type different from the first conductivity type surrounding the through wiring.

7. The photodetector according to claim 6, wherein the second conductive well layer has an annular portion surrounding the through wiring and a protruding portion projecting from the annular portion in the in-plane direction of the second semiconductor layer.

8. A second contact portion is formed on the aforementioned protruding portion. The photodetector according to claim 7, wherein the third wiring is electrically connected to the second contact portion.

9. The second semiconductor layer further has a first contact portion for applying a voltage to the first conductivity type well layer, The photodetector according to claim 6, wherein the first contact portion is located near the first transistor and the second transistor.

10. The second semiconductor layer is embedded in the second surface and further has an element isolation region that spans the second conductivity type well layer and the first conductivity type well layer. The photodetector according to claim 6, wherein a portion of the second gate electrode extends, in a plan view, from the second channel region to the element isolation region embedded in the well layer of the second conductivity type.

11. The second semiconductor layer has a third contact portion connected to a power line, The photodetector according to claim 1, wherein the third contact portion is arranged between adjacent first transistors.

12. The photodetector according to claim 11, wherein one or more contact wirings are connected to the third contact portion.

13. The light detection device according to claim 11, wherein a contact wiring having a planar shape in which one of the first and second directions, which are mutually orthogonal in a plan view, is longer than the other, is connected to the third contact portion.

14. It includes a second transistor that, together with the first transistor, constitutes the readout circuit, The readout circuit includes an amplification transistor, a reset transistor, a selection transistor, and an FD conversion gain switching transistor. The first transistor is the amplification transistor, The photodetector according to claim 1, wherein the second transistor is the reset transistor, the selection transistor, and the FD conversion gain switching transistor.

15. The photodetector according to claim 14, wherein the terminals are the gate electrode, source electrode and drain electrode of the reset transistor, the gate electrode and drain electrode of the selection transistor, and the gate electrode, source electrode and drain electrode of the FD conversion gain switching transistor.

16. The first substrate and the second substrate each have one or more bonding electrodes on their respective bonding surfaces. The photodetector according to claim 1, wherein the first substrate and the second substrate are electrically connected by bonding of the one or more bonding electrodes.

17. The third substrate further includes a control circuit that controls the driving of the aforementioned pixels and the readout circuit. The photodetector according to claim 1, wherein the first substrate, the second substrate, and the third substrate are stacked in this order.

18. Equipped with a light detection device, The aforementioned light detection device is A first substrate including a first semiconductor layer having a photoelectric conversion unit provided for each pixel and a charge holding unit that temporarily holds the charge transferred from the photoelectric conversion unit, A second semiconductor layer having a first surface facing the first semiconductor layer and a second surface opposite to the first surface, and having a readout circuit on the second surface side that outputs a pixel signal based on the charge output from the pixel, and a second substrate including a wiring layer provided on the second surface side of the second semiconductor layer, A through-wiring penetrates the second semiconductor layer and electrically connects the charge holding portion and the readout circuit, The readout circuit comprises a first transistor having a first gate electrode electrically connected to the charge holding portion via the through-wiring, a first channel region provided on the second surface of the second semiconductor layer facing the first gate electrode, and a first source region and a first drain region provided on the second surface of the second semiconductor layer with the first channel region in between. A first wiring provided in the wiring layer that electrically connects the through wiring and the first gate electrode, a second wiring provided in the same layer as the first wiring and electrically connected to a terminal whose voltage does not change in conjunction with the voltage change of the charge holding part, and a third wiring provided in the same layer as the first and second wirings and disposed between the first and second wirings, which is electrically connected to the first source region. A powerful electronic device.

Images