Photoelectric conversion element and light receiving device

Abstract

The present invention provides a photoelectric conversion element and a light receiving device equipped therewith that can reduce inter-terminal capacitance. [Solution] The PIN photodiode 1 comprises a substrate 11 made of P-type silicon. An i-layer 12 is laminated on the substrate 11. The i-layer 12 is made of P-type silicon doped with a lower concentration of impurities (acceptors) than the substrate 11. The surface layer of the i-layer 12 has n + A semiconductor region 13 is formed. + The type semiconductor region 13 is formed by diffusing impurities (donors) from its surface into the i-layer 12, and is doped with a higher concentration of impurities than the i-layer 12. + The semiconductor region 13 has a linear shape that extends linearly in one direction when viewed from above.

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion element and a light receiving device equipped therewith. [Background technology]

[0002] Photodiodes, which convert light into electrical signals, are widely known as photoelectric conversion elements. PIN photodiodes, a type of photodiode, are widely used in remote control and optical communication devices due to their excellent high-speed response, high sensitivity, and low dark current.

[0003] Figure 20 is a cross-sectional view illustrating the structure of a conventional PIN photodiode. In a conventional PIN photodiode, an i (intrinsic) layer 102 is formed on a p-type substrate 101, and n is formed on the surface of the i layer 102. + A type region 103 is formed. When the cathode 104 is connected to a high potential and the anode 105 is connected to a low potential, a reverse bias is applied to the PIN photodiode, n + A depletion layer extends from the junction between the type region 103 and the i-layer 102 into the i-layer 102. When light is shone on the PIN photodiode, electrons in the valence band are excited to the conduction band, and holes remain in the valence band, so carriers (electrons, holes) are mainly generated in the depletion layer. Due to the electric field generated inside, electrons are n + The holes move to the neutral region of the p-type substrate 101. For example, when a load resistor is connected to the anode 105, current flows through the load resistor, and the voltage generated across the load resistor is amplified by the amplifier, and this amplified voltage is extracted as an electrical signal.

[0004] The response speed of the PIN photodiode is determined by the following three elements t1, t2, and t3: (1) to (3).

[0005] (1) Time constant t1 in an electronic circuit including a PIN photodiode and load resistor (2) Time t2 required for the diffusion of carriers generated outside the depletion layer (3) Time t3 of the carrier traveling through the depletion layer

[0006] The response speed of the PIN photodiode can be improved by reducing the values ​​of each element t1, t2, and t3. The time constant t1 is proportional to the product of the terminal capacitance of the PIN photodiode and the resistance of the load resistor, and the improvement of the response speed of the PIN photodiode is often constrained by the time constant t1. Therefore, reducing the terminal capacitance of the PIN photodiode to decrease the time constant t1 is the most effective way to improve the response speed of the PIN photodiode. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Publication No. 2005-216874 [Overview of the Initiative] [Problems that the invention aims to solve]

[0008] The object of the present invention is to provide a photoelectric conversion element and a light receiving device equipped therewith that can reduce inter-terminal capacitance. [Means for solving the problem]

[0009] To achieve the above objective, a photoelectric conversion element according to one aspect of the present invention includes a semiconductor layer of a first conductivity type, a low-concentration impurity semiconductor layer formed on the semiconductor layer and having a lower impurity concentration than the semiconductor layer, and a high-concentration impurity semiconductor region formed linearly on the surface of the low-concentration impurity semiconductor layer and having a higher impurity concentration than the low-concentration impurity semiconductor layer and belonging to a second conductivity type different from the first conductivity type, wherein the high-concentration impurity semiconductor region is linear and has substantially no width in the width direction perpendicular to both its length direction and the thickness direction of the low-concentration impurity semiconductor layer.

[0010] In this configuration, a low-concentration impurity semiconductor layer with a lower impurity concentration than the first conductivity type semiconductor layer is formed on top of the first conductivity type semiconductor layer. On the surface of the low-concentration impurity semiconductor layer, a high-concentration impurity semiconductor region of the second conductivity type is formed in a linear shape with substantially no width.

[0011] In conventional photoelectric conversion elements (PIN photodiodes), a high-concentration impurity semiconductor region (shown in Figure 20) is present in the surface layer of the low-concentration impurity semiconductor layer (corresponding to layer i 102 shown in Figure 20). + In conventional photoelectric conversion elements, a wide area (corresponding to type region 103) is formed in a planar manner. In contrast, in the photoelectric conversion element according to the present invention, a high-concentration impurity semiconductor region is formed linearly on the surface of the low-concentration impurity semiconductor layer. As a result, the photoelectric conversion element according to the present invention can reduce the junction capacitance compared to conventional photoelectric conversion elements, and consequently reduce the inter-terminal capacitance. As a result, the response speed of the photoelectric conversion element can be improved.

[0012] In a photoelectric conversion element, a light-receiving region is set in the low-concentration impurity semiconductor layer to receive light from the outside, and the photoelectric conversion element may further include an anti-reflective film formed in the light-receiving region and in contact with the surface of the low-concentration impurity semiconductor layer.

[0013] In this configuration, in the light-receiving region, the anti-reflective film is in contact with the surface of the low-concentration impurity semiconductor layer, and no electrodes (wiring connected to the high-concentration impurity semiconductor region) or insulating films are formed between the surface of the low-concentration impurity semiconductor layer and the anti-reflective film. Therefore, interference of light between the anti-reflective film and the low-concentration impurity semiconductor layer can be prevented.

[0014] The photoelectric conversion element further includes a first conductive layer formed above a low-concentration impurity semiconductor layer, the first conductive layer extending in the length direction opposite to at least a portion of the high-concentration impurity semiconductor region in the thickness direction, and may be connected to a fixed potential.

[0015] This configuration allows the first conductive layer to block electromagnetic noise even if it enters the high-concentration impurity semiconductor region from the outside. Therefore, it is possible to prevent external electromagnetic noise from reaching the high-concentration impurity semiconductor region and eliminate adverse effects caused by electromagnetic noise.

[0016] The photoelectric conversion element further includes a plurality of second conductive layers formed above a low-concentration impurity semiconductor layer, the plurality of second conductive layers each extending in the length direction, facing each other in the thickness direction with respect to different portions of the high-concentration impurity semiconductor region, and connected to a fixed potential.

[0017] This configuration allows electromagnetic noise to be blocked by the first or second conductive layer even if it enters the high-concentration impurity semiconductor region from the outside. Therefore, it is possible to further prevent external electromagnetic noise from reaching the high-concentration impurity semiconductor region and eliminate adverse effects caused by electromagnetic noise.

[0018] The photoelectric conversion element may further include an interlayer film formed between a first conductive layer and a second conductive layer, and vias that extend in the longitudinal direction, penetrate the interlayer film in the thickness direction, and connect the first conductive layer and the second conductive layer.

[0019] In this configuration, even if electromagnetic noise enters the high-concentration impurity semiconductor region from the outside in a direction that intersects the thickness direction, that electromagnetic noise can be blocked by the first conductive layer, the second conductive layer, or vias. Therefore, it is possible to prevent external electromagnetic noise from reaching the high-concentration impurity semiconductor region and eliminate adverse effects caused by electromagnetic noise.

[0020] The photoelectric conversion element further includes an interlayer film formed between a low-concentration impurity semiconductor layer and a first conductive layer, and two vias extending in the length direction and penetrating the interlayer film in the thickness direction to connect the first conductive layer and the low-concentration impurity semiconductor layer. On the surface of the low-concentration impurity semiconductor layer, a first conductivity type contact region with a higher impurity concentration than the low-concentration impurity semiconductor layer is formed with a gap between it and the high-concentration impurity semiconductor region in the width direction, and the two vias may be connected to the contact regions on one and the other sides in the width direction relative to the high-concentration impurity semiconductor region, respectively.

[0021] This configuration allows the first conductive layer to block electromagnetic noise even if it enters the high-concentration impurity semiconductor region from the outside in the thickness direction. Furthermore, even if electromagnetic noise enters the high-concentration impurity semiconductor region from the outside in a direction intersecting the thickness direction, it can be blocked by the first conductive layer or vias. Therefore, it is possible to prevent external electromagnetic noise from reaching the high-concentration impurity semiconductor region and eliminate adverse effects caused by electromagnetic noise.

[0022] The photoelectric conversion element may further include an insulating film formed above a low-concentration impurity semiconductor layer, and a transparent conductive film formed on the insulating film and connected to a fixed potential.

[0023] In this configuration, even if electromagnetic noise enters the high-concentration impurity semiconductor region from the outside, that electromagnetic noise can be blocked by the transparent conductive film. Therefore, it is possible to prevent external electromagnetic noise from reaching the high-concentration impurity semiconductor region and eliminate the adverse effects of electromagnetic noise.

[0024] If the insulating film is an interlayer film and a passivation film is formed above the insulating film, the transparent conductive film may be formed on the passivation film.

[0025] Furthermore, if the transparent conductive layer is formed on a passivation film, a protective film may be formed on the transparent conductive layer to protect it.

[0026] The photoelectric conversion element further includes a semiconductor region for fixed potential connection of a first conductivity type formed on the surface of a low-concentration impurity semiconductor layer, the fixed potential connection semiconductor region may be provided with a gap in the width direction relative to the high-concentration impurity semiconductor region, extend in the length direction, and be connected to a fixed potential.

[0027] In this configuration, even if electromagnetic noise enters an area adjacent to the high-concentration impurity semiconductor region in the width direction, that electromagnetic noise can be blocked by the fixed-potential connection semiconductor region. Therefore, it is possible to prevent external electromagnetic noise from reaching the high-concentration impurity semiconductor region and eliminate adverse effects caused by electromagnetic noise.

[0028] Furthermore, by bonding the electrodes to the surface of a semiconductor region for fixed-potential connection and connecting the electrodes to a fixed potential, the semiconductor layer can be connected to a fixed potential via the semiconductor region for fixed-potential connection and the low-concentration impurity semiconductor layer. Therefore, when the photoelectric conversion element is a photodiode, the electrodes can be either anode electrodes or cathode electrodes.

[0029] A light-receiving device according to another aspect of the present invention comprises a photoelectric conversion element, an amplification circuit for amplifying a signal output from the photoelectric conversion element, wiring connecting the photoelectric conversion element and the amplification circuit, and a conductive layer formed at least above the wiring, facing the entire wiring, and connected to a fixed potential. The photoelectric conversion element includes a semiconductor layer of a first conductivity type, a low-concentration impurity semiconductor layer formed on the semiconductor layer and having a lower impurity concentration than the semiconductor layer, a high-concentration impurity semiconductor region formed linearly on the surface of the low-concentration impurity semiconductor layer and having a higher impurity concentration than the low-concentration impurity semiconductor layer and belonging to a second conductivity type different from the first conductivity type, and a first conductive layer formed above the low-concentration impurity semiconductor layer. The high-concentration impurity semiconductor region is linear and has substantially no width in the width direction perpendicular to both its length direction and the thickness direction of the low-concentration impurity semiconductor layer. The first conductive layer faces at least a portion of the high-concentration impurity semiconductor region and the thickness direction of the low-concentration impurity semiconductor layer, extends in the length direction of the high-concentration impurity semiconductor region, and is connected to a fixed potential.

[0030] Furthermore, a light receiving device according to another aspect of the present invention comprises a photoelectric conversion element, an amplification circuit for amplifying a signal output from the photoelectric conversion element, wiring connecting the photoelectric conversion element and the amplification circuit, and a conductive layer formed at least above the wiring, facing the entire wiring, and connected to a fixed potential. The photoelectric conversion element includes a semiconductor layer of a first conductivity type, a low-concentration impurity semiconductor layer formed on the semiconductor layer and having a lower impurity concentration than the semiconductor layer, a high-concentration impurity semiconductor region of a second conductivity type, formed linearly on the surface of the low-concentration impurity semiconductor layer and having a higher impurity concentration than the low-concentration impurity semiconductor layer and different from the first conductivity type, an insulating film formed above the low-concentration impurity semiconductor layer, and a transparent conductive film formed on the insulating film and connected to a fixed potential. The high-concentration impurity semiconductor region is linear and has substantially no width in the width direction perpendicular to both its length direction and the thickness direction of the low-concentration impurity semiconductor layer.

[0031] In these light-receiving devices, the photoelectric conversion element has a shielding structure, and the wiring (signal lines) connecting the photoelectric conversion element and the amplification circuit is shielded with a conductive layer, resulting in seamless shielding from the photoelectric conversion element to the amplification circuit. Therefore, the light-receiving device can be prevented from being adversely affected by external electromagnetic noise.

[0032] In a light-receiving device, it is preferable that the conductive layer is formed to surround the wiring from above and from the sides.

[0033] This allows the wiring to be shielded more effectively with a conductive layer.

[0034] Furthermore, the statement that a high-concentration impurity semiconductor region has virtually no width in the width direction means that the high-concentration impurity semiconductor region is essentially a line.

[0035] In photoelectric conversion elements, a light-receiving region is set in a low-concentration impurity semiconductor layer to receive light from the outside. The high-concentration impurity semiconductor region is essentially a line and has virtually no width in the width direction, but if its width is expressed in comparison to the width of the light-receiving region in the width direction, it can be said that the ratio of the width of the high-concentration impurity semiconductor region to the width of the light-receiving region in the width direction is set to 1% or less.

[0036] A structure in which the high-concentration impurity semiconductor region is substantially linear can be applied to a photoelectric conversion element that employs a shielded structure, which has a first conductive layer formed above the low-concentration impurity semiconductor layer, extending in the longitudinal direction of the high-concentration impurity semiconductor region and connected to a fixed potential, facing at least a portion of the high-concentration impurity semiconductor region and the thickness direction of the low-concentration impurity semiconductor layer.

[0037] For example, in a structure where the first conductive layer has the same width in the width direction as the linewidth of the high-concentration impurity semiconductor region, and the first conductive layer faces the entire high-concentration impurity semiconductor region in the thickness direction, electromagnetic noise entering the high-concentration impurity semiconductor region from the outside can be effectively blocked by the first conductive layer, and a high shielding effect against external electromagnetic noise can be achieved.

[0038] In photoelectric conversion elements employing such a shielding structure, as the proportion of the high-concentration impurity semiconductor region in the light-receiving area increases, the area shielded by the first conductive layer increases, resulting in a decrease in the amount of light received. Along with the decrease in the amount of light received, the photocurrent value decreases.

[0039] In a structure where the high-concentration impurity semiconductor region is essentially a line, the region affected by light shielding by the first conductive layer can be made as close to zero as possible. This suppresses the decrease in light reception due to the shielding structure and thus reduces the decrease in photocurrent value.

[0040] It goes without saying that a structure in which the high-concentration impurity semiconductor region is substantially linear may be applied to a photoelectric conversion element that does not have a shielding structure. A photoelectric conversion element to which a structure in which the high-concentration impurity semiconductor region is substantially linear is applied may have a shielding structure added to its exterior.

[0041] When multiple high-concentration impurity semiconductor regions are provided, it is preferable that the ratio of the sum of the areas of the high-concentration impurity semiconductor regions to the area of ​​the light-receiving region is 5% or less.

[0042] This study compares a photoelectric converter with a shielded structure with a photoelectric converter that does not employ a shielded structure but otherwise has the same structure as the one with a shielded structure. In order to ensure the same signal-to-noise ratio (S / N) as a photoelectric converter without a shielded structure, the resistance value of the resistor connected to the photoelectric converter (the resistor that converts current to voltage) must be increased in proportion to the square of the reciprocal of the rate of decrease in the photocurrent value (the ratio of the decrease in the photocurrent value of the photoelectric converter with a shielded structure to the photocurrent value of the photoelectric converter without a shielded structure).

[0043] Furthermore, as the sum of the areas of the high-concentration impurity semiconductor regions increases, the junction area between the low-concentration impurity semiconductor layer and the high-concentration impurity semiconductor region increases accordingly, and consequently, the inter-terminal capacitance of the photoelectric conversion element increases.

[0044] The response speed of a photoelectric converter is strongly influenced by the product of the terminal capacitance of the photoelectric converter and the resistance of the resistor connected to the photoelectric converter. Therefore, as shown in Figure 21, the response speed of a photoelectric converter with a shielded structure decreases as the proportion of the high-concentration impurity semiconductor region in the light-receiving area increases. If the proportion of the high-concentration impurity semiconductor region in the light-receiving area is 5% or less, the attenuation of the optical signal intensity compared to a photoelectric converter without a shielded structure can be kept below -3dB. Therefore, a photoelectric converter with a high-concentration impurity semiconductor region of 5% or less in the light-receiving area can be used with a shielded structure without affecting the circuit design or specifications. [Brief explanation of the drawing]

[0045] [Figure 1] This is a cross-sectional view illustrating the structure of a PIN photodiode according to one embodiment of the present invention. [Figure 2] Figure 1 is a plan view of the PIN photodiode shown. [Figure 3] This is a cross-sectional diagram illustrating the structure of a PIN photodiode with a shielding structure. [Figure 4] Figure 3 is a plan view of the PIN photodiode shown. [Figure 5] This is a cross-sectional diagram illustrating the structure of a PIN photodiode with other shielding structures. [Figure 6] Figure 5 is a plan view of the PIN photodiode shown. [Figure 7] This is a cross-sectional diagram illustrating the structure of a PIN photodiode with additional shielding structures. [Figure 8] Figure 7 is a plan view of the PIN photodiode shown. [Figure 9] This is a cross-sectional diagram illustrating the structure of a PIN photodiode with additional shielding structures. [Figure 10] Figure 9 is a plan view of the PIN photodiode shown. [Figure 11]This is a cross-sectional diagram illustrating the structure of a PIN photodiode with additional shielding structures. [Figure 12] Figure 11 is a plan view of the PIN photodiode shown. [Figure 13] This is a cross-sectional diagram illustrating the structure of a PIN photodiode with additional shielding structures. [Figure 14] This is a cross-sectional diagram illustrating the structure of a PIN photodiode with its two electrodes arranged on the surface. [Figure 15] This is a cross-sectional diagram illustrating another example of a PIN photodiode structure in which the two electrodes are arranged on the surface. [Figure 16] Figure 15 is a plan view of the PIN photodiode shown. [Figure 17] This diagram illustrates the configuration of a light-receiving device according to another embodiment of the present invention. [Figure 18] Figure 17 is a diagrammatic cross-sectional view illustrating the cross-section obtained when the light receiving device is cut along the cutting line AA shown in Figure 17. [Figure 19] This is a cross-sectional view illustrating the structure shown in Figure 18 and another structure. [Figure 20] This is a cross-sectional view illustrating the structure of a conventional PIN photodiode. [Figure 21] This graph shows the relationship between the proportion of the light-receiving region occupied by the high-concentration impurity semiconductor region and the ratio (relative response speed) of the response speed of a photoelectric conversion element with a shielded structure to the response speed of a photoelectric conversion element without a shielded structure. [Modes for carrying out the invention]

[0046] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0047] <PINフォトダイオード> Figure 1 is a schematic cross-sectional view illustrating the structure of a PIN photodiode 1 according to one embodiment of the present invention, and Figure 2 is a plan view thereof.

[0048] The PIN photodiode 1 includes a substrate 11 that forms its base. The substrate 11 is made of, for example, P-type silicon (Si).

[0049] An i-layer 12 is laminated on the substrate 11. The i-layer 12 is formed, for example, by epitaxial growth and is made of P-type silicon doped with a lower concentration of impurities (acceptors) than the substrate 11. The impurity concentration of the i-layer 12 is 1e16 cm -3 or less.

[0050] On the surface layer part of the i-layer 12, a plurality (five in the structure shown in FIGS. 1 and 2) of n + -type semiconductor regions 13 are formed. The n + -type semiconductor regions 13 are formed by diffusing impurities (donors) into the i-layer 12 from its surface and are doped with a higher concentration of impurities than the i-layer 12. The n + -type semiconductor regions 13 are linear, extending linearly in one direction in plan view as shown in FIG. 2, and have substantially no width in the width direction orthogonal to both the length direction and the thickness direction of the low-concentration impurity semiconductor layer. The n + -type semiconductor regions 13 extend linearly beyond one end edge and the other end edge in the longitudinal direction of the light-receiving region LA and extend outward of the light-receiving region LA in the longitudinal direction in plan view. Also, the plurality of n + -type semiconductor regions 13 are arranged side by side with a space in the lateral direction (width direction).

[0051] An insulating film 14 is formed on the i-layer 12 so as to surround the periphery of the light-receiving region LA. The insulating film 14 is not formed in the light-receiving region LA, and the surface of the i-layer 12 is exposed from the insulating film 14 throughout the entire area of the light-receiving region LA. That is, an opening for exposing the surface of the i-layer 12 is formed in the insulating film 14, and the light-receiving region LA is defined by the opening. The insulating film 14 is made of an insulating material such as silicon dioxide (SiO2) or silicon nitride (Si3N4).

[0052] An anti-reflective film 15 is formed in the light-receiving region LA so as to cover the surface of the i-layer 12. The anti-reflective film 15 is made of a dielectric material having a refractive index between that of silicon and that of air, such as silicon nitride (Si3N4) or magnesium fluoride (MgF2).

[0053] On the insulating film 14, electrodes 16 made of a metal or non-metallic conductive material are formed outside the light-receiving region LA in a plan view and on one side in the longitudinal direction relative to the light-receiving region LA. The electrodes 16 consist of multiple n + It extends linearly in the lateral direction, spanning the semiconductor region 13. Each n + A contact hole (not shown) is formed in the insulating film 14 in the thickness direction at the portion where the semiconductor region 13 and the electrode 16 face each other in the thickness direction perpendicular to both the vertical and transverse directions. The contact hole is filled with the material of the electrode 16, and the electrode 16 passes through the contact hole to each n + It is connected to the semiconductor region 13.

[0054] Furthermore, electrodes 17 made of metal or a non-metallic conductive material are formed on the back surface of the substrate 11.

[0055] In the PIN photodiode 1, electrode 16 acts as the cathode and electrode 17 acts as the anode. To apply a reverse bias to the PIN photodiode 1, electrode 16 (cathode) is connected to a high potential and electrode 17 (anode) is connected to a low potential. The PIN photodiode 1 is also connected to an amplification circuit. The amplification circuit is, for example, a transimpedance amplifier (TIA), and electrode 17 (anode) is connected to the input terminal of the transimpedance amplifier by wiring.

[0056] When a reverse bias is applied to the PIN photodiode 1, n +A depletion layer extends from the junction between the semiconductor region 13 and the i-layer 12 into the i-layer 12. When light is shone on the light-receiving region LA, electrons in the valence band are excited to the conduction band, and holes remain in the valence band, thereby generating carriers (electrons, holes) mainly in the i-layer 12. Then, electrons n + As the holes move to the neutral region of the semiconductor region 13 and then to the neutral region of the substrate 11, current is input from the electrode 16 (cathode) to the input terminal of the transimpedance amplifier. This causes current to flow through the feedback resistor of the transimpedance amplifier, and this current is converted into a voltage, which is then output from the transimpedance amplifier.

[0057] <Effects> As described above, in the PIN photodiode 1, multiple linear n are present on the surface of the i-layer 12. + The semiconductor regions 13 are formed by arranging them side by side with a gap between them laterally. The inter-terminal capacitance of the PIN photodiode 1 is the sum of the package capacitance and the junction capacitance, and the junction capacitance is the i-layer 12 and n-layer 12. + It depends on the area (junction area) where the semiconductor region 13 is joined. In conventional PIN photodiodes, as shown in Figure 20, n + The type region 103 is formed as a wide-area planar structure. In contrast, in the PIN photodiode 1, n + Since the semiconductor region 13 is formed in a linear shape, the junction capacitance can be reduced compared to conventional PIN photodiodes, and consequently, the inter-terminal capacitance can be reduced. As a result, the response speed of the PIN photodiode 1 can be improved.

[0058] Let's compare the conventional PIN photodiode (see Figure 20) with PIN photodiode 1 using specific numerical examples. The light-receiving area of ​​the conventional PIN photodiode is 1 mm × 1 mm, and n + Bonding depth of mold region 103 (n relative to the surface of layer i 102) + The dimension of the mold region 103 in the thickness direction is 0.4 μm, and the i layer 102 and n + The bonding area with the mold region 103 is approximately 1 mm². 2Assume that in PIN photodiode 1, when the size of the light-receiving region LA is the same as the size of the light-receiving region of a conventional PIN photodiode, n + The junction depth of the semiconductor region 13 is 0.4 μm, and the n in the photodetector region LA + The line width (horizontal length) of the semiconductor region 13 is set to 0.4 μm, and n in the photoreceiving region LA + The line length (length in the vertical direction) of the semiconductor region 13 is set to 1 mm, and adjacent n + By setting the spacing of the semiconductor regions 13 (hereinafter referred to as "line spacing") to 30 μm, the i-layer 12 and n + The junction area with the semiconductor region 13 is approximately 1 / 25 of the junction area of ​​a conventional PIN photodiode. As a result, the junction capacitance of the PIN photodiode 1 is approximately 1 / 25 of that of a conventional PIN photodiode, and the terminal capacitance of the PIN photodiode 1 can be made smaller than that of a conventional PIN photodiode. A PIN photodiode 1 with this design can be manufactured using the 0.25 μm process rule that has been widely used for some time.

[0059] n + The line width of the semiconductor region 13 is constrained by the process rule (process node) used in the manufacture of the PIN photodiode 1. For example, if a 0.6 μm process rule is used in the manufacture of the PIN photodiode 1, n + The minimum line width of the semiconductor region 13 is approximately 1 μm, and when a 0.25 μm process rule is used to manufacture the PIN photodiode 1, n + The minimum line width of the semiconductor region 13 is thought to be around 0.4 μm, but by using an even finer process rule in the manufacture of the PIN photodiode 1, n + The line width of the semiconductor region 13 can be further reduced, making it possible to further reduce the junction capacitance.

[0060] When PIN photodiode 1 is used for optical communication, n +The linewidth of the type semiconductor region 13 may be set considering the communication speed of optical communication. For example, the material of the i-layer 12 is not limited to silicon, but a compound semiconductor such as gallium arsenide (GaAs) may be used, and when the i-layer 12 is made of a compound semiconductor, it is assumed that an optical signal of 40 Gbps or more will be received by the PIN photodiode 1. Under this assumption, n + Considering the lateral movement speed of fractional carriers in the semiconductor region 13, n + The line width of the semiconductor region 13 is preferably 2 μm or less, and in order to support the current maximum communication speed of 100 Gbps, n + The line width of the semiconductor region 13 is more preferably 1 μm or less.

[0061] The size of the light-receiving region LA is generally 200 μm square or larger. In a PIN photodiode 1 with a minimum size (200 μm square) light-receiving region LA, n + Even when the PIN photodiode 1 is designed with a junction depth of 0.4 μm, a line width of 2 μm, and a line spacing of 20 μm, the junction area of ​​the PIN photodiode 1 is about 1 / 7 that of a conventional photodiode with the same size light-receiving region, and the junction capacitance is also about 1 / 7. In the PIN photodiode 1 with a 200 μm square light-receiving region LA, the conversion efficiency hardly decreases even if the line spacing is 20 μm or more.

[0062] When layer i12 is made of silicon, assuming reception of near-infrared light with a wavelength of 870 nm or less, and assuming the absorption coefficient α of layer i12 is about 500, if the thickness of layer i12 is 32 μm, more than 80% of the optical signal can be absorbed by layer i12 when receiving an optical signal. When layer i12 is made of a compound semiconductor, assuming reception of light with a wavelength of 850 nm, for example, if the absorption coefficient α is 8000 or more, and the thickness of layer i12 is 2 μm, more than 80% of the optical signal can be absorbed by layer i12 when receiving an optical signal. Therefore, the thickness of layer i12 is preferably 2 to 32 μm.

[0063] Furthermore, when light is shone on the light-receiving region LA, holes generated in the i-layer 12 move toward the substrate 11 in the thickness direction. On the other hand, electrons generated in the i-layer 12 move toward the line spacing (n adjacent to each other). + As the spacing of the semiconductor regions 13 increases, n + The amount of movement in the direction perpendicular to the thickness direction toward the semiconductor region 13 becomes large, and depending on the line spacing, the amount of movement in the direction perpendicular to the thickness direction becomes larger than the amount of electron movement in the thickness direction.

[0064] Therefore, by changing the line spacing, the electrons generated by light irradiation are n + The average arrival time to reach the semiconductor region 13 can be adjusted, and the conversion efficiency of the PIN photodiode 1 can also be adjusted. + The line width of the semiconductor region 13 is sufficiently small, which allows for highly precise adjustment of the conversion efficiency of the PIN photodiode 1.

[0065] Furthermore, by changing the line spacing, the rise time waveform of the photocurrent generated by light irradiation can also be adjusted. The mobility of electrons in a semiconductor is greater than the mobility of holes (for example, the electron mobility in a single-crystal silicon substrate is 1500 cm²). 2 While / Vs is the case, the mobility of the hole is 450 cm. 2 / Vs.) Therefore, by increasing the line spacing and bringing the electron migration time closer to the hole migration time, the rising and falling waveforms of the photocurrent can be smoothed. n relative to the line spacing + Because the linewidth of the semiconductor region 13 is sufficiently small, high-precision control of the rising and falling waveforms of the photocurrent is possible.

[0066] Furthermore, if there is an undepleted region remaining in a part of layer i12, minority carriers will be generated by photoelectric conversion in that undepleted region as well (majority carrier holes will not be generated effectively), and these minority carriers will move through the undepleted region. Even in this case, if the line spacing is sufficiently large relative to the average depth reached by the light incident on layer i12, electrons will move n + The average time to reach the semiconductor region 13 and the conversion efficiency of the PIN photodiode 1 can be adjusted.

[0067] Furthermore, when light with a wavelength that penetrates the i-layer 12 and reaches the substrate 11 is incident on the light-receiving region LA, photoelectric conversion occurs in the substrate 11 as well, generating electrons, which are minority carriers. These minority carriers generated in the substrate 11 contribute to slowing down the response speed of the PIN photodiode 1. Therefore, a blocking layer (a layer that acts as a potential barrier for electrons, which are minority carriers) of the same type (p-type) and higher density than the substrate 11 may be provided between the substrate 11 and the i-layer 12 to improve the response characteristics.

[0068] In the PIN photodiode 1, an electrode 16(n + Since no wiring (connecting the semiconductor regions 13 in parallel) is formed, interference from the electrodes 16 to the light irradiated onto the light-receiving region LA does not occur.

[0069] Furthermore, since no insulating film 14 is formed on the light-receiving region LA, the entire i-layer 12 exposed to the light-receiving region LA can be covered with the anti-reflective film 15.

[0070] In a configuration where the PIN photodiode 1 is connected to a transimpedance amplifier, if the inter-terminal capacitance of the PIN photodiode 1 is small, noise near the cutoff frequency of the transimpedance amplifier can be reduced without increasing the feedback capacitance provided to ensure negative feedback stability in the transimpedance amplifier. Furthermore, since it is not necessary to increase the feedback capacitance of the transimpedance amplifier to reduce noise, the frequency bandwidth of the transimpedance amplifier is not limited, and a wider bandwidth of the transimpedance amplifier can be achieved.

[0071] <Shield structure 1> Figure 3 is a schematic cross-sectional view illustrating the structure of the PIN photodiode 21 with a shielding structure, and Figure 4 is a plan view thereof. In Figures 3 and 4, the parts corresponding to the parts shown in Figures 1 and 2 are given the same reference numerals as those parts. The following explanation of the parts with the same reference numerals will be omitted.

[0072] The PIN photodiode 21 is fabricated on a substrate 11, along with other semiconductor elements such as a CMOS (Complementary Metal Oxide Semiconductor) transistor. Therefore, interlayer films 22 and 23, which are part of the multilayer wiring structure for other semiconductor elements, are stacked on the i-layer 12 in this order from the i-layer 12 side, and the interlayer films 22 and 23 remain on the i-layer 12 within the light-receiving region LA without being removed. The interlayer films 22 and 23 are made of insulating materials such as silicon dioxide or silicon nitride.

[0073] On the interlayer membrane 23, each n + Corresponding to the type semiconductor region 13, a first conductive layer 24 made of a metal or a non-metallic conductive material (for example, polysilicon) is formed. The first conductive layer 24 is n + It is provided above the semiconductor region 13, extends in the vertical direction, and n +The entire semiconductor region 13 is opposite in the thickness direction. Outside the light-receiving region LA, for example, another interlayer film is further stacked on the interlayer film 23, and wiring for a fixed potential, such as ground potential or power supply potential, is provided on the other interlayer film. The first conductive layer 24 is connected to the fixed potential by being connected to the wiring via vias that penetrate the other interlayer film in the thickness direction.

[0074] This configuration allows electromagnetic noise to be introduced from the outside. + Even if electromagnetic noise enters the semiconductor region 13, it is blocked by the first conductive layer 24. Therefore, external electromagnetic noise is blocked. + This prevents the semiconductor region 13 from being reached, thus eliminating adverse effects from electromagnetic noise.

[0075] In the PIN photodiode 21, the first conductive layer 24 is located below it. + Although the entire semiconductor region 13 is said to be opposite in the thickness direction, the first conductive layer 24 is below it in n + If at least a portion of the semiconductor region 13 is facing the first conductive layer 24 in the thickness direction, some degree of electromagnetic noise shielding effect from the first conductive layer 24 will be exerted.

[0076] Although the first conductive layer 24 is assumed to be connected to a fixed-potential wiring outside the light-receiving region LA, the first conductive layer 24 may also be connected to a fixed-potential wiring inside the light-receiving region LA. Alternatively, a semiconductor region containing a high concentration of impurities may be formed on the surface of layer i 12, and the first conductive layer 24 may be connected to a fixed potential via this semiconductor region.

[0077] Furthermore, the first conductive layer 24 may be divided into two vertical sections, with these sections spaced apart vertically (creating a gap between the two sections), and each section connected to a fixed potential outside the light-receiving region LA. Not limited to two sections, the first conductive layer 24 may be divided into three or more vertical sections, with these sections spaced apart vertically, and each section connected to a fixed potential outside or inside the light-receiving region LA. In other words, regardless of whether the first conductive layer 24 is divided into multiple vertical sections, the method of connection is not limited as long as the first conductive layer 24 can be connected to a fixed potential.

[0078] <Shield structure 2> Figure 5 is a schematic cross-sectional view illustrating the structure of the PIN photodiode 31 with other shielding structures, and Figure 6 is a plan view thereof. In Figures 5 and 6, the parts corresponding to the parts shown in Figures 3 and 4, respectively, are given the same reference numerals as those parts. The following explanation of the parts with the same reference numerals will be omitted.

[0079] The PIN photodiode 31, like the PIN photodiode 21, is fabricated on the substrate 11 along with other semiconductor elements. In the PIN photodiode 31, an interlayer film 22 is formed on the i-layer 12 within the light-receiving region LA.

[0080] On the interlayer membrane 22, each n + Multiple second conductive layers 32 are formed corresponding to the type semiconductor region 13. The multiple second conductive layers 32 are n + They are provided above the semiconductor region 13, and are spaced apart from each other in the lateral direction and extending in the vertical direction, n + The semiconductor region 13 is opposed to each other in the thickness direction by different parts. In the structure shown in Figures 5 and 6, the two second conductive layers 32 are each n + Two second conductive layers 32 are provided above the type semiconductor region 13, and each of them is n +The second conductive layer 32 is located opposite one lateral end and the other lateral end of the semiconductor region 13 in the thickness direction along its entire length in the longitudinal direction. The second conductive layer 32 is made of a metal or a non-metallic conductive material (for example, polysilicon). Outside the light-receiving region LA, for example, another interlayer film is further laminated on the interlayer film 22, and wiring for a fixed potential, such as ground potential or power potential, is provided on the other interlayer film. The second conductive layer 32 is connected to the fixed potential by being connected to the wiring via vias that penetrate the interlayer film in the thickness direction.

[0081] In this configuration as well, electromagnetic noise from the outside n + When electromagnetic noise enters the semiconductor region 13, it is blocked by the second conductive layer 32. Therefore, external electromagnetic noise is blocked. + This prevents the semiconductor region 13 from being reached, thus eliminating adverse effects from electromagnetic noise.

[0082] Although it has been stated that the second conductive layer 32 is connected to a fixed-potential wiring outside the light-receiving region LA, the second conductive layer 32 may also be connected to a fixed-potential wiring inside the light-receiving region LA. Furthermore, a semiconductor region containing a high concentration of impurities may be formed on the surface of layer i 12, and the second conductive layer 32 may be connected to a fixed potential via this semiconductor region.

[0083] Furthermore, the second conductive layer 32 may be divided into two vertical sections, with these sections spaced apart vertically (creating a gap between the two sections), and each section connected to a fixed potential outside the light-receiving region LA. Not limited to two sections, the second conductive layer 32 may be divided into three or more vertical sections, with these sections spaced apart vertically, and each section connected to a fixed potential outside or inside the light-receiving region LA. In other words, regardless of whether the second conductive layer 32 is divided into multiple vertical sections, the method of connection is not limited as long as the second conductive layer 32 can be connected to a fixed potential.

[0084] The second conductive layer 32 is n +Since it faces a portion of the semiconductor region 13 in the thickness direction, it can be said to be an example of the "first conductive layer" of the present invention.

[0085] <Shield structure 3> Figure 7 is a schematic cross-sectional view illustrating the structure of the PIN photodiode 41, which also includes other shielding structures, and Figure 8 is a plan view thereof. In Figures 7 and 8, the parts corresponding to those shown in Figures 3 and 4 are given the same reference numerals. The following explanation of the parts with the same reference numerals will be omitted.

[0086] The PIN photodiode 41, like the PIN photodiode 21, is fabricated on the substrate 11 along with other semiconductor elements. In the PIN photodiode 41, each n is fabricated on the interlayer film 23. + Corresponding to the type semiconductor region 13, a first conductive layer 42 made of a metal or a non-metallic conductive material (for example, polysilicon) is formed. The first conductive layer 42 is n + It is provided above the semiconductor region 13, extends in the vertical direction, and n + It faces the entire semiconductor region 13 in the thickness direction. Also, the first conductive layer 42 is n + The lateral dimensions are larger than those of the semiconductor region 13, and the lateral ends of the first conductive layer 42 are, respectively, n + The i-layer 12 is located on one and the other lateral sides of the semiconductor region 13. The first conductive layer 42 is connected to a fixed potential wiring, such as ground potential or power supply potential, outside the light-receiving region LA.

[0087] Furthermore, vias 43 and 44 made of a metal such as tungsten are formed between one and the other lateral end of the first conductive layer 42 and the i-layer 12, respectively. The vias 43 and 44 penetrate the interlayer films 22 and 23. Also, vias 43 and 44 are n +It extends vertically beyond the vertical length of the semiconductor region 13. The upper ends of vias 43 and 44 are connected to the first conductive layer 42. The lower ends of vias 43 and 44 are connected to the i-layer 12. In the i-layer 12, contact regions 45 and 46 are formed in the areas where vias 43 and 44 are connected, where the acceptor is doped to a higher concentration than the surrounding area. In other words, the surface layer of the i-layer 12 has n + P-type contact regions 45 and 46 are formed on one and the other sides of the lateral semiconductor region 13, respectively, with a higher concentration of acceptor doping than the surrounding area. The contact regions 45 and 46 extend vertically, and the lower ends of vias 43 and 44 are joined to the contact regions 45 and 46, respectively. As a result, vias 43 and 44 make ohmic contact with the i-layer 12.

[0088] This configuration allows electromagnetic noise to be introduced from the outside. + Even if electromagnetic noise penetrates in the thickness direction toward the semiconductor region 13, it is blocked by the first conductive layer 42. Also, electromagnetic noise from the outside n + Even if electromagnetic noise enters the semiconductor region 13 in a direction intersecting the thickness direction, it is blocked by the first conductive layer 42 or vias 43, 44. Therefore, external electromagnetic noise is blocked. + This prevents the semiconductor region 13 from being reached, thus eliminating adverse effects from electromagnetic noise.

[0089] Although it has been stated that the first conductive layer 42 is connected to a fixed-potential wiring outside the light-receiving region LA, the first conductive layer 42 may also be connected to a fixed-potential wiring inside the light-receiving region LA. Furthermore, a semiconductor region containing a high concentration of impurities may be formed on the surface of layer i 12, and the first conductive layer 42 may be connected to a fixed potential via this semiconductor region.

[0090] Furthermore, the first conductive layer 42 may be divided into two vertical sections, with these sections spaced apart vertically (creating a gap between the two sections), and each section connected to a fixed potential outside the light-receiving region LA. Not limited to two sections, the first conductive layer 42 may be divided into three or more vertical sections, with these sections spaced apart vertically, and each section connected to a fixed potential outside or inside the light-receiving region LA. In other words, regardless of whether the first conductive layer 42 is divided into multiple vertical sections, the method of connection is not limited as long as the first conductive layer 42 can be connected to a fixed potential.

[0091] Furthermore, vias 43 and 44 may each be divided into multiple parts in the vertical direction, with these divided parts spaced apart vertically from each other, and gaps created between adjacent divided parts.

[0092] <Shield structure 4> Figure 9 is a schematic cross-sectional view illustrating the structure of the PIN photodiode 51 with other shielding structures, and Figure 10 is a plan view thereof. In Figures 9 and 10, the parts corresponding to those shown in Figures 7 and 8 are given the same reference numerals. The following explanation of the parts with the same reference numerals will be omitted.

[0093] The PIN photodiode 51, like the PIN photodiode 21, is fabricated on the substrate 11 along with other semiconductor elements. In the PIN photodiode 51, each n is fabricated on the interlayer film 22. + Multiple second conductive layers 52 are formed corresponding to the type semiconductor region 13. The multiple second conductive layers 52 are n + The second conductive layer 52 is provided above the type semiconductor region 13, and extends vertically while being spaced apart from each other laterally. + The semiconductor region 13 may or may not face each other in the thickness direction. In the structures shown in Figures 9 and 10, the two second conductive layers 52 are each n + Two second conductive layers 52 are provided above the semiconductor region 13, and n +The semiconductor region 13 is not facing the second conductive layer 52 in the thickness direction. The second conductive layer 52 is made of a metal or a non-metallic conductive material (for example, polysilicon).

[0094] Furthermore, in the PIN photodiode 51, one lateral end and the other lateral end of the first conductive layer 42 on the interlayer film 23 are opposite the second conductive layer 52 in the thickness direction. Vias 53 and 54 made of a metal such as tungsten are formed between the first conductive layer 42 and the second conductive layer 52, respectively. Vias 53 and 54 penetrate the interlayer film 23. The upper ends of vias 53 and 54 are connected to the first conductive layer 42, and their lower ends are connected to the second conductive layer 52. Also, vias 53 and 54 are n + It extends in the vertical direction beyond the vertical length of the semiconductor region 13.

[0095] This configuration allows electromagnetic noise to be introduced from the outside. + Even if electromagnetic noise penetrates in the thickness direction toward the semiconductor region 13, it is blocked by the first conductive layer 42 or the second conductive layer 52. Furthermore, electromagnetic noise from the outside n + Even if electromagnetic noise enters the semiconductor region 13 in a direction intersecting the thickness direction, it is blocked by the first conductive layer 42, the second conductive layer 52, or vias 53, 54. Therefore, external electromagnetic noise is blocked. + This prevents the semiconductor region 13 from being reached, thus eliminating adverse effects from electromagnetic noise.

[0096] Furthermore, vias 53 and 54 may each be divided into multiple parts in the vertical direction, with these divided parts spaced apart vertically from each other, and gaps may be created between adjacent divided parts.

[0097] Furthermore, the first conductive layer 42 may be connected to a fixed potential, or the second conductive layer 52 may be connected to a fixed potential outside or inside the light-receiving region LA.

[0098] <Shield structure 5> FIG. 11 is a cross-sectional view schematically showing the structure of a PIN photodiode 61 having another shield structure, and FIG. 12 is a plan view thereof. In FIGS. 11 and 12, parts corresponding to the respective parts shown in FIGS. 3 and 4 are denoted by the same reference numerals as those parts. Hereinafter, description of the parts denoted by the same reference numerals will be omitted.

[0099] The PIN photodiode 61, like the PIN photodiode 21, is fabricated on a substrate 11 serving as a substrate together with other semiconductor elements. In the PIN photodiode 61, a plurality (six in the structures shown in FIGS. 11 and 12) of p + -type semiconductor regions 62 are formed in the surface layer portion of the i-layer 12. The p + -type semiconductor regions 62 are formed by diffusing an impurity (acceptor) from the surface into the i-layer 12, and are doped with a higher concentration of impurity than the i-layer 12. The p + -type semiconductor regions 62 are spaced laterally from the n + -type semiconductor region 13 and form a strip shape extending linearly in the longitudinal direction. Outside the light receiving region LA, for example, wiring is provided on the interlayer film 22, and a reverse bias is applied between the adjacent n + -type semiconductor regions 13 and the p + -type semiconductor regions 62. The p + -type semiconductor regions 62 are connected to a fixed potential such as a ground potential or a power supply potential via the wiring.

[0100] With this configuration, even if electromagnetic noise enters from the outside toward the n + -type semiconductor region 13, the electromagnetic noise is blocked by the first conductive layer 24. Also, even if electromagnetic noise enters from the outside between the adjacent n + [[ID=z6]]-type semiconductor regions 13, the electromagnetic noise is blocked by the p c + -type semiconductor regions 62. Therefore, it is possible to prevent external electromagnetic noise from reaching the n + -type semiconductor region 13, and the adverse effects of electromagnetic noise can be eliminated.

[0101] Note that the p+ Although the n-type semiconductor region 62 is connected to a fixed potential via wiring outside the light-receiving region LA, p + type semiconductor region 62 may be connected to a fixed potential via wiring inside the light-receiving region LA. Further, an n-type semiconductor region extending in a direction intersecting the longitudinal direction is formed in the surface layer portion of the i-layer 12, and p + type semiconductor region 62 may be connected to a fixed potential via the n-type semiconductor region extending in a direction intersecting the longitudinal direction thereof. + type semiconductor region 62 may be connected to a fixed potential via the n-type semiconductor region extending in a direction intersecting the longitudinal direction thereof. + type semiconductor region 62 may be connected to a fixed potential via the n-type semiconductor region extending in a direction intersecting the longitudinal direction thereof.

[0102] Further, p + type semiconductor region 62 may be divided into two in the longitudinal direction, and the divided portions are separated from each other in the longitudinal direction (a gap is formed between the two divided portions), and each divided portion may be connected to a fixed potential outside the light-receiving region LA. Not limited to two, p + type semiconductor region 62 may be divided into three or more in the longitudinal direction, and the divided portions are separated from each other in the longitudinal direction, and each divided portion may be connected to a fixed potential outside or inside the light-receiving region LA. That is, p + regardless of whether the n-type semiconductor region 62 is divided into a plurality in the longitudinal direction or not, p + as long as the n-type semiconductor region 62 can be connected to a fixed potential, the connection method is not limited.

[0103] <Shield structure 6> FIG. 13 is a cross-sectional view schematically showing the structure of a PIN photodiode 71 provided with another shield structure. In FIG. 13, parts corresponding to the respective parts shown in FIG. 1 are given the same reference numerals as those parts. Hereinafter, the description of the parts given the same reference numerals will be omitted.

[0104] The PIN photodiode 71 and PIN photodiode 41, like the PIN photodiode 21, are fabricated on the substrate 11 along with other semiconductor elements. Therefore, the insulating films 72, 73, and 74 included in the multilayer wiring structure for other semiconductor elements are stacked on the i-layer 12 in this order from the i-layer 12 side, and the insulating films 72, 73, and 74 remain on the i-layer 12 within the light-receiving region LA without being removed. The insulating films 72, 73, and 74 are made of insulating materials such as silicon dioxide or silicon nitride.

[0105] A transparent conductive film 75 is formed on the uppermost insulating film 74. The transparent conductive film 75 is made of a light-transmitting and conductive material, such as indium tin oxide. The transparent conductive film 75 is connected to a fixed potential, such as ground potential or power supply potential, outside the light-receiving region LA.

[0106] This configuration allows electromagnetic noise to be introduced from the outside. + Even if electromagnetic noise enters the semiconductor region 13, it is blocked by the transparent conductive film 75. Therefore, external electromagnetic noise is blocked. + This prevents the semiconductor region 13 from being reached, thus eliminating adverse effects from electromagnetic noise.

[0107] <Surface electrode 1> Figure 14 is a schematic cross-sectional view illustrating the structure of the PIN photodiode 1 in which the electrodes 17 are arranged on the surface.

[0108] In the structure shown in Figure 1, the electrode 17 is formed on the back surface of the substrate 11, but as shown in Figure 14, the electrode 17 may also be formed on the surface of the PIN photodiode 1. In the PIN photodiode 1 shown in Figure 14, impurities (acceptors) are diffused from the surface to the peripheral edge of the surface layer of the i layer 12, +A type of contact region 76 is formed in an annular shape surrounding the light-receiving region LA. In the insulating film 14 surrounding the light-receiving region LA, an annular contact hole is formed in the portion facing the contact region 76, penetrating the insulating film 14 in the thickness direction. The contact hole is filled with the material of the electrode 17, and the electrode 17 is joined to the contact region 76 through the contact hole. As a result, the electrode 17 is in ohmic contact with the i-layer 12.

[0109] The structure shown in Figure 14 is suitable when the PIN photodiode 1 is used in the light receiving device 81 described below. By using the PIN photodiode 1 with the structure shown in Figure 14 in the light receiving device 81, wire bonding is unnecessary, and external wiring such as bonding wires can be eliminated.

[0110] Also, p + Since the contact region 76 is formed in an annular shape surrounding the light-receiving region LA, the spread of the depletion layer in the vertical and horizontal directions from within the light-receiving region LA can be suppressed, and the adverse effects of this depletion layer spread on the surrounding circuitry can be prevented.

[0111] <Surface electrode 2> Figure 15 is a diagrammatic cross-sectional view illustrating another example of a structure in which the electrodes 17 of the PIN photodiode 1 are arranged on the surface, and Figure 16 is a plan view thereof.

[0112] In the configuration shown in Figure 14, p is present at the peripheral edge of the surface layer of layer i 12. + Although it was stated that a type of contact region 76 is formed, in the configuration shown in Figures 15 and 16, it is the surface layer of the i layer 12, and the adjacent linear n + Between the type semiconductor regions 13, p +A contact region 77 of a certain type is formed. The contact region 77 is formed by diffusing impurities (acceptors) from its surface into the i-layer 12, and is doped with a higher concentration of impurities than the substrate 11 and the i-layer 12. Furthermore, the contact region 77 is linear in shape in the vertical direction when viewed from above, extending linearly beyond one and the other vertical edge of the light-receiving region LA to the outside of the light-receiving region LA.

[0113] Furthermore, on the insulating film 14, an electrode 17 made of a metal or non-metallic conductive material is formed outside the light-receiving region LA in a plan view and on the opposite side of the electrode 16 in the longitudinal direction relative to the light-receiving region LA. The electrode 17 extends linearly in the transverse direction so as to span multiple contact regions 77. Contact holes (not shown) are formed in the insulating film 14 in the thickness direction at the portions where each contact region 77 and the electrode 17 face each other in the thickness direction. The contact holes are filled with the material of the electrode 17, and the electrode 17 is joined (ohmic contact) to each contact region 77 through the contact holes.

[0114] The structures shown in Figures 15 and 16, like the structure shown in Figure 14, eliminate the need for external wiring such as bonding wires by using the PIN photodiode 1 in the light receiving device 81 described below.

[0115] <Other Embodiments> Figure 17 is a diagram illustrating the configuration of a light receiving device 81 according to another embodiment of the present invention.

[0116] The light receiving device 81 is an integrated circuit (IC) that integrates a photodiode 82 and an amplification circuit 83. The photodiode 82 is one of the PIN photodiodes 21, 31, 41, 51, 61, or 71, which have a shielded structure. The amplification circuit 83 is, for example, a transimpedance amplifier. In this case, the cathode of the photodiode 82 and the input terminal of the transimpedance amplifier are connected by wiring 84.

[0117] Figure 18 is a cross-sectional view illustrating the cross-section obtained when the light receiving device 81 is cut along the cutting line AA shown in Figure 17.

[0118] The wiring 84 is formed on an interlayer film 85 made of an insulating material. On the interlayer film 85, conductive layers 86 and 87 made of metal or a non-metallic conductive material (for example, polysilicon) are formed, spaced apart on one and the other sides of the wiring 84 in the lateral direction.

[0119] An interlayer film 88 made of an insulating material is formed on the interlayer film 85. A conductive layer 89 is formed on the interlayer film 88. The conductive layer 89 faces the entire wiring 84 in the thickness direction, with the interlayer films 85 and 88 in between. In addition, one end and the other end of the conductive layer 89 in the lateral direction face the conductive layers 86 and 87, respectively, with the interlayer film 88 in between, in the thickness direction.

[0120] Furthermore, vias 91 and 92 made of a metal such as tungsten are formed between one lateral end of the conductive layer 89 and the conductive layer 86, and between the other lateral end of the conductive layer 89 and the conductive layer 87, respectively. The vias 91 and 92 penetrate the interlayer film 88. The upper ends of the vias 91 and 92 are connected to the conductive layer 89. The lower ends of the vias 91 and 92 are connected to the conductive layers 86 and 87, respectively. As a result, the conductive layers 86 and 87 are electrically connected to the conductive layer 89. The conductive layer 89 is connected to a fixed potential such as ground potential or power supply potential.

[0121] In this configuration, the wiring 84 is surrounded from above and on both sides by conductive layers 86, 87, and 89. Therefore, even if electromagnetic noise enters the wiring 84 from the outside, it is blocked by the conductive layers 86, 87, and 89. Because the photodiode 82 has a shielding structure and the wiring 84 (signal line) is shielded by conductive layers 86, 87, and 89, the photodiode 82 to the amplification circuit 83 is seamlessly shielded, thus preventing the light receiving device 81 from being adversely affected by external electromagnetic noise.

[0122] Instead of the configuration shown in Figure 18, the configuration shown in Figure 19 may be adopted. In the configuration shown in Figure 19, the conductive layers 86 and 87 shown in Figure 18 are not formed. Also, a step is created on the surface of the interlayer film 88 due to the step difference between the surface of the interlayer film 85 and the surface (upper surface) of the wiring 84. The conductive layer 89 is formed on the interlayer film 88, utilizing the step on the surface of the interlayer film 88, facing the upper surface of the wiring 84 in the thickness direction and wrapping around both sides of the wiring 84 in the lateral direction.

[0123] As shown in Figure 19, the wiring 84 is surrounded by the conductive layer 89 from above and on both sides in the lateral direction. Therefore, even if electromagnetic noise enters the wiring 84 from the outside, the conductive layer 89 can effectively block the external electromagnetic noise.

[0124] In the configuration shown in Figure 19, the conductive layer 89 may be formed so as not to wrap around to either side of the wiring 84 in the lateral direction. However, it is preferable that measures be taken to prevent external electromagnetic noise from entering the wiring 84 from its sides. Such measures may include, for example, providing a shielding plate to block electromagnetic noise inside the case housing the light receiving device 81.

[0125] <Variation> Although embodiments of the present invention have been described above, the present invention can also be implemented in other forms.

[0126] For example, the i-layer 12 is not limited to P-type silicon doped with a lower concentration of impurities than the substrate 11, but may also be an intrinsic semiconductor (silicon single crystal) that does not contain impurities.

[0127] Furthermore, in the PIN photodiode 51 shown in Figures 9 and 10, vias 53 and 54 may be omitted, and the first conductive layer 42 and the second conductive layer 52 may be connected to a fixed potential outside the light-receiving region LA. In this configuration as well, electromagnetic noise can be introduced from the outside. +When electromagnetic noise enters the semiconductor region 13 in the thickness direction, it can be blocked by the first conductive layer 42 or the second conductive layer 52. Also, when electromagnetic noise enters from the outside n + Even if electromagnetic noise enters the semiconductor region 13 in a direction intersecting the thickness direction, it can be blocked by the first conductive layer 42 or the second conductive layer 52. Therefore, external electromagnetic noise can be blocked. + This prevents the semiconductor region 13 from being reached, thus eliminating adverse effects from electromagnetic noise.

[0128] In the structure shown in Figure 14, the contact region 76 and the electrode 17 are assumed to be formed in an annular shape surrounding the light-receiving region LA. However, the contact region 76 and the electrode 17 may also be formed in a shape that surrounds the light-receiving region LA from three sides, or in an L-shape extending vertically and horizontally outside the light-receiving region LA, or in a band shape extending linearly on both the vertical or horizontal sides relative to the light-receiving region LA, or in a band shape extending linearly vertically or horizontally outside the light-receiving region LA.

[0129] In the above-described embodiment, n + We have considered a configuration in which the semiconductor region 13 is linear in shape, extending in one direction in a plan view. However, n + The semiconductor region 13 is linear, but is not limited to a straight line. For example, it may have a curved or bent shape (arc-shaped, roughly V-shaped), a meandering shape, or a zigzag shape.

[0130] Also, n + At least one semiconductor region 13 is required.

[0131] n + The semiconductor region 13 may be circular in shape, in which case n + The length direction of the semiconductor region 13 is circular n + This is the tangential direction of the semiconductor region 13. And the circular n + There may be one type semiconductor region 13, or multiple circular n +The semiconductor regions 13 may be arranged in a concentric pattern.

[0132] Other, + A configuration in which the semiconductor regions 13 intersect each other may be adopted, for example, multiple n + The semiconductor region 13 may be formed in a lattice or mesh pattern.

[0133] Furthermore, while we have discussed the case where the first conductivity type is p-type and the second conductivity type is n-type, it is also possible for the first conductivity type to be n-type and the second conductivity type to be p-type.

[0134] Furthermore, various design modifications can be made to the aforementioned configuration within the scope of the matters described in the patent claims. [Explanation of symbols]

[0135] 1, 21, 31, 41, 51, 61, 71: PIN photodiode (photoelectric conversion element) 11: Substrate (semiconductor layer) 12: i-layer (low-concentration impurity semiconductor layer) 13:n + Semiconductor region (high-concentration impurity semiconductor region) 22,23: Interlaminar 24,42: First conductive layer 32,52: Second conductive layer 43,44: Beer 53, 54: Beer 62:p + Semiconductor region (semiconductor region for fixed-potential connection) 72, 73, 74: Insulating film 75: Transparent conductive film 77: Contact area (semiconductor area for fixed potential connection) 81: Light receiving device 82: Photodiode (photoelectric conversion element) 83: Amplifier Circuit 84: Wiring 86, 87, 89: Conductive layer

Claims

1. A first-conductivity semiconductor layer, A low-concentration impurity semiconductor layer formed on the aforementioned semiconductor layer, having a lower impurity concentration than the aforementioned semiconductor layer, The region includes a high-concentration impurity semiconductor region formed on the surface of the low-concentration impurity semiconductor layer, having a higher impurity concentration than the low-concentration impurity semiconductor layer and a second conductivity type different from the first conductivity type, The photoelectric conversion element wherein the high-concentration impurity semiconductor region is linear and has substantially no width in the width direction perpendicular to both its length direction and the thickness direction of the low-concentration impurity semiconductor layer.

2. A light-receiving region is set in the low-concentration impurity semiconductor layer to receive light from the outside. The photoelectric conversion element according to claim 1, wherein the width of the high-concentration impurity semiconductor region is set such that the ratio of the width of the high-concentration impurity semiconductor region to the width of the light-receiving region in the width direction is 1% or less.

3. The present invention further includes a first conductive layer formed above the low-concentration impurity semiconductor layer, The photoelectric conversion element according to claim 1, wherein the first conductive layer extends in the length direction opposite to at least a portion of the high-concentration impurity semiconductor region in the thickness direction and is connected to a fixed potential.

4. The present invention further includes a plurality of second conductive layers formed above the low-concentration impurity semiconductor layer, The photoelectric conversion element according to claim 3, wherein the plurality of second conductive layers each extend in the length direction, facing each other in the thickness direction with respect to different portions of the high-concentration impurity semiconductor region, and are connected to the fixed potential.

5. An interlayer film formed between the low-concentration impurity semiconductor layer and the first conductive layer, The present invention further includes two vias that extend in the longitudinal direction and penetrate the interlayer film in the thickness direction, connecting the first conductive layer and the low-concentration impurity semiconductor layer. On the surface of the low-concentration impurity semiconductor layer, a first conductivity type contact region is formed with a higher impurity concentration than the low-concentration impurity semiconductor layer, with a gap between it and the high-concentration impurity semiconductor region in the width direction. The photoelectric conversion element according to claim 3, wherein the two vias are connected to the contact regions on one and the other side in the width direction with respect to the high-concentration impurity semiconductor region, respectively.

6. The present invention further includes a semiconductor region for fixed potential connection of a first conductivity type formed on the surface of the low-concentration impurity semiconductor layer, The photoelectric conversion element according to any one of claims 1 to 5, wherein the semiconductor region for fixed potential connection is provided with a gap in the width direction relative to the high-concentration impurity semiconductor region, extends in the length direction, and is connected to the fixed potential.

7. Photoelectric conversion element, An amplification circuit that amplifies the signal output from the photoelectric conversion element, Wiring connecting the photoelectric conversion element and the amplification circuit, A conductive layer is formed at least above the wiring, facing the entire wiring, and connected to a fixed potential, The aforementioned photoelectric conversion element is A first-conductivity semiconductor layer, A low-concentration impurity semiconductor layer formed on the aforementioned semiconductor layer, having a lower impurity concentration than the aforementioned semiconductor layer, A high-concentration impurity semiconductor region is formed linearly on the surface of the low-concentration impurity semiconductor layer, has a higher impurity concentration than the low-concentration impurity semiconductor layer, and is of a second conductivity type different from the first conductivity type. It includes a first conductive layer formed above the low-concentration impurity semiconductor layer, The high-concentration impurity semiconductor region is linear and has substantially no width in the width direction perpendicular to both its length direction and the thickness direction of the low-concentration impurity semiconductor layer. The first conductive layer extends in the longitudinal direction of the high-concentration impurity semiconductor region, facing at least a portion of the high-concentration impurity semiconductor region and the thickness direction of the low-concentration impurity semiconductor layer, and is connected to a fixed potential, in a light-receiving device.

8. Photoelectric conversion element, An amplification circuit that amplifies the signal output from the photoelectric conversion element, Wiring connecting the photoelectric conversion element and the amplification circuit, A conductive layer is formed at least above the wiring, facing the entire wiring, and connected to a fixed potential, The aforementioned photoelectric conversion element is A first-conductivity semiconductor layer, A low-concentration impurity semiconductor layer formed on the aforementioned semiconductor layer, having a lower impurity concentration than the aforementioned semiconductor layer, A high-concentration impurity semiconductor region is formed linearly on the surface of the low-concentration impurity semiconductor layer, has a higher impurity concentration than the low-concentration impurity semiconductor layer, and is of a second conductivity type different from the first conductivity type. An insulating film formed above the low-concentration impurity semiconductor layer, The insulating film comprises a transparent conductive film formed on the insulating film and connected to a fixed potential, A light-receiving device wherein the high-concentration impurity semiconductor region is linear and has substantially no width in the width direction perpendicular to both its length direction and the thickness direction of the low-concentration impurity semiconductor layer.

9. The light receiving device according to claim 7 or 8, wherein the conductive layer is formed to surround the wiring from above and from the side.

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