FPGA, control program, control method, electronic circuit device

Abstract

We can provide FPGAs, control programs, control methods, and electronic circuit devices that offer improved protection against side-channel attacks on FPGAs and computers equipped with FPGAs. [Solution] The field-programmable gate array (FPGA) 1 of the present invention includes an encryption processing unit 12 that performs encryption processing that processes multiple rounds per clock cycle for predetermined input data, and a pattern changing unit 13 that changes multiple round patterns, each with different target rounds, per clock cycle during the encryption processing.

Description

Technical Field

[0005]

[0001] This invention relates to, for example, an FPGA, a control program, a control method, and an electronic circuit device mounted on an electronic device.

Background Art

[0002] Conventionally proposed computers for information processing include a data storage medium such as a main memory and a system-on-chip that executes a program stored in this main memory, and some of them process various data. For example, as one type of system-on-chip, a CPU and an FPGA (Field Programmable Gate Array) are known.

[0003] In the field related to such computers, encryption technology is used to prevent eavesdropping and tampering of data. For example, as an example of data protection by encryption, data before encryption (plaintext / clear text) is converted (encrypted) into data that cannot be decoded by a third party, and the data converted by encryption (ciphertext) can be returned to the original data (decryption / deciphering) only when having an encryption key.

[0004] The most important thing in protection by encryption is the encryption key. However, in recent years, it has been found that the encryption key can be obtained by side-channel attacks for decrypting encryption. As shown in Patent Document 1, technologies for preventing side-channel attacks on CPUs have been proposed. However, no technology for preventing side-channel attacks specialized for FPGAs has been proposed.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] The present invention has been made in view of the above-mentioned problems, and aims to provide an FPGA, a control program, a control method, and an electronic circuit device that improve the protection performance against side-channel attacks on FPGAs and computers equipped with FPGAs. [Means for solving the problem]

[0007] The present invention is characterized by an FPGA, control program, control method, and electronic circuit device comprising: an encryption processing unit that performs cryptographic processing on predetermined input data, including an active round for processing the input data and a dummy round for not processing the input data; a storage unit that stores a plurality of types of round patterns in which the arrangement of the active round and the dummy round differs from each other; and a pattern setting unit that sets a round pattern to be used from the plurality of types of round patterns when executing the cryptographic processing, wherein the encryption processing unit is configured to pass through a plurality of rounds in one clock and to perform round processing in two or more clocks, and the encryption processing unit has a data processing path that can select whether to construct a path for inputting input data to make it an active round or construct a path for not inputting input data to make it a dummy round for each of the plurality of rounds in each clock, and further comprises a path selection unit that controls the data processing path according to the round pattern set in the pattern setting unit to make each of the plurality of rounds in each clock an active round or a dummy round. [Effects of the Invention]

[0008] The present invention provides an FPGA, a control program, a control method, and an electronic circuit device that offer improved protection against side-channel attacks on FPGAs and computers equipped with FPGAs. [Brief explanation of the drawing]

[0009] [Figure 1] Functional block diagram of the FPGA in one embodiment of the present invention. [Figure 2] A diagram illustrating the round processing flow in one embodiment of the present invention. [Figure 3] A diagram illustrating input data in one embodiment of the present invention. [Figure 4] A flowchart of the cryptographic processing in one embodiment of the present invention. [Figure 5] A diagram illustrating the information processing flow in a modified embodiment of the present invention. [Figure 6A] A diagram illustrating the data processing path in a modified embodiment of the present invention. [Figure 6B] An illustrative diagram showing an example of data processing in a modified embodiment of the present invention. [Figure 6C] An illustrative diagram showing an example of data processing in a modified embodiment of the present invention. [Modes for carrying out the invention]

[0010] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The present invention relates to a field-programmable gate array (FPGA, FPGA module, FPGA device, FPGA apparatus) 1. FPGA 1 is an integrated circuit, a device in which a specific circuit configuration can be defined by program. That is, FPGA 1 has a plurality of functional units depending on the type of information processing to be performed. For example, FPGA 1 has a plurality of programmable logic blocks, a programmable interconnect for connecting these blocks to each other, and input / output blocks.

[0011] The programmable logic blocks of FPGA1 include multiple circuit components such as lookup tables (LUTs), flip-flops, multiplexers, and arithmetic logic units (ALUs). These circuit components allow FPGA1 to construct basic logic circuits such as logic gates, registers, adders, and shifters.

[0012] Furthermore, FPGA1 programs are written using hardware description languages ​​(HDL), allowing for the realization of desired circuit configurations through programming. This programmability enables reconfiguration even after manufacturing, facilitating design changes, optimizations, and rapid adaptation to different applications. Therefore, FPGA1 is highly versatile and widely used in various fields.

[0013] Figure 1 is a functional block diagram of FPGA1 in one embodiment of the present invention. As shown in Figure 1, FPGA1 in this embodiment has an input unit 10, an arithmetic unit 11, an encryption processing unit 12, a pattern setting unit 13, a random number generation unit 14, an invalid data input unit 15, and an output unit 16. Each of the input unit 10, arithmetic unit 11, encryption processing unit 12, pattern setting unit 13, random number generation unit 14, invalid data input unit 15, and output unit 16 is a functional unit defined within FPGA1 by a program and can cooperate with each other. FPGA1 also has an on-chip memory (storage unit) 20.

[0014] The input unit 10 receives data input to FPGA1 via input / output blocks. For example, the input data is data used for information processing performed by FPGA1. The output unit 16 outputs data (output data) output from FPGA1 via input / output blocks. For example, the output data is data (result data) of the information processing performed by FPGA1.

[0015] The arithmetic unit 11 performs calculations on the input data according to the type of information processing configured (set) by the program, and generates intermediate data or final data for the information processing.

[0016] The encryption processing unit 12 performs encryption processing on input data, output data, or various data generated within the FPGA 1. Encryption processing refers to converting data into data that cannot be decoded by a third party in order to prevent eavesdropping and tampering of the data, and converting data that cannot be decoded by a third party back to the original data. The data that cannot be decoded by a third party, which has been converted by encryption processing, can only be restored to the original data when it has an encryption key. Data that has not been encrypted (original data) is called plaintext data or cleartext data, and encrypted data may be called ciphertext (encrypted data). Also, the conversion from plaintext data or cleartext data to encrypted data is sometimes called "encryption", and the conversion from encrypted data back to the original plaintext data or cleartext data is sometimes called "decryption / decryption". Note that the data generated by decryption / decryption may sometimes be called decrypted data.

[0017] The encryption processing unit 12 performs encryption processing using a predetermined encryption algorithm including round processing. The encryption algorithm applicable to the present invention is not particularly limited, but for example, there is a block cipher method (such as AES). Also, the encryption processing unit 12 can support different key lengths (lengths of keys) and encryption modes (CBC, CTR mode, etc.), and is designed to be able to handle flexible encryption requirements.

[0018] The round processing included in the encryption algorithm is the basic repetitive processing applied when encrypting or decrypting data in the encryption algorithm. For example, taking the block cipher method as an example, the round processing is a process of repeatedly applying a series of operations using a key to input data (plaintext data, encrypted data, or intermediate result data) multiple times to generate the final encrypted data or decrypted data. In the block cipher method, block data of a specific bit length is converted over a plurality of rounds. Also, in the block cipher method, the round processing is composed of an initial round (pre-round), a main round, and a final round.

[0019] For example, in each round, a series of steps including SubBytes (Substitute Bytes), ShiftRows (Shift Rows), MixColumns (Mix Columns), and AddRoundKey (Add Round Key) are sequentially executed to convert the input data. SubBytes is an operation of byte substitution and is non-linearly substituted. ShiftRows is an operation of circularly shifting the bytes in each row of the state array by a certain amount. MixColumns is an operation of applying a linear transformation to each column. AddRoundKey is an operation of performing a bitwise exclusive OR (XOR) using the generated round key.

[0020] Each round in the block cipher mode is usually sequentially executed based on a clock signal. Specifically, each round includes a series of steps such as SubBytes, ShiftRows, MixColumns, and AddRoundKey as described above, and the timing of the start and end of the round is controlled by the clock signal.

[0021] In addition, the encryption processing unit 12 is provided with flip-flops (storage elements) for temporarily holding the output data of each round. Further, the storage unit 20 of the FPGA1 stores a plurality of types of round processing patterns (round patterns). In encryption processing, when executing round processing, one round pattern is set from among a plurality of types of round patterns. For example, the round pattern to be used is set from among four or more types of round patterns.

[0022] FIG. 2 is an illustrative diagram showing a round pattern in an embodiment of the present invention. As shown in FIG. 2, for example, the storage unit 20 stores four types of round patterns (Patterns 1 to 4). The number of types of round patterns stored in the storage unit 20 is not particularly limited, but if there are at least four types, the protection performance is enhanced.

[0023] Conventional cryptographic processing was configured to process one round per clock cycle. However, FPGA1 of the present invention is configured to process multiple rounds per clock cycle by passing through multiple round processing units. The round pattern of the present invention has a predetermined number of rounds (total rounds) that are greater than the number of rounds required to process the input data (effective rounds). In the round pattern, rounds other than the effective rounds that process the input data are dummy rounds that do not process the input data. In the example shown in Figure 2, the total number of rounds is 12, the number of effective rounds is 10, and the number of dummy rounds is 2. In this example, three rounds (processing units A to C) are processed per clock cycle, and processing of all rounds (12 rounds) is completed in the fourth clock cycle. The number of effective rounds is set appropriately according to the key length, and the number of dummy rounds is set appropriately according to the number of effective rounds so that the total number of rounds is a multiple of the number of rounds processed in each clock cycle. In the present invention, each of the multiple types of round patterns has a different arrangement of effective rounds and dummy rounds. For example, round patterns such as the first round of the first clock cycle (processing unit A) and the second round of the second clock cycle (processing unit B) being dummy rounds (Pattern 1 in the upper left of Figure 2), and patterns where the third round of the third and fourth clock cycles (processing unit C) are dummy rounds (Pattern 2 in the upper right of Figure 2) are stored in the storage unit 20. The four types of round patterns are set to differ in at least one aspect, such as the arrangement of rounds or the number of valid rounds processed in each clock cycle (clock cycles 1 to 4 in the above example). The round pattern data stored in the storage unit 20 includes data on the total number of rounds, the number of clock cycles required, the number of rounds in each clock cycle, and data indicating the arrangement of valid rounds and dummy rounds.

[0024] The pattern setting unit 13 has the function of setting (selecting) the round pattern to be used from among multiple round patterns when executing cryptographic processing. Therefore, in the FPGA1 of the present invention, the arrangement of valid rounds and dummy rounds is set for each cryptographic process.

[0025] The random number generation unit 14 has the function of generating random numbers (SEL) for determining the round pattern used by the pattern setting unit 13.

[0026] Furthermore, the pattern setting unit 13 is configured to set the round pattern to be used based on the random numbers generated by the random number generation unit 14. Therefore, the pattern setting unit 13 sets the round pattern based on the generated random numbers.

[0027] The invalid data input unit 15 inputs invalid data to the encryption processing unit 12 when there is no data to input to the encryption processing unit 12. Figure 3 is a diagram illustrating the input data in one embodiment of the present invention. In Figure 3, the shaded data is valid data (the data originally input), and the white data is invalid data (the data input by the invalid data input unit 15). As shown in Figure 3, the invalid data input unit 15 inputs invalid data before and after the valid data (the parts where no data exists). That is, the input data includes both valid data and invalid data, which are input to the encryption processing unit 12, and both the valid data and invalid data are encrypted in the valid round. The output data also includes both valid data and invalid data. That is, both the valid data and invalid data are input to the flip-flop in the encryption processing unit 12.

[0028] The above-described configuration of FPGA1 is merely an example and is not limited to it. Although only the functional parts related to the present invention have been described, FPGA1 can be equipped with other necessary functions depending on the application.

[0029] The following describes an example of the operation of cryptographic processing performed on FPGA1. Cryptographic processing is the process performed on FPGA1 when encrypted data is input to FPGA1, when encrypted data is output, when data that needs to be encrypted is processed within FPGA1, or when encrypted data is decrypted.

[0030] Figure 4 is a flowchart of the cryptographic processing in one embodiment of the present invention. As shown in Figure 4, the pattern setting unit 13 sets a round pattern based on the random number generated in the previous step S1 (step S2), and the cryptographic processing unit 12 executes round processing using the round pattern set in the previous step S2 (step S3).

[0031] Next, a decision is made to terminate the encryption process (step S4). Here, it is determined whether the number of rounds executed since the start of the encryption process (number of completed rounds) has reached the number corresponding to the total number of rounds (number of final rounds). Specifically, if the number of completed rounds is less than the number of final rounds, it is decided not to terminate the encryption process; if the number of completed rounds is equal to the number of final rounds, it is decided to terminate the encryption process.

[0032] If it is determined not to terminate the encryption process (Step S4: NO), the process returns to Step S2. On the other hand, if it is determined to terminate the encryption process (Step S4: YES), the encryption result data is generated (Step S5), and the encryption process is terminated. The encryption result data may be output to the outside of FPGA1 as output data as needed, or it may be used as intermediate result data for information processing performed by FPGA1.

[0033] Here, one attack method against encryption technology is the side-channel attack. A side-channel attack is an attack method that illegally obtains confidential information related to encryption (for example, encryption keys) by utilizing externally observable information that is leaked when a device performing encryption processing physically processes the data. Unlike conventional decryption methods, side-channel attacks exploit design flaws or physical characteristics of the system. Externally observable information includes, for example, electromagnetic fields near ICs, common-mode currents in cables, radiation fields from cables and enclosures, switching currents, and information related to electromagnetic waves and power, such as power supply voltage fluctuations. Specific examples of side-channel attacks include power analysis attacks and electromagnetic wave analysis attacks, which utilize the above-mentioned externally observable information. A power analysis attack is an attack method that obtains confidential information by monitoring fluctuations in the power consumption of a device and analyzing its patterns. Techniques such as simple power analysis (SPA) and differential power analysis (DPA) exist, each extracting information in a different way. An electromagnetic wave analysis attack is an attack method that measures electromagnetic waves emitted from a device and infers confidential information from changes in its waveform and intensity. In particular, in side-channel attacks as described above, noise generated at the time data is input to the flip-flop and noise generated at the time of round transitions are often observed. These noises are known to change depending on the Hamming distance (amount of data transition) and Hamming weight (number of bits that are "1" in the bit sequence, input value).

[0034] According to the FPGA1 of the present invention, in cryptographic processing that processes multiple rounds per clock cycle for predetermined input data, one round pattern is set from among multiple round patterns in which the arrangement of valid rounds and dummy rounds differs from one another. Therefore, since the arrangement of valid rounds and dummy rounds is not constant each time cryptographic processing is performed, the Hamming distance and Hamming weight can be disrupted, thereby increasing the resilience to side-channel attacks on FPGA1 and the computer equipped with FPGA1, and improving protection performance. In particular, against side-channel attacks, by irregularly changing the physical operation through changes in the round pattern, it is possible to make it difficult or impossible to decipher the original data from data obtained by physically observing it.

[0035] Furthermore, according to the present invention, if there is no input data (valid data) to be input to the cryptographic processing unit 12, invalid data is input to the cryptographic processing unit 12. Therefore, in addition to the data necessary for processing, noise is generated by the invalid data (noise when flip-flops are input, noise when rounds are switched). As a result, noise is generated not only when processing input data but also when processing invalid data, which can disrupt the Hamming distance and Hamming weight, thereby improving protection against side-channel attacks. In addition, if only valid data is input, there is a problem that the noise component increases only during cryptographic processing, making it easier to pinpoint the timing during cryptographic processing. However, according to the present invention, by inputting invalid data, it is possible to expect the effect of making it difficult to pinpoint the timing of the encryption processing.

[0036] Furthermore, according to the present invention, since the round pattern to be used is selected from four or more types of round patterns, the risk of key information being deciphered can be reduced and the protection performance against side-channel attacks can be improved.

[0037] Furthermore, according to the present invention, the data to be input when invalid is set based on the random number generated by the random number generation unit 14. As a result, irregular changes in Hamming distance and Hamming weight occur every clock cycle according to the random number, which can disrupt noise, reduce the risk of key information being deciphered, and improve protection against side-channel attacks.

[0038] In this invention, FPGA corresponds to FPGA1, and similarly, the arithmetic unit corresponds to arithmetic unit 11, the cryptographic processing unit corresponds to cryptographic processing unit 12, the pattern modification unit corresponds to pattern setting unit 13, the invalid data input unit corresponds to invalid data input unit 15, and the random number generation unit corresponds to random number generation unit 14. However, this invention is not limited to this embodiment and can take various other forms. Furthermore, the specific configurations and other details listed in the above-described embodiments are merely examples and can be appropriately modified according to the actual product.

[0039] Figure 5 is a diagram illustrating the flow of information processing in a modified embodiment of the present invention. For example, as shown in Figure 5, when performing information processing based on data stored in an external device (such as a server) 2, unencrypted data can be used only within FPGA 1 (unencrypted data area A). In this case, in a system including FPGA 1 and external device 2, data existing outside of FPGA 1 is always encrypted. Conventionally, there has been a technology to perform processing of data stored in external device 2 using FPGA, but the encryption processing was handled by the CPU, and there was no data protection between the CPU and FPGA. In contrast, in the present invention, since the calculations related to encryption processing and information processing are completed within FPGA 1, the protection performance can be improved. In particular, there is the advantage of high resistance to side-channel attacks.

[0040] Furthermore, the present invention can be provided not only as an FPGA1, but also as a control program for operating each functional part of the FPGA1, a control method for the FPGA1, and an electronic circuit device equipped with the FPGA1.

[0041] The data processing path in the cryptographic processing unit 12 of the present invention can be configured as shown in Figure 6A. As shown in Figure 6A, the cryptographic processing unit 12 has a data processing path 120 that can select whether to construct a path to input input data for each of the multiple rounds in each clock cycle to make it an effective round, or construct a path that does not input input data to make it a dummy round. Specifically, for the rounds from when the input data is input until the flip-flop (processing units A to C in this embodiment), there is an input data input path for inputting the input data into each round, and an input data bypass path that directs the input data to the next round or flip-flop without going through each round, and switches are placed at the branching points of these paths. In addition, the data processing path 120 is provided with a random number input path for inputting random numbers generated by the random number generation unit 14 into each round, and a random number bypass path that directs the random numbers to the next round or flip-flop without going through each round, and switches are placed at the branching points of these paths. The control of the switches is performed by the cryptographic processing unit 12 according to the round pattern. Figure 6B shows the processing during the first clock cycle when pattern 1 is set, and Figure 6C shows the processing during the second clock cycle when pattern 1 is set. In Figures 6B and 6C, the paths shown by solid lines are the enabled paths (selected paths), and the paths shown by dotted lines are the disabled paths (unselected paths). As shown in Figure 6B, in the first clock cycle, the input data is bypassed without inputting it to processing A, the input data is input to processing B and processing C, and a random number is input to processing A. That is, in the first clock cycle, processing A is a dummy round, and processing B and processing C are enabled rounds. Also, as shown in Figure 6C, in the second clock cycle, after inputting the data to processing A, the input data is bypassed without inputting it to processing B, the input data is input to processing C, and a random number is input to processing B. That is, in the second clock cycle, processing B is a dummy round, and processing A and processing C are enabled rounds. In this way, cryptographic processing according to the round pattern can be performed.In this way, a dummy round can be implemented from the first round in each clock cycle, preventing specific processes from occurring at fixed timings and thus increasing resistance to side-channel attacks. Furthermore, by inputting random numbers into the dummy round, dummy operations can be executed, disrupting the Hamming distance and Hamming weights, and preventing information leakage that occurs during operations within the processing unit (such as SubBytes). [Industrial applicability]

[0042] The present invention can be used in various industries related to FPGAs and electronic devices equipped with FPGAs. [Explanation of Symbols]

[0043] 1…FPGA 10...Input section 11...Arithmetic section 12…Cryptographic Processing Unit 13...Pattern setting section 14...Random number generation unit 15...Invalid data input section 16…Output section 20...Storage section

Claims

1. An encryption processing unit that performs cryptographic processing on predetermined input data, including multiple rounds such as an active round for processing the input data and a dummy round for processing the input data, A storage unit that stores multiple types of round patterns in which the arrangement of the effective rounds and the dummy rounds are different from each other, The system includes a pattern setting unit that sets the round pattern to be used from among the multiple types of round patterns when executing the aforementioned cryptographic processing, The encryption processing unit is configured to pass through multiple rounds in one clock cycle and to perform round processing in two or more clock cycles. The encryption processing unit has a data processing path that allows it to select whether to construct a path for inputting data to make each of the multiple rounds in each clock cycle an effective round, or to construct a path for not inputting data to make it a dummy round. The system further includes a path selection unit that controls the data processing path according to the round pattern set in the pattern setting unit, so that each of the multiple rounds in each clock cycle is either an active round or a dummy round. FPGA.

2. It further includes a random number generation unit that generates random numbers, The pattern setting unit is configured to set the round pattern to be used based on the random numbers generated by the random number generation unit. The FPGA according to claim 1.

3. The random number generation unit inputs random numbers into the dummy round. The FPGA according to claim 2.

4. The FPGA comprises an encryption processing unit that performs cryptographic processing on predetermined input data, including multiple rounds that process the input data and dummy rounds that do not process the input data; a storage unit that stores multiple types of round patterns in which the arrangement of the effective rounds and dummy rounds differs from each other; and a pattern setting unit that sets the round pattern to be used from among the multiple types of round patterns when executing the cryptographic processing, wherein the encryption processing unit is configured to pass through multiple rounds in one clock cycle and perform round processing in two or more clock cycles, and for each of the multiple rounds in each clock cycle, it has a data processing path that can select whether to construct a path to input input data to make it an effective round, or construct a path not to input input data to make it a dummy round. In accordance with the round pattern set in the pattern setting unit, the data processing path is controlled and the path selection unit functions to make each of the multiple rounds in each clock either an active round or a dummy round. Control program.

5. An FPGA control method comprising: an encryption processing unit that performs cryptographic processing on predetermined input data, including an active round that processes the input data and a dummy round that does not process the input data; a storage unit that stores multiple types of round patterns in which the active round and the dummy round are arranged differently from each other; and a pattern setting unit that sets the round pattern to be used from among the multiple types of round patterns when executing the cryptographic processing, wherein the encryption processing unit is configured to pass through multiple rounds in one clock cycle and perform round processing in two or more clock cycles, and has a data processing path that can control whether to construct a path to input input data for each of the multiple rounds in each clock cycle to make it an active round, or to construct a path not to input input data to make it a dummy round, According to the round pattern set in the pattern setting unit, the data processing path is controlled to make each of the multiple rounds in each clock cycle either an active round or a dummy round. Control method.

6. The FPGA according to claim 1, The FPGA is equipped with a memory capable of communication. Electronic circuit equipment.

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