Indication device

Abstract

To provide a display device that can achieve improved reliability and reduced power consumption. [Solution] The display device comprises a substrate, a transistor arranged in each of a plurality of subpixels located in a display area on the substrate, the transistor including an active layer having a channel region and first and second source-drain regions on both sides of the channel region, and a gate electrode overlapping the active layer, an outer metal layer located between the active layer and the substrate and overlapping the active layer, and an inner metal layer located between the active layer and the outer metal layer and overlapping the active layer and the outer metal layer, wherein the plurality of subpixels include a first subpixel and a second subpixel that emit different colors from each other, the width of the non-overlapping region in the first subpixel where the outer metal layer overlaps the active layer and does not overlap the inner metal layer, and the width of the non-overlapping region in the second subpixel where the outer metal layer overlaps the active layer and does not overlap the inner metal layer.

Description

Technical Field

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[0001] The present disclosure relates to a display device.

Background Art

[0002] In display devices that display images on televisions, monitors, smart phones, tablet PCs, notebook computers, etc., various methods and configurations are used.

[0003] The display device includes a display panel having a plurality of light emitting elements or liquid crystals for displaying an image and transistors for controlling the operation of each light emitting element or liquid crystal, and displays the image as intended through the plurality of light emitting elements or liquid crystals.

[0004] The display device includes a plurality of pixels including light emitting elements, and a plurality of driving and switching elements are provided to drive and control the light emitting elements provided in each pixel. The driving and switching elements may be composed of transistors.

[0005] Recently, various research and developments have been conducted to improve the performance and reliability of transistors.

Summary of the Invention

Problems to be Solved by the Invention

[0006] One of the technical problems of the present disclosure is to provide a display device with improved reliability.

[0007] Another technical problem of the present disclosure is to set the S factor and the on-current value to be different according to the light emission characteristics of each sub-pixel.

[0008] Another technical problem of the present disclosure is to improve the image quality displayed by the display panel.

[0009] This disclosure addresses the technical challenge of achieving ESG (Environmental, Social, and Governance) through improved transistor reliability and reduced power consumption. [Means for solving the problem]

[0010] The display device according to this disclosure includes a substrate, a transistor disposed in each of a plurality of subpixels located in a display area on the substrate and including an active layer having a channel region and first and second source-drain regions on both sides of the channel region, and a gate electrode overlapping the active layer, an external metal layer located between the active layer and the substrate and overlapping the active layer, and an internal metal layer located between the active layer and the external metal layer and overlapping the active layer and the external metal layer, wherein the plurality of subpixels include a first subpixel and a second subpixel that emit different colors from each other, and in the first subpixel, the width of the non-overlapping region of the region in which the external metal layer overlaps the active layer but does not overlap the internal metal layer is different from the width of the non-overlapping region of the region in which the external metal layer overlaps the active layer but does not overlap the internal metal layer in the second subpixel.

[0011] In one example of the present disclosure, in each of the first and second subpixels, the entire channel region overlaps with the outer metal layer, the width of the inner metal layer is smaller than the width of the outer metal layer, and one end of the inner metal layer located on the opposite side of the non-overlapping region of the outer metal layer may be located in a portion that overlaps with either the first or second source-drain region.

[0012] In one example of this disclosure, the transistor may be a drive transistor that supplies a drive current to the light-emitting element of each subpixel.

[0013] In one example of the present disclosure, in each of the first and second subpixels, the outer metal layer may be electrically connected to either one of the first or second source-drain regions and either of the gate electrodes, and the inner metal layer may be electrically connected to either one of the first or second source-drain regions and the remaining one of the gate electrodes.

[0014] As an example of the present disclosure, in each of the first and second subpixels, the internal metal layer is electrically connected to either the first or second source / drain region, the external metal layer is electrically connected to the gate electrode, the first subpixel emits green light, the second subpixel emits blue light, and in the first subpixel, the first width of the non-overlapping region of the external metal layer is smaller than the second width of the non-overlapping region of the external metal layer in the second subpixel.

[0015] In one example of the present disclosure, one side of the inner metal layer of the first subpixel overlaps the first source-drain region, the other end of the inner metal layer adjacent to the non-overlapping region of the outer metal layer overlaps the second source-drain region, and in the second subpixel, one side of the inner metal layer overlaps the first source-drain region, and the other end of the inner metal layer adjacent to the non-overlapping region of the outer metal layer may overlap the channel region.

[0016] In one example of the present disclosure, the plurality of subpixels include a third subpixel that emits a different color from the first and second subpixels, and in the third subpixel, the third width of the non-overlapping region that does not overlap with the internal metal layer among the regions in which the external metal layer overlaps with the active layer may be different from the first and second widths.

[0017] In one example of this disclosure, the third subpixel emits red light, and the third width of the non-overlapping region of the outer metal layer in the third subpixel is greater than the first width and less than the second width.

[0018] As an example of the present disclosure, in each of the first and second subpixels, the internal metal layer is electrically connected to the gate electrode, the external metal layer is electrically connected to either the first or second source / drain region, the first subpixel emits green light, the second subpixel emits blue light, and the fourth width of the non-overlapping region of the external metal layer in the first subpixel is greater than the fifth width of the non-overlapping region of the external metal layer in the second subpixel.

[0019] In one example of the present disclosure, one side of the inner metal layer of the first subpixel overlaps the first source-drain region, the other end of the inner metal layer adjacent to the non-overlapping region of the outer metal layer overlaps the channel region, and in the second subpixel, one side of the inner metal layer overlaps the first source-drain region, and the other end of the inner metal layer adjacent to the non-overlapping region of the outer metal layer may overlap the second source-drain region.

[0020] In one example of the present disclosure, the plurality of subpixels include a third subpixel that emits a different color from the first and second subpixels, and the sixth width of the non-overlapping region of the outer metal layer in the third subpixel may differ from the fourth and fifth widths.

[0021] In one example of this disclosure, the third subpixel emits red light, and the sixth width of the non-overlapping region of the outer metal layer in the third subpixel is greater than the fifth width and less than the fourth width.

[0022] A display device according to another example of this specification comprises a substrate, a drive transistor located in each of a plurality of subpixels located in a display area on the substrate, each subpixel including a first active layer having a channel region and first and second source-drain regions on both sides of the channel region, and a first gate electrode overlapping the first active layer, an outer metal layer located between the first active layer and the substrate and overlapping the first active layer, and an inner metal layer located between the first active layer and the outer metal layer and overlapping the first active layer and the outer metal layer, wherein the plurality of subpixels include a first subpixel that emits different colors from each other. A switching transistor may include a second subpixel, wherein in the first subpixel, the width of the non-overlapping region in the region where the outer metal layer overlaps with the first active layer, which does not overlap with the inner metal layer, is different from the width of the non-overlapping region in the region where the outer metal layer overlaps with the first active layer, which does not overlap with the inner metal layer, and each of a plurality of subpixels located in the display area on the substrate, and includes a second active layer, a second gate electrode overlapping with the second active layer, and a lower metal layer located in the same layer as either the inner metal layer or the outer metal layer. The lower metal layer may be connected to the second gate electrode via a gate coupling electrode.

[0023] In one example of this disclosure, the thickness of the lower metal layer may be the same as the thickness of either the inner metal layer or the outer metal layer.

[0024] As an example of the present disclosure, in each of the first and second subpixels, the internal metal layer is electrically connected to either the first or second source / drain region, the external metal layer is electrically connected to the gate electrode, the first subpixel emits green light, the second subpixel emits blue light, and in the first subpixel, the first width of the non-overlapping region of the external metal layer is smaller than the second width of the non-overlapping region of the external metal layer in the second subpixel.

[0025] In an example of the present disclosure, the plurality of sub-pixels includes a third sub-pixel that emits a color different from that of the first and second sub-pixels. In the third sub-pixel, among the regions where the external metal layer overlaps with the first active layer, the third width of the non-overlapping region that does not overlap with the internal metal layer may be different from the first and second widths.

[0026] In an example of the present disclosure, the third sub-pixel emits red light, and in the third sub-pixel, the third width of the non-overlapping region of the external metal layer is larger than the first width and smaller than the second width.

[0027] As an example of the present disclosure, in each of the first and second sub-pixels, the internal metal layer is electrically connected to the gate electrode, the external metal layer is electrically connected to one of the first and second source / drain regions, the first sub-pixel emits green light, the second sub-pixel emits blue light, and in the first sub-pixel, the fourth width of the non-overlapping region of the external metal layer is larger than the fifth width of the non-overlapping region of the external metal layer in the second sub-pixel.

[0028] In an example of the present disclosure, the plurality of sub-pixels includes a third sub-pixel that emits a color different from that of the first and second sub-pixels. In the third sub-pixel, the sixth width of the non-overlapping region of the external metal layer may be different from the fourth and fifth widths.

[0029] In an example of the present disclosure, the third sub-pixel emits red light, and in the third sub-pixel, the sixth width of the non-overlapping region of the external metal layer is larger than the fifth width and smaller than the fourth width.

[0030] In one example of the present disclosure, the present invention relates to a substrate, an active layer located in each of a plurality of subpixels located in a display area on the substrate, having a channel area and first and second source-drain areas on both sides of the channel area, a transistor including a gate electrode overlapping the active layer, an internal metal layer located between the active layer and the substrate and between the active layer and the external metal layer, the internal metal layer overlapping the active layer and the external metal layer includes a first subpixel and a second pixel subpixel that emit different colors from each other, wherein in the first subpixel, the width of the specific gravity chart region overlapping the internal metal layer in the region where the external metal layer overlaps the active layer is different from the width of the specific gravity chart region overlapping the internal metal layer in the second subpixel.

[0031] In one example of the present disclosure, in each of the first and second subpixels, the entire channel region is superimposed on the outer metal layer, the width of the inner metal layer is smaller than the width of the outer metal layer, and one end of the inner metal layer located opposite the non-superimposed region of the outer metal layer may be located in a portion that superimposes on either the first or second source-drain region.

[0032] In one example of this disclosure, the transistor may be a drive transistor that supplies a drive current to the light-emitting element of each subpixel.

[0033] In one example of the present disclosure, in each of the first and second subpixels, the outer metal layer may be electrically connected to either one of the first and second source / drain regions and either one of the gate electrodes, and the inner metal layer may be electrically connected to either one of the first and second source / drain regions and the remaining one of the gate electrodes.

[0034] As an example of this disclosure, in each of the first and second subpixels, the internal metal layer is electrically connected to one of the first and second source / drain regions, the external metal layer is electrically connected to the gate electrode, the first subpixel emits green light, the second subpixel emits blue light, and in the first subpixel, the first width of the specific gravity chart region of the external metal layer is smaller than the second width.

[0035] In one example of the present disclosure, in the first subpixel, one side of the internal metal layer may overlap the first source-drain region, and the other end of the internal metal layer adjacent to the specific gravity chart region of the external metal layer may overlap the second source-drain region. In the second subpixel, one side of the internal metal layer may overlap the first source-drain region, and the other end of the internal metal layer adjacent to the specific gravity chart region of the external metal layer may overlap the channel region.

[0036] In one example of the present disclosure, the plurality of subpixels include a third subpixel that emits a different color from the first and second subpixels, and the third width of the non-overlapping region of the region in the third subpixel where the outer metal layer overlaps with the active layer but does not overlap with the inner metal layer may differ from the first and second widths.

[0037] In one example of this disclosure, the third subpixel emits red light, and the third width of the specific gravity chart region of the outer metal layer in the third subpixel is greater than the first width and less than the second width.

[0038] In one example of the present disclosure, as a second embodiment, in each of the first and second subpixels, the internal metal layer is electrically connected to the gate electrode, the external metal layer is electrically connected to either the first or second source / drain region, the first subpixel emits green light, the second subpixel emits blue light, and the fourth width of the specific gravity chart region of the external metal layer in the first subpixel is greater than the fifth width of the specific gravity chart region of the external metal layer in the second subpixel.

[0039] In one example of the present disclosure, in the first subpixel, one side of the internal metal layer may overlap the first source-drain region, and the other end of the internal metal layer adjacent to the non-overlapping region of the external metal layer may overlap the channel region; in the second subpixel, one side of the internal metal layer may overlap the first source-drain region, and the other end of the internal metal layer adjacent to the non-overlapping region of the external metal layer may overlap the second source-drain region.

[0040] In one example of the present disclosure, the plurality of subpixels include a third subpixel that emits a different color from the first and second subpixels, and the sixth width of the gravity field region of the outer metal layer may differ from the fourth and fifth widths in the third subpixel.

[0041] In one example of this disclosure, the third subpixel emits red light, and the sixth width of the specific gravity chart region of the outer metal layer in the third subpixel is greater than the fifth width and less than the fourth width.

[0042] In one example of the present disclosure, a display device according to another example of the Spec. may include a substrate, a drive transistor having a channel region and a first active layer having first and second source-drain regions on both sides of the channel region and a first gate electrode overlapping the first active layer, a switch transistor having an outer metal layer overlapping the first active layer and an inner metal layer located between the first active layer and the substrate, and a plurality of subpixels having different colors from each other, wherein in the first subpixel, the width of the region where the outer metal layer overlaps the active layer is different from the width of the region where the outer metal layer overlaps the first active layer and the inner metal layer, and a switch transistor having a second gate electrode overlapping the second active layer and a lower metal layer located on the same floor as either the inner metal layer or the outer metal layer.

[0043] As an example of this disclosure, in each of the first and second subpixels, the internal metal layer is electrically connected to one of the first and second source / drain regions, the external metal layer is electrically connected to the gate electrode, the first subpixel emits green light, the second subpixel emits blue light, and in the first subpixel, the first width of the specific gravity chart region of the external metal layer is smaller than the second width.

[0044] In one example of the present disclosure, the plurality of subpixels include a third subpixel that emits a different color from the first and second subpixels, and the third width of the non-overlapping region of the region in which the outer metal layer overlaps with the first active layer in the third subpixel that does not overlap with the inner metal layer may differ from the first and second widths.

[0045] In one example of this disclosure, the third subpixel emits red light, and the third width of the specific gravity chart region of the outer metal layer in the third subpixel is greater than the first width and less than the second width.

[0046] In one example of the present disclosure, in each of the first and second subpixels, the internal metal layer is electrically connected to the gate electrode, the external metal layer is electrically connected to either the first or second source / drain region, the first subpixel emits green light, the second subpixel emits blue light, and the fourth width of the specific gravity chart region of the external metal layer in the first subpixel is greater than the fifth width of the specific gravity chart region of the external metal layer in the second subpixel.

[0047] In one example of the present disclosure, the plurality of subpixels include a third subpixel that emits a different color from the first and second subpixels, and the sixth width of the gravity field region of the outer metal layer may differ from the fourth and fifth widths in the third subpixel.

[0048] In one example of this disclosure, the third subpixel emits red light, and the sixth width of the specific gravity chart region of the outer metal layer in the third subpixel is greater than the fifth width and less than the fourth width. [Effects of the Invention]

[0049] In an example of the present disclosure, a display device can be configured to set different S-factors and on-current values ​​of transistors to match the light emission characteristics of each subpixel by configuring the width of the specific gravity mating region between the internal metal layer and the external metal layer connected to the drive transistor to differ for each subpixel. This can improve the image quality displayed by the display panel.

[0050] The embodiments of this disclosure can constitute an ESG (Environmental Stimulus Generator) without adding any additional configurations, as they include an internal metal layer and an external metal layer connected to a drive transistor, and the image quality of the display device can be improved by changing the width of the specific gravity mating region of the internal and external metal layers. [Brief explanation of the drawing]

[0051] [Figure 1] This figure illustrates an example applicable to the display device of this disclosure. [Figure 2] This figure illustrates an example of a subpixel circuit diagram applicable to the display device of this disclosure. [Figure 3] This figure illustrates an example of a transistor provided in the first subpixel of the display device of the present disclosure. [Figure 4] This figure illustrates an example of a transistor provided in the second subpixel of the display device of the present disclosure. [Figure 5] This figure illustrates an example of a transistor provided in the third subpixel of the display device of the present disclosure. [Figure 6] Figures 3 and 4 illustrate an example of how the first subpixel transistor shown in the diagram is applied to a display device. [Figure 7] This figure illustrates another example of a transistor provided in the first subpixel of the display device of the present disclosure. [Figure 8] This figure illustrates another example of a transistor provided in a second subpixel in the display device of the present disclosure. [Figure 9] This figure illustrates another example of a transistor provided in a third subpixel in the display device of the present disclosure. [Figure 10] This figure illustrates another embodiment of a transistor provided in a third subpixel in the display device of the present disclosure. [Modes for carrying out the invention]

[0052] The following describes an embodiment with reference to the drawings.

[0053] Identical drawing reference numerals refer to the same component. Furthermore, parts of the drawing may be exaggerated for effective explanation of the thickness, proportions, and dimensions of components. The scale of components depicted in the drawing is not limited to the scale shown in the drawing, as it may differ from the actual scale for illustrative purposes.

[0054] In this specification, when a component (or region, layer, part, etc.) is referred to as "on top of," "connected to," or "joined" another component, it means that it may be directly connected to / joined to the other component, or a third component may be positioned between them.

[0055] "and / or" includes all possible combinations of one or more related configurations.

[0056] Terms such as "first," "second," etc., can be used to describe a variety of components, but the components are not limited by these terms. The terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the rights of this embodiment, the first component may be named the second component, and similarly, the second component may be named the first component. A singular expression includes plural expressions unless the context clearly indicates otherwise.

[0057] Terms such as "below," "below," "above," and "upper" are used to describe the relationships between components illustrated in a drawing. These terms are relative concepts and are described in relation to the direction shown in the drawing. For example, unless "immediately" or "directly" is used, one or more different parts may be located between two parts. Spatially relative terms such as "below," "beneath," "lower," "above," and "upper" can be used to easily describe the correlation between one element or component and another, as shown in the drawing. Therefore, for example, "below" and "below" relative to the first component may be in the opposite direction to "above" and "upper" relative to the first component.

[0058] Spatially relative terms must be understood to include not only the directions illustrated in the drawings, but also the different directions of elements in use or operation. For example, if elements illustrated in a drawing are flipped over, an element described as "below" or "beneath" another element may be placed "above" the other element. Therefore, the illustrative term "below" can include both downward and upward directions.

[0059] Terms such as "includes" or "has" are intended to specify the presence of features, numbers, stages, operations, components, parts, or combinations thereof as described in the specification, and should be understood not to preemptively exclude the possibility of the presence or addition of one or more other features, numbers, stages, operations, components, parts, or combinations thereof.

[0060] The features of each of the multiple embodiments described herein can be combined or combined in part or in whole, enabling a variety of technical interdependencies and drives, and each embodiment may be implemented independently of the others, or together in relation to one another.

[0061] The display devices described herein can be examined below through the attached drawings and examples.

[0062] Figure 1 is a diagram illustrating an example of a display device applicable to the present invention, and Figure 2 is a diagram illustrating an example of a circuit diagram of a subpixel SP applicable to the display device of the present invention.

[0063] Referring to Figures 1 and 2, an example of a display device according to this specification includes a display panel 10, which may include a display area AA and a non-display area NA.

[0064] Display area AA may be an area for displaying video. Multiple subpixels SP are arranged in display area AA of the display panel 10, and video can be displayed using multiple subpixels SP. The area where multiple subpixels SP are arranged becomes display area AA, and the area other than display area AA may be a non-display area NA.

[0065] The non-display area NA may be located in the edge region surrounding the display area AA, which displays the image. The non-display area NA may contain at least one drive unit for driving multiple subpixels SP. The drive unit may be a gate-in-panel (GIP).

[0066] The non-display area NA may contain various additional elements for driving subpixels SP within the display area AA.

[0067] At least one of the multiple subpixels SP may include, for example, a first transistor TR1, a second transistor TR2, a capacitor Cst, and a light-emitting element OLED, as shown in Figure 2(a) or Figure 2(b).

[0068] For example, the first transistor TR1 may be a switching transistor, and the second transistor TR2 may be a driving transistor.

[0069] The first electrode (e.g., drain electrode) of the first transistor TR1 is electrically connected to the data line DL, the second electrode (e.g., source electrode) is electrically connected to the first node N1, and the gate electrode of the first transistor TR1 is electrically connected to the gate line GL. The first transistor TR1 can transmit a data signal supplied via the data line DL to the first node N1 in response to a scanning signal supplied via the gate line GL.

[0070] Capacitor Cst is electrically connected to the first node N1 and can be charged by the voltage applied to the first node N1.

[0071] A high-potential drive voltage EVDD is applied to the first electrode (e.g., the drain electrode) of the second transistor TR2, and the second electrode (e.g., the source electrode) is electrically connected to the first electrode (e.g., the anode electrode) of the light-emitting element OLED. The second transistor TR2 can control the amount of drive current flowing to the light-emitting element OLED depending on the voltage applied to its gate electrode.

[0072] The active layer of the first transistor TR1 and / or the second transistor TR2 may contain, but is not limited to, a semiconductor oxide such as IGZO (Indium-Gallium-Zinc-Oxide).

[0073] The light-emitting element OLED outputs light corresponding to the drive current. The light-emitting element OLED can output light corresponding to one of the following colors: red (R), green (G), blue (B), or white (white).

[0074] A light-emitting element OLED may include an anode electrode, a light-emitting layer placed on the anode electrode, and a cathode electrode that supplies a common voltage. The light-emitting layer may be implemented to emit light of the same color for each pixel, such as white light, or it may be implemented to emit different colors for each subpixel SP, such as red (R), green (G), or blue (B) light.

[0075] A light-emitting OLED can be either a front-emitting diode or a back-emitting diode.

[0076] Figure 2(a) shows an example where the second transistor TR2, which is the driving transistor, is directly connected to the light-emitting element OLED. However, the present invention is not limited to this, and as shown in Figure 2(b), the second transistor TR2 can be connected to the light-emitting element OLED via a third transistor TR3, which is a switching transistor.

[0077] Specifically, as shown in Figure 2(b), the third transistor TR3 may be placed between the second transistor and the light-emitting element OLED. The first electrode of the third transistor TR3 may be connected to the second electrode of the second transistor TR2, and the second electrode of the third transistor TR3 may be electrically connected to the first electrode of the light-emitting element OLED. In response to the light-emitting signal applied to the gate electrode of the second transistor TR2, the on / off switching of the drive current applied from the second transistor TR2 to the light-emitting element OLED can be controlled.

[0078] Although not shown in Figures 2(a) and (b), the subpixel SP may further include a compensation circuit to compensate for the threshold voltage of the second transistor TR2, which is the driving transistor. The compensation circuit may include at least one or more transistors connected to the second transistor TR2 and may be provided within the subpixel SP.

[0079] Depending on the configuration of the compensation circuit, the subpixel SP can have various structures such as 3T1C, which includes three transistors and one capacitor Cst, or 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, 7T2C, which include four transistors and two capacitor Csts.

[0080] In Figures 2(a) and (b), each transistor may include an active layer containing a semiconductor material and a gate electrode that controls the on / off state of the channel provided in the active layer.

[0081] In this specification, the second transistor TR2, which is a driving transistor, may comprise multiple metal layers superimposed on the active layer to minimize the influence of external light on the active layer and to improve the S-factor and on-current value of the driving transistor provided in each subpixel SP. Each of these multiple metal layers may be electrically connected to either the first or second source-drain region of the active layer for a stable operating environment of the transistor, or it may be electrically connected to the gate electrode to improve the turn-on characteristics of the transistor. This will be explained in detail with reference to Figure 3 and subsequent figures.

[0082] On the other hand, in the display device of the present invention described in Figures 1 and 2, the multiple subpixels SP provided within the display area AA are formed in a single unit pixel by adding a white subpixel SP in addition to the first subpixel SP1 that emits green G, the second subpixel SP2 that emits blue B, the third subpixel SP3 that emits red R, the subpixel SP2, and the cell SP3.

[0083] For example, multiple subpixels may include red, green, and blue subpixels, in which case the red, green, and blue subpixels may be arranged repeatedly. Alternatively, multiple subpixels may include red, green, blue, and white subpixels, in which case the red, green, blue, and white subpixels may be arranged repeatedly, or the red, green, blue, and white subpixels may be arranged in a quad configuration. For example, red subpixels, blue subpixels, and green subpixels may be arranged sequentially along the row direction, or red subpixels, blue subpixels, green subpixels, and white subpixels may be arranged sequentially along the row direction. However, in embodiments of the present invention, the types of subpixel colors, the types of arrangement, and the order of arrangement are not limited and can be configured in various forms depending on the luminescence characteristics, device lifespan, and device specifications.

[0084] On the other hand, each subpixel may have a different emission area depending on its emission characteristics. For example, a subpixel that emits light of a different color than a blue subpixel may have a different emission area than a blue subpixel. For example, a red subpixel, a blue subpixel, a green subpixel, or a red subpixel, a blue subpixel, a white subpixel, and a green subpixel may each have a different emission area.

[0085] Each unit pixel may realize a desired color coordinate by adjusting the brightness of the light emitted from the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3, and the desired color can be expressed by summing the light emitted from each subpixel.

[0086] The color coordinates and color perception of the subpixel SPs mentioned above can vary depending on the S-factor and on-current value of the transistor that supplies the drive current to the light-emitting element within each subpixel.

[0087] The S-factor (sub-threshold swing) can be determined from the electrical characteristic curve of the drive transistor that generates the drive current and supplies it to the light-emitting OLED, as the reciprocal of the slope of the transition interval when it changes from the off state to the on state.

[0088] The S-factor can be used, for example, as an indicator of the degree of change in the drain-source current Ids with respect to the gate-source voltage Vgs during the transition interval of a drive transistor. Here, the gate-source voltage Vgs is the voltage difference between the gate electrode and the source electrode of the drive transistor, and the drain-source current Ids is the drive current supplied to the light-emitting element OLED. A larger S-factor means that the rate of change of the drain-source current Ids with respect to the gate voltage is smaller during the transition interval, and a smaller S-factor means that the rate of change of the drain-source current Ids with respect to the gate voltage is larger during the transition interval.

[0089] Therefore, when the S-factor is large, the rate of change of the drain-source current Ids with respect to the gate voltage is small, so the change in drain-source current Ids may progress slowly in response to changes in gate voltage, allowing for more stable and finer control of gradation expression. Conversely, when the S-factor is small, the rate of change of the drain-source current Ids with respect to the gate voltage is large, so the change in drain-source current Ids may progress relatively rapidly in response to changes in gate voltage, which can lead to relatively unstable gradation expression.

[0090] Furthermore, an increase in the transistor's on-current can relatively increase the concentration of carriers that move when the transistor is turned on, thereby relatively increasing the drive current and potentially further enhancing the brightness of the light emitted by the corresponding pixel.

[0091] The display device according to the present invention can improve color coordinates and color perception by appropriately adjusting the S-factor and on-current value of the drive transistors provided for each subpixel SP. To this end, the display device according to the present invention can be configured so that the width of the non-overlapping region of a plurality of metal layers connected to the second transistor TR2, which is a drive transistor that supplies drive current to the light-emitting layer, differs for each subpixel SP.

[0092] The widths of the non-overlapping regions of multiple metal layers applied to each subpixel SP in different ways are described below with reference to Figures 3 to 6.

[0093] Figure 3 is a diagram illustrating an example of a transistor provided in the first subpixel SP1 in the display device of the present invention, Figure 4 is a diagram illustrating an example of a transistor provided in the second subpixel SP2 in the display device of the present invention, and Figure 5 is a diagram illustrating an example of a transistor provided in the third subpixel SP3 in the display device of the present invention.

[0094] As shown in Figures 3 to 5, in the present invention, each of the first, second, and third subpixels SP1, SP2, and SP3 contained in a single unit pixel may comprise multiple metal layers LSa and LSb that overlap with the active layer ACT of the transistor.

[0095] The first, second, and third subpixels SP1, SP2, and SP3 may be subpixels that emit different colors. For example, the first subpixel SP1 in Figure 3 may be a subpixel that emits green (G), and the second subpixel SP2 in Figure 4 may be a subpixel that emits blue (B). The third subpixel SP3 in Figure 5 may be a subpixel that emits red (R), and the transistors shown in Figures 3 to 5 may be drive transistors TR2 provided for the first, second, and third subpixels SP1, SP2, and SP3, respectively.

[0096] Each of the drive transistors shown in Figures 3 to 5 may be the second transistor TR2 shown in Figure 2, and can generate a drive current to drive light-emitting elements that emit green (G), blue (B), or red (R) light, which are provided in the first, second, and third subpixels SP1, SP2, and SP3, respectively.

[0097] Although Figures 3 to 5 do not show the circuit board, the circuit board can be placed below the transistor, for example, as shown in Figure 7, which will be discussed later.

[0098] As shown in Figures 3 to 5, each of the first, second, and third subpixels SP1, SP2, and SP3 may comprise a drive transistor TR2 including an active layer ACT, a gate electrode G, and first and second source / drain electrodes SDa and SDb, as well as an external metal layer LSb and an internal metal layer LSa.

[0099] The active layer ACT may comprise a channel region CH and first and second source / drain regions ASDa and ASDb on both sides of the channel region CH.

[0100] The active layer ACT may be formed including an oxide semiconductor material. The oxide semiconductor material included in the active layer ACT may include at least one of the following: IZO(InZnO)-based, IGO(InGaO)-based, ITO(InSnO)-based, IGZO(InGaZnO)-based, IGZTO(InGaZnSnO)-based, GZTO(GaZnSnO)-based, or GZO(GaZnO)O)-based oxide semiconductor materials.

[0101] The channel region CH is located in the region overlapping with the gate electrode G, and the first and second source / drain regions ASDa and ASDb may be located on the outside of the channel region CH on both sides. The first and second source / drain regions ASDa and ASDb may include the first source / drain region ASDa located on one side of the channel region CH and the second source / drain region ASDb located on the other side of the channel region CH.

[0102] The channel region CH has a relatively lower dopant doping concentration than the first and second source / drain regions ASDa and ASDb, and may have electrical conductivity corresponding to the voltage applied to the gate electrode G, forming a channel to which carriers can move depending on the voltage applied to the gate electrode G. In some cases, the channel region CH may maintain the intrinsic properties of the oxide semiconductor material without dopant doping.

[0103] The first and second source / drain regions ASDa and ASDb may have higher dopant concentrations than the channel region CH, and can therefore be conductive regions with high electrical conductivity.

[0104] The gate electrode G may be positioned on the active layer ACT, spaced apart from and overlapping with the active layer ACT. The gate electrode G can control the formation of a channel in the channel region CH of the active layer ACT via the applied voltage.

[0105] The gate electrode G may contain a conductive material, such as metals like aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W).

[0106] The gate insulating film GI is located between the gate electrode G and the active layer ACT and can insulate between the gate electrode G and the active layer ACT. The gate insulating film GI may contain at least one of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiOxNy). For example, silicon oxide (SiO) may contain silicon dioxide (SiO2).

[0107] For example, the gate insulating film GI may consist of a single or multilayer silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiOxNy). For example, the gate insulating film GI may be formed from a single or multilayer inorganic film. For example, a single layer inorganic film may be a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a silicon oxynitride (SiOxNy), and a multilayer inorganic film may consist of at least one of one or more silicon oxide (SiOx) films, one or more silicon nitride (SiNx) films, and one or more silicon oxynitride (SiOxNy) films, however, exemplary embodiments of this disclosure are not limited thereto.

[0108] An interlayer insulating film ILD may be provided on the gate insulating film GI, covering the gate insulating film GI. The interlayer insulating film ILD may extend along the gate insulating film GI. The interlayer insulating film ILD may contain an insulating material such as silicon oxide (SiOx) or silicon oxide nitride (SiOxNy). For example, the interlayer insulating film ILD may consist of a single layer or multiple layers of silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiOxNy). For example, the interlayer insulating film ILD may be formed of a single layer or multiple layers of inorganic film. For example, a single layer inorganic film may be a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a silicon oxynitride (SiOxNy), and a multiple layers of inorganic film may consist of at least one of one or more silicon oxide (SiOx) films, one or more silicon nitride (SiNx) films, and one or more silicon oxynitride (SiOxNy) films. The exemplary embodiments of this disclosure are not limited thereto.

[0109] A planarization film PLN containing an insulating material may be located on the interlayer insulating film ILD. The planarization film PLN can eliminate the step generated by the transistor within the subpixel SP. The upper surface of the planarization film PLN has a flat plane and may contain a material with high fluidity. For example, the planarization film PLN may contain an organic insulating material. For example, the planarization film PLN may be formed from an organic layer such as an acrylic material, epoxy material, phenolic material, polyamide material, or polyimide material, but embodiments of this disclosure are not limited thereto.

[0110] The first and second source / drain electrodes SDa and SDb are located on the planarization film PLN and are electrically connected to the first and second source / drain regions ASDa and ASDb, respectively. The first source / drain electrode SDa is in contact with the first source / drain region ASDa, and the second source / drain electrode SDb is in contact with the second source / drain region ASDb.

[0111] Figures 3 to 5 show an example where the first and second source / drain electrodes SDa and SDb are electrically connected to the first and second source / drain regions ASDa and ASDb by penetrating the planarization film PLN, the interlayer insulating film ILD, and the gate insulating film GI.

[0112] However, the present invention is not necessarily limited thereto, and the first and second source and drain electrodes SDa and SDb may be located on the interlayer insulating film ILD and electrically contact the first and second source and drain regions ASDa and ASDb through the interlayer insulating film ILD and the gate insulating film GI. The first and second source and drain electrodes SDa and SDb are electrically insulated from the gate electrode G by the interlayer insulating film ILD and the gate insulating film GI.

[0113] An internal metal layer LSa and an external metal layer LSb may be provided separately below the active layer ACT, and a buffer layer BUF may be located between the active layer ACT, the internal metal layer LSa, and the external metal layer LSb. The buffer layer BUF may contain inorganic insulating materials such as silicon oxide (SiO) and silicon nitride (SiN), and may have a multilayer structure including first and second buffer layers BUF1 and BUF2.

[0114] For example, each of the first and second buffer layers BUF1 and BUF2 may consist of a single or multilayer silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiOxNy). For example, each of the first and second buffer layers BUF1 and BUF2 may be formed of a single or multilayer inorganic film. For example, a single layer inorganic film may be a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a silicon oxynitride (SiOxNy), and a multilayer inorganic film may consist of at least one of one or more silicon oxide (SiOx) films, one or more silicon nitride (SiNx) films, and one or more silicon oxynitride (SiOxNy) films. The exemplary embodiments of this disclosure are not limited thereto.

[0115] The first buffer layer BUF1 may be located between the internal metal layer LSa and the external metal layer LSb, and the second buffer layer BUF2 may be located between the internal metal layer LSa and the active layer ACT.

[0116] The external metal layer LSb may be placed between the active layer ACT and the substrate (e.g., 100 in Figure 7). For example, as shown in Figures 3 to 5, the external metal layer LSb may be located below the buffer layer BUF adjacent to the substrate, separated from the active layer ACT. The external metal layer LSb and the active layer ACT may be separated from each other and insulated by the buffer layer BUF.

[0117] The outer metal layer LSb may contain conductive materials, such as metals like aluminum (Al), titanium (Ti), copper (Cu), chromium (Cr), molybdenum (Mo), and tungsten (W).

[0118] The external metal layer LSb can stabilize the transistor's driving characteristics by blocking ambient light that passes through the substrate and reaches the active layer ACT.

[0119] The outer metal layer LSb may overlap with the active layer ACT. For example, in each of the first, second, and third subpixels SP1, SP2, and SP3, the width of the outer metal layer LSb from one end adjacent to the first source / drain region ASDa to the other end adjacent to the second source / drain region ASDb is longer than the width of the channel region CH. Therefore, the entire channel region CH may overlap with the outer metal layer LSb. For example, as in Figures 3 to 5, both ends of the outer metal layer LSb may be located in the portion overlapping with the first and second source / drain regions ASDa and ASDb. However, the present invention is not necessarily limited thereto, and depending on the design requirements, both ends of the outer metal layer LSb may be located outside the first and second source / drain regions ASDa and ASDb. For example, the first and second source / drain regions ASDa and ASDb may partially overlap with the outer metal layer LSb, or the entire first and second source / drain regions ASDa and ASDb may overlap with the outer metal layer LSb, but are not limited to this.

[0120] The outer metal layer LSb is electrically connected to either the first or second source / drain region ASDa, ASDb or to either the gate electrode G. For example, as shown in Figures 3 to 5, the outer metal layer LSb may be electrically connected to the gate electrode G via a connecting wire CTb, or it may be electrically connected to the first or second source / drain region ASDa, ASDb.

[0121] The external metal layer LSb, when electrically connected to the gate electrode G, can enhance the electric field exerted on the channel region CH when a turn-on voltage is applied to the gate electrode G, thereby increasing the amount of carriers moving along the channel region CH and potentially improving the on-current value of the drive transistor TR2. As a result, the drive transistor TR2 can generate a relatively higher drive current compared to a structure in which the external metal layer and the gate electrode are not connected.

[0122] The internal metal layer LSa may contain conductive materials, such as, but is not limited to, metals like aluminum (Al), titanium (Ti), copper (Cu), chromium (Cr), molybdenum (Mo), and tungsten (W).

[0123] The internal metal layer LSa is located between the active layer ACT and the external metal layer LSb, but can be separated from both the active layer ACT and the external metal layer LSb. The internal metal layer LSa and the active layer ACT, and the internal metal layer LSa and the external metal layer LSb, can be insulated by a buffer layer BUF.

[0124] For example, the internal metal layer LSa and the external metal layer LSb may be insulated by a first buffer layer BUF1, and the internal metal layer LSa and the active layer ACT may be insulated by a second buffer layer BUF2. The first and second buffer layers BUF1 and BUF2 may contain insulating materials. For example, the first and second buffer layers BUF1 and BUF2 may contain inorganic insulating materials such as silicon oxide (SiO) and silicon nitride (SiN).

[0125] The internal metal layer LSa may overlap with the active layer ACT and the external metal layer LSb between them.

[0126] The width of the internal metal layer LSa is smaller than the width of the external metal layer LSb when extending from one end adjacent to the first source / drain region ASDa to the other end adjacent to the second source / drain region ASDb.

[0127] Here, one end of the internal metal layer LSa, located opposite the non-overlapping region NOA of the external metal layer LSb, may be located in a region that overlaps with either the first or second source-drain region ASDa or ASDb. Figures 3 to 5 show an example where one end of the internal metal layer LSa overlaps with the first source-drain region ASDa. However, this is just an example, and depending on the design requirements, one end of the internal metal layer LSa may be located outside the first source-drain region ASDa. For example, the first source-drain region ASDa may partially overlap with the internal metal layer LSa, or the entire first source-drain region ASDa may overlap with the internal metal layer LSa, but is not limited to these.

[0128] Figures 3 to 5 show an example where one end of the inner metal layer LSa is substantially aligned to one end of the outer metal layer LSb within the design tolerance range, but the present invention is not necessarily limited to this. For example, the edge of one surface of the inner metal layer LSa does not have to be aligned with the edge of one surface of the outer metal layer LSb.

[0129] Considering the spacing between the internal metal layer LSa and the active layer ACT, and the spacing between the external metal layer LSb and the active layer ACT, the thickness of the internal metal layer LSa is greater than the thickness of the external metal layer LSb, as shown in Figures 3-5. This allows the magnitude of the electric field exerted by the internal metal layer LSa on the active layer ACT in the vertical direction to be similar to the magnitude of the electric field exerted by the external metal layer LSb on the active layer ACT in the vertical direction. For example, the magnitude of the electric field applied by the internal metal layer LSa to the active layer ACT in the vertical direction may be the same as the magnitude of the electric field applied by the external metal layer LSb to the active layer ACT in the vertical direction. However, the present invention is not necessarily limited thereto, and the thickness may differ from that indicated depending on the design requirements.

[0130] The internal metal layer LSa can be electrically connected to either the first or second source / drain region ASDa, ASDb, or the other of the gate electrode G. For example, as shown in Figures 3 to 5, if the external metal layer LSb is electrically connected to the gate electrode G, the internal metal layer LSa can be electrically connected to either the first or second source / drain region ASDa, ASDb. Figures 3 to 5 show an example where the internal metal layer LSa is electrically connected to the first source / drain region ASDa via a connecting wire CTa. However, it is also possible to connect the internal metal layer LSa to the second source / drain region ASDb. For example, if the external metal layer LSb is electrically connected to the gate electrode G, the internal metal layer LSa may be connected to the second source / drain region ASDb.

[0131] By electrically connecting the internal metal layer LSa to the first source-drain region ASDa or the second source-drain region ASDb, the driving characteristics of the transistor can be improved. More specifically, when the internal metal layer LSa is electrically connected to the first source-drain region ASDa or the second source-drain region ASDb, the S-factor of the transistor may be improved, the tonal range may be finer, and the image quality may be improved.

[0132] In each of the first, second, and third subpixels SP1, SP2, and SP3, the width of the outer metal layer LSb may be greater than the width of the inner metal layer LSa. Therefore, the width of the outer metal layer LSb that overlaps with the active layer ACT may differ from the width of the inner metal layer LSa that overlaps with the active layer ACT. For example, the width of the outer metal layer LSb that overlaps with the active layer ACT may be greater than the width of the inner metal layer LSa that overlaps with the active layer ACT.

[0133] In the drive transistor TR2 provided in the first, second, and third subpixels SP1, SP2, and SP3, respectively, the outer metal layer LSb may include an overlapping region OA and a non-overlapping region NOA. The overlapping region OA refers to the region where the outer metal layer LSb overlaps with the active layer ACT and also overlaps with the inner metal layer LSa, while the non-overlapping region NOA refers to the region where the outer metal layer LSb overlaps with the active layer ACT and does not overlap with the inner metal layer LSa.

[0134] Figures 3 to 5 show an example where the width of the active layer ACT is greater than the width of the external metal layer LSb, but the present invention is not necessarily limited to this. For example, the width of the external metal layer LSb may be greater than the width of the active layer ACT, depending on the design requirements. Even in such cases, the definitions of the overlapping region OA and the non-overlapping region NOA remain the same. However, since the width of the external metal layer LSb is greater than the width of the active layer ACT, the sum of the widths of the overlapping region OA and the non-overlapping region NOA of the external metal layer LSb may be limited to the width range of the active layer ACT. For example, the sum of the widths of the overlapping region OA and the non-overlapping region NOA of the external metal layer LSb may be the same as the width of the active layer ACT.

[0135] In this invention, the width of the non-overlapping region NOA of the outer metal layer LSb can be varied for each subpixel SP that emits different colors. That is, in this invention, the width of the non-overlapping region NOA of the outer metal layer LSb can be varied for each subpixel SP, taking into account the emission characteristics of the light-emitting element and the characteristics of the color emitted, thereby further improving image quality.

[0136] If any unit pixel contains three first, second, and third subpixels SP1, SP2, and SP3, the widths of the non-overlapping regions NOA of the outer metal layer LSb in each drive transistor TR2 provided for the first, second, and third subpixels SP1, SP2, and SP3 may differ from one another, as shown in Figures 3 to 5.

[0137] As shown in Figure 3, the first width W1 of the non-overlapping region NOA of the outer metal layer LSb in the first subpixel SP1 that emits green G may differ from the second width W2 of the non-overlapping region NOA of the outer metal layer LSb in the second subpixel SP2 that emits blue B, as shown in Figure 4.

[0138] For example, in the driving transistor TR2 of the first subpixel SP1 shown in Figure 3, the first width W1 of the non-overlapping region NOA of the outer metal layer LSb may be smaller than the second width W of the non-overlapping region NOA of the outer metal layer LSb in the driving transistor TR2 of the second subpixel SP2 shown in Figure 4.

[0139] As shown in Figure 3, in the first subpixel SP1 that emits green light G, one side of the internal metal layer LSa is superimposed on the first source-drain region ASDa, and the other end of the internal metal layer LSa adjacent to the non-superimposed region NOA of the external metal layer LSb is the second source-drain region ASDb.

[0140] As shown in Figure 4, in the second subpixel SP2 that emits blue light B, one side of the internal metal layer LSa superimposed on the first source / drain region ASDa, and the other end of the internal metal layer LSa adjacent to the non-superimposed region NOA of the external metal layer LSb may superimpose on the channel region CH.

[0141] Furthermore, as shown in Figure 5, in the third subpixel SP3 that emits red R light, the third width W3 of the non-overlapping region NOA, which is the region where the external metal layer LSb overlaps with the active layer ACT and does not overlap with the internal metal layer LSa, may differ from the first width W1 in Figure 3 and the second width W in Figure 4.

[0142] For example, as shown in Figure 5, in the third subpixel SP3, the third width W3 of the non-overlapping region NOA of the external metal layer LSb is greater than the first width W1 and smaller than the second width W2.

[0143] Thus, the present invention allows for different widths of the non-overlapping region NOA of the outer metal layer LSb in each subpixel SP, thereby varying the overlap width of the inner metal layer LSa with the active layer ACT. That is, the overlap width of the inner metal layer LSa with the active layer ACT may be inversely proportional to the width of the non-overlapping region NOA of the outer metal layer LSb. Therefore, the greater the width of the non-overlapping region NOA of the outer metal layer LSb, the smaller the overlap width of the inner metal layer LSa with the active layer ACT may become, and conversely, the greater the greater the width of the non-overlapping region NOA of the outer metal layer LSb, the greater the overlap width of the inner metal layer LSa with the active layer ACT may become.

[0144] As a result, this disclosure is a subpixel-specific SP, and can be configured such that the magnitude of the electric field exerted by the internal metal layer LSa on the active layer ACT is different from the magnitude of the electric field exerted by the external metal layer LSb on the active layer ACT.

[0145] In the superposition region OA of the outer metal layer LSb, the inner metal layer LSa is located, so the electric field due to the outer metal layer LSb is blocked by the inner metal layer LSa, and the electric field due to the inner metal layer LSa may affect the active layer ACT. In the non-superposition region NOA of the outer metal layer LSb, the inner metal layer LSa is not located, so the electric field due to the outer metal layer LSb may affect the active layer ACT.

[0146] The magnitude of the influence of the internal metal layer LSa on the active layer ACT may be proportional to the width of the overlapping region OA where the internal metal layer LSa and the active layer ACT overlap, and the magnitude of the influence of the external metal layer LSb on the active layer ACT may be proportional to the width of the non-overlapping region NOA of the external metal layer LSb.

[0147] As the width of the non-superimposed region NOA of the external metal layer LSb decreases, the S-factor of the drive transistor TR2 improves, and the threshold voltage Vth shifts in the (+) direction, which can suppress the on-current value.

[0148] Furthermore, as the width of the non-superposition region NOA of the external metal layer LSb increases, the on-current value of the drive transistor TR2 improves, the threshold voltage Vth shifts in the (-) direction, and the S-factor may decrease.

[0149] In this invention, for the first subpixel SP1 that emits green (G), which has a relatively large proportion of luminance expression when representing white, the non-overlapping region NOA of the external metal layer LSb may have a first width W1 that is relatively smaller than the second width W2 and third width W of the second and third subpixels SP2 and SP3, as shown in Figure 3.

[0150] This allows the interval required for the drive current to change from the off state to the on state for the first subpixel SP1 to be longer than that for the second and third subpixels SP2 and SP3. In this case, the S-factor of the first subpixel SP1 can be set to be relatively larger than that of the second and third subpixels SP2 and SP3, ensuring a larger gradation expression interval for the first subpixel SP1, which has greater brightness control, and enabling more stable and precise control in full white display.

[0151] Furthermore, considering that the threshold voltage Vth of a light-emitting element that emits blue (B) light is higher than the threshold voltage Vth of a light-emitting element that emits green (G) or red (R) light, the present invention allows the second subcell that emits blue light to have a second width W2, which is relatively larger than the first width W1 and third width W3 of the first and third subpixels SP, in order to maximize the on-current value of the drive transistor of the second subpixel SP2 that emits blue (B) light, as shown in Figure 4. This allows the on-current value of the saturation state when the drive transistor TR2 of the second subpixel SP2 is turned on to be set relatively high. For example, the on-current value of the saturation state when the drive transistor TR2 of the second subpixel SP2 is turned on may be greater than the on-current value of the saturation state when the drive transistor TR2 of the first subpixel SP1 is turned on and the on-current value of the saturation state when the drive transistor TR3 of the third subpixel SP3 is turned on. In other words, considering that the threshold voltage Vth of a light-emitting element that emits blue light, which is a short wavelength, is higher than the threshold voltage Vth of a light-emitting element that emits green (G) or red (R), which are relatively long wavelengths, the present invention allows the on-current value of the saturation state at turn-on for the drive transistor TR2 to be set to match each subpixel by varying the width of the non-superimposed region NOA of the external metal layer LSb.

[0152] Furthermore, even if the same gate voltage applied to the drive transistor TR2 of the second subpixel SP2 is the same as the voltage applied to the drive transistor TR2 of the first and third subpixels SP1 and SP3, the drive transistor TR2 of the second subpixel SP2 can generate a relatively high drive current. This makes it possible to improve the color perception so that the brightness of the blue light emitted by the second subpixel SP2 is at the same level as the brightness of the green or red light.

[0153] Furthermore, considering that a light-emitting element that emits red light has light emission characteristics between those of a light-emitting element that emits green light and a light-emitting element that emits blue light, the present invention makes it possible to make the S-factor or on-current value of the third subpixel SP3 that emits red light have a value between that of the first subpixel SP1 and the second subpixel SP2, by making the non-spy region NOA of the outer metal layer LSb larger than the first width (W1) of the first subpixel SP1 and smaller than the second width W2 of the second subpixel SP2, as shown in Figure 5.

[0154] As a result, the present invention allows the non-overlapping region NOA of the outer metal layer LSb to have different widths in each subpixel SP, which can further improve the color perception of the unit pixel, make gradation expression more accurate, and improve image quality.

[0155] Figure 6 is a diagram illustrating the electrical characteristic curves for the SP drive transistor TR2 for each subpixel according to an example of the present invention.

[0156] Figure 6(a) shows the electrical characteristic curve for the first subpixel SP1, which emits green light, with respect to the driving transistor TR2, and Figure 6(b) shows the electrical characteristic curve for the second subpixel SP2, which emits blue light, with respect to the driving transistor TR2.

[0157] In Figures 6(a) and (b), SL1 is the slope of the rate of change of the drain-source current Ids with respect to the gate-source voltage Vgs during the transition interval of the drive transistor TR2 provided in the first subpixel SP1, and SL2 is the slope of the rate of change of the drive transistor TR2 current Ids provided in the second subpixel SP2.

[0158] I1 is the drain-source current Ids value when the gate-source voltage Vgs of the drive transistor TR2 provided in the first subpixel SP1 is at its maximum (e.g., 20V), and I2 may be the drain-source current Ids value when the gate-source voltage Vgs of the drive transistor TR2 provided in the second subpixel SP2 is at its maximum (e.g., 20V).

[0159] The present invention allows the non-spy region (NOA) of the outer metal layer (LSb) provided in the first subpixel (SP1) to have a relatively small first width (W1), so that in the transition section, the slope (SL1) of the electrical characteristic curve of the first subpixel (SP1) is smaller than the slope (SL2) of the electrical characteristic curve of the second subpixel (SP2), as shown in Figure 6.

[0160] Since the S-factor is determined as the reciprocal of the slope of the electrical characteristic curve in the transition section, in this invention, the S-factor for the first subpixel SP1 may be larger than the S-factor for the second subpixel SP2. For example, if the first width W1 of the non-overlapping region NOA of the external metal layer LSb included in the first subpixel SP1 is smaller than the second width W2 of the non-overlapping region NOA of the external metal layer LSb included in the second subpixel SP2, then in the transition section, the S-factor value of the first subpixel SP1 may be smaller than the slope SL2 of the electrical characteristic curve of the first subpixel SP1, and therefore larger than the S-factor value of the second subpixel SP2.

[0161] Therefore, the present invention makes it possible to express the gradation of the first subpixel SP1 that emits green light more delicately and accurately.

[0162] Furthermore, by ensuring that the non-overlapping region NOA of the external metal layer LSb provided in the second subpixel SP2 has a relatively large second width W2, as shown in Figure 6, when the gate-source voltage Vgs is at its maximum in the electrical characteristic curves of the first and second subpixels SP, the drain-source current value of the second subpixel S2 can be greater than the drain-source current value I1 by I. Thus, the present invention can further improve the on-current value of the second subpixel SP2, further improve the luminescence brightness of the blue-emitting second subpixel SP2, and further improve the power consumption of the second subpixel SP2.

[0163] Furthermore, although not clearly shown in Figure 6(b), the non-overlapping region NOA of the external metal layer LSb provided in the second subpixel SP2 can be made to have a relatively large second width W2, thereby shifting the electrical characteristic curve of the second subpixel SP2 with respect to the driving transistor TR2 in the (-) direction.

[0164] Furthermore, although not shown in Figure 6, the third subpixel SP3 may have a third width W3 such that the non-overlapping region NOA of the external metal layer LSb is greater than the first width W1 of the first subpixel SP1 and smaller than the second width W2 of the second subpixel SP2, so that the S-factor or on-current value of the third subpixel SP3 is between the values ​​of the first subpixel SP1 and the second subpixel SP2. For example, if the third width W3 of the non-overlapping region NOA of the external metal layer LSb included in the third subpixel SP3 is greater than the first width W1 of the first subpixel SP1 and smaller than the second width W2 of the second subpixel SP2, then in the transition interval, the slope SL of the electrical characteristic curve of the third subpixel SP3 may be greater than the slope SL1 of the electrical characteristic curve of the third subpixel SP3 and less than the slope SL2 of the electrical characteristic curve of the second subpixel SP2, and the S-factor value of the third subpixel SP3 may be smaller than the S-factor value of the first subpixel SP1 and greater than the S-factor value of the second subpixel SP2.

[0165] Thus, the present invention allows the non-overlapping region NOA of the external metal layer LSb to have different widths in each subpixel SP, further improving the S factor and on-current value in each subpixel SP, which can lead to more accurate gradation expression, improved color perception, and ultimately, improved image quality.

[0166] The following section describes an example of applying the drive transistor TR2, as explained in Figures 3 to 5, to a display device.

[0167] Figure 7 illustrates an example of a cross-section where the subpixel SP shown in Figure 2 is applied to a display device.

[0168] Figure 7 illustrates a case where the subpixel SP shown in Figure 2(a) is applied to a display device, and the driving transistor for the first subpixel SP1 that emits green light G as shown in Figure 3 is applied. The transistor for the second subpixel SP2 shown in Figure 4 and the transistor for the third subpixel SP3 shown in Figure 5 can also be applied to a display device in the same way as in Figure 7.

[0169] Specifically, when the drive transistors in Figure 4 and Figure 5 are applied, the width of the region in Figure 7 where the outer metal layer LSb does not overlap with the inner metal layer LSa is changed to W2 in Figure 4 and W3 in Figure 5, while the rest of the structure remains the same as in Figure 7.

[0170] Note that Figure 7 omits the configuration in which the outer metal layer LSb is connected to the gate electrode G of the drive transistor, but as explained in Figures 3 to 5 above, the outer metal layer LSb can be connected to the gate electrode G of the drive transistor via the connecting wire CTb.

[0171] The display device shown in Figure 7 shows a cross-section of the first subpixel SP1 region that emits green light. Therefore, the structure of the first subpixel SP1 region shown in Figure 7, including the drive transistor for the first subpixel that emits green light, the internal metal layer LSa, and the external metal layer LSb, as described in Figure 3, can be applied. Accordingly, in the case of the second subpixel SP2 region that emits blue light in the display device, the structure of the first subpixel drive transistor for the second subpixel SP2 that emits blue light, the internal metal layer LSa, and the external metal layer LSb, as described in Figure 4, can be applied. Furthermore, in the case of the third subpixel SP3 region that emits red light in the display device, the structure of the first subpixel drive transistor for the second subpixel SP2 that emits red light, the internal metal layer LSa, and the external metal layer LSb, as described in Figure 5, can be applied.

[0172] In the following explanation, we will use the case shown in Figure 7, where the display panel is the first subpixel SP1 region that emits green light, as an example.

[0173] In Figures 7 and below, explanations of the same parts as those explained in Figures 1 to 6 will be omitted, and the explanation will focus on other parts.

[0174] As shown in Figure 7, a display device to which a driving transistor for the first subpixel SP1 is applied may include a substrate 100, a first insulating film 110, a second insulating film 130, an element buffer film 140, a first transistor TR1 which is a switching transistor, a second transistor TR2 which is a driving transistor for the first subpixel SP1, an internal metal layer LSa, an external metal layer LSb, a gate insulating film 150, an interlayer insulating film 200, a first planarization film 300, a second planarization film 400, first and second intermediate electrodes CE1 and CE2, a bank insulating film 500, and a light-emitting element 600.

[0175] The cross-sectional structure of the display device shown in Figure 7 is an example for understanding the present invention, and the present invention is not necessarily limited thereto.

[0176] The substrate 100 may be formed from a flexible plastic material and may have flexible properties, and may include a flexible, thin glass material. For example, the substrate may include a flexible polymer film. For example, the flexible polymer film may be made from any of the following: polyimide (PI), polyethyllen terephthalate (PET), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethyllen naphthalate (PEN), polycarbonate (PC) (PAR), polysulfone (PSF), cyclic olefin copolymer (COC), triacetylcellulose (TAC), polyvinyl alcohol (PVA), and polystyrene (PS), and the present invention is not limited thereto. Furthermore, as another example, the substrate 100 may include a flexible, thin glass material.

[0177] The substrate 100 may have a multilayer structure including an insulating material. For example, as shown in Figure 7, the substrate 100 has a structure in which a first substrate layer 101, a substrate insulating layer 102, and a second substrate layer 103 are stacked in order, and the first and second substrate layers 101 and 103 may include a polymer material such as polyimide (PI). The substrate insulating layer 102 may include an insulating material. For example, the substrate insulating layer 102 may be formed as a single or multilayer of an inorganic film material such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiOxNy), but the exemplary embodiments of this disclosure are not limited thereto.

[0178] The first insulating film 110 is disposed on the display area AA and the non-display area NA on the substrate 100. The first insulating film 110 is sometimes called a buffer film. The first insulating film 110 is disposed on the substrate 100 and can protect structures on the substrate 100 that are susceptible to moisture permeability from moisture penetrating the substrate 100 and can planarize the surface of the substrate 100. Such a first insulating film 110 may be formed as a single layer of inorganic film or may include a first a insulating film 111 and a first b insulating film 112 formed as a multilayer structure of multiple inorganic films, as shown in Figure 7. For example, each of the first a, 1b insulating films 111 and 112 may include one or more inorganic films from among silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxidnitride (SiOxNy). Each of the first a insulating film 111 and the first b insulating film 112 may consist of a single layer or multilayer of silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxidnitride (SiOxNy). For example, each of the first a insulating film 111 and the first b insulating film 112 may be formed as a single-layer or multilayer inorganic film. For example, a single-layer inorganic film may be a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a silicon oxynitride (SiOxNy), and a multilayer inorganic film may consist of at least one of one or more silicon oxide (SiOx) films, one or more silicon nitride (SiNx) films, and one or more silicon oxynitride (SiOxNy) films, and one or more. Exemplary embodiments of the present disclosure are not limited thereto.

[0179] The second insulating film 130 may be placed on the first insulating film 110. The second insulating film 130 may function as an interlayer insulating film 200 that insulates a transistor (not shown) constituting a gate drive unit (not shown) located in the non-display region NA. The second insulating film 130 may contain an inorganic material. The inorganic material may include, for example, a silicon nitride film (SiNx), but exemplary embodiments of this disclosure are not limited thereto.

[0180] Between the first insulating film 110 and the second insulating film 130, for example, a lower metal layer BOT may be provided, which is connected to the gate electrode G to stabilize the driving characteristics of the first transistor TR1, which is a switching transistor as shown in Figure 2.

[0181] The lower metal layer BOT may contain a different metal material from the gate electrode SG of the first transistor TR1, which is a switching transistor.

[0182] The element buffer film 140 may be provided on the second insulating film 130. The element buffer film 140 may completely cover the display area AA of the substrate 100 and may contain an insulating material. For example, the element buffer film 140 may contain an inorganic insulating material such as silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiOxNy).

[0183] The element buffer film 140 may include a multilayer structure in which a first element buffer film 141 and a second element buffer film 142 are stacked, for example, as shown in Figure 7. The first and second element buffer films 141 and 142 may be formed from the same material or from different materials. For example, the first element buffer film 141 and the second element buffer film 142 may each be composed of a single layer or multiple layer of silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiOxNy). For example, the first element buffer film 141 and the second element buffer film 142 may each be formed from a single layer or multiple layer of inorganic film. For example, a single-layer inorganic film may be a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a silicon oxynitride (SiOxNy) film, and a multilayer inorganic film may consist of at least one of one or more silicon oxide (SiOx) films, one or more silicon nitride (SiNx) films, and one or more silicon oxynitride (SiOxNy) films, but exemplary embodiments of this disclosure are not limited thereto.

[0184] On the element buffer film 140, the active layer SACT of the first switching transistor TR1 and the active layer ACT of the second driving transistor TR2 are arranged. As shown in Figure 7, if the first and second transistors TR1 and TR2 are identical and arranged on the element buffer film 140, the manufacturing process can be further simplified.

[0185] However, not all switching transistors and drive transistors are formed on the same element buffer film 140, and the present invention is not limited to this. For example, the cross-sectional structure can be modified in various ways, such as some of the switching transistors and drive transistors being formed on the same element buffer film 140, or only one of the transistors, the switching transistor or the drive transistor, being formed on the element buffer film 140.

[0186] The element buffer film 140 in Figure 7 may be the same as the buffer layer BUF described in Figures 3 to 5. Therefore, the first element buffer film 141 in Figure 7 may be the same as the first buffer layer BUF1 in Figures 3 to 5, and the second element buffer film 142 in Figure 7 may be the same as the second buffer layer BUF2 in Figures 3 to 5.

[0187] Here, the outer metal layer LSb described in Figures 3 to 5 may be located between the second insulating film 130 and the first element buffer film 141, and the inner metal layer LSa may be located between the first element buffer film 141 and the second element buffer film 142. The descriptions of the inner metal layer LSa and the outer metal layer LSb may be the same as those described in Figures 3 to 5 above.

[0188] A first transistor TR1, which is a switching transistor, and a second transistor TR2, which is a driving transistor, are arranged on the element buffer film 140. As shown in Figure 7, when the first and second transistors TR1 and TR2 are formed on the same element buffer film 140, the process can be simplified, production energy can be reduced, the generation of greenhouse gases that may occur during the manufacturing process can be reduced, and ESG (Environment / Social / Governance) can be realized.

[0189] The first switching transistor TR1 may include an active layer SACT, a gate electrode SG, and source / drain electrodes SSD on the element buffer film 140.

[0190] The active layer SACT of the first transistor TR1 may include an oxide semiconductor material. The oxide semiconductor material included in the active layer SACT may include at least one of the following oxide semiconductor materials: IZO (InZnO), IGO (InGaO), ITO (InSnO), IGZO (InGaZnO), IGZTO (InGaZnSnO), GZTO (GaZnSnO), GZO (GaZn)nO), ITZO (InSnZnO), or FIZO (FeInZnO).

[0191] The active layer SACT of the first transistor TR1 is not shown in the diagram, but it comprises a channel region and source / drain regions on both sides of the channel region, where the dopant concentration in the channel region CH is relatively low and the dopant concentration in the source / drain regions is relatively high. For example, the dopant concentration in the source / drain region may be greater than that in the channel region CH.

[0192] The gate electrode SG of the first transistor TR1 and the active layer SACT are insulated by a gate insulating film 150. The gate insulating film 150 in Figure 7 may be the same as the gate insulating film GI described in Figures 3 to 5 above. For example, the gate insulating film 150 may consist of a single layer or multiple layers of silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiOxNy). For example, the gate insulating film 150 may be formed of a single layer or multiple layers of inorganic film. For example, a single layer inorganic film may be a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a silicon oxynitride (SiOxNy), and a multiple layers of inorganic film may consist of at least one of one or more silicon oxide (SiOx) films, one or more silicon nitride (SiNx) films, and one or more silicon oxynitride (SiOxNy) films. The exemplary embodiments of this disclosure are not limited thereto.

[0193] The gate electrode SG of the first transistor TR1 may be superimposed on the active layer SACT and located on the gate insulating film 150. The gate electrode SG can control the formation of a channel in the channel region of the active layer SACT via an applied voltage.

[0194] The interlayer insulating film 200 may be located on the gate electrode SG of the first transistor TR1. The interlayer insulating film 200 in Figure 7 may be the same as the interlayer insulating film ILD described in Figures 3 to 5 above. For example, the interlayer insulating film 200 may consist of a single or multilayer of silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiOxNy). For example, the interlayer insulating film 200 can be formed as a single or multilayer inorganic film. It may also be oxynitride (SiOxNy), and the multilayer inorganic film may be formed by alternately stacking at least one of one or more silicon oxide (SiOx) films, one or more silicon nitride (SiNx) films, and one or more silicon nitride (SiOxNy) films with one or more amorphous silicon (a-Si), but exemplary embodiments of this disclosure are not limited thereto.

[0195] The source and drain electrodes SSD and the gate connection electrode CSG of the first transistor TR1 may be located on top of the interlayer insulating film 200.

[0196] The source and drain electrodes SSD of the first transistor TR1 may be located on the interlayer insulating film 200 of the first transistor TR1. The source and drain electrodes SSD of the first transistor TR1 may include an electrode that contacts one side source and drain region of the active layer ACT and an electrode that contacts the other side source and drain region of the active layer ACT.

[0197] The source and drain electrodes SSD of the first transistor TR1 penetrate the interlayer insulating film 200 and the gate insulating film 150 and contact the source and drain regions on both sides of the active layer ACT, respectively. In Figure 7, for convenience, only the source and drain electrodes SSD that contact one side of the active layer ACT are shown, and the source and drain electrodes that contact the other side are omitted.

[0198] The gate connection electrode CSG can connect the gate electrode SG of the first transistor TR1 to the lower metal layer BOT. One end of the gate connection electrode CSG may penetrate the interlayer insulating film 200 and contact the gate electrode SG, while the other end may penetrate the interlayer insulating film 200, the gate insulating film 150, the element buffer film 140, and the second insulating film 130 to connect to the lower metal layer BOT.

[0199] By connecting the lower metal layer BOT to the gate electrode SG via the gate connection electrode CSG, control of the channel region of the active layer ACT can be performed more quickly.

[0200] The switching transistor of the present invention may include an internal metal layer LSa located below the drive transistor and a lower metal layer located in the same layer as either the external metal layer LSb. Figure 7 shows an example where the lower metal layer located below the first transistor TR1, which is a switching transistor, is the lower metal layer BOT, and the lower metal layer BOT is located in the same layer as the external metal layer LSb. The lower metal layer BOT may be located on the first insulating film 110, similar to the external metal layer LSb.

[0201] However, the present invention is not limited thereto. For example, unlike in Figure 7, the lower metal layer of the first transistor TR1 may be placed on the same layer as the internal metal layer LSa. That is, the lower metal layer BOT may be located on the first element buffer film 141, similar to the internal metal layer LSa.

[0202] Although Figure 7 shows the thickness of the lower metal layer BOT to be greater than the thickness of the outer metal layer LSb, the present invention is not limited to this, and unlike Figure 7, the thickness of the lower metal layer BOT may be the same as that of either the inner metal layer LSa or the outer metal layer LSb.

[0203] The second transistor TR2, which is a driving transistor, is located on the element buffer film 140 and may include a gate electrode G, an active layer ACT, and first and second source / drain electrodes SDa and SDb. As mentioned above, the second transistor TR2 may be a driving transistor for the first subpixel SP1 that emits green light, as shown in Figure 3.

[0204] The active layer ACT is located on the element buffer film 140 and may be separated from the internal metal layer LSa. The active layer ACT may comprise a channel region CH and first and second source / drain regions ASDa and ASDb.

[0205] The gate electrode G may be located separately from the active layer ACT and may overlap with the channel region CH. The gate electrode G and the active layer ACT may be insulated by the gate insulating film 150. Although not shown in Figure 7, the gate electrode G may be electrically connected to the outer metal layer LSb, as described in Figure 3.

[0206] The gate electrode G of the first transistor TR1 and the active layer ACT, and the gate electrode G of the second transistor TR2 and the active layer ACT, can be insulated by the same gate insulating film 150. The gate insulating film 150 in Figure 7 may be the same as the gate insulating film GI described in Figures 3 to 5 above.

[0207] An interlayer insulating film 200 is located on the gate electrode G of the second transistor TR2. The first and second source and drain electrodes SDa and SDb of the second transistor TR2 are located on the interlayer insulating film 200 of the second transistor TR2.

[0208] One end of the first source / drain electrode SDa can penetrate the interlayer insulating film 200 and contact the first source / drain region ASDa of the active layer ACT, and the other end of the first source / drain electrode SDa can penetrate the interlayer insulating film 200, the gate insulating layer and the second buffer layer BUF2 and connect to one end of the internal metal layer LSa.

[0209] One end of the second source / drain electrode SDb may penetrate the interlayer insulating film 200 and contact the second source / drain region ASDb of the active layer ACT, and the other end of the second source / drain electrode SDb is electrically connected to the anode electrode of the light-emitting element 600.

[0210] The outer metal layer LSb of the first subpixel SP1, which emits green light, may overlap with the active layer ACT and the inner metal layer LSa. In the region where the outer metal layer LSb overlaps with the active layer ACT, the non-overlapping region NOA, which does not overlap with the inner metal layer LSa, may have a first width W1, similar to Figure 3 above.

[0211] However, in the case of the second subpixel SP2 that emits blue light, as explained in Figure 4 above, the width of the non-overlapping region NOA of the outer metal layer LSb may have a second width W2 that is larger than the first width W1, and in the case of the third subpixel SP3 that emits red light, as explained in Figure 5 above, the specific gravity region NOA of the outer metal layer LSb may have a third width W3 that is larger than the first width W1 and smaller than the second width W2. For example, if the third width W3 of the non-overlapping region NOA of the external metal layer LSb contained in the third subpixel SP3 is greater than the first width W1 of the first subpixel SP1 and less than the second width W2 of the second subpixel SP2, then in the transition interval, the S-factor value of the third subpixel SP3 may be greater than the slope SL1 of the electrical characteristic curve of the first subpixel SP3 and less than the slope SL2 of the electrical characteristic curve of the second subpixel SP2, and the S-factor value of the third subpixel SP3 may be less than the S-factor value of the first subpixel SP1 and greater than the S-factor value of the second subpixel SP2.

[0212] A first planarization film 300 and a second planarization film 400 can be sequentially stacked on the first and second transistors TR1 and TR2, respectively.

[0213] The first planarization film 300 and the second planarization film 400 can eliminate steps caused by the drive circuit. For example, the upper surface of the second planarization film 400 facing the light-emitting element (OLED, 600) may be a flat surface. The first planarization film 300 and the second planarization film 400 may contain insulating materials. The first planarization film 300 and the second planarization film 400 may contain materials with high fluidity. For example, the first planarization film 300 and the second planarization film 400 may contain organic insulating materials. The second planarization film 400 may contain a material different from that of the first planarization film 300. As a result, in the display device according to the embodiment of the present invention, steps caused by the drive circuit can be effectively eliminated.

[0214] The first and second intermediate electrodes CE1 and CE2 of the second transistor TR2 may be located between the first planarization film 300 and the second planarization film 400. The first and second intermediate electrodes CE1 and CE2 may contain conductive materials. For example, the first and second intermediate electrodes CE1 and CE2 may contain metals such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W).

[0215] The first intermediate electrode CE1 may electrically connect the first transistor TR1 and the second transistor TR2, or it may electrically connect the first and second transistors to other circuit configurations not shown.

[0216] The second intermediate electrode CE2 can electrically connect the second transistor TR2 and the light-emitting element. For example, as shown in Figure 7, the second intermediate electrode CE2 can electrically connect the second source / drain electrode SDb of the second transistor TR2 and the first electrode (anode electrode) of the light-emitting element.

[0217] A bank insulating film 500 may be located on the second planarization film 400.

[0218] The bank insulating film 500 may include an insulating material. For example, the bank insulating film 500 may include an organic insulating material. The bank insulating film 500 may include a different material from the first planarization film 300 and the second planarization film 400. The bank insulating film 500 may cover the edge of the first electrode 610 (e.g., the anode electrode). The light-emitting layer 620 and the second electrode 630, for example, the cathode electrode, may be laminated on a portion of the first electrode 610 exposed by the bank insulating film 500. For example, the bank insulating film 500 may define a light-emitting region in each subpixel SP. The bank insulating film 500 may be formed of an opaque material (e.g., black) to prevent light interference between adjacent pixels. In this case, the bank insulating film 500 may include, but is not limited to, a light-shielding material consisting of at least one of a dye, organic black, or carbon.

[0219] For example, the bank insulating film 500 can be formed from an organic insulating material. The bank insulating film 500 can consist of a single layer or a multilayer organic insulating material. For example, the bank insulating film 500 can be formed from a photoresist, polyimide (PI), or acrylic material, but embodiments of the present invention are not limited thereto.

[0220] On the other hand, the bank insulating film 500 may contain an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), or it may be formed from a black resin. However, the present invention is not limited thereto.

[0221] A light-emitting element 600 may be located in the light-emitting region, and the light-emitting element 600 may include a first electrode 610, a light-emitting layer 620, and a second electrode 630.

[0222] In the light-emitting element OLED 600, the first electrode 610 functions, for example, as an anode electrode and may contain a conductive material. The first electrode 610 may have high reflectivity. For example, the first electrode 610 may contain metals such as aluminum (Al) and silver (Ag). The first electrode 610 may have a multilayer structure. For example, the first electrode 610 may have a structure in which a reflective electrode made of metal is positioned between transparent electrodes made of transparent conductive materials such as ITO or IZO.

[0223] The light-emitting layer 620 can generate light with a brightness corresponding to the voltage difference between the first electrode 610 and the second electrode 630. For example, the light-emitting layer 620 may include an Emission Material Layer (EML) containing a light-emitting material. The light-emitting material may include an organic material, an inorganic material, or a hybrid material. For example, the light-emitting layer 620 may include a light-emitting material layer made of an organic material.

[0224] The light-emitting layer 620 may include at least one of a first light-emitting common layer (not shown) located between it and the first electrode 610, and a second light-emitting common layer (not shown) located between it and the second electrode 630. The first light-emitting common layer (not shown) and the second light-emitting common layer (not shown) may each include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0225] The light-emitting layer 620 can emit red (R), green (G), or blue (B). In the case of the first subpixel SP1, the light-emitting layer can emit green light; in the case of the second subpixel SP2, the light-emitting layer can emit blue light; and in the case of the third subpixel SP3, the light-emitting layer can emit red light. In Figure 7, the light-emitting layer can emit green light.

[0226] The second electrode 630 functions, for example, as a cathode electrode and may contain a conductive material. The second electrode 630 may contain a different material from the first electrode 610. For example, the second electrode 630 may be a transparent electrode made of a transparent conductive material such as ITO and IZO. The second electrode 630 may have a higher transmittance than the first electrode 610. Therefore, in a display device according to one embodiment of the present invention, light generated by the light-emitting layer 620 can be emitted through the second electrode 630.

[0227] Figure 7 illustrates a case where the second transistor TR2, which is a driving transistor, is connected to the light-emitting element 600 (OLED), as an example, but the present invention is not necessarily limited to this.

[0228] As explained in Figure 2(b), if a third transistor TR3, which is a switching transistor, is provided, the second transistor TR2 is connected to the third transistor TR3, and the third transistor TR3 is electrically connected to the light-emitting element 600 and the OLED.

[0229] As described above, in the display device according to the embodiment of the present invention, by configuring the width of the non-overlapping region NOA of the external metal layer LSb connected to the drive transistor for each subpixel SP to be different, the S-factor and on-current value can be set differently for each subpixel SP to match the light emission characteristics of the subpixel SP. This makes it possible to improve the image quality displayed by the display panel.

[0230] For example, as explained in Figures 3 to 5 above, with an external metal layer LSb provided on each of several subpixels SP electrically connected to the gate electrode G, and an internal metal layer LSa electrically connected to either the first or second source / drain region ASDa or ASDb, the widths of the non-spy region NOA of the external metal layer LSb can be made different for each subpixel SP that emit different colors from each other.

[0231] Specifically, in the case of a first subpixel SP1 equipped with a green light-emitting layer, since it greatly affects the color perception expressed by the unit pixel, the non-overlapping region NOA of the external metal layer LSb may be configured to have a relatively small first width W1 so that the S factor increases relatively in order to express finer gradations. In the case of a second subpixel SP2 equipped with a blue light-emitting layer, since the brightness of the light emitted with the same drive current is lower than that of green or red, a relatively large drive current is generated for the same gate-source voltage Vgs, so the non-overlapping region NOA of the external metal layer LSb may be configured to have a relatively large second width W2.

[0232] In the case of the third subpixel SP3 having a red light-emitting layer, since it has less influence on color perception than green and greater light luminance than blue, the non-overlapping region NOA of the external metal layer LSb can be configured to have a third width W3 that is larger than the first width W1 and smaller than the second width W2.

[0233] As a result, the present invention can improve the image quality of a display panel by configuring the width of the non-overlapping region NOA of the outer metal layer LSb to differ so that the S factor and on-current value differ for each subpixel SP.

[0234] Up to this point, we have explained using the example where the external metal layer LSb provided on each of the multiple subpixels SP is electrically connected to the gate electrode G, and the internal metal layer LSa is electrically connected to one of the first and second source / drain regions ASDa and ASDb, and the width of the non-overlapping region NOA of the external metal layer LSb is made different for each subpixel SP that emits different colors.

[0235] However, the present invention is not limited thereto and can also be applied when the external metal layer LSb is electrically connected to either the first or second source / drain region ASDa, ASDb, and the internal metal layer LSa is electrically connected to the gate electrode G.

[0236] In such cases, the width of the non-superposition region NOA of the outer metal layer LSb may differ from that described in Figures 3 to 7 above. This will be explained below with reference to Figures 8 to 10.

[0237] Figure 8 illustrates another example of a transistor provided in the first subpixel SP1 in the display device of the present invention, Figure 9 illustrates another example of a transistor provided in the second subpixel SP2 in the display device of the present invention, and Figure 10 illustrates another example of a transistor provided in the third subpixel SP3 in the display device of the present invention.

[0238] As shown in Figures 8 to 10, in the drive transistor TR2 provided in the first, second, and third subpixels SP1, SP2, and SP3, the internal metal layer LSa is electrically connected to the gate electrode G via connecting wiring CTa, and the external metal layer LSb can be electrically connected to either the first or second source / drain region ASDa or ASDb via connecting wiring CTb. Figures 8 to 10 show an example where the external metal layer LSb is electrically connected to the first source / drain region ASDa.

[0239] Here, the first subpixel SP1 in Figure 8 may emit green light as shown in Figure 3, the second subpixel SP2 in Figure 9 may emit blue light as shown in Figure 4, and the third subpixel SP3 in Figure 10 may emit red light as shown in Figure 5.

[0240] Thus, unlike in Figures 3 to 5, when the electrical connection structure between the internal metal layer LSa and the external metal layer LSb is reversed, the internal metal layer LSa has a relatively larger influence on the transistor's on-current value, and the external metal layer LSb can have a relatively larger influence on the transistor's threshold voltage Vth and S-factor, contrary to what was explained in Figures 3 to 5.

[0241] In such cases, the widths of the non-overlapping regions NOA of the outer metal layer LSb may differ in each of the first, second, and third subpixels SP1, SP2, and SP3. For example, the fourth width W1' of the non-overlapping region NOA of the outer metal layer LSb in the first subpixel SP1 may be larger than the fifth width W2' of the non-overlapping region NOA of the outer metal layer LSb in the second subpixel SP2, and the sixth width W3' of the non-overlapping region NOA of the outer metal layer LSb in the third subpixel SP3 may be larger than the fifth width W2' and smaller than the fourth width W1'.

[0242] As a result, in the first subpixel SP1 of Figure 8, one side of the internal metal layer LSa can be superimposed on the first source / drain region ASDa, and the other end of the internal metal layer LSa adjacent to the non-superimposed region NOA of the external metal layer LSb can be superimposed on the channel region CH.

[0243] Furthermore, in the second subpixel SP2 of Figure 9, one side of the internal metal layer LSa may overlap the first source / drain region ASDa, and the other end of the internal metal layer LSa adjacent to the non-overlapping region NOA of the external metal layer LSb may overlap the second source / drain region ASDb.

[0244] As a result, the present invention can further improve the S-factor of the first subpixel SP1 that emits green light and further improve the on-current value of the second subpixel SP2 that emits blue light.

[0245] Thus, the present invention provides a drive transistor TR2 for each subpixel SP with an internal metal layer LSa that contacts the source and drain regions and an external metal layer LSb that contacts the gate electrode G. By configuring the width of the non-overlapping region NOA of the external metal layer LSb to differ for each subpixel SP, the on-current value and S-factor for the drive transistor TR2 can be made different to suit each subpixel SP, thereby further improving image quality.

[0246] As described above, those skilled in the art will understand that various changes and modifications are possible without departing from the technical concept of the present invention. Therefore, the technical scope of the present invention is not limited to what is described in the detailed description of the specification, but should be defined by the claims. [Explanation of Symbols]

[0247] 10 Display Panel SP subpixel DL Dataline GL Gate Line

Claims

1. circuit board and A transistor is provided, which is arranged in each of a plurality of subpixels located in the display area on the substrate, and includes a channel region, an active layer having a first source-drain region and a second source-drain region on the side of the channel region, and a gate electrode overlapping the active layer. An external metal layer located between the active layer and the substrate, overlapping the active layer, The system comprises an internal metal layer located between the active layer and the external metal layer, and overlapping the active layer and the external metal layer. The plurality of subpixels include a first subpixel and a second subpixel that emit different colors from each other. A display device in which, in the first subpixel, the width of the non-overlapping region in the region where the outer metal layer overlaps with the active layer, where the outer metal layer does not overlap with the internal metal layer, is different from the width of the non-overlapping region in the second subpixel in the region where the outer metal layer overlaps with the active layer, where the internal metal layer does not overlap with the internal metal layer.

2. In each of the first and second subpixels, The entire channel region overlaps with the outer metal layer. The width of the internal metal layer is smaller than the width of the external metal layer. The display device according to claim 1, wherein one end of the internal metal layer located on the opposite side of the non-overlapping region of the external metal layer is located in a portion that overlaps with either the first or second source / drain region.

3. The display device according to claim 1, wherein the transistor is a drive transistor that supplies a drive current to the light-emitting element of the corresponding subpixel of the plurality of subpixels.

4. In each of the first and second subpixels, The outer metal layer is electrically connected to either of the gate electrodes and to either of the first or second source / drain regions. The display device according to claim 1, wherein the internal metal layer is electrically connected to the other gate electrode and to either the first or second source / drain region.

5. In each of the first and second subpixels, The outer metal layer is electrically connected to the gate electrode. The display device according to claim 4, wherein the internal metal layer is electrically connected to either the first or second source / drain region.

6. In each of the first and second subpixels, The external metal layer is electrically connected to either the first or second source / drain region. The display device according to claim 4, wherein the internal metal layer is electrically connected to the gate electrode.

7. In each of the first and second subpixels, The internal metal layer is electrically connected to either the first or second source / drain region, and the external metal layer is electrically connected to the gate electrode. The first subpixel is configured to emit green light, and the second subpixel is configured to emit blue light. The display device according to claim 1, wherein the first width of the non-overlapping region of the external metal layer in the first subpixel is smaller than the second width of the non-overlapping region of the external metal layer in the second subpixel.

8. One end of the internal metal layer of the first subpixel overlaps the first source-drain region, and the other end of the internal metal layer adjacent to the non-overlapping region of the external metal layer overlaps the second source-drain region. The display device according to claim 7, wherein one end of the internal metal layer of the second subpixel overlaps the first source-drain region, and the other end of the internal metal layer adjacent to the non-overlapping region of the external metal layer overlaps the channel region.

9. The plurality of subpixels include a third subpixel that emits a different color from the first and second subpixels. The display device according to claim 7, wherein in the third subpixel, the third width of the non-overlapping region that does not overlap with the internal metal layer among the region in which the external metal layer overlaps with the active layer is different from the first width and the second width.

10. The aforementioned third subpixel emits red light, The display device according to claim 9, wherein in the third subpixel, the third width of the non-overlapping region of the external metal layer is greater than the first width and less than the second width.

11. In each of the first and second subpixels, the internal metal layer is electrically connected to the gate electrode, and the external metal layer is electrically connected to either the first or second source / drain region. The first subpixel emits green light, and the second subpixel emits blue light. The display device according to claim 1, wherein the fourth width of the non-overlapping region of the external metal layer in the first subpixel is greater than the fifth width of the non-overlapping region of the external metal layer in the second subpixel.

12. In the first subpixel, one end of the internal metal layer overlaps the first source-drain region, and the other end of the internal metal layer adjacent to the non-overlapping region of the external metal layer overlaps the channel region. The display device according to claim 11, wherein in the second subpixel, one end of the internal metal layer overlaps with the first source-drain region, and the other end of the internal metal layer adjacent to the non-overlapping region of the external metal layer overlaps with the second source-drain region.

13. The plurality of subpixels include a third subpixel that emits a different color from the first and second subpixels. The display device according to claim 11, wherein the sixth width of the non-overlapping region of the external metal layer in the third subpixel is different from the fourth width and the fifth width.

14. The aforementioned third subpixel emits red light, The display device according to claim 13, wherein the sixth width of the non-overlapping region of the external metal layer in the third subpixel is greater than the fifth width and less than the fourth width.

15. The display device according to claim 1, wherein the active layer comprises an oxide semiconductor material.

16. circuit board and A drive transistor is provided, which is arranged in each of a plurality of subpixels located in the display area on the substrate, and includes a channel region, a first active layer having a first source-drain region and a second source-drain region on the side of the channel region, and a first gate electrode overlapping the first active layer. An external metal layer located between the first active layer and the substrate, overlapping the first active layer, The device comprises an internal metal layer located between the first active layer and the external metal layer, and overlapping the first active layer and the external metal layer. The plurality of subpixels include a first subpixel and a second subpixel that emit different colors from each other. In the first subpixel, the width of the non-overlapping region in the area where the outer metal layer overlaps with the first active layer, which does not overlap with the inner metal layer, is different from the width of the non-overlapping region in the area where the outer metal layer overlaps with the first active layer, which does not overlap with the inner metal layer, in the second subpixel. A display device further comprising a switching transistor, which is arranged in each of a plurality of subpixels located in a display area on the substrate, and which includes a second active layer, a second gate electrode overlapping the second active layer, and a lower metal layer located in the same layer as either the internal metal layer or the external metal layer.

17. The display device according to claim 16, wherein the lower metal layer is connected to the second gate electrode via a gate connection electrode.

18. The display device according to claim 16, wherein the thickness of the lower metal layer is the same as the thickness of either the inner metal layer or the outer metal layer.

19. In each of the first and second subpixels, The internal metal layer is electrically connected to either the first or second source / drain region, and the external metal layer is electrically connected to the gate electrode. The first subpixel emits green light and the second subpixel emits blue light. The display device according to claim 16, wherein the first width of the non-overlapping region of the external metal layer in the first subpixel is smaller than the second width of the non-overlapping region of the external metal layer in the second subpixel.

20. The plurality of subpixels include a third subpixel that emits a different color from the first and second subpixels. The display device according to claim 19, wherein in the third subpixel, the third width of the non-overlapping region that does not overlap with the internal metal layer among the region in which the external metal layer overlaps with the first active layer is different from the first width and the second width.

21. The aforementioned third subpixel emits red light, The display device according to claim 20, wherein the third width of the non-overlapping region of the external metal layer in the third subpixel is greater than the first width and less than the second width.

22. In each of the first and second subpixels, the internal metal layer is electrically connected to the gate electrode, and the external metal layer is electrically connected to either the first or second source / drain region. The first subpixel emits green light, and the second subpixel emits blue light. The display device according to claim 16, wherein the fourth width of the non-overlapping region of the external metal layer in the first subpixel is greater than the fifth width of the non-overlapping region of the external metal layer in the second subpixel.

23. The plurality of subpixels include a third subpixel that emits a different color from the first and second subpixels. The display device according to claim 22, wherein the sixth width of the non-overlapping region of the external metal layer in the third subpixel is different from the fourth width and the fifth width.

24. The aforementioned third subpixel emits red light, The display device according to claim 23, wherein the sixth width of the non-overlapping region of the external metal layer in the third subpixel is greater than the fifth width and less than the fourth width.

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