Information processing device, error estimation program, and error estimation method

Abstract

This reduces the time required to estimate the location of errors in logical qubits. [Solution] The information processing device 10 identifies pairs of second vertices 4a to 4f corresponding to each second qubit in which an error was detected by syndrome measurement, and which are determined to be close based on a first criterion of whether the distance between the second vertices 4a to 4f is far or near. The information processing device 10 determines a second weight for the second edge connecting the second vertices constituting the pair, based on a first weight for the first edge included in the path connecting the pair on the first decode graph 3. The information processing device 10 generates a second decode graph 7 which has second vertices constituting the pair and second edges connecting the second vertices constituting the pair, and a second weight is set for the second edge. The information processing device 10 then estimates the third qubit in which the error occurred, based on the second weight of the second edge of the second decode graph 7.

Description

[Technical Field]

[0001] The present invention relates to an information processing device, an error estimation program, and an error estimation method. [Background technology]

[0002] To achieve high-precision quantum computation using quantum computers, quantum error correction technology is being developed. To enable quantum error correction, the state of a single qubit is encoded using multiple physical qubits, for example, in a surface code. This encoded qubit is called a logical qubit. Errors in the physical qubits constituting the logical qubit can be detected by syndrome measurement using auxiliary qubits. The position of the physical qubit where the error occurred is determined by decoding the code based on the results of the syndrome measurement.

[0003] As quantum error correction techniques, for example, a qubit error estimation device has been proposed that estimates errors within a required time using a practical code distance size, without using an approximation that assumes a constant probability of bit errors occurring. Techniques for encoding quantum circuits into a three-price-particle scheme to identify the results of flag qubits have also been proposed. Quantum error correction for correcting the stream of syndrome measurement values ​​has also been proposed. Furthermore, efficient methods for decoding quantum state information have been proposed. Techniques for implementing decoders responsible for diagnosing noise-induced diagnostic errors on FPGAs (Field-Programmable Gate Arrays) and ASICs (Application Specific Integrated Circuits) have also been proposed. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2024-59124 [Patent Document 2] Special Publication No. 2022-553169 [Patent Document 3] U.S. Patent Application Publication No. 2022 / 0382632 [Patent Document 4] U.S. Patent No. 11847020 [Non-patent literature]

[0005] [Non-Patent Document 1] Ben Barber, et al. "A real-time, scalable, fast and highly efficient resource decoder for a quantum computer", arXiv:2309.05558v2, quant-ph, 24-Sep-2024 [Overview of the project] [Problems that the invention aims to solve]

[0006] In quantum computers, the process of sequentially executing gate operations on multiple quantum gates represented in a quantum circuit frequently involves syndrome measurements of logic qubits and estimation of error locations based on the measurement results. Therefore, calculations to estimate error locations within logic qubits are required to be executed in a very short time, for example, within 1 μs. However, conventional error location estimation algorithms have difficulty estimating error locations in a short time due to reasons such as the large amount of data used.

[0007] In one aspect, this project aims to reduce the time required to estimate the location of errors in logical qubits. [Means for solving the problem]

[0008] One proposal provides an information processing device having the following processing unit: The processing unit has a first vertex corresponding to each of a plurality of first qubits used for detecting an error occurring in a qubit in a quantum bit device, and a first edge connecting between first vertices corresponding to two first qubits that target a common qubit for error detection. For the first edge, a first decoding graph is generated in which a first weight corresponding to the probability of detecting an error with the first qubits corresponding to the first vertices at both ends is set. The processing unit identifies a pair of second vertices corresponding to each of a plurality of second qubits in which an error has been detected by syndrome measurement among the plurality of first vertices, and the pair is determined to be close based on a first determination criterion as to whether the distance between the second vertices is far or near. The processing unit determines a second weight of a second edge connecting between the second vertices constituting the pair based on the first weight of the first edge included in the path connecting the pair on the first decoding graph. The processing unit has a second vertex constituting the pair and a second edge connecting between the second vertices constituting the pair, and generates a second decoding graph in which the second weight is set for the second edge. Then, the processing unit estimates a third qubit in which an error has occurred based on the second weight of the second edge of the second decoding graph.

Advantages of the Invention

[0009] According to one aspect, the time required to estimate the error location of a logical qubit is shortened.

Brief Description of the Drawings

[0010] [Figure 1] It is a diagram showing an example of an error estimation method according to the first embodiment. [Figure 2] It is a diagram showing an example of the configuration of a quantum computing system. [Figure 3] It is a diagram showing an example of the hardware of a classical computer and a quantum computer. [Figure 4] It is a diagram showing an example of quantum bit encoding. [Figure 5] It is a diagram showing an example of an error occurring in a logical qubit. [Figure 6]This figure shows an example of error location estimation processing using a decode graph. [Figure 7] This figure shows an example of error estimation processing that determines the location of a logical error. [Figure 8] This figure shows an example of error pattern estimation using an MWPM decoder. [Figure 9] This figure shows an example of the processing procedure for an MWPM decoder. [Figure 10] This diagram shows an example of how to expand a cluster. [Figure 11] This figure shows an example of decoding using the Ising model. [Figure 12] This block diagram shows an example of a quantum computing function that involves decoding using a simplified decode graph. [Figure 13] This figure shows an example of a processing procedure for calculations based on quantum circuits. [Figure 14] This flowchart shows an example of the procedure for decoding graph region partitioning. [Figure 15] This figure shows an example of a three-dimensional decode graph. [Figure 16] This figure shows an example of the decode graph splitting process. [Figure 17] This figure shows an example of a divided decode graph. [Figure 18] This figure shows an example of addresses assigned to divided regions. [Figure 19] This figure shows an example of the average weight of the divided regions. [Figure 20] This flowchart shows an example of the decoding process. [Figure 21] This figure shows an example of a simplified decoding graph. [Figure 22] This figure shows an example of a decoding process using a simplified decoding graph. [Figure 23] This figure shows the accuracy evaluation results when decoding was performed using MWPM with a simplified decoding graph. [Figure 24]This figure shows the evaluation results of memory usage when decoding with an Ising decoder using a simplified decoding graph. [Modes for carrying out the invention]

[0011] The following description of this embodiment will be made with reference to the drawings. Note that each embodiment can be implemented by combining multiple embodiments within a reasonable scope. [First Embodiment] The first embodiment is an error estimation method that can estimate the location of an error in a logical qubit in a short amount of time.

[0012] Figure 1 shows an example of an error estimation method according to the first embodiment. Figure 1 shows an information processing device 10 for implementing the error estimation method. The information processing device 10 is connected to a qubit device 1 via, for example, an operation signal generator 2. The qubit device 1 is a device that realizes a qubit, which is the smallest unit of quantum information. Multiple qubits are realized within the qubit device 1. The operation signal generator 2 is a device that generates signals (e.g., microwaves) for manipulating the state of a qubit or measuring its state.

[0013] The information processing device 10 realizes quantum computation using the qubit device 1 by generating signals in the operation signal generator 2 according to the quantum gates shown in the quantum circuit corresponding to the problem to be solved. In this case, the information processing device 10 can implement the error estimation method according to the first embodiment by, for example, executing an error estimation program.

[0014] The information processing device 10 includes a storage unit 11 and a processing unit 12. The storage unit 11 is, for example, a memory or storage device of the information processing device 10. The processing unit 12 is, for example, a processor of the information processing device 10. The information processing device 10 may have multiple processors. Some of the multiple processes performed by the information processing device 10 may be executed on different processors.

[0015] The memory unit 11 stores information about the quantum circuit to be executed (such as the quantum gate to be executed, the qubits to be used, the code distance, etc.). The processing unit 12 transmits control signals for gate operation to the operation signal generator 2 according to the quantum circuit. Furthermore, when the processing unit 12 obtains the measurement results of the syndrome measurement for error detection from the operation signal generator 2, it executes error detection processing. The procedure for error detection processing is as follows:

[0016] The processing unit 12 generates a first decode graph 3. The first decode graph 3 has multiple vertices (first vertices) and edges (first edges) connecting the first vertices. Each of the first vertices corresponds to one of the multiple first qubits used to detect errors occurring in the qubits within the qubit device 1. The first qubits are also called auxiliary qubits.

[0017] The first edge connects the first vertices corresponding to the two first qubits that share a common qubit as the error detection target. A first weight is assigned to the first edge, corresponding to the probability of detecting an error in the first qubits corresponding to the first vertices at both ends. The first weight becomes larger, for example, as the likelihood of an error occurring in the qubit being detected increases.

[0018] The processing unit 12 identifies pairs of vertices (second vertices 4a to 4f) corresponding to each of the multiple second qubits for which an error was detected by syndrome measurement among the multiple first vertices, and which are determined to be close based on a first criterion of whether the distance between the second vertices 4a to 4f is far or near. For example, the first criterion is a Manhattan distance threshold. In this case, the processing unit 12 determines that the pairs are close if the Manhattan distance is less than or equal to the threshold, and far if the Manhattan distance exceeds the threshold.

[0019] The processing unit 12 may divide the region where the first decode graph 3 exists into multiple subregions 3a, 3b, ... In that case, the processing unit 12 determines whether the distance between the two second vertices to be determined is far or near, based on a first determination criterion concerning the positional relationship of the subregions to which each of the two second vertices to be determined belongs. In the example in Figure 1, the processing unit 12 determines that the two second vertices are close if the subregions to which each of the two second vertices belongs are adjacent to each other. For example, focusing on the second vertex 4a, the other second vertices 4b to 4d that are within the first range 5 which includes the subregion adjacent to the subregion to which the second vertex 4a belongs are determined to be close, while the other second vertices 4e and 4f are determined to be far.

[0020] After identifying the second pair of vertices, the processing unit 12 determines the second weights of the second edges 7a to 7e connecting the pair based on the first weights of the first edges included in the path connecting the pair on the first decode graph 3. For example, the processing unit 12 uses the sum of the first weights of the first edges included in the shortest path connecting the pair on the first decode graph 3 as the second weights of the second edges 7a to 7e connecting that pair.

[0021] Next, the processing unit 12 generates a second decode graph 7 which has a second vertex forming a pair and second edges 7a to 7e connecting the second vertices forming the pair, and a second weight is set on the second edges 7a to 7e. The second decode graph 7 is a graph with a simpler structure than the first decode graph 3.

[0022] The processing unit 12 then estimates the third qubit where the error occurred based on the second weight of the second edge of the second decode graph 7. For example, the processing unit 12 combines the second edges 7a to 7e of the second decode graph 7 such that the second vertices 4a to 4f are the ends of any of the second edges 7a to 7e. The processing unit 12 identifies the combination of second edges 7a to 7e that minimizes the sum of the weights of the second edges 7a to 7e included in the combination. The processing unit 12 identifies the first edge included in the path on the first decode graph 3 between the second vertices at both ends of each of the second edges 7a, 7c, and 7e included in the identified combination. The processing unit 12 then estimates that the error occurred in the qubit corresponding to the identified first edge.

[0023] The error location is estimated using the simplified second decode graph 7. The second decode graph 7 is significantly simplified compared to the complete graph, which is created by brute-forcing all the second vertices 4a to 4f corresponding to the second qubit where the error was detected. Therefore, error location estimation based on the second decode graph 7 can be computed with less data and computation time compared to error location estimation using the complete graph.

[0024] Furthermore, when the processing unit 12 determines the proximity of the distance between two vertices, it makes a determination based on a first criterion concerning the positional relationship of the subregions 3a, 3b, ... of the first decode graph 3, thereby enabling it to quickly determine whether the distance between the second vertices is far or near.

[0025] The processing unit 12 may determine the method for calculating the second weight based on whether a second criterion for determining that the distance between the subregions to which each of the second vertices of the pair belongs is met. For example, the processing unit 12 determines that the distance is close if the subregion to which the other second vertex of the pair belongs is included within a second range 6 centered on the subregion to which one of the second vertices of the pair belongs. In the example in Figure 1, the second range 6 when focusing on the second vertex 4a is the subregion to which that second vertex 4a belongs.

[0026] The processing unit 12 determines the second weight using the first calculation method if the positional relationship of the subregions to which each of the second vertices of the pair belongs satisfies the second criterion, and if it does not satisfy the second criterion, it determines the second weight using a second calculation method that is more approximate than the first calculation method. As a result, when the second vertices of the pair are far apart, the second weight can be calculated approximately in a short time. This reduces the calculation time for the second weight.

[0027] For example, the processing unit 12 calculates the average weight of the first edge within each of the multiple subregions in the first decode graph 3. If the second criterion is not met, it replaces the weight of the first edge with the average weight of the subregion to which the first edge belongs. Then, the processing unit 12 uses the replaced weight of the first edge to determine the second weight. This reduces the calculation time for the second weight.

[0028] Furthermore, the processing unit 12 may prevent the number of pairs that each second vertex forms with other second vertices (the number of second edges connected to each second vertex) from exceeding a predetermined upper limit. This prevents the total number of second edges in the second decode graph 7 from becoming too large. As a result, the time required to estimate the error location can be reliably reduced.

[0029] [Second Embodiment] The second embodiment is a quantum computing system with quantum error correction. Figure 2 shows an example of the configuration of a quantum computing system. The quantum computing system 300 is a computer system that performs calculations using, for example, the principles of quantum mechanics. The quantum computing system 300 has a classical computer 100 and a quantum computer 200. The classical computer 100 is a von Neumann type computer. The quantum computer 200 is a non-von Neumann type computer that performs quantum calculations by applying quantum gates to qubits. For example, the quantum computer 200 performs quantum calculations using the quantum gate method.

[0030] A terminal device 30 is connected to the classical computer 100 via a network 20. The terminal device 30 is a computer used by users who request quantum computations from the quantum computing system 300. The classical computer 100 accepts quantum computation requests, including quantum circuits, from terminal devices 30, for example. A quantum circuit indicates the sequence of gate operations on qubits by the arrangement of elements such as gates. A qubit is a bit that can represent a superposition state between a "0" state and a "1" state.

[0031] The classical computer 100 instructs the quantum computer 200 to perform gate operations on qubits according to the quantum computation request received from the terminal device 30. The classical computer 100 also obtains the measurement results for each qubit from the quantum computer 200.

[0032] The quantum computer 200 performs gate operations on qubits according to instructions from the classical computer 100. The quantum computer 200 also measures the state of the quantum gate and transmits the measurement results to the classical computer 100.

[0033] Figure 3 shows an example of the hardware of a classical computer and a quantum computer. In the classical computer 100, the entire device is controlled by a processor 101. The processor 101 is connected to memory 102 and several peripheral devices via bus 100a.

[0034] The classical computer 100 may be a multiprocessor system having multiple processors. The set of multiple processors in a multiprocessor system can be called a processor 101. A processor 101 may also be called a processor circuitry. Each of the multiple processors can execute some or all of the multiple processes that are executed on the classical computer 100. When there are multiple related processes, the processor that executes one process may be different from the processor that executes a different process.

[0035] The processor 101 is, for example, a CPU (Central Processing Unit), an MPU (Micro Processing Unit), or a DSP (Digital Signal Processor). At least some of the functions that the processor 101 implements by executing a program may be implemented by electronic circuits such as an ASIC or a PLD (Programmable Logic Device).

[0036] Memory 102 is used as the main memory of the classical computer 100. Memory 102 temporarily stores at least a portion of the OS (Operating System) program and application programs that are to be executed by the processor 101. Memory 102 also stores various data used for processing by the processor 101. For memory 102, a volatile semiconductor memory device such as RAM (Random Access Memory) is used.

[0037] Peripheral devices connected to bus 100a include a storage device 103, a graphics controller 104, an input interface 105, an optical drive device 106, a device connection interface 107, a network interface 108, and a communication interface 109.

[0038] The storage device 103 electrically or magnetically writes and reads data from its built-in recording medium. The storage device 103 is used as an auxiliary storage device for the classical computer 100. The storage device 103 stores the OS program, application programs, and various data. For example, the storage device 103 can be an HDD (Hard Disk Drive) or an SSD (Solid State Drive).

[0039] The graphics controller 104 is an arithmetic unit that performs image processing. The graphics controller 104 is, for example, a GPU (Graphics Processing Unit). A monitor 21 is connected to the graphics controller 104. The graphics controller 104 displays images on the screen of the monitor 21 according to instructions from the processor 101. The monitor 21 can be an OLED (Electroluminescence) display device or a liquid crystal display device. If a GPU is used as the graphics controller 104, the graphics controller 104 can also perform complex numerical calculations such as matrix calculations.

[0040] The input interface 105 is connected to a keyboard 22 and a mouse 23. The input interface 105 transmits signals from the keyboard 22 and mouse 23 to the processor 101. Note that the mouse 23 is just one example of a pointing device; other pointing devices can also be used. Other pointing devices include touch panels, tablets, touchpads, and trackballs.

[0041] The optical drive device 106 uses laser light or the like to read data recorded on the optical disc 24 or write data to the optical disc 24. The optical disc 24 is a portable recording medium on which data is recorded in a way that makes it readable by the reflection of light. Examples of optical discs 24 include DVD (Digital Versatile Disc), DVD-RAM, CD-ROM (Compact Disc Read Only Memory), and CD-R (Recordable) / RW (ReWritable).

[0042] The device connection interface 107 is a communication interface for connecting peripheral devices to the classical computer 100. For example, a memory device 25 and a memory reader / writer 26 can be connected to the device connection interface 107. The memory device 25 is a recording medium equipped with a communication function with the device connection interface 107. The memory reader / writer 26 is a device that writes data to or reads data from the memory card 27. The memory card 27 is a card-type recording medium.

[0043] The network interface 108 is connected to the network 20. The network interface 108 transmits and receives data to and from other computers or communication devices via the network 20. The network interface 108 is a wired communication interface, for example, connected by cable to a wired communication device such as a switch or router. Alternatively, the network interface 108 may be a wireless communication interface, connected by radio waves to a wireless communication device such as a base station or access point.

[0044] The communication interface 109 is connected to the quantum computer 200. The communication interface 109 communicates with the quantum computer 200. For example, the communication interface 109 sends quantum gate operation instructions based on quantum circuits to the quantum computer 200. The communication interface 109 also receives the execution results of quantum circuits from the quantum computer 200.

[0045] The classical computer 100 can realize the processing functions of the second embodiment with the hardware described above. The device shown in the first embodiment can also be realized with hardware similar to that of the classical computer 100 shown in Figure 3.

[0046] The classical computer 100 implements the processing functions of the second embodiment by executing a program recorded on a computer-readable recording medium, for example. The program describing the processing to be executed by the classical computer 100 can be recorded on various recording media. For example, the program to be executed by the classical computer 100 can be stored in the storage device 103. The processor 101 loads at least a portion of the program in the storage device 103 into the memory 102 and executes the program. Alternatively, the program to be executed by the classical computer 100 can be recorded on a portable recording medium such as an optical disc 24, a memory device 25, or a memory card 27. The program stored on the portable recording medium becomes executable after being installed in the storage device 103, for example, under control from the processor 101. The processor 101 can also directly read and execute the program from the portable recording medium.

[0047] The quantum computer 200 comprises a control unit 210, a qubit device 220, and a high-frequency signal generator 230. Although the control unit 210 is located within the quantum computer 200, it is fundamentally a classical computer.

[0048] The control device 210 performs gate operations on the qubits in the qubit device 220 according to instructions from the classical computer 100. For example, the control device 210 transmits a control signal to the high-frequency signal generator 230 instructing it to irradiate the qubit with microwaves of a predetermined frequency.

[0049] The control device 210 includes an arithmetic circuit 210a and a memory 210b. The arithmetic circuit 210a is a logic circuit such as a processor or ASIC, or a combination thereof. The arithmetic circuit 210a performs decoding processing based on the results of syndrome measurement, for example, and determines whether or not there is an error in the logical Z operator or logical X operator. The memory 210b stores data used for decoding, for example.

[0050] The qubit device 220 has multiple qubits. The qubit device 220 may have qubits of various types, such as superconducting, ion trapping, or cold atom types. The qubit device 220 is sometimes also called a QPU (Quantum Processing Unit).

[0051] The high-frequency signal generator 230 generates high-frequency signals to manipulate or measure the qubits in the qubit device 220, in accordance with the control signal from the control device 210. The generated high-frequency signals manipulate the qubits in the qubit device 220.

[0052] A user of the quantum computing system 300 uses a terminal device 30 to generate a quantum circuit for solving a problem, for example, using quantum computation. When the user instructs the terminal device 30 to execute a quantum computation, the terminal device 30 transmits a quantum computation request, including the generated quantum circuit, to the quantum computing system 300.

[0053] In the quantum computing system 300, the classical computer 100 instructs the quantum computer 200 to perform quantum calculations based on quantum circuits in response to quantum computation requests. At this time, the classical computer 100 converts the quantum circuit to be executed into a quantum circuit using executable quantum gates, in accordance with the hardware specifications of the quantum computer 200 (such as native gates corresponding to the qubit device). The classical computer 100 transmits a quantum circuit execution instruction to the quantum computer 200, which includes information such as the timing of the operation of the quantum gates shown in the converted quantum circuit and the intensity of the microwaves used for operation. The quantum computer 200 performs gate operations on the qubits and measures the state of the qubits according to the quantum circuit execution instruction. The quantum computer 200 then transmits the measurement results to the classical computer 100.

[0054] Such a system makes it possible to perform quantum computations using qubits. Because the state of physical qubits is fragile, encoded logical qubits are used in quantum computations.

[0055] Figure 4 shows an example of qubit coding. In quantum computing, qubit 31 corresponds to the bits in classical computing. In addition to the states "|0>" and "|1>", qubit 31 has a superposition state "(|0>+|1>) / 2 1 / 2 You can take "".

[0056] Quantum bit 31 is very fragile. Therefore, in quantum computer 200, encoding is performed to combine multiple physical qubits into a single logical qubit 32. A typical error correction code is surface coding. In surface coding, the state of logical qubit 32 is represented by multiple data qubits 32a. In addition, multiple auxiliary qubits 32b are provided for error detection.

[0057] The bit sequences of the data qubits at the edges of logical qubit 32 constitute the logical X operator 32c. The state of the data qubits constituting the logical X operator 32c indicates the measurement value obtained when a projection measurement is performed on logical qubit 32.

[0058] Figure 4 shows multiple auxiliary qubits 32b for the X stabilizer, but there are also multiple auxiliary qubits for the Z stabilizer that are not shown. Furthermore, the logic qubit 32 includes a bit sequence of data qubits representing the logic Z operator. The following explanation primarily describes the quantum error correction technique for the logic X operator using multiple auxiliary qubits 32b for the X stabilizer, but it is similarly applicable to quantum error correction for the logic Z operator using multiple auxiliary qubits for the Z stabilizer.

[0059] Figure 5 shows an example of an error that can occur in a logical qubit. Errors can occur in the physical qubits that make up the logical qubit 32. An error that occurs in any of the multiple data qubits 32a can be detected by the auxiliary qubit adjacent to the data qubit where the error occurred.

[0060] For each auxiliary qubit, if the number of erroneous data qubits among its neighbors is odd, the syndrome measurement value inverts from "+1" to "-1". On the other hand, for each auxiliary qubit, if the number of erroneous data qubits among its neighbors is even, the syndrome measurement value does not invert.

[0061] In the example in Figure 5, Z errors occur in each of the data qubits 33a to 33d. When a syndrome measurement is performed on the auxiliary qubits 34a to 34d adjacent to the data qubits 33a to 33d where the Z errors occurred, an inverted measurement is obtained. Since the auxiliary qubit 34e is adjacent to the two data qubits 33c and 33d where the errors occurred, the measurement value of the syndrome measurement is not inverted.

[0062] In quantum error correction, the location of an error in a data qubit is estimated based on the syndrome measurement values ​​of each auxiliary qubit. The function that identifies the location of an error from the syndrome measurement values ​​of a code, such as a surface code, is called a decoder. A decoding graph, for example, is used by the decoder to estimate the location of the error.

[0063] Figure 6 shows an example of error location estimation processing using a decode graph. For example, a decode graph 35 is generated based on the measurement results of syndrome measurements of multiple auxiliary qubits (for X stabilizers) that constitute the logical qubit 32.

[0064] The decode graph 35 is a graph in which the results of syndrome measurements in auxiliary qubits are used as vertices (nodes), and adjacent data qubits that share common auxiliary qubits are connected by edges. In quantum error correction, the syndrome measurement is performed repeatedly multiple times so that errors that occur during the syndrome measurement can also be detected. Based on the results of these multiple syndrome measurements, the location of the error is estimated.

[0065] The results of multiple syndrome measurements on a particular auxiliary qubit are represented by the difference (exclusive OR) between the result of the most recent syndrome measurement and the result of the previous one. A syndrome measurement result expressed as such a difference is called a difference syndrome. In the first syndrome measurement, if the measurement value is reversed in that measurement, the result of the difference syndrome measurement will also be reversed. In subsequent syndrome measurements, if a different measurement value is obtained from the previous measurement, the result of the difference syndrome measurement will also be reversed.

[0066] In the decode graph 35, a flag indicating that the measurement value has been inverted (shown as a star in Figure 6) is set at the vertices that represent the auxiliary qubits 34a to 34d corresponding to the difference syndrome in which the measurement value has been inverted.

[0067] The surface code decoder finds an error occurrence pattern for the data qubits such that the syndrome measurement values ​​for the auxiliary qubits 34a to 34d are inverted in the decode graph 35. Multiple error occurrence patterns may be generated. In the example in Figure 6, an error occurrence pattern indicating that an error occurred in data qubits 33a to 33d and an error occurrence pattern indicating that an error occurred in data qubits 33c to 33e can be generated.

[0068] In the decoder, a different error pattern may be estimated (Z error occurring at data qubits 33c to 33e) than the actual error pattern (Z error occurring at data qubits 33a to 33d). In the estimated error pattern (Z error occurring at data qubits 33c to 33e), the number of data qubits where the error occurred within the logical X operator 32c is "0". In contrast, in reality, Z errors occurred at two data qubits 33a and 33b within the logical X operator 32c.

[0069] As shown above, the estimated location of the error may be incorrect. However, if there is no difference in whether the number of errors in the logical X operator 32c is even or odd, it will not result in a logical error. In the example in Figure 6, the estimated number of errors in the logical X operator 32c is "0" (even), while the actual number of errors is "2" (even). In this case, since both the actual number of errors and the estimated number of errors are even, it does not result in a logical error.

[0070] Figure 7 shows an example of the error location estimation process for logical errors. In the example in Figure 7, a Z error occurs in data qubits 33b, 33f, and 33h. In this case, the measured values ​​of the syndrome measurement in auxiliary qubits 34b, 34c, 34f, and 34g are inverted. Then, a decode graph 36 corresponding to the measurement result of that syndrome measurement is generated.

[0071] Based on the decode graph 36, it is possible to estimate the location of the error, for example, that a Z error occurred in data qubits 33h, 33i to 33k. In this case, although the actual number of errors in the logical X operator 32c is "1" (odd), the estimated number of errors becomes "0" (even). As a result, a logical error occurs in logical qubit 32.

[0072] Thus, the decoder only needs to be able to estimate whether the errors occurred even or odd times in the logical operators. Furthermore, since quantum data correction is performed repeatedly during the quantum computation process, decoding is required in a very short time, for example, within 1 μs.

[0073] As explained in Figures 6 and 7, the location of errors in data qubits can be estimated by using a decode graph. At this time, it is important to reduce the possibility of logical errors due to the difference between the estimated error location and the actual error location. Therefore, algorithms have been devised to estimate error patterns by calculating minimum-weight perfect matching (MWPM) between syndromes. This algorithm is called an MWPM decoder.

[0074] Figure 8 shows an example of error pattern estimation by the MWPM decoder. In the example in Figure 8, when a syndrome measurement was performed on logic qubit 32, an inversion of the measured values ​​was detected in auxiliary qubits 34b, 34c, 34i, and 34j. A decode graph 37 is generated based on the results of the syndrome measurement.

[0075] In MWPM, error weights are assigned to the edges connected to the vertices of the decode graph 37. The error weight of an edge is the physical error probability p of the data qubit corresponding to the edge. e It is calculated based on the error weight w. e It can be calculated using the following formula.

[0076]

number

[0077] The error weight w shown in equation (1) e p is the probability of a physical error. e The larger the value, the smaller the value. In MWPM, for example, based on the decode graph 37, the error occurrence pattern that minimizes the sum of error weights of the edges corresponding to the data qubit where the error occurred is identified among the possible error occurrence patterns. Then, it is estimated that an error of the identified error occurrence pattern has occurred.

[0078] In the example in Figure 8, the weight of the edge connecting vertices 37a and 37b, which correspond to the inverted auxiliary qubits 34c and 34j, is "20". In contrast, the weight of the edge connecting vertex 37a and vertex 37c is "0.1", the weight of the edge connecting vertex 37c and vertex 37d is "0.1", and the weight of the edge connecting vertex 37d and vertex 37b is "0.1". Then the sum of the weights of the edges on the path 37e (dashed polyline) from vertex 37a to vertex 37b via vertices 37c and 37d is "0.3". Therefore, the sum of the weights of the edges on this path 37e is smaller. Consequently, it is presumed that an error occurred in the data qubit corresponding to the edge on path 37e.

[0079] Figure 9 shows an example of the processing procedure for the MWPM decoder. For example, suppose the difference syndromes corresponding to the six vertices 38a to 38f of the decode graph 38 are inverted. Dijkstra's algorithm is performed on all combinations of the inverted difference syndromes to generate the complete graph 39.

[0080] The complete graph 39 has vertices 39a to 39f, each corresponding to an inverted difference syndrome. Each of the vertices 39a to 39f is connected to all other vertices by edges. Each edge of the complete graph 39 is assigned an error weight.

[0081] The error weights for edges in the complete graph 39 are, for example, the sum of the error weights for edges on the connection path in the decode graph 38 in the difference syndrome corresponding to the vertices at both ends of the edge. In the example in Figure 9, for simplicity, the error weights for edges in the complete graph 39 are set assuming that the error weight set for each edge in the decode graph 38 is "1".

[0082] Based on the complete graph 39, error occurrence patterns are estimated by MWPM. MWPM is performed, for example, by the Blossom algorithm. For example, it is estimated that errors occurred in the data qubits corresponding to the edges connecting vertices 39a and 39b, the data qubits corresponding to the edges connecting vertices 39c and 39e, and the data qubits corresponding to the edges connecting vertices 39d and 39f.

[0083] The complete graph 39, which contains information about the error locations, is returned to the decoded graph 38. In the decoded graph 38 after MWPM execution, information indicating that the edges where errors occurred are located (dotted lines in Figure 9) is added to the edges where errors occurred.

[0084] Such MWPM decoder algorithms calculate weights for every edge of the complete graph 39, resulting in high computational complexity. Therefore, it is conceivable to estimate the location of errors without using the complete graph 39. For example, one method involves expanding clusters centered around the difference syndrome.

[0085] Figure 10 shows an example of how to expand a cluster. For example, suppose a Z error occurs in three data qubits 33a, 33c, and 33d. In this case, a difference syndrome of inverted measurements is obtained in the auxiliary qubits 34a, 34c, and 34d. A decode graph 40 is created from the syndrome measurement results. Clusters 40d to 40f are generated, each centered on vertices 40a to 40c corresponding to the inverted difference syndrome in the decode graph 40. The initial state of clusters 40d to 40f is a circle centered on vertices 40a to 40c, with a radius half the length of its sides.

[0086] Of the generated clusters 40d to 40f, cluster 40d has reached the region representing the logical X operator. In this case, it is presumed that an error has occurred in the data qubits constituting the logical X operator, and the expansion of cluster 40d is stopped.

[0087] Clusters 40e and 40f are gradually expanded. As a result, clusters 40e and 40f come into contact with each other. It is then estimated that an error occurred in the data qubits corresponding to the two edges connecting clusters 40e and 40f. With this method of expanding clusters 40d to 40f, the complete graph 39 shown in Figure 9 is unnecessary.

[0088] However, the method of expanding clusters 40d to 40f requires storing information about which edges belong to which cluster originating from which difference syndrome. If the sign distance is d and the degree of the graph (number of edges connected to a vertex) is "12", the amount of memory used is approximately "12d" of the records that indicate the information to be stored. 3 This will be equivalent to the capacity of ' items.

[0089] To repeatedly perform decoding in a short time of less than 1 μs, the amount of data referenced should be as small as possible. Therefore, algorithms that reference a large amount of data are unsuitable. Furthermore, to repeatedly perform decoding during the quantum computation process, it is efficient to perform the decoding in a device near the qubit device 220, such as the control device 210 of the quantum computer 200, using a logic circuit like an FPGA or ASIC. However, it is not practical to incorporate a large amount of memory within a logic circuit.

[0090] Implementing this cluster expansion method faithfully would result in insufficient memory. Therefore, it is conceivable to calculate the distance between differential syndromes using Manhattan distance including hook errors, without storing values ​​on the edges (see Non-Patent Document 1 mentioned above). However, this method may not yield sufficient performance in real-world environments that deviate from the error model.

[0091] Another method for estimating the location of an error is to use a decoder based on the Ising model (an Ising decoder). FIG. 11 is a diagram showing an example of decoding using an Ising model. For example, similar to the logical qubit 32 shown in FIG. 6, it is assumed that Z errors occur in four data qubits 33a to 33d, and a decoding graph 35 is generated. In this case, spins of the Ising model (arrows on the sides in FIG. 11) are associated with each side of the decoding graph 35. Then, an Ising model for obtaining a Hamiltonian H as shown in the following equation (2) is defined.

[0092]

Number

[0093] V is the total number of differential syndromes. b v is the presence or absence of inversion of the v-th differential syndrome (+1 if not inverted, -1 if inverted). σ e is the value of the spin of the e-th side. σ e is, for example, +1 when no error has occurred in the data qubit corresponding to the relevant side, and -1 when an error has occurred. E is the number of sides (equal to the number of data qubits). δv is the side connected to the v-th differential syndrome. J and h are predetermined coefficients (positive real numbers).

[0094] The value of the spin of each side that minimizes the cost function shown on the right side of equation (2) is obtained by an Ising solver. When the value of the cost function is minimized, it is estimated that an error has occurred in the data qubit corresponding to the side where the spin value is -1.

[0095] In this way, the error occurrence location can be estimated by an Ising decoder based on the decoding graph 35. However, since the Ising decoder assigns spin values to all sides, a large amount of memory is required in the same way as the method of expanding clusters.

[0096] As described above, implementing a decoding function for estimating the location of errors using an FPGA or ASIC is effective, but this requires reducing the amount of memory used. Therefore, the quantum computing system 300 assigns addresses to each region of the decoding graph and generates a simplified decoding graph that connects only the difference syndromes between nearby addresses during decoding. By performing decoding using the simplified decoding graph, decoding becomes possible with less memory capacity. As a result, the decoding function can be implemented in the control device 210, for example. Below, we will specifically explain how to implement decoding using the simplified decoding graph, taking the case where the decoding function is implemented in the control device 210 as an example.

[0097] Figure 12 is a block diagram showing an example of a quantum computing function involving decoding using a simplified decode graph. For example, the control device 210 includes a qubit device management unit 211, a gate operation unit 212, a measurement result acquisition unit 213, and an error detection unit 214.

[0098] The qubit device management unit 211 manages the state of the physical qubits within the qubit device 220. For example, the qubit device management unit 211 manages the timing of gate operations on the physical qubits, manages the timing of measuring the state of the physical qubits, and records the measurement results.

[0099] For example, the qubit device management unit 211 receives a gate operation request from the classical computer 100, corresponding to the quantum circuit that corresponds to the problem to be solved. The gate operation request includes the physical qubit to be used, the coding scheme, the code distance, the content of the gate operation, and the parameters for the gate operation. Parameters for the gate operation include the microwave intensity, the timing of the syndrome measurement, and the number of times the syndrome measurement is repeated. The qubit device management unit 211 instructs the gate operation unit 212 to perform a gate operation or measurement of the physical qubit according to the information it has received.

[0100] The qubit device management unit 211 also obtains the measurement results from the measurement result acquisition unit 213 when all gate operations and measurements of the quantum circuit are completed. The qubit device management unit 211 obtains error information that occurred during the calculation process from the error detection unit 214 and corrects the measurement results based on the error information. For example, if a logic error in the logic X operator is recorded, the state of the logic X operator obtained from the measurement results is corrected to obtain the final measurement result. The qubit device management unit 211 transmits the measurement results corrected based on the error information to the classical computer 100.

[0101] The gate operation unit 212 controls the high-frequency signal generator 230 according to the quantum circuit input from the classical computer 100, causing it to perform gate operations or measurement operations on the qubit device 220. In between gate operations according to the quantum circuit corresponding to the problem to be solved, the gate operation unit 212 also controls the high-frequency signal generator 230 to perform gate operations or measurements for syndrome measurement.

[0102] When a measurement operation is performed on a physical qubit, the measurement result acquisition unit 213 acquires the measurement result from the high-frequency signal generator 230. When the measurement result acquisition unit 213 acquires the measurement result of the measurement shown in the quantum circuit corresponding to the problem to be solved, it transmits the measurement result to the qubit device management unit 211. Also, when the measurement result acquisition unit 213 acquires the measurement result of the syndrome measurement, it transmits the measurement result to the error detection unit 214.

[0103] The error detection unit 214 detects errors in logical qubits based on the measurement results of the syndrome measurement. The error detection unit 214 includes a graph construction unit 214a, a storage unit 214b, and a decoder 214c.

[0104] The graph construction unit 214a constructs a simplified decode graph. For example, the graph construction unit 214a divides the unsimplified decode graph into multiple regions. The graph construction unit 214a then generates a decode graph consisting of edges connecting vertices corresponding to inverted difference syndromes in two regions within a predetermined distance, and vertices connected to those edges.

[0105] Furthermore, when a syndrome measurement is performed, the graph construction unit 214a obtains the measurement results from the storage unit 214b. Based on the measurement results of the syndrome measurement, the graph construction unit 214a generates a simplified decoded graph from a pre-generated decoded graph.

[0106] The memory unit 214b stores information such as the addresses of regions obtained by dividing the decode graph, whether or not the difference syndrome is reversed, the connection relationships between difference syndromes, and the decode result. The memory unit 214b also stores the decode graph before simplification (including information on the divided regions and their addresses) and the decode graph after simplification.

[0107] The decoder 214c estimates the location of errors using a simplified decoding graph based on the syndrome measurement results. Then, based on the estimated location of errors, the decoder 214c determines whether or not each of the multiple logic qubits has a logic error. The decoder 214c stores the information regarding the presence or absence of errors for each logic qubit in the storage unit 214b.

[0108] By controlling the qubit device 220 with such a control device 210, quantum computations according to the quantum circuit are performed while detecting errors in the logical qubits. The processing procedure in the control device 210 will be described in detail below.

[0109] Figure 13 shows an example of the processing steps for a quantum circuit-based calculation. The process shown in Figure 13 will be explained below according to the step numbers. [Step S101] The qubit device management unit 211 receives a gate operation request from the classical computer 100, corresponding to the quantum circuit that corresponds to the problem to be solved.

[0110] [Step S102] The error detection unit 214 performs a decode graph region division process. Details of the decode graph region division process will be described later (see Figure 14). [Step S103] The qubit device management unit 211 determines the next gate operation or measurement to be performed and instructs the gate operation unit 212 to perform that gate operation or measurement. The gate operation unit 212 performs the gate operation or measurement operation on the specified physical qubit according to the instruction. The gate operation or measurement at this time may be the gate operation or measurement shown in the quantum circuit corresponding to the problem to be solved, or the gate operation or measurement for syndrome measurement.

[0111] When a measurement operation is performed, the measurement result acquisition unit 213 acquires the measurement result. If the measurement result acquisition unit 213 acquires the measurement result of the measurement indicated on the quantum circuit to be solved, it transmits the measurement result to the qubit device management unit 211. If the measurement result acquisition unit 213 acquires the measurement result of a syndrome measurement, it stores the measurement result in the storage unit 214b of the error detection unit 214.

[0112] [Step S104] The graph construction unit 214a of the error detection unit 214 determines whether it has acquired a predetermined number of syndrome measurement results at the error detection timing by syndrome measurement. If the graph construction unit 214a has acquired the predetermined number of syndrome measurement results, it proceeds to step S105. If the graph construction unit 214a has not acquired the predetermined number of syndrome measurement results, it proceeds to step S108.

[0113] [Step S105] The error detection unit 214 performs a decoding process. Details of the decoding process will be described later (see Figure 20). [Step S106] The decoder 214c of the error detection unit 214 determines whether or not there is an error in the logical qubit. If there is an error, the decoder 214c proceeds to step S107. If there is no error, the decoder 214c proceeds to step S108.

[0114] [Step S107] The decoder 214c records the error details in the memory unit 214b. The error details include information such as which logical qubit is affected and the type of error. The type of error is, for example, whether it is an inversion error of the logical X operator or an inversion error of the logical Z operator.

[0115] [Step S108] The qubit device management unit 211 determines whether the execution of the quantum circuit has finished. If the execution of the quantum circuit has finished, the qubit device management unit 211 proceeds to step S109. If the execution of the quantum circuit has not finished, the qubit device management unit 211 proceeds to step S103.

[0116] [Step S109] The qubit device management unit 211 outputs the measurement results corrected based on the errors that occurred to the classical computer 100. As described above, gate operations are performed according to the quantum circuit, and the measurement results after the gate operations are corrected based on the errors that occurred. Next, the decode graph domain partitioning process will be explained in detail.

[0117] Figure 14 is a flowchart showing an example of the decode graph region partitioning process. The process shown in Figure 14 will be explained below according to the step numbers. [Step S121] The graph construction unit 214a of the error detection unit 214 divides the region of the decode graph into subregions. For example, the graph construction unit 214a divides the three-dimensional space of the decode graph, which is represented by two axes of a plane showing the arrangement of physical qubits constituting logical qubits and an axis (time axis) showing the number of syndrome measurements, in each axis direction.

[0118] [Step S122] The graph construction unit 214a assigns addresses (i, j, k) to the subregions (where i, j, k are natural numbers). For example, the graph construction unit 214a represents the positions of the divided regions on the two axes of the plane showing the arrangement of physical qubits with "i" and "j", and the position of the divided region in the time axis direction with "k".

[0119] [Step S123] The graph construction unit 214a calculates the average weight of the sub-regions. For example, for each sub-region, the graph construction unit 214a identifies the edges connected to the vertices in the decode graph that are included in that sub-region. Then, for each sub-region, the graph construction unit 214a calculates the average weight of the identified edges in the decode graph. The graph construction unit 214a uses the calculation result as the average weight of each sub-region.

[0120] The decoding graph region partitioning process will be explained in detail below with reference to Figures 15 to 19. Figure 15 shows an example of a three-dimensional decoding graph. For example, each time a gate operation is performed on a logic qubit, multiple syndrome measurements are performed, and measurement results 51, 52, ... are obtained for each syndrome measurement. One measurement result 51 can be represented by a graph 51a having a vertex indicating the auxiliary qubit being measured and a line connecting auxiliary qubits connected to the same data qubit. Graph 51a can be represented by a plane consisting of, for example, the X axis and the Y axis.

[0121] When the measurement results 51, 52, ... from multiple syndrome measurements are arranged in accordance with the elapsed time from the first syndrome measurement to the acquisition of the measurement results, the measurement results 51, 52, ... are placed on the time axis. By connecting the vertices of the graphs representing each of the measurement results 51, 52, ... that are consecutive in the time direction and correspond to the same auxiliary qubit with edges, a three-dimensional decode graph 60 is obtained.

[0122] Figure 16 shows an example of the decode graph partitioning process. For example, the space in which the decode graph 60 exists is divided in the direction of each of the three axes. The partitioning generates multiple subregions 61a, 61b, ... of a rectangular prism. In the example in Figure 16, each axis is divided into subregions 61a, 61b, ... each containing three vertices corresponding to auxiliary qubits.

[0123] In the decoded graph 60 shown in Figure 16, a maximum of 6 edges are connected to a single vertex. However, if errors occurring during syndrome measurement are also taken into consideration, a maximum of 12 edges can be connected to a single vertex (maximum degree is "12").

[0124] Figure 17 shows an example of a divided decode graph. The decode graph 62 shown in Figure 17 is divided into partitioned regions with α vertices in each of the spatial and temporal axes. Each of these partitioned regions is assigned an address.

[0125] Figure 18 shows an example of addresses assigned to partitioned regions. Figure 18 shows the addresses of the partitioned regions located closest to the viewer in the time axis direction of the decode graph 62. The addresses are represented as (i, j, k). i indicates the position in the horizontal axis direction (X axis) of space. j indicates the position in the vertical axis direction (Y axis) of space. k indicates the position in the time axis direction. A weighted average value is also calculated for each partitioned region.

[0126] Figure 19 shows an example of the weight average of a divided region. In Figure 19, the weight average of the subregion at address (i,j,k) is "W (i,j,k) (W is overlined). The weighted average is, for example, the average of the weights of the edges connected to the vertices included in the subdomain.

[0127] Once the syndrome measurement is performed, a decoding process is executed based on the decode graph 62, which has been divided into sub-regions, to determine whether or not there are errors in the logical qubits. Figure 20 is a flowchart showing an example of the decoding process. The process shown in Figure 20 will be explained below according to the step numbers.

[0128] [Step S131] The graph construction unit 214a constructs the vertex S of the inverted difference syndrome. i Select this option. [Step S132] The graph construction unit 214a constructs the vertex S of the inverted difference syndrome. i The vertices of the inverted difference syndrome belonging to other neighboring subregions of the subregion to which belongs are listed in order of proximity, S. j Selected as such. Neighboring subregions are, for example, subregions whose address difference from the subregion to which it belongs is less than or equal to a predetermined value. The address difference is, for example, the Manhattan distance.

[0129] [Step S133] The graph construction unit 214a constructs vertex S i and vertex S j The graph construction unit 214a determines whether the difference in addresses of the subregions to which and belong is less than or equal to γ. γ is a non-negative integer. If the difference in addresses is less than or equal to γ, the graph construction unit 214a proceeds to step S135. If the difference in addresses exceeds γ, the graph construction unit 214a proceeds to step S134.

[0130] [Step S134] The graph construction unit 214a uses the values ​​obtained by approximate calculation as weights for the vertices S i and vertex S j The points are connected by edges. For example, the graph construction unit 214a has vertices S i From the subregion to which it belongs, vertex S j The weight is calculated based on the average weight of each subregion along the path to the subregion to which the vertex S belongs. Specifically, the graph construction unit 214a further averages the average weight of each subregion along the path and assigns the weight to the resulting average value. i and vertex S j The Manhattan distance is multiplied. Then, the graph construction unit 214a proceeds to step S136.

[0131] [Step S135] The graph construction unit 214a uses the values ​​obtained by high-precision calculation as weights for the vertices S iand vertex S j Connect and with edges. For example, the graph construction unit 214a uses, for example, the A* algorithm to construct vertices S on the decoded graph before simplification. i and vertex S j The graph construction unit 214a then identifies the path with the minimum weight connecting the two points. The graph construction unit 214a then calculates the sum of the weights of each edge on the identified path, and assigns it to the vertex S i and vertex S j This represents the weight of the edge connecting the two points.

[0132] [Step S136] The graph construction unit 214a constructs vertex S i The degree of (vertex S) i The graph construction unit 214a determines whether the number of connected edges has reached β. β is a natural number that represents the maximum degree of the simplified decoded graph. If the degree has reached β, the graph construction unit 214a proceeds to step S137. If the degree has not reached β, the graph construction unit 214a proceeds to step S132.

[0133] In this way, by setting an upper limit β for the degree and preventing the generation of vertices with a degree greater than β, the complexity of the simplified decode graph is suppressed. [Step S137] The graph construction unit 214a determines whether all of the vertices of the inverted difference syndrome have been selected. If all of the relevant vertices have been selected, the graph construction unit 214a proceeds to step S138. If there are any unselected vertices, the graph construction unit 214a proceeds to step S131.

[0134] [Step S138] The decoder 214c performs decoding using the graph (simplified decode graph) generated by the processing in steps S131 to S137, and determines whether or not there is a logical error.

[0135] In this way, decoding is performed using a simplified decoding graph, and the presence or absence of logical errors can be determined. The simplification of the decoding graph enables decoding in a short amount of time.

[0136] The decoding process using the simplified decoding graph will be explained in detail below with reference to Figures 21 and 22. Figure 21 shows an example of a simplified decode graph. Among the auxiliary qubits corresponding to the vertices (lattice points) of the unsimplified decode graph 63, the inverted difference syndrome is measured in the auxiliary qubits corresponding to vertices 63a to 63f, indicated by asterisks. The decode graph 63 is divided into multiple subregions with thick rectangles as boundaries. In this example, vertices on the boundary lines are assumed to belong to both subregions touching the boundary line.

[0137] Here, we focus on one vertex 63a that corresponds to the inverted difference syndrome. This vertex 63a belongs to the subregion at address (2,1,0). In this example, the difference syndromes belonging to the eight subregions surrounding the subregion to which the focused vertex 63a belongs are the ones for which the distance between vertices of the difference syndrome is calculated. In the example in Figure 21, vertices 63b to 63d are included in the distance calculation, while vertices 63e to 63f are not.

[0138] Of the vertices whose distances are being calculated, vertices 63b to 63c belong to the same subdomain (2,1,0) as the vertex 63a that is under consideration. Therefore, accurate distance calculations are performed between vertex 63a and vertices 63b to 63c. The A* algorithm is one example of an accurate distance calculation method.

[0139] For example, one path that can be traced from vertex 63a to vertex 63b has edges with weights of "0.2", "0.1", and "0.5" respectively. The sum of the weights of the edges in this path is "0.8". Another path that can be traced from vertex 63a to vertex 63b has edges with weights of "0.2", "0.7", and "0.3" respectively. The sum of the weights of the edges in this path is "1.2". The minimum sum of the weights is "0.8", and the distance between vertex 63a and vertex 63b is calculated as "0.8".

[0140] Furthermore, one path that can be traced from vertex 63a to vertex 63c has edge weights of "0.1" and "0.4" respectively. The sum of the edge weights in this path is "0.5". Another path that can be traced from vertex 63a to vertex 63c has edge weights of "0.2" and "0.8" respectively. The sum of the edge weights in this path is "1.0". The minimum sum of the weights is "0.5", and the distance between vertex 63a and vertex 63c is calculated as "0.5".

[0141] Of the vertices whose distance is being calculated, vertex 63d belongs to a subregion at a different address (1,2,0) than the vertex 63a that is under consideration. Therefore, the distance between vertex 63a and vertex 63d is calculated using a fast approximate method.

[0142] In the example in Figure 21, the average weight of the subregion to which the vertex 63a belongs is "0.4". The average weight of the subregion to which vertex 63d belongs is "0.8". The Manhattan distance between vertex 63a and vertex 63d on the decode graph 63 is "7". In this case, the distance between vertex 63a and vertex 63d is "{(0.4+0.8) / 2}×7=4.2". By performing distance calculations using this approximation method, it becomes easier to calculate the distance between vertices belonging to neighboring subregions.

[0143] Vertices for which distance calculations have been performed are connected by edges. Each edge is assigned a weighted distance between the vertices connected by that edge. By focusing on each of the vertices 63b through 63f (excluding vertex 63a) and performing distance calculations and edge connections, a simplified decode graph is generated. Then, the decoding process is performed using this simplified decode graph.

[0144] Figure 22 shows an example of decoding using a simplified decoding graph. In the simplified decoding graph 64, vertices that were the subject of distance calculations are connected by edges. The distance obtained from the distance calculation is set as the weight of each edge. The accuracy of the edge weights varies depending on the method of distance calculation (accurate or approximate). The weights of edges connecting far apart vertices use the average weight of the subregion, thus being averaged to the average error model. The weights of edges between nearby vertices use the edge weights from the original decoding graph 63, and the minimum value is set correctly.

[0145] Decoding is performed using this simplified decoding graph 64. Methods such as using Ising data or MWPM can be used for decoding. In the example in Figure 22, the combination of edges 64a to 64c has the minimum sum of weights among the edge combinations corresponding to the inverted difference syndrome. Therefore, the decoding result indicates that an error occurred in the data qubits corresponding to edges 64a to 64c, indicated by the dashed lines.

[0146] The decoder 214c may, during decoding, add edges to at least some of the vertices of the simplified decoding graph 64, for example, via the data qubits that constitute the logical operators. If there are logical X operators on the left and right, and a logical X error is detected, the vertices to which edges are added are, for example, the leftmost and rightmost vertices. The decoder 214c may also add edges to vertices belonging to the left and right edge subregions, connecting to the data qubits that constitute the logical operators.

[0147] For example, decoder 214c adds an edge to a vertex to which an edge is to be added, which can be connected to any of the data qubits constituting the logical operator by the shortest distance. The weight of that edge is, for example, the sum of the weights of the edges in the unsimplified decode graph that correspond to that edge. Adding such edges can suppress decoding failures. Decoding failures occur when an error pattern corresponding to the inverted difference syndrome cannot be found.

[0148] Furthermore, by adding edges that connect to the data qubits that constitute the logical operator, the likelihood of correctly calculating the number of errors in the data qubits constituting the logical operator increases. As a result, the accuracy of detecting logical errors improves.

[0149] Figure 23 shows the accuracy evaluation results when decoding is performed by MWPM using a simplified decoding graph. Graph 71 shows the logical error probability corresponding to the physical error probability when the code distance is "3, 5, 7, 9, 11, 15, 23". In Graph 71, the horizontal axis is the physical error probability and the vertical axis is the logical error probability.

[0150] As shown in Graph 71, if the probability of physical error is below a certain level, the probability of logical error decreases as the code distance increases. In other words, even with a simplified decoding graph, the probability of logical error is suppressed in proportion to the code distance. This indicates that the performance required of a decoder, which is that accuracy improves as the code distance increases, is being met.

[0151] Figure 24 shows the evaluation results of memory usage when decoding is performed using an Ising decoder with a simplified decode graph. Graph 72 shows the memory usage when the physical error probability p is "0.01%, 0.05%, 0.10%, 0.50%, 1.00%" and when a non-simplified decode graph is used (w / o simplification). In Graph 72, the horizontal axis is the code distance and the vertical axis is the number of bits used in the calculation.

[0152] The number of bits used when using an unsimplified decode graph is "12d 3 The number of bits used when using the simplified decoding graph is a value determined through experimentation.

[0153] As shown in Graph 72, the amount of memory required, expressed in bits, is significantly reduced by using a simplified decoding graph. This reduction in memory makes it easier to implement the decoder on an FPGA or ASIC, and facilitates a reduction in the time required for error location estimation.

[0154] [Other embodiments] In the second embodiment, decoding is performed in the control device 210 within the quantum computer 200, but if the communication delay between the quantum computer 200 and the classical computer 100 is sufficiently small, decoding can also be performed within the classical computer 100.

[0155] The control device 210 may determine the value of β, which represents the maximum order of the vertex corresponding to the inverted difference syndrome, based on the physical error probability of the qubit device 220. For example, the control device 210 determines the value of β by the following procedure.

[0156] [Step 1] The control device 210 decodes the decode graph as is without simplifying it, and the logical error probability P original Calculate. [Step 2] The control device 210 sets the initial value of β to "1" (β=1).

[0157] [Step 3] The control device 210 decodes using the simplified decode graph and calculates the logical error probability P simple(β) Calculate. [Step 4] The control device 210 is P original =P simple(β) If the condition is not met, add "1" to β and proceed to step 3.

[0158] [Step 5] In step 4, the control device 210 original =P simple(β) If the condition is met, the value of β at that time is considered the optimal β. In this way, the value of β, which represents the maximum degree of the vertex corresponding to the inverted difference syndrome, can be determined to be an appropriate value. By setting β appropriately, the amount of data used and the computation time can be reduced by simplifying the decode graph, while suppressing a decrease in the accuracy of error location estimation.

[0159] Although embodiments have been illustrated above, the configurations of each part shown in the embodiments can be replaced with others having similar functions. Furthermore, other arbitrary components or processes may be added. Moreover, any two or more configurations (features) from the embodiments described above may be combined. [Explanation of Symbols]

[0160] 1. Qubit device 2. Operation signal generator 3. First Decode Graph 3a,3b,... partial area 4a~4f Second vertex 5. 1st Scope 6. Second Scope 7. Second Decode Graph 7a~7e Second side 10 Information Processing Devices 11 Storage section 12 Processing Units

Claims

1. A first decode graph is generated, having a first vertex corresponding to each of a plurality of first qubits used to detect errors occurring in qubits within a qubit device, and a first edge connecting the first vertices corresponding to each of two of the first qubits whose common qubit is the target of error detection, wherein a first weight is set for the first edge according to the probability of detecting an error in the first qubits corresponding to the first vertices at both ends, A pair of second vertices corresponding to each of the multiple second qubits in which an error was detected by syndrome measurement among the multiple first vertices, wherein the pair is determined to be close based on a first criterion of whether the distance between the second vertices is far or near, Based on the first weight of the first edge included in the path connecting the pair on the first decode graph, the second weight of the second edge connecting the second vertices constituting the pair is determined. A second decode graph is generated having the second vertices that constitute the pair and the second edges connecting the second vertices that constitute the pair, and the second weights are set on the second edges. Based on the second weight of the second edge of the second decode graph, the third qubit where the error occurred is estimated. Processing unit, An information processing device having

2. In the process of identifying the pair, the region in which the first decode graph exists is divided into a plurality of subregions, and based on the first determination criterion regarding the positional relationship of the subregions to which each of the two second vertices to be determined belongs, it is determined whether the distance between the two second vertices to be determined is far or near. The information processing apparatus according to claim 1.

3. In the process of determining the second weight of the second edge, the method for calculating the second weight is determined by whether or not the second criterion for determining that the distance between the subregions to which each of the second vertices constituting the pair belongs is met. The information processing apparatus according to claim 1.

4. In the process of determining the second weight of the second edge, if the positional relationship of the subregion to which each of the second vertices constituting the pair belongs satisfies the second criterion, the second weight is determined by the first calculation method; otherwise, the second weight is determined by a second calculation method that is more approximate than the first calculation method. The information processing apparatus according to claim 3.

5. In the process of determining the second weight of the second edge, for each of the multiple subregions in the first decode graph, the average weight of the first edge in the subregion is calculated, and if the second criterion is not met, the weight of the first edge is replaced with the average weight of the subregion to which the first edge belongs, and the second weight is determined. The information processing apparatus according to claim 4.

6. In the process of identifying the pair, the number of pairs that each of the second vertices forms with other second vertices is prevented from exceeding a predetermined upper limit. The information processing apparatus according to claim 1.

7. A first decode graph is generated, having a first vertex corresponding to each of a plurality of first qubits used to detect errors occurring in qubits within a qubit device, and a first edge connecting the first vertices corresponding to each of two of the first qubits whose common qubit is the target of error detection, wherein a first weight is set for the first edge according to the probability of detecting an error in the first qubits corresponding to the first vertices at both ends, A pair of second vertices corresponding to each of the multiple second qubits in which an error was detected by syndrome measurement among the multiple first vertices, wherein the pair is determined to be close based on a first criterion of whether the distance between the second vertices is far or near, Based on the first weight of the first edge included in the path connecting the pair on the first decode graph, the second weight of the second edge connecting the second vertices constituting the pair is determined. A second decode graph is generated having the second vertices that constitute the pair and the second edges connecting the second vertices that constitute the pair, and the second weights are set on the second edges. Based on the second weight of the second edge of the second decode graph, the third qubit where the error occurred is estimated. An error estimation program that instructs a computer to perform a process.

8. A first decode graph is generated, having a first vertex corresponding to each of a plurality of first qubits used to detect errors occurring in qubits within a qubit device, and a first edge connecting the first vertices corresponding to each of two of the first qubits whose common qubit is the target of error detection, wherein a first weight is set for the first edge according to the probability of detecting an error in the first qubits corresponding to the first vertices at both ends, A pair of second vertices corresponding to each of the multiple second qubits in which an error was detected by syndrome measurement among the multiple first vertices, wherein the pair is determined to be close based on a first criterion of whether the distance between the second vertices is far or near, Based on the first weight of the first edge included in the path connecting the pair on the first decode graph, the second weight of the second edge connecting the second vertices constituting the pair is determined. A second decode graph is generated having the second vertices that constitute the pair and the second edges connecting the second vertices that constitute the pair, and the second weights are set on the second edges. Based on the second weight of the second edge of the second decode graph, the third qubit where the error occurred is estimated. A method for estimating errors when a computer performs a process.

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