Output circuit

Abstract

This provides an output circuit configuration that enables back-gate control while simultaneously achieving both high current drive capability and reduced circuit area. [Solution] The back gate control circuit 101N is provided for at least one of the high-side output transistor Mn1 and the low-side output transistor Mn2. The back gate control circuit 101N includes a resistive element Rb electrically connected between the back gate terminals BGn1 and BGn2 of the output transistors Mn1 and Mn2 and the source terminal S, and a current generation circuit 110N that generates a control current Ib that passes through the resistive element Rb. For N-type output transistors Mn1 and Mn2, the current generation circuit 110N generates a control current Ib in a direction that causes a voltage drop across the resistive element Rb where the voltage at the back gate terminals BGn1 and BGn2 is higher than the voltage at the source terminal S.

Description

Technical Field

[0001] The present disclosure relates to an output circuit.

Background Art

[0002] In recent years, due to the demand for high-speed and large-capacity data communication, the fifth-generation (5G) mobile communication standard is becoming widespread, and the demand for power amplifiers (PAs) using high-frequency power devices represented by GaN and the like for base stations is increasing. Since the power amplifier needs to amplify a high-frequency modulated signal at high speed, deterioration of communication quality due to heat generation of the device often becomes a problem. Therefore, a bias control circuit for appropriately controlling the level of the gate bias voltage of the power amplifier according to temperature is required and is widely used in general PA modules.

[0003] On the other hand, since the RF modulated signal input to the gate of the PA has a high power and its level fluctuates at high speed, the bias control circuit needs to output a current whose peak and polarity fluctuate at high speed on the order of several tens to several hundreds (mA) to drive the load. Furthermore, the output of the PA needs to have the ability to turn on and off a power device with a large area (i.e., having a large gate capacitance) at high speed. Therefore, there is an increasing need to realize an output circuit that has low power consumption and a small circuit area and enables high-speed switching in order to drive the bias control circuit of the PA. Also, the need for such an output circuit is increasing not only for application to PAs.

[0004] In particular, in output circuits for CMOS (Complementary Metal-Oxide-Semiconductor) mixed-signal ASICs (Application Specific Integrated Circuits) where bipolar devices cannot be used, increasing the drive current of MOS transistors (field-effect transistors) of the same size, i.e., improving current drive capability, becomes an important issue in order to suppress the increase in circuit area, due to the fact that the current capability of MOS transistors is smaller than that of bipolar transistors.

[0005] One known technique for increasing the current drive capability of an output circuit is to connect the back gate of a MOS-FET (Field Effect Transistor) to the output terminal to suppress the rise in threshold voltage due to the substrate bias effect. This technique is particularly effective in source follower type output circuit configurations where there is a potential difference between the source and the back gate.

[0006] For example, Japanese Patent Publication No. 5-7149 (Patent Document 1) discloses a configuration in which a switch is placed between the back gate and the output terminal connected to the source, and which is turned on when the output circuit is operating. Turning on this switch can improve the current driving capability by eliminating the substrate bias effect. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Application Publication No. 5-7149 [Overview of the project] [Problems that the invention aims to solve]

[0008] However, the improvement in current driving capability in the output circuit of Patent Document 1 is limited to suppressing the rise in threshold voltage due to the substrate bias effect, and no further effect can be obtained. In other words, it is understood that there is room for improvement in the current driving capability of the output circuit described in Patent Document 1.

[0009] This disclosure was made to solve these problems, and the object of this disclosure is to provide an output circuit configuration that enables back gate control to improve the current driving capability of the output circuit. [Means for solving the problem]

[0010] In certain aspects of this disclosure, an output circuit is provided. The output circuit generates output voltages at an output terminal to which a load is connected, corresponding to a first input voltage and a second input voltage. The output circuit comprises first and second field-effect output transistors and a back gate control circuit provided for at least one of the first and second output transistors. The first output transistor has a gate terminal that receives a first input voltage, connected between a first power supply node that transmits a first power supply voltage and an output terminal to which a load is connected. The second output transistor has a gate terminal that receives a second input voltage, connected between a second power supply node that transmits a second power supply voltage lower than the first power supply voltage and an output terminal. The back gate control circuit includes a first resistive element and a current generating circuit. The first resistive element is electrically connected between the back gate terminal and the source terminal of the corresponding output transistor among the first and second output transistors. The current generating circuit generates a first current that passes through the first resistive element. Furthermore, the current generation circuit generates a control current in a direction that causes a voltage drop across the first resistive element such that the voltage at the back gate terminal is higher than the voltage at the source terminal for the N-type output transistor, and generates a control current in a direction that causes a voltage drop across the first resistive element such that the voltage at the source terminal is higher than the voltage at the back gate terminal for the P-type output transistor. [Effects of the Invention]

[0011] According to this disclosure, in an output transistor equipped with a back gate control circuit, the current driving capability can be improved by performing back gate control, which generates a voltage difference between the back gate terminal and the source terminal in a direction that lowers the threshold voltage of the output transistor. [Brief explanation of the drawing]

[0012] [Figure 1] This is a circuit diagram illustrating the configuration of the output circuit in the comparative example. [Figure 2] This is a circuit diagram illustrating an example of the configuration of the output circuit according to Embodiment 1. [Figure 3] Figure 2 is a circuit diagram illustrating a first example configuration of the current generation circuit shown. [Figure 4] Figure 2 is a circuit diagram illustrating a second example configuration of the current generation circuit shown. [Figure 5] This is a circuit diagram illustrating a third configuration example of the current generation circuit shown in Figure 2. [Figure 6] This is a circuit diagram illustrating a modified configuration of the output circuit according to Embodiment 2. [Figure 7] Figure 6 is a circuit diagram illustrating a first example configuration of the current generation circuit shown. [Figure 8] Figure 6 is a circuit diagram illustrating a second configuration example of the current generation circuit shown. [Figure 9] This is a circuit diagram illustrating a third configuration example of the current generation circuit shown in Figure 6. [Figure 10] This is a conceptual circuit diagram illustrating a first configuration example of the output buffer circuit according to Embodiment 3. [Figure 11] This is a conceptual circuit diagram illustrating a second configuration example of the output buffer circuit according to Embodiment 3. [Figure 12] This is a block diagram illustrating an example configuration of a power amplification module according to Embodiment 3. [Figure 13] This is a circuit diagram illustrating an example of the configuration of the output circuit according to Embodiment 4. [Figure 14]It is a circuit diagram for explaining a configuration example of an output circuit according to a modification of Embodiment 4.

Embodiments for Carrying Out the Invention

[0013] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following, the same or corresponding parts in the drawings are denoted by the same reference numerals, and the description thereof will not be repeated in principle.

[0014] Embodiment 1. (Explanation of Comparative Example) First, a comparative example for explaining the problems in Patent Document 1 will be described in detail.

[0015] FIG. 1 is a circuit diagram for explaining the configuration of an output circuit 10X according to a comparative example. The output circuit 10X in FIG. 1 has the same circuit configuration as the output circuit described in Patent Document 1 (including FIG. 2, more specifically FIG. 20).

[0016] As shown in FIG. 1, the output circuit 10X according to the comparative example includes an N-type transistor Mn1 on the high-side, an N-type transistor Mn2 on the low-side, and a back-gate control circuit 100X. The back-gate control circuit 100X has an N-type transistor M3 and an N-type transistor M4. Note that the N-type transistors Mn1, Mn2, M3, M4 can be replaced with P-type transistors as described in Patent Document 1, but here, a configuration using N-type transistors will be described as a comparative example.

[0017] The N-type transistor Mn1 on the high-side is electrically connected between the power supply node Np and the output terminal No. The N-type transistor Mn1 has a drain terminal connected to the power supply node Np, a source terminal connected to the output terminal No, a gate terminal Gn1, and a back-gate terminal BGn1 connected to the back-gate control circuit 100X.

[0018] Output terminal No is connected to one or more nodes of downstream circuits that constitute the load, and transmits the output voltage Vout of output circuit 10X. Power supply node Np transmits the power supply voltage VDD, and power supply node Ns transmits the power supply voltage VSS. The power supply voltage VSS is either the ground voltage GND or a negative voltage. That is, VDD > VSS holds true.

[0019] The low-side N-type transistor Mn2 is electrically connected between the output terminal No and the power supply node Ns. The N-type transistor Mn2 has a source terminal connected to the power supply node Ns, a drain terminal connected to the output terminal No, a gate terminal Gn2, and a back gate terminal BGn2 connected to the back gate control circuit 100X.

[0020] The input voltage Vin1 is input to gate terminal Gn1, and the input voltage Vin2 is input to gate terminal Gn2. In the comparative example, the input voltages Vin1 and Vin2 are set in the output circuit 10X as digital signals that are complementary to either a logic high level (hereinafter simply referred to as "H level") or a logic low level (hereinafter simply referred to as "L level"). The input voltages Vin1 and Vin2 are set to the power supply voltage VDD (power supply node Np) at the H level, and to the power supply voltage VSS (power supply node Ns) at the L level.

[0021] In other words, when Vin1 = H level (VDD) and Vin2 = L level (VSS), the output circuit 10X outputs Vout = L level (VSS) by turning on the N-type transistors Mn1 and Mn2 on the high side and turning them off on the low side. Conversely, when Vin1 = L level (VSS) and Vin2 = H level (VDD), the output circuit 10X outputs Vout = L level (VSS) by turning on the N-type transistors Mn1 and Mn2 on the low side and turning them off on the high side. In this way, the output circuit 10X can operate as an "inverter" that takes a digital signal as input.

[0022] In the back gate control circuit 100X, the N-type transistor M3 is connected between the back gate terminal BGn1 of the N-type transistor Mn1 and the output terminal No, and is controlled to be on or off depending on the input to the gate terminal G3. The N-type transistor M4 is connected between the back gate terminal BGn2 of the N-type transistor Mn2 and the power supply node Ns, and is controlled to be on or off depending on the input to the gate terminal G4.

[0023] In Figure 1, if the N-type transistors M3 and M4 that constitute the back gate control circuit 100X are not present, in the above-described scenario (Vin1 = L level, Vout > VDD), the voltage at the back gate terminal BGn1 becomes higher than the power supply voltage VDD, causing the parasitic diode (pn junction) between the back gate and drain of the N-type transistor Mn1 to be forward-biased. As a result, leakage current is generated in the path from output terminal No to back gate terminal BGn1 (Mn1) to drain (Mn1) to power supply node Np.

[0024] In contrast, the output circuit 10X in the comparative example includes a back gate control circuit 100X. In the back gate control circuit 100X, similar to embodiment 17 of Patent Document 1 (Figure 20), the gate terminal G3 (N-type transistor M3) is connected to the power supply node Np. In addition, the inverted signal of the input voltage Vin1 of the gate terminal G1 of the N-type transistor Mn1 is input to the gate terminal G4 (N-type transistor M4).

[0025] The placement of the back gate control circuit 100X allows the N-type transistor M3 to be turned off during periods when Vin1 = L level, when a voltage level higher than the power supply voltage VDD of the power supply node Np is applied to the output terminal No from the downstream side. Conversely, the N-type transistor M4 operates in a complementary manner to the N-type transistor M3.

[0026] Turning off the N-type transistor M3 prevents the generation of leakage current (N-type transistor Mn1) through the path from the back gate terminal BGn1 to the power node Np. Furthermore, turning on the N-type transistor M4 prevents the potential of the back gate terminal BGn1 from becoming floating.

[0027] Thus, the output circuit 10X is particularly effective in applications where an output signal higher than the power supply voltage VDD is applied to the output terminal No from an external source. Furthermore, in other situations not described above, the connection destination of the back gate terminal BGn1 can be controlled by inputting enable signals or the like to the gate terminals G3 and G4 to control the on / off state of the N-type transistors M3 and M4.

[0028] However, in the back gate control circuit 100X, the field-effect transistor (N-type transistor M3) is directly connected to output terminal No. As a result, the N-type transistor M3 requires ESD protection due to electrostatic discharge from output terminal No, and it is anticipated that this will require a relatively large area (for example, about 50 μm x 50 μm).

[0029] In this specification, P-type transistors and N-type transistors can typically be constructed using P-type and N-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), respectively.

[0030] The threshold voltage Vthn of an N-type MOS transistor is known to depend on the transistor structure or manufacturing process and is expressed by the following equation (1). In equation (1), Vt0 is the threshold voltage when the source-back gate voltage Vsb = 0, φf is the Fermi voltage, and γ is the substrate bias coefficient.

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[0031] Therefore, when Vsb > 0, Vthn > Vt0, while when Vsb < 0, Vthn < Vt0. Thus, in the N-type transistor Mn1, the threshold voltage Vthn can be lowered by making the voltage between the source and the back gate, i.e., the voltage of the back gate terminal BGn1, higher than the source voltage, so that Vsb becomes a negative value.

[0032] In the output circuit 10X of the comparative example, when the N-type transistor M4 is on while the N-type transistor M3 is off (referred to as "state 1"), since Vsb = Vout - VSS, Vthn increases by ΔVthn shown in Equation (2).

Equation

[0033] Assuming that the coefficient value in Equation (2) is γ = 0.25V , φf = 0.3, and calculating ΔVthn at Vout - VSS = 5.0 (V), we get ΔVthn ≈ 0.4V. This phenomenon is generally called the "body bias effect".

[0034] Contrary to the above state 1, in the state where the N-type transistor M3 is on while the N-type transistor M4 is off (referred to as "state 2"), since Vsb = 0, the increase in Vthn due to the body bias effect can be prevented. Thus, by suppressing the body bias effect, the current driving ability of the N-type transistor Mn1 can be enhanced.

[0035] However, since the back gate terminal is composed of a P-type semiconductor and the source and drain terminals are composed of an N-type semiconductor, as described above, parasitic diodes are formed between the back gate and the source and between the back gate and the drain due to pn junctions. Therefore, when a forward bias is applied to the parasitic diodes, the currents of the diodes (the current between the back gate and the source Ibs, the current between the back gate and the drain Idb) are respectively represented by the following equations (3) and (4).

Equation

[0036] In Equations (3) and (4), I0 is the saturation current, Vbs is the voltage between the back gate and the source, Vbd is the voltage between the back gate and the drain, n is the slope factor, and Ut is the thermal voltage. At 300 (K), the thermal voltage Ut is approximately 26 (mV).

[0037] In the above state 2 (M3 = on, M4 = off), since Vbs = 0, Ibs = 0 according to Equation (3). However, when VDD < Vout, Vbd > 0, so in Equation (4), Idb > 0, and current will exponentially occur in the path including the forward-biased parasitic diode.

[0038] Therefore, when applying the output circuit 10X to an application where VDD < Vout may occur, switch control to return the back gate control circuit 100X to state 1 is required. Also, as described above, the N-type transistor M3 requires a relatively large area for ESD countermeasures. <​​​​​​​Next, we will describe an output circuit according to this embodiment that addresses the problems in the comparative example output circuit 10X shown in Figure 1, and aims to improve current driving capability by controlling threshold voltage reduction and reduce circuit area for leakage current suppression. First, in Embodiment 1, we will describe an output circuit equipped with a back gate control circuit that realizes improved current driving capability.

[0041] Figure 2 is a circuit diagram illustrating the configuration of the output circuit 10A according to Embodiment 1. As shown in Figure 2, the output circuit 10A includes N-type transistors Mn1 and Mn2, similar to the output circuit 10X in Figure 1, and a back gate control circuit 100N.

[0042] As in Figure 1, the N-type transistors Mn1 and Mn2 are electrically connected in series between power supply nodes Np and Ns via output terminal No. That is, the high-side N-type transistor Mn1 is electrically connected between power supply node Np and output terminal No, and has a drain terminal connected to power supply node Np, a source terminal connected to output terminal No, a gate terminal Gn1 to which the input voltage Vin1 is input, and a back gate terminal BGn1.

[0043] Similarly, the low-side N-type transistor Mn2 is electrically connected between the output terminal No and the power supply node Ns, and has a source terminal connected to the power supply node Ns, a drain terminal connected to the output terminal No, a gate terminal Gn2 to which the input voltage Vin2 is input, and a back gate terminal BGn2. In the following, the N-type transistors Mn1 and Mn2 will also be referred to as "N-type output transistors."

[0044] The high-side output transistor (N-type transistor Mn1 in FIG. 2) corresponds to an embodiment of the "first output transistor", and the low-side output transistor (N-type transistor Mn2 in FIG. 2) corresponds to an embodiment of the "second output transistor". Also, the power supply voltage VDD corresponds to an embodiment of the "first power supply voltage", and the power supply voltage VSS (VSS < VDD) corresponds to an embodiment of the "second power supply voltage". Therefore, the power supply node Np corresponds to an embodiment of the "first power supply node", and the power supply node Ns corresponds to an embodiment of the "second power supply node". Furthermore, the input voltage Vin1 corresponds to the "first input voltage", and the input voltage Vin2 corresponds to the "second input voltage".

[0045] The back-gate control circuit 100N is provided for at least one of the N-type output transistors Mn1 and Mn2 and is connected to the back-gate terminal of the output transistor. The back-gate control circuit 100N provided corresponding to the N-type transistor Mn1 is connected to the back-gate terminal BGn1, and the back-gate control circuit 100N provided corresponding to the N-type transistor Mn2 is connected to the back-gate terminal BGn2.

[0046] The back-gate control circuit 100N connected to the high-side N-type transistor Mn1 (hereinafter also referred to as the high-side back-gate control circuit 100N) includes a current generation circuit 110N connected between a power supply node Npb that transmits the power supply voltage VDDb and a node N1, and a resistance element Rb connected between the node N1 and an output terminal No. The node N1 is connected to the back-gate terminal BGn1. Hereinafter, the resistance value of the resistance element Rb is also denoted as Rb. Thereby, the resistance element Rb is electrically connected between the back-gate terminal BGn1 and the source terminal (S) of the N-type transistor Mn1 via the node N1 and the output terminal No.

[0047] The resistive element Rb corresponds to one embodiment of the "first resistive element," and the current Ib generated by the current generation circuit 110N corresponds to one embodiment of the "control current." Furthermore, the resistive element Rb and node N1 connected to the back gate terminal BGn1 or BGn2 correspond to one embodiment of the "internal node."

[0048] The output circuit 10A can operate independently as an inverter by receiving digital signal input voltages Vin1 and Vin2, as explained in Figure 1. Furthermore, as will be described later, it is also possible to operate the input voltages Vin1 and Vin2 and the output voltage Vout as analog voltages by combining them with negative feedback, for example, by using an operational amplifier.

[0049] (Effect of current drive capability by back gate control circuit 100N) Next, the configuration and operation of the back gate control circuit 100N will be described in detail, focusing on the high-side back gate control circuit 100N.

[0050] The back gate voltage VBGn1, which is the voltage at the back gate terminal BGn1 connected to the high-side back gate control circuit 100N, is given by VBGn1 = Vout + Ib·Rb, where Ib is the current from the current generation circuit 110N. Therefore, the source-back gate voltage Vsbn1 of the high-side N-type transistor Mn1 is given by equation (5) below. Vsbn1 = -Ib·Rb …(5)

[0051] From equation (5) and equation (1) above, the threshold voltage Vthn of the high-side N-type transistor Mn1 is given by equation (6) below.

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[0052] In equation (6), if Ib·Rb is a positive value, the second term becomes a negative value, allowing the threshold voltage Vthn to be lowered below Vt0. This explains why the current driving capability of the N-type transistor Mn1 is increased compared to the comparative example output circuit 10X, which can only reduce the threshold voltage Vthn to Vt0.

[0053] Furthermore, the diode current of a pn junction can be expressed by the following equations (7) and (8), which are modified versions of equations (3) and (4) above. Equation (7) represents the back gate-source current Ibs, and equation (8) represents the back gate-drain current Ibd.

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[0054] In equations (7) and (8), if Ib·Rb is a positive value, the back gate-source current Ibs1 shown in Figure 2 may occur.

[0055] However, when a back gate-source current Ibs1 is generated, the current Ids1 flowing between the drain and source of the N-type transistor Mn1 decreases by the same amount as the output current Iout from the N-type transistor Mn1 to the output terminal No. This increases the current capacity of the N-type transistor Mn1, which improves the DC characteristics of the circuit.

[0056] However, a decrease in the transconductance (gm1) of the N-type transistor Mn1 can change the pole configuration, potentially affecting circuit stability. Therefore, to prevent excessive back-gate-source current Ibs1, it is desirable to keep the back-gate voltage VBGn1 of the N-type transistor Mn1 below the forward voltage Vf of the pn junction diode (typically around 0.6(V) to 0.7(V)).

[0057] Regarding the current Ibd1 between the back gate and the drain, it can be understood from Equation (8) that if Vout + Ib·Rb < VDD, then Ibd1 = 0 and no current flows. When the current Ibd1 between the back gate and the drain occurs, Ids1 = Iout - Ibd1. For the N-type transistor Mn1, additional current driving ability is required, so the effect of improving the current driving ability by reducing the threshold voltage Vthn is offset. Therefore, it can be understood that voltage conditions where Ibd > 0 need to be avoided.

[0058] From the above, when using VSS, VDD, Vout, and Vf, the constraint conditions to be satisfied in order for BGn1 to enjoy the effect of reducing the threshold of the N-type transistor Mn1 without turning on the pn junction diode can be sorted out and expressed by the following Equation (9a). Equation (9a) corresponds to the conditional expression for making the exponential term of exp sufficiently small in Equations (7) and (8). Note that min(A,B) in Equation (9a) is a function that compares the magnitude relationship between A and B and selects the smaller value. VSS ≤ VBGn1 < min(VDD, Vout + Vf) …(9a)

[0059] Thus, by designing the current generation circuit 110N and the resistance element Rb (Ib·Rb) to satisfy the condition of Equation (9a), the leakage current due to the parasitic diode in the N-type output transistor provided with the back gate control circuit 100N can be suppressed.

[0060] As shown in Figure 2, a back gate control circuit 100N with a similar configuration, consisting of a current generation circuit 110N and a resistor Rb connected in series, can also be provided for the low-side N-type transistor Mn2 (output transistor). In the low-side back gate control circuit 100N provided for the N-type transistor Mn2, the current generation circuit 110N is connected between the power supply node Npb and node N1, which is connected to the back gate terminal BGn2 of the N-type transistor Mn2, and the resistor Rb is connected between node N1 and the power supply node Ns. On the low-side, the resistor Rb is also electrically connected between the back gate terminal BGn2 and the source terminal (S) of the N-type transistor Mn2 via node N1 and the power supply node Ns. This allows for an improvement in the current driving capability of the low-side N-type output transistor Mn2 using a mechanism similar to that of the high-side back gate control circuit 100N.

[0061] Furthermore, when the high-side and low-side output transistors (N-type) are included, equation (9a) is extended to equation (9b) below. In equation (9b), the back gate voltage VBGn of the N-type output transistor controlled by the back gate control circuit 100N is defined in relation to the source voltage Vs and drain voltage Vd of the output transistor (N-type). As mentioned above, VBGn is given by VBGn = Vs + Rb·Ib. VSS≦VBGn1 <min(Vd,Vs+Vf) …(9b)

[0062] For the N-type transistor Mn1, equation (9a) can be obtained by substituting Vd=VDD and Vs=Vout into equation (9b). Thus, it can be understood that equation (9b) shows the voltage range for suppressing leakage current due to parasitic diodes for the back gate voltage VBGn of the N-type output transistor controlled by the back gate control circuit 100N.

[0063] As described above, according to the output circuit according to Embodiment 1, by controlling the voltage of the back gate terminal by the back gate control circuit 100N (Vsb < 0), the drain-source current for the same size of the output transistors (Mn1, Mn2) is increased, so that the current driving ability can be improved.

[0064] Note that, in the output circuit 10A according to Embodiment 1, a configuration for suppressing the leakage current in the situation where the output voltage Vout of the output terminal No rises above the power supply voltage VDD (power supply node Np) (VDD < Vout) described in the comparative example of FIG. 1 is not arranged. However, if it is possible to limit the application to an application where it is not necessary to assume the situation where VDD < Vout, the improvement effect of the current driving ability can be enjoyed by applying the output circuit 10A.

[0065] (Configuration example of current generation circuit 110N) Here, using FIGS. 3 to 5, current generation circuits 110A to 110C, which are configuration examples of the current generation circuit 110N shown in FIG. 2, will be described.

[0066] FIG. 3 shows a current generation circuit 110A according to a first configuration example. As shown in FIG. 3, the current generation circuit 110A can be configured to include a P-type transistor Mpb for outputting a constant current. The P-type transistor Mpb is connected between the power supply node Npb and the node N1 (back gate terminal BGn1), and has a source terminal connected to the power supply node Npb, a drain terminal connected to the node N1 (back gate terminal BGn1), and a gate terminal. The P-type transistor Mpb corresponds to an embodiment of the "current generation transistor", and the power supply node Npb corresponds to an embodiment of the "third power supply node". <C

[0067] A bias voltage Vbp (constant voltage) from the bias circuit 102 is input to the gate of the P-type transistor Mpb. Note that, for the bias circuit 102, any circuit configuration of a known bias circuit for outputting a constant voltage can be applied.

[0068] As a result, the P-type transistor Mpb can supply a constant bias current Ib from the power supply node Np to node N1, corresponding to the bias voltage Vbp. This enables the function of the current generation circuit 110N described in Figure 2.

[0069] When the P-type transistor Mpb for current generation is operated in the saturation region, the current Ib is given by equation (10) below, using the bias voltage Vbp.

number

[0070] In equation (10), the gain coefficient β is a circuit constant expressed as β = (Wg / Lg)·μ·Cox, where μ is the electron mobility of each transistor, Cox is the gate oxide capacitance per unit area, Wg is the gate width, and Lg is the gate length, and Vthp is the threshold voltage of the P-type transistor.

[0071] Therefore, the source-back gate voltage Vsbn1 of Mn1 can be expressed by the following equation (11), which is a modification of equation (5).

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[0072] In equation (11), if Vbp is a positive value (Vbp>0) and is higher than Vthp (Vbp>Vthp), then Vsbn1<0. In this case, in equation (6), Ib·Rb becomes a positive value, so the second term becomes a negative value, and the threshold voltage Vthn of the N-type transistor can be lowered below Vt0.

[0073] In the output circuit 10A to which the current generation circuit 110A shown in Figure 3 is applied, it is possible to generate a current Ib that does not depend on the output voltage Vout, power supply voltage VDD, VDDb, as shown in equation (10). Therefore, in addition to the improved current driving capability mentioned above, it is possible to realize an output circuit 10A that operates stably against voltage fluctuations.

[0074] On the other hand, when the bias circuit 102 is started, the current Ib generated by the current generation circuit 110A is not fixed until the bias voltage Vbp stabilizes. Therefore, in applications that require fast startup and fast load driving immediately after startup, or in applications where the power supply is switched on and off rapidly, this configuration is at a disadvantage compared to the other second and third configuration examples described later.

[0075] Furthermore, the bias circuit 102 can typically use a common circuit for generating the bias voltage used in a group of circuits (e.g., amplifiers, etc.) placed before or after the output circuit 10A in a system in which the output circuit 10A is installed. In other words, in applications where it is not necessary to place a bias circuit 102 specifically for the output circuit 10A, the output circuit 10A can be configured while suppressing an increase in circuit area.

[0076] Figure 4 shows the current generation circuit 110B according to the second configuration example. As shown in Figure 4, the current generation circuit 110B is configured to include a resistor R0 connected between the power supply node Np and node N1 (back gate terminal BGn1). This results in resistors R0 and Rb being connected in series between the power supply node Np and output terminal No via node N1. Hereafter, the resistance value of resistor R0 will also be denoted as R0. In Figure 4, resistor R0 corresponds to one embodiment of the "second resistor," and power supply node Npb corresponds to one embodiment of the "third power supply node."

[0077] As a result, the current Ib generated by the current generation circuit 110B is given by equation (12) below. Ib=(VDDb-Vout) / (R0+Rb) …(12)

[0078] The current Ib supplied from the current generation circuit 110B to node N1 flows through the path from the resistive element Rb to the output terminal No. Therefore, a voltage drop equivalent to Ib·Rb occurs across the resistive element Rb.

[0079] Therefore, the back gate voltage VBGn1 of the N-type transistor Mn1 is Vout + Ib·Rb. Substituting this into equation (12), the back gate voltage VBGn1 is given by equation (13) below. VBGn1=(R0·Vout+Rb·Vddb) / (R0+Rb) …(13)

[0080] Therefore, from equation (13), the source-back gate voltage Vsbn1 = Vout - VBGn1 of the N-type transistor Mn1 is given by the following equation (14). Vsbn1=-(VDDb-Vout)·Rb / (Rb+R0) …(14)

[0081] From equation (14), if VDDb > Vout, then Vsbn1 < 0. In this case, in equation (6), Ib·Rb becomes a positive value and the second term becomes a negative value, which allows the threshold voltage Vthn of the N-type transistor to be lowered below Vt0.

[0082] In the current generation circuit 110B according to the second configuration example, as can be understood from equation (14), the source-back gate voltage Vsbn1 of the N-type transistor can be adjusted by the voltage division ratio of the resistive elements R0 and Rb.

[0083] Therefore, without requiring the activation of the bias circuit 102 for the current generation circuit 110A, the voltage at node N1, i.e., the voltage at the back gate terminal BGn1, can be generated according to equation (13) in response to the activation of the power supply voltage VDDb. As a result, the source-back gate voltage Vsbn1 of equation (14) can be generated, improving the current driving capability of the output transistor. Therefore, in applications where it is necessary to respond quickly to a large load when the power supply is started up, the output circuit 10A using the current generation circuit 110B (Figure 4) according to the second configuration example is preferable to using the current generation circuit 110A (Figure 4).

[0084] Furthermore, in the current generation circuit 110A of the first configuration example, there is a concern that the bias voltage Vbp output from the bias circuit 102 will vary due to process variations in the components of the bias circuit 102 (especially the transistors). Since variations in the bias voltage Vbp will also cause variations in the current Ib, it will be necessary to implement trimming to compensate for process variations in order to generate a process-independent, highly accurate back gate voltage VBGn1.

[0085] On the other hand, in the current generation circuit 110B of the second configuration example, the accuracy of the back gate voltage VBGn1 depends on the accuracy of the voltage division ratio by the resistive elements Rb and R0. Therefore, compared to the bias voltage Vbp output from the bias circuit 102, the effect of process variations is generally smaller. Consequently, in applications where process variations have a severe impact, the output circuit 10A using the current generation circuit 110B of the second configuration example is advantageous.

[0086] However, in the current generation circuit 110B, as shown in equation (14), the back gate voltage VBGn1 changes depending on the power supply voltage VDDb and the output voltage Vout. Therefore, the source-back gate voltage Vsbn1, which affects the threshold voltage Vthn, is affected by variations in the power supply voltage VDDb and fluctuations in the output voltage Vout.

[0087] Therefore, in applications where power supply voltage fluctuations are relatively large, or where a wide output range is required for the output voltage Vout, there is a concern that the back gate voltage VBGn1 will vary or its range will become large. As mentioned above, the back gate voltage VBGn1 must satisfy equations (9a) and (9b) as constraints for the pn junction diode not to turn on. However, when VBGn1 fluctuates greatly, it becomes more difficult to satisfy the conditions of equations (9a) and (9b). Furthermore, as can be understood from equation (14), the higher the output voltage Vout and the smaller the difference with the power supply voltage VDDb, the lower the source-back gate voltage Vsbn1 becomes, and the effect of improving the current drive capability due to the threshold voltage reduction of the N-type transistor Mn1 becomes smaller.

[0088] Figure 5 shows the current generation circuit 110N according to the third configuration example. As shown in Figure 5, the current generation circuit 110C can be configured to include an N-type transistor Mnb1 that outputs a current Ib proportional to the current (Ids) of an N-type transistor Mn1 (output transistor). The N-type transistor Mnb1 is connected between the power supply node Np and node N1 (back gate terminal BGn1) and has a drain terminal connected to the power supply node Npb, a source terminal and a back gate terminal connected to node N1, and a gate terminal. The gate terminal of the N-type transistor Mnb1 is interconnected with the gate terminal Gn1 of the N-type transistor Mn1 (output transistor). In Figure 5, the N-type transistor Mnb1 corresponds to one embodiment of the "current generation transistor," and the power supply node Npb corresponds to one embodiment of the "third power supply node."

[0089] An N-type transistor Mnb1 has an aspect ratio (1 / α) times that of an N-type transistor Mn1 (α>1). Here, the aspect ratio is the ratio expressed as Wg / Lg, where Wg is the gate width and Lg is the gate length of the transistor.

[0090] When both N-type transistors Mnb1 and Mn1 are operating in the saturation region, the current Ib output by N-type transistor Mnb1 and the current Is output by N-type transistor (output transistor) Mn can be expressed by the following equations (15) and (16). In equations (15) and (16), VGn1 is the voltage at the gate terminal Gn1 of the N-type transistor (gate voltage).

number

number

[0091] Furthermore, the relationship between the output current Iout flowing through output terminal No and the currents Ib and Is can be expressed by the following equation (17). Iout = Ib + Is …(17)

[0092] Here, assuming that the initial state is Ib·Rb≈0 and that the threshold voltages Vthn of the N-type transistors Mn1 and Mnb1 are equal, the currents Ib and Is in this initial state are given by equations (18) and (19) below, based on equations (15) to (17). Ib = Iout / (1 + α) …(18) Is = iout·α / (1+α) …(19)

[0093] From equations (18) and (19), it can be understood that Is = α·Ib. Therefore, in the current generation circuit 110C of the third configuration example, in the initial state when the output current Iout begins to flow at output terminal No, it is possible to supply a current Ib, which is (1 / α) times the current Is of the N-type transistor Mn1 (output transistor), to node N1 (resistor Rb).

[0094] On the other hand, in the steady state where the output current Iout continues to flow and the current Ib increases, the term (Rb·Ib) included in Equation (15) increases, so the current Ib will gradually decrease rather than the expression shown in Equation (18) above. However, since this operation (Ib decrease) is a negative feedback operation, it is understood that the current Ib will eventually converge to a certain value.

[0095] Here, a specific numerical example is used to explain the steady-state value of the current Ib. For example, assuming a case where the power supply voltage VSS corresponding to the L level is a negative voltage, VGn1 = -1.0 (V), Vout = -3.0 (V), Rb·Ib = 0.5 (V), Vthn = 1.0 (V), μ·Cox = 100 (μA / V 2 ), and Wg = 3 (mm), Lg = 3 (μm), and α = 1000. Under this numerical example, by using the numerical calculations of Equation (18) and β = (Wg / Lg)·μ·Cox, the calculation results of the currents Ib and Is are as follows.

[0096] Ib = 50 (μA / V 2 )·0.5 2 (V 2 ) ≒ 12.5 (μA) Is = 0.5·100 (μA / V 2 )·1000·1 (V 2 ) = 50 (mA)

[0097] Here, since Ib << Is, it can be obtained that Iout ≒ Is = 50 (mA). Then, by using this calculation result and the assumption of Rb·Ib = 0.5 (V), the resistance value Rb = 0.5 (V) / 12.5 (μA) = 40 (kΩ) can be designed.

[0098] In the output circuits equipped with current generation circuits 110A and 110B in the first and second configuration examples (Figures 3 and 4), when the output current Iout increases in a positive value (i.e., when the current Is of the N-type transistor Mn1 increases), the gate voltage VGn1 of the N-type transistor Mn1 also increases according to equation (16). This puts pressure on the voltage headroom (corresponding to VDD-VGn1 in Figures 3 and 4). As a result, the maximum current Ioutmax that the output circuit 10A can output to drive the load at a certain output voltage Vout is given by equation (20) below. Note that in deriving equation (20), Ib < <IsとしてIout≒Isとしている。

number

[0099] In contrast, in the output circuit 10A (Figure 5) equipped with the current generation circuit 110C of the third configuration example, as can be understood from equation (15), as the gate voltage VGn1 increases with increasing output current Iout, the current Ib supplied by the current generation circuit 110C also increases accordingly. Therefore, it is possible to lower the threshold voltage Vthn (a function of Ib) in accordance with the magnitude of the output current Iout. Thus, the more it is necessary to drive the load with a larger output current Iout, the lower the threshold voltage Vthn of the N-type transistor Mn1 can be. As a result, the current generation circuit 110C of the third configuration example is more advantageous than the current generation circuits 110A and 110B of the first and second configuration examples for applications requiring a large output current Iout.

[0100] On the other hand, in the current generation circuit 110C, due to the characteristic that the current Ib is not a constant current but depends on the output current Iout, contrary to the above effect, when the output current Iout is large, there is a concern that VBGn1 = Vout + Ib·Rb will become large, and the constraints of equations (9a) and (9b) will not be satisfied. Conversely, current generation circuits 110A and 110B are advantageous over current generation circuit 110C in that they can operate stably under the constraints of equations (9a) and (9b).

[0101] However, as described above, the current Ib does not increase linearly with the increase in the output current Iout. Due to the negative feedback, a restraining force acts in the direction of decreasing the current Ib as soon as the current Ib increases. Also, by using an overcurrent detection circuit or the like, when an output current Iout larger than expected flows, a mechanism to detect and shut it down can generally be adopted. Therefore, the concerns regarding the constraint conditions of equations (9a) and (9b) can be alleviated. In the current generation circuit 110C of the third configuration example as well, if the aspect ratio α is sufficiently large, Ib (= Is / α) << Is, so similar to the current generation circuits 110A and 110B of the first and second configuration examples, the maximum current Ioutmax can be expressed by equation (20).

[0102] Thus, it is possible to configure the current generation circuit 110N of FIG. 2 by the current generation circuits 110A to 110C illustrated in FIGS. 3 to 5, and thereby realize the output circuit 10A (FIG. 2) according to Embodiment 1, which has excellent current driving ability. The current generation circuits 110A to 110C can be selectively applied as appropriate in consideration of the above-mentioned pros and cons with respect to the required fast startup performance, process variations, power supply voltage fluctuations, and output voltage Vout fluctuation range, etc. in the application of the output circuit 10A.

[0103] Also, as illustrated in FIGS. 3 to 5, since the current generation circuit 110N can be configured by small-area transistors and / or resistor elements that do not require ESD countermeasures, it can be configured with a significantly smaller area compared to when ESD countermeasures are required. As a result, it is understood that the circuit area for arranging the current generation circuit 110N is significantly reduced compared to the circuit area of the N-type transistor M3 (FIG. 1) in the comparative example.

[0104] Embodiment 2. (Configuration of Output Circuit) Embodiment 2 describes the operation of a back gate control circuit for suppressing leakage current when a voltage Vout > VDD is applied to output terminal No, as also explained in the comparative example in Figure 1.

[0105] Figure 6 is a circuit diagram illustrating an example of the configuration of the output circuit 10B according to Embodiment 2. As shown in Figure 6, output circuit 10B differs from output circuit 10A shown in Figure 2 in that it includes a back gate control circuit 101N instead of back gate control circuit 100N (Figure 2), and that enable control switches SW1 and SW2 are included. Back gate control circuit 101N differs from back gate control circuit 100N (Figure 2) in that it includes a current generation circuit 120N instead of current generation circuit 110N.

[0106] The enable control switch SW1 is connected between the gate terminal Gn1 of the N-type transistor Mn1 and the power supply node Ns. The enable control switch SW2 is connected between the gate terminal Gn2 of the N-type transistor Mn2 and the power supply node Npc. The power supply node Npc transmits the power supply voltage VDDc. The enable signal EN input to the enable control switches SW1 and SW2 is set to either a high level (power supply voltage VDDc in Figure 6) or a low level (power supply voltage VSS in Figure 6), and the thresholds for the high and low levels are set to (VDDc + VSS) / 2.

[0107] The enable control switches SW1 and SW2 are turned on or off in response to the enable signal EN. Specifically, when the enable signal EN is at a high level (enable on), the enable control switches SW1 and SW2 are in the off state (non-conductive), and conversely, when the enable signal EN is at a low level (enable off), the enable control switches SW1 and SW2 are in the on state (conductive). Enable control switch SW1 corresponds to one embodiment of the "first enable control switch," and enable control switch SW2 corresponds to one embodiment of the "second enable control switch."

[0108] Therefore, during the enable-on period (EN=H level), the gate voltages of the N-type transistors (output transistors) Mn1 and Mn2 are biased by the input voltages Vin1 and Vin2 to the gate terminals Gn1 and Gn2. This makes it possible to drive the subsequent circuit (not shown) connected to the output terminal No with the output voltage Vout corresponding to the input voltages Vin1 and Vin2.

[0109] On the other hand, during the enable-off period (EN=L level), the gate terminals Gn1 and Gn2 are connected to power supply nodes Ns (VSS) and Npc (VDDc) when the enable control switches SW1 and SW2 are turned on. As a result, the N-type transistors Mn1 and Mn2 are biased by the power supply voltages VSS and VDDc, respectively. This causes the high-side N-type transistor Mn1 to be in the off state and the low-side N-type transistor Mn2 to be in the on state. Consequently, if the impedance of the N-type transistor Mn2 is sufficiently low with respect to the current flowing into the N-type transistor Mn2 from output terminal No, the output voltage Vout of output terminal No is clamped to the power supply voltage VSS.

[0110] The current generation circuit 120N is configured to operate upon receiving an enable signal EN. The enable signal EN input to the current generation circuit 120N is set to either an H level (power supply voltage VDDb in Figure 6) or an L level (power supply voltage VSS in Figure 6), and the threshold values ​​for the H and L levels are (VDDb + VSS) / 2. Although the H level voltages of the enable signals EN to the enable control switches SW1 and SW2 and the enable signal EN to the current generation circuit 120N are different, the H level period and L level period are provided at the same timing for each.

[0111] The current generation circuit 120N, like the current generation circuit 110N whose configuration example is shown in Figures 3 to 5, is usually implemented using resistors and / or transistors, and therefore can be given an enable function.

[0112] Specifically, the current generation circuit 120N generates current Ib in the same way as the current generation circuit 110N when the enable signal EN is at a high level (enable-on period). On the other hand, when EN is at a low level, it is configured not to generate current and to be in a high-impedance state. A specific example of the configuration of the current generation circuit 120N will be explained in detail later.

[0113] As described above, the output circuit 10B according to Embodiment 2 has an enable function added to the output circuit 10A (Embodiment 1). Below, we will explain the operation of the output circuit 10B when the power is off and when the enable is off, which is the situation in which the voltage Vout > VDD applied to output terminal No, as explained in the comparative example, becomes problematic. Note that when the power is off, the enable is off and VDD = VSS = 0 [V], so it is possible to comprehensively address this by the enable-off control described later.

[0114] When the enable is off (EN=L level), the current generation circuit 120N has a high impedance with respect to the resistive element Rb. Therefore, in the high-side back gate control circuit 101N, the back gate voltage VBGn1 of the N-type transistor Mn1, which is connected to output terminal No via the resistive element Rb, becomes equivalent to the output voltage Vout of output terminal No. As a result, when the enable is off, the output voltage Vout is clamped to the power supply voltage VSS when the enable control switch SW2 is turned on. Consequently, VBGn1 is fixed at VSS.

[0115] Therefore, in the N-type transistor Mn1, Vbs=0 in equation (3), so Ibs1=0. On the other hand, for the back gate-drain current Ibd, while the drain terminal is at the power supply voltage VDD, the back gate voltage VBGn1=VSS results in the parasitic diode (pn junction) between the back gate and drain being reverse-biased (Vbd=VSS-VDD), and as a result, Ibd1=0.

[0116] When the enable is off (EN=L level), in the low-side back gate control circuit 101N, the back gate terminal BGn2 of the N-type transistor Mn2 is connected to the power supply node Ns via a resistor Rb. Therefore, the back gate voltage VBGn2 of the N-type transistor Mn2 is equivalent to the power supply voltage VSS transmitted by the power supply node Np. As a result, VBGn2 is fixed at VSS. Furthermore, the source terminal of the N-type transistor Mn2 is connected to the power supply node Ns (power supply voltage VSS), and the drain terminal is connected to the output terminal No, which is clamped to the power supply voltage VSS.

[0117] Therefore, in the N-type transistor Mn2, Vbs=0 in equation (3) and Vbd=0 in equation (4). As a result, Ibs2=Ibd2=0 in the N-type transistor Mn2.

[0118] As a result, according to the output circuit 10B of Embodiment 2, the arrangement of the current generation circuit 120N having an enable function and the enable control switches SW1 and SW2 makes it possible to suppress the leakage current generated in the parasitic diodes that have the back gate terminals of the output transistors Mn1 and Mn2 connected to the output terminal No as the anode (p).

[0119] In other words, according to the output circuit 10B of Embodiment 2, in addition to the effects of the output circuit of Embodiment 1, the effect of suppressing leakage current generated in the parasitic diode between the back gate terminal and the source terminal or drain terminal of the output transistor connected to output terminal No can be enhanced. Specifically, a leakage current suppression effect similar to that of the N-type transistor M3 in Comparative Example (Figure 1) can be obtained.

[0120] Furthermore, output circuit 10B can achieve the same leakage current suppression effect as the comparative example (Figure 1) without requiring the placement of a large-area N-type transistor M3 (Figure 1) that necessitates ESD countermeasures, thereby reducing the circuit area. Compared to the comparative example's output circuit 10X (Figure 1), output circuit 10B replaces the N-type transistors M3 and M4 (Figure 1) with a current generation circuit 120N and enable control switches SW1 and SW2.

[0121] As will be described later, the current generation circuit 120N can also be realized by adding a small-area transistor (for switching) that does not require ESD countermeasures to the configuration of the current generation circuit 110N, so it can be constructed in a significantly smaller area than the comparative example that requires ESD countermeasures.

[0122] Furthermore, since the enable control switches SW1 and SW2 are simply switches, they can be constructed using the smallest possible transistors, thus not significantly increasing the circuit area. As a result, it is understood that the circuit area required for arranging the current generation circuit 120N and the enable control switches SW1 and SW2 is significantly reduced compared to the circuit area of ​​the N-type transistors M3 and M4 in the comparative example (Figure 1).

[0123] Furthermore, the enable control switches SW1 and SW2 do not need to be newly installed specifically for the output circuit 10B; switches from other circuits can be reused. For example, in circuits that generate input voltages Vin1 and Vin2, which are placed before the output circuit 10B, it is common to place a switch for the enable function at the node where the input voltages Vin1 and Vin2 are generated.

[0124] For example, the above-mentioned enable function can be achieved by providing a switch that turns on and off in response to the enable signal EN, which is common to the enable control switches SW1 and SW2, for fixing Vin1 to a low level and Vin2 to a high level when the enable is off. In this case, the functions of the enable control switches SW1 and SW2 in Figure 6 can be achieved by this switch, so it is understood that there is no need to provide separate enable control switches SW1 and SW2 specifically for the output circuit 10B.

[0125] Furthermore, in output circuit 10A (Figure 2), it is also possible to modify the configuration by replacing the current generation circuit 110N with a current generation circuit 120N that has an enable function. This modification results in a configuration similar to output circuit 10A (Figure 6) but without the enable control switches SW1 and SW2. Therefore, in this modified output circuit, the leakage current suppression effect (in the Vout > VDD phase) seen in output circuit 10B does not occur, but power consumption can be reduced compared to output circuit 10A by having the current generation circuit 120N stop supplying current during the enable-off period.

[0126] (Example configuration of current generation circuit 120N) Next, using Figures 7 to 9, we will explain the current generation circuits 120A to 120C, which are examples of the configuration of the current generation circuit 120N shown in Figure 6.

[0127] Figure 7 shows the current generation circuit 120A according to the first configuration example. As shown in Figure 7, the current generation circuit 120A is configured to include a P-type transistor Mswb for enable control, in addition to the configuration of the current generation circuit 110A (Figure 3). The P-type transistor Mswb is connected between the power supply node Np and the gate terminal of the P-type transistor Mpb for current supply.

[0128] The P-type transistor Mswb has a source terminal connected to the power supply node Npb, a drain terminal connected to the gate terminal of the P-type transistor Mpb, and a gate terminal to which the enable signal EN is input. As a result, the P-type transistor Mswb operates as a switch that turns on and off in response to the enable signal EN. In Figure 7, the P-type transistor Mswb corresponds to one embodiment of the "switch transistor".

[0129] During the enable-on period (EN=H level), the P-type transistor Mswb is in the off state. As a result, the bias voltage Vbp from the bias circuit 102 is input to the gate terminal of the P-type transistor Mpb used for current supply. Therefore, the current generation circuit 120A operates similarly to the current generation circuit 110A, supplying a constant bias current Ib corresponding to the bias voltage Vbp to the resistor Rb via node N1. This has the effect of improving the current driving capability by lowering the threshold voltage of the output transistor Mn1, as described in Embodiment 1 (Figure 3).

[0130] On the other hand, during the enable-off period (EN=L level), the P-type transistor Mswb is in the ON state. As a result, the P-type transistor Mpb, which supplies current, is turned off when the power supply voltage VDDb is input to its gate terminal. Consequently, the current generation circuit 120A enters a high-impedance state, and the current Ib becomes almost zero.

[0131] Thus, the current generation circuit 120A can operate in the same way as the current generation circuit 110A during the enable-on period, supplying current Ib, while stopping current Ib (Ib=0) during the enable-off period, thus having an enable function.

[0132] Furthermore, the P-type transistors Mpb and Mswb and the resistor Rb that constitute the current generation circuit 120A can be constructed in a significantly smaller area compared to the transistor requiring ESD countermeasures (N-type transistor M3: Figure 1). Therefore, compared to the circuit area of ​​the back gate control circuit 100X in the comparative example (Figure 1), it can be seen that the circuit area required for the arrangement of the back gate control circuit 101N including the current generation circuit 120A and the enable control switches SW1 and SW2 is significantly smaller.

[0133] In addition, in the current generation circuits 110A and 120A, it is also possible to configure the current supply P-type transistor Mpb in a cascode configuration in order to improve the accuracy of the current Ib. In this case, a P-type transistor Mbpc (not shown) for the cascode stage is inserted and connected between the drain terminal and node N1 of the P-type transistor Mpb in Figure 3 or Figure 7. Furthermore, a cascode connection can be achieved by inputting a second bias voltage Vbpc (not shown) to the gate terminal of the P-type transistor Mbpc. This second bias voltage Vbpc may be output from bias circuit 102, or from another bias circuit (not shown) different from bias circuit 102.

[0134] Typically, in configurations where the above-described cascode configuration is applied, the bias circuit 102 that generates the bias voltage Vbp is also often cascoded. Therefore, for the second bias voltage Vbpc, it is preferable to reuse the bias circuit 102 intended for other circuits and input it to the P-type transistor Mbpc for the cascode stage, similar to the bias voltage Vbp.

[0135] Figure 8 shows the current generation circuit 120B according to the second configuration example. As shown in Figure 8, the current generation circuit 120B is configured to include a P-type transistor Mswb for enable control, in addition to the configuration of the current generation circuit 110B (Figure 4). The P-type transistor Mpb is connected between the power supply node Npb and node N0. The resistor R0 is connected between nodes N0 and N1. Thus, the P-type transistor Mpb is connected in series with the resistor R0 between the power supply node Npb and node N1.

[0136] The gate terminal of the P-type transistor Mswb receives the enable inversion signal ENB. The enable inversion signal ENB is the inverse of the enable signal EN, and is set to a low level during the enable-on period and a high level during the enable-on period. As a result, the P-type transistor Mswb operates as a switch that turns on and off in response to the enable inversion signal ENB. In other words, in Figure 8, the P-type transistor Mswb corresponds to one embodiment of a "switch transistor".

[0137] During the enable-on period (EB=L level), the P-type transistor Mswb is in the ON state. By designing the on-resistance of the P-type transistor Mswb to be sufficiently small compared to the sum of the resistances of the resistors R0 and Rb (R0+Rb), the current generation circuit 120B can operate to supply the current Ib shown in equation (12) to node N1 (resistor R1), similar to the current generation circuit 110B. This has the effect of improving the current driving capability by lowering the threshold voltage of the output transistor Mn1, as explained in Embodiment 1 (Figure 4).

[0138] During the enable-off period (EB=H level), the P-type transistor Mswb is in the off state. The off-resistance of the P-type transistor Mswb is usually sufficiently large compared to the sum of the resistances of the resistors R0 and Rb (R0+Rb), so the current Ib can be reduced to approximately 0 during the enable-off period.

[0139] Thus, the current generation circuit 120B can operate in the same way as the current generation circuit 110B during the enable-on period (EB=L level), supplying current Ib, while stopping current Ib (Ib=0) during the enable-off period (EB=H level), thus having an enable function.

[0140] During the enable-off period, the back gate voltage VBGn1 of the N-type transistor Mn1 is given by VBGn1 = Vout + Ib·Rb, so when Ib ≈ 0, the back gate voltage VBGn1 is equivalent to the output voltage Vout. As described above, in the output circuit 10B, the output voltage Vout during the enable-off period is fixed to the power supply voltage VSS by the enable control switch SW2, so as explained in Figure 6, leakage current due to the parasitic diodes (pn junctions) of the N-type transistors Mn1 and Mn2 can be suppressed.

[0141] In the current generation circuit 120B, the P-type transistor Mswb and resistors R0 and Rb can be constructed in a significantly smaller area compared to the transistor requiring ESD countermeasures (N-type transistor M3: Figure 1). Therefore, compared to the circuit area of ​​the back gate control circuit 100X in the comparative example (Figure 1), the circuit area required for the arrangement of the back gate control circuit 101N including the current generation circuit 120B and the enable control switches SW1 and SW2 is significantly smaller.

[0142] Figure 9 shows a current generation circuit 120C according to the third configuration example. As shown in Figure 9, the current generation circuit 120C is configured to include a P-type transistor Mswb for enable control, in addition to the configuration of the current generation circuit 110C (Figure 5). The P-type transistor Mpb is connected between the power supply node Npb and the N-type transistor Mnb1 (drain terminal) for current supply. An enable inversion signal ENB, similar to that in Figure 8, is input to the gate terminal of the P-type transistor Mswb. As a result, the P-type transistor Mswb operates as a switch that turns on and off in response to the enable inversion signal ENB. In other words, the P-type transistor Mswb corresponds to one embodiment of a "switch transistor".

[0143] During the enable-on period (EB=L level), the P-type transistor Mswb is in the ON state. As a result, the current generation circuit 120C, like the current generation circuit 110C, can operate so that the N-type transistor Mnb1, which has an aspect ratio (1 / α) times that of the N-type transistor Mn1, supplies a current Ib (Ib=Iout / (1+α)) to node N1 (resistor R1) according to equation (19). This has the effect of improving the current driving capability by lowering the threshold voltage of the output transistor Mn1, as explained in Embodiment 1 (Figure 5).

[0144] During the enable-off period (EB=H level), the P-type transistor Mswb is in the off state, so the current Ib can be set to almost 0.

[0145] Thus, the current generation circuit 120C can operate in the same way as the current generation circuit 110C during the enable-on period (EB=L level), supplying current Ib, while stopping current Ib (Ib=0) during the enable-off period (EB=H level), thus having an enable function.

[0146] In the current generation circuit 120C, the N-type transistor Mnb1, the P-type transistor Mswb, and the resistor Rb can be constructed in a significantly smaller area compared to the transistor requiring ESD countermeasures (N-type transistor M3: Figure 1). Therefore, compared to the circuit area of ​​the back gate control circuit 100X in the comparative example (Figure 1), the circuit area required for the arrangement of the back gate control circuit 101N including the current generation circuit 120C and the enable control switches SW1 and SW2 is significantly smaller.

[0147] Thus, the current generation circuit 120N in Figure 6 can be constructed using the current generation circuits 120A to 120C illustrated in Figures 7 to 9. As a result, in the output circuit 10B to which the current generation circuit 120N is applied, in addition to improving the current driving capability, a leakage current suppression effect (Vout > VDD phase) can be further realized. Furthermore, as described above, in the output circuit 10A according to Embodiment 1 (Figure 2), by replacing the current generation circuit 110 with the current generation circuits 120A to 120C, power consumption during the enable-off period can be reduced.

[0148] Furthermore, the current generation circuits 120A to 120C have the same advantages and disadvantages as those described for the current generation circuits 110A to 110C in Embodiment 1. Therefore, the current generation circuits 120A to 120C can also be selectively applied as appropriate, taking into account the aforementioned advantages and disadvantages in relation to the required fast startup, process variations, power supply voltage fluctuations, and output voltage Vout fluctuation range in the application of output circuit 10A or 10B.

[0149] As explained in Figures 6 to 9, in a multi-power supply system configuration where different power supply nodes Np (power supply voltage VDD) and Npb (power supply voltage VDDb) are connected to the output transistor (Mn1) and current generation circuit 120 (120A to 120C), constraints arise on the circuit conditions in order to achieve the leakage current suppression effect.

[0150] As can be seen from Figures 6 to 9, in the back gate control circuit 101N including the current generation circuit 120, the back gate voltage VBGn1 of the high-side N-type transistor (output transistor) Mn1 is less than or equal to the power supply voltage VDDb of the power supply node Npc.

[0151] Therefore, when VDD = VDDb, that is, in a configuration where the output transistor (Mn1) and the current generation circuit 120 (120A~120C) are connected to a single power supply, it is guaranteed that the back gate voltage VBGn1 of the N-type transistor Mn1 is VBGn1 ≤ VDDb and VBGn1 ≤ VDD.

[0152] In contrast, in the above-mentioned multi-power supply system, since VDDb ≠ VDD, the power supply voltage VDD at the drain terminal of the N-type transistor Mn1 becomes lower than the back gate voltage VBGn1 = Vout + Rb·Ib of the N-type transistor Mn1, which may cause the current Ibd in equation (4), i.e., leakage current due to the parasitic diode, to occur.

[0153] For example, in a situation where VDD=3.3(V), VDDb=5.0(V), Vout=3(V), and Rb·Ib=0.5(V), Vout+Rb·Ib=3.5(V), so VDD>Vout+Rb·Ib, and a current Ibd will be generated. In this case, it can be avoided by satisfying the relationship VDDmin>Voutmax+Rbmax·Ibmax under any PVT variation conditions.

[0154] Here, P represents process variation, V represents variation with respect to power supply voltage fluctuations, T represents variation with respect to temperature, VDDmax represents the maximum value of VDD voltage, Voutmax represents the maximum value of output voltage Vout, Rbmax represents the maximum value of resistance Rb, and Ibmax represents the maximum value of current Ib.

[0155] On the other hand, regarding the back gate voltage VBGn2 of the low-side N-type transistor Mn2, the relationship Vout ≤ VDD holds between the output voltage Vout and the power supply voltage VDD. Therefore, when controlling the back gate on the low side, care must be taken to prevent it from rising too high, even with a single power supply. In this case, under any PVT variation conditions, the relationship VOUTmin > VSSmax + Rbmax·Ibmax can be satisfied to avoid the generation of leakage current due to the parasitic diode of the N-type transistor Mn2. Here, VSSmax is the maximum value of the power supply voltage VSS.

[0156] Voutmax corresponds to the upper voltage limit that the output voltage Vout must guarantee according to the specifications. Therefore, in order to satisfy the above relationship, it is understood that in circuit design, it is necessary to understand VDDmin (how low VDD can go) and VSSmax (how high VSS can go) and then adjust the current Ib and resistance value Rb (resistor Rb).

[0157] Thus, in both Embodiments 1 and 2, the power supply nodes Np, Npb, and Npc may each supply different power supply voltages (VDD≠VDDb≠VDDc), or any two of the power supply voltages, or all of the power supply voltages, may be equivalent (VDD=VDDb, VDDb=VDDc, VDDc=VDD, VDD=VDDb=VDDc). In other words, the power supply nodes Np, Npb, and Npc may be electrically isolated from each other, or any two of the power supply nodes, or all of the power supply nodes, may be electrically interconnected.

[0158] The power supply voltage VSS transmitted by power supply node Ns may be GND potential or a negative power supply voltage (VSS < 0). Furthermore, when the power supply voltage VSS is a negative voltage, the power supply voltages VDD, VDDb, VDDc are not limited to positive voltages, but can also be negative voltages or GND potential. However, the degrees of freedom for the power supply voltages VDD, VDDb, VDDc, and VSS described above must be limited to the range where the relationship VDD, VDDc, VDDb > VSS is satisfied. In addition, the voltage values ​​of the power supply voltages VDD, VDDb, VDDc, and VSS must be set considering the margin of voltage headroom in the circuit.

[0159] Furthermore, in applications where the output voltage Vout of output circuits 10A and 10B fluctuates rapidly, a delay occurs before the fluctuation in output voltage Vout is transmitted to the fluctuation in back gate voltage VBGn1. If this transmission delay is longer than the required settling time, there is a concern that undesirable fluctuations will occur in the output voltage Vout, causing a delay in settling. The amount of this transmission delay can be calculated using the parasitic capacitance Cbd of the N-type transistor Mn1 (output transistor) and the time constant τ = Rb·Cbd. Therefore, it is necessary to adjust the circuit constant Rb·Cbd appropriately, taking into account the required settling time.

[0160] In Figures 2 to 5 (output circuit 10A according to Embodiment 1) and Figures 6 to 9 (output circuit 10B according to Embodiment 2), a configuration in which back gate control circuits 100N and 101N are provided for each of the N-type transistors Mn1 and Mn2 (output transistors) on the high-side and low-side, respectively, is illustrated. However, it is also possible to configure the system so that the back gate control circuits 100N and 101N are provided for only one of the N-type transistors Mn1 and Mn2 on the high-side and low-side. In this case, the back gate terminal of the N-type transistor (output transistor) for which the back gate control circuits 100N and 101N are not provided can be connected to the source terminal or to the terminal with the lowest potential in the output circuits 10A and 10B. Thus, the back gate control circuits 100N and 101N can be provided for at least one of the N-type transistors Mn1 and Mn2 on the high-side and low-side.

[0161] Embodiment 3. In Embodiment 3, an output buffer circuit and a power amplification module are described as examples of applications of the output circuit according to Embodiment 1 or 2.

[0162] Figure 10 is a conceptual circuit diagram illustrating an example configuration of the output buffer circuit 210 according to Embodiment 3.

[0163] As shown in Figure 10, the output buffer circuit 210 comprises an operational amplifier 5 and an output circuit 10. The output circuit 10 comprehensively represents both the output circuit 10A according to Embodiment 1 and the output circuit 10B according to Embodiment 2. The operational amplifier 5 operates by receiving power supply voltage from power supply nodes Npc (VDDc) and Nsc (VSSc). The output circuit 10A operates by receiving power supply voltage from power supply nodes Np (VDD) and Ns (VSS).

[0164] The operational amplifier 5 is configured such that the input voltage Vin to the output buffer circuit 210 is input to the positive polarity input terminal (+), while the output voltage Vout of the output circuit 10 is input to the negative polarity input terminal (-).

[0165] The positive output (+) of op-amp 5 is input to the output circuit 10 as input voltage Vin1. The negative output (-) of op-amp 5 is input to the output circuit 10 as input voltage Vin2. Specifically, input voltage Vin1 is input to the gate terminal Gn1 of the high-side N-type transistor Mn1 shown in Figure 2, and input voltage Vin2 is input to the gate terminal Gn2 of the low-side N-type transistor Mn2 shown in Figure 2.

[0166] As a result, the output buffer circuit 210 constitutes a voltage follower circuit, and the output voltage Vout of the output circuit 10 can change in accordance with the input voltage Vin to the output buffer circuit 210.

[0167] Therefore, in the output buffer circuit 210 of Figure 10, the following equation (22) holds between the input voltage Vin and the output voltage Vout. Vout = Vin …(22)

[0168] Figure 11 is a conceptual circuit diagram illustrating an example configuration of the output buffer circuit 220 according to Embodiment 3.

[0169] As shown in Figure 11, the output buffer circuit 220 includes the same operational amplifier 5 and output circuit 10 as the output buffer circuit 210 (Figure 10), plus resistors R1 and R2. Hereafter, the resistance values ​​of the resistors R1 and R2 will also be denoted as R1 and R2.

[0170] In the output buffer circuit 220, the input connection to the operational amplifier 5 differs from that of the output buffer circuit 210. Specifically, the operational amplifier 5 is configured such that the reference voltage VREF is input to the positive polarity input terminal (+), while the negative polarity input terminal (-) is connected to node Na. Furthermore, node Na is connected to the input terminal of the input voltage Vin via resistor R1, and also to the output terminal No of the output circuit 10 via resistor R2. As a result, it is understood that the operational amplifier 5 operates as an "inverting amplifier".

[0171] Therefore, in the output buffer circuit 220 in Figure 11, the following equation (23) holds between the input voltage Vin and the output voltage Vout. The constant Rk in equation (23) represents the ratio of the resistance values ​​of the resistors R1 and R2, and Rk = (R2 / R1). Vout=-Rk·Vin+(1+Rk)·VREF …(23)

[0172] In the output buffer circuit 220 in Figure 11, when the power supply voltage VSSc transmitted by the power supply node Nsc is a negative voltage, the reference voltage VREF can be set to GND potential (0V). In this case, by setting VREF = 0 (V) in equation (23), the following equation (24) holds between the input voltage Vin and the output voltage Vout. Vout = -(R2 / R1)·Vin …(24)

[0173] Thus, when the output circuit 10 is applied to the output buffer circuits 210 and 220 shown in Figures 10 and 11, it is clear that the output voltage Vout has a voltage range of analog voltage according to the input voltage Vin, as shown in equations (22) to (24).

[0174] On the other hand, as assumed in Embodiments 1 and 2, if there is no negative feedback path from the output voltage Vout to the input voltage Vin (in the case of an open-loop system), the output voltage Vout will take discrete values ​​of the power supply voltage VDD or power supply voltage VSS depending on the level of the input voltage Vin. In such an open-loop system, it is common to form the output circuit with a complementary combination of a P-type transistor (high-side) and an N-type transistor (low-side) as the output transistors.

[0175] Furthermore, in the output circuit 10 applied to the negative feedback system illustrated in Figures 10 and 11, the output voltage Vout becomes an analog value whose value can be arbitrarily designed by equations (22) to (24). Therefore, through design adjustments, it is possible to stably satisfy equation (9b) throughout the on and off states of the output transistor. In other words, the output circuit 10 according to this embodiment easily avoids the problem of the parasitic diode path between the back gate and drain being turned on, and is understood to be useful for such negative feedback system applications.

[0176] Next, an example configuration of a power amplifier module to which the output circuit according to Embodiment 1 or 2 is applied will be described.

[0177] Figure 12 is a block diagram illustrating an example configuration of a power amplification module according to Embodiment 3.

[0178] As shown in Figure 12, the power amplification module 230 according to Embodiment 3 comprises a power amplification IC (Integrated Circuit) 250 and a bias control IC 300.

[0179] The power amplifier IC 250 is configured as a typical "Doherty amplifier circuit," having an input terminal 252 for the high-frequency signal RFIN, an output terminal 255 for the high-frequency signal RFIN, power amplifiers 260a and 260b, and 90-degree transmission lines 270a and 270b.

[0180] Input terminal 252 is connected to power amplifier 260a and 90-degree transmission line 270b. The input high-frequency signal RFIN is distributed to two paths; one is amplified by power amplifier 260a, and the other is converted to a signal orthogonal to the original RFIN by 90-degree transmission line 270b before being input to power amplifier 260b.

[0181] The signal amplified by power amplifier 260a is converted into an orthogonal signal by 90-degree transmission line 270b. The output signal of 90-degree transmission line 270b and the signal amplified by power amplifier 260b are merged and combined into a high-frequency output signal RFOUT at output terminal 255.

[0182] The bias control IC 300 is configured to supply a DC bias voltage to the power amplifiers 260a and 260b. The bias control IC 300 includes an output section 301, a D / A (Digital to Analog) converter (DAC) 302, a control circuit 303, a temperature sensor 304, and a non-volatile memory 305.

[0183] The temperature sensor 304 and the non-volatile memory 305 are connected to the control circuit 303. This allows the temperature information of the power amplifier module measured by the temperature sensor 304 to be stored in the non-volatile memory 305.

[0184] The control circuit 303 is connected to the DAC 302, and a control signal based on the stored temperature information is sent to the DAC. The control signal based on the temperature information is then converted by the DAC 302 into an analog bias voltage value. The output voltage (analog voltage) of the DAC 302 is then supplied as a bias voltage to the power amplifiers 260a and 260b by the output unit 301.

[0185] The power amplification module 230 is configured to supply a bias voltage to the power amplifiers 260a and 260b, while the signal information input to the power amplification IC 250 is high frequency (high frequency signal RFIN). Therefore, it is desirable for the output section 301 to use an output circuit suitable for outputting analog values. Accordingly, it is suitable to use the output buffer circuits 210 and 220 to which the output circuit 10 according to this embodiment, as illustrated in Figures 10 and 11, is applied as the output section 301.

[0186] In this case, the output circuit 10 according to this embodiment can be applied to any type of load current (output current) applied to the output terminal No of the output unit 301, regardless of whether it is a sink type flowing from output terminal No (Vout) to power node Ns (VSS), a sink-source type flowing from power node Np (VDD) to output terminal No (Vout), or a sink-source type flowing in both directions.

[0187] In particular, when applied to the power amplification module 230 (Figure 12), the load current rapidly changes polarity due to the influence of the input high-frequency signal RFIN, and also has a high peak value. For this reason, the application of the output circuit 10, in which current driving capability is configured by back gate control according to this embodiment, is useful.

[0188] Embodiment 4. While Embodiments 1 and 2 described back gate control for an N-type output transistor, Embodiment 4 describes back gate control for a P-type output transistor as a variation of this embodiment.

[0189] Figure 13 is a circuit diagram illustrating an example configuration of the output circuit 10C according to Embodiment 4. As shown in Figure 13, the output circuit 10C comprises P-type transistors Mp1 and Mp2 with opposite polarity to the output circuit 10A, and a back gate control circuit 100P.

[0190] P-type transistors Mp1 and Mp2 are electrically connected in series between power supply nodes Np and Ns via output terminal No. Specifically, the high-side P-type transistor Mp1 is electrically connected between power supply node Np and output terminal No, and has a source terminal connected to power supply node Np, a drain terminal connected to output terminal No, a gate terminal Gn1 to which the input voltage Vin1 is input, and a back gate terminal BGp1.

[0191] The low-side P-type transistor Mp2 is electrically connected between the output terminal No and the power supply node Ns, and has a drain terminal connected to the power supply node Ns, a source terminal connected to the output terminal No, a gate terminal Gn2 to which the input voltage Vin2 is input, and a back gate terminal BGp2. In the following, P-type transistors Mp1 and Mp2 will also be referred to as "P-type output transistors."

[0192] Therefore, in Embodiment 4, the high-side P-type transistor Mp1 corresponds to one embodiment of the "first output transistor," and the low-side P-type transistor Mp2 corresponds to one embodiment of the "second output transistor." Similar to Embodiments 1 and 2, the power node Np that transmits the power supply voltage VDD corresponds to one embodiment of the "first power supply node," and the power node Ns that transmits the power supply voltage VSS corresponds to one embodiment of the "second power supply node." Furthermore, the input voltage Vin1 corresponds to the "first input voltage," and the input voltage Vin2 corresponds to the "second input voltage."

[0193] The back gate control circuit 100P is provided for at least one of the P-type output transistors Mp1 and Mp2 and is connected to the back gate terminal of the output transistor. The back gate control circuit 100P provided for P-type transistor Mp1 is connected to the back gate terminal BGp1, and the back gate control circuit 100P provided for P-type transistor Mp2 is connected to the back gate terminal BGp2.

[0194] The high-side back gate control circuit 100P includes a resistor Rb connected between power node Np and node N2, which transmit the power supply voltage VDD, and a current generation circuit 110P. The current generation circuit 110P is connected between node N2 and power node Ns, which transmits the power supply voltage VSSb. Node N2 is connected to the back gate terminal BGp1. As a result, the resistor Rb is electrically connected between the back gate terminal BGp1 and the source terminal (S) of the P-type transistor Mp1 via node N2 and power node Np.

[0195] The low-side back gate control circuit 100P includes a resistor Rb connected between output terminal No and node N2, and a current generation circuit 110P. The current generation circuit 110P is connected between node N2 and power supply node Nsb. Node N2 is connected to the back gate terminal BGp2. In the back gate control circuit 100P, the resistor Rb corresponds to one embodiment of the "first resistor". The current Ib generated by the current generation circuit 110P corresponds to one embodiment of the "control current".

[0196] Furthermore, in the back gate control circuit 100P, node N2 corresponds to one embodiment of an "internal node," and power node Nsb corresponds to one embodiment of a "third power node."

[0197] The back gate control circuit 100P is configured with the opposite polarity to the back gate control circuit 100N in Figure 2, and the low-side back gate control circuit 100P is positioned between the output terminal No and the back gate terminal BGn2. As a result, even on the low-side, the resistive element Rb is electrically connected between the back gate terminal BGp2 and the source terminal (S) of the P-type transistor Mp2 via node N2 and output terminal No.

[0198] The current generation circuit 110P can be constructed by reversing the polarity of the transistors and power supplies in the current generation circuits 110A to 110C illustrated in Figures 3 to 5. Specifically, the current generation circuit 110P can be constructed by replacing each N-type transistor with a P-type transistor, replacing power supply node Npb with power supply node Nsb, and power supply node Ns with power supply node Npb.

[0199] Specifically, when applying the configuration of the current generation circuit 110A in Figure 3 to the current generation circuit 110P, the P-type transistor Mpb corresponding to the "current generation transistor" can be replaced with an N-type transistor and connected between the power supply node Nsb and node N2. Therefore, the N-type transistor can be configured to have a source terminal connected to the power supply node Nsb, a drain terminal connected to node N2, and a gate terminal to which the bias voltage from the bias circuit 102 is input.

[0200] Similarly, when applying the configuration of the current generation circuit 110B in Figure 4 to the current generation circuit 110P, the resistor R0 corresponding to the "second resistor" can be connected between the power supply node Nsb and node N2.

[0201] Furthermore, when applying the configuration of the current generation circuit 110C in Figure 5 to the current generation circuit 110P, the N-type transistor Mnb1 corresponding to the "current generation transistor" can be replaced with a P-type transistor and connected between the power supply node Nsb and node N2. Therefore, the P-type transistor can be configured to have a drain terminal connected to the power supply node Nsb, a source terminal connected to node N2, and a gate terminal interconnected with the gate terminal of the output transistor, the P-type transistor Mp1.

[0202] Figure 13 illustrates the effect of the low-side back gate control circuit 101P on lowering the threshold voltage of the P-type transistor.

[0203] The back gate voltage VBGp2 applied to the back gate terminal BGp2 of the P-type transistor Mp2 is controlled by the back gate control circuit 101P to VBGp2 = Vout - Ib·Rb. Also, the source voltage Vs2 = Vout of the P-type transistor Mp2. Therefore, the source-back gate voltage Vsbp2 (Vsbp2 = Vs2 - VBGp2) of the P-type transistor Mp2 is given by the following equation (25). Vsbp² = Ib·Rb …(25)

[0204] As shown in equation (1), it is known that the threshold voltage of a transistor is a function of the reverse voltage of the pn junction. In the case of an N-type transistor, the reverse voltage of the pn junction is the voltage applied from the source terminal (n) to the back gate terminal (p), and in equation (1), the second term is a function of the source-back gate voltage Vsb. On the other hand, in a P-type transistor, the reverse voltage is the voltage applied from the back gate terminal (n) to the source terminal (p), so "Vsb" in equation (1) is replaced by the back gate-source voltage "Vbs = -Vsb". Therefore, the threshold voltage Vthp2 of a P-type transistor Mp2 is given by equation (26) below, derived from equations (1) and (25) above.

number

[0205] Therefore, by controlling the back gate voltage with the back gate control circuit 101P so that the source voltage is higher (Vsbp2>0), the second term of equation (26) can be made negative, making it possible to lower the threshold voltage Vthp2 below Vt0 even in a P-type transistor.

[0206] As a result, according to the output circuit 10C of Embodiment 4, the current driving capability can be improved by increasing the drain-source current for the same size P-type output transistors through voltage control (Vsb>0) of the back gate terminals of the P-type transistors Mp1 and Mp2 by the back gate control circuit 100P.

[0207] Furthermore, the current generation circuit 110P, like the current generation circuit 110N, can be constructed using small-area transistors and / or resistors that do not require ESD countermeasures. Therefore, it can be constructed in a significantly smaller area compared to when ESD countermeasures are required. As a result, it is understood that the circuit area required to house the current generation circuit 110P is significantly reduced compared to the circuit area of ​​the N-type transistor M3 in the comparative example (Figure 1).

[0208] Furthermore, the voltage range for suppressing leakage current due to parasitic diodes in the back gate voltage VBGp of the P-type output transistor controlled by the back gate control circuit 100P can also be expressed by equation (27), which is a modified version of equation (9b). max(Vs-Vf,Vd)≦VBGp≦VDD…(27)

[0209] In equation (27), the back gate voltage VBGp of a P-type output transistor controlled by the back gate control circuit 100P is defined by the relationship between the source voltage Vs and drain voltage Vd of the output transistor (P-type). As mentioned above, VBGp is ​​given by VBGp = Vs - Rb·Ib. Max(A,B) is a function that compares the magnitudes of A and B and selects the largest value among them.

[0210] A modified example of Embodiment 4. In the output circuit 10C according to Embodiment 4, similar to the output circuit 10A, there is room for improvement in suppressing leakage current due to parasitic diodes formed on the P-type transistors Mp1 and Mp2. Therefore, the effect of suppressing leakage current can be enhanced by arranging the enable control switches SW1 and SW2 for the P-type output transistors Mp1 and Mp2 in the same way as in the output circuit 10B (Figure 6).

[0211] Figure 14 is a circuit diagram illustrating an example of the configuration of the output circuit 10D according to a modified example of Embodiment 4.

[0212] As shown in Figure 14, the output circuit 10D differs from the output circuit 10C shown in Figure 13 in that it includes a back gate control circuit 101P instead of the back gate control circuit 100P, and that it includes enable control switches SW1 and SW2. The back gate control circuit 101P differs from the back gate control circuit 100P (Figure 2) in that it includes a current generation circuit 120P instead of the current generation circuit 110P.

[0213] The enable control switch SW1 is connected between the gate terminal Gp1 of the P-type transistor Mp1 and the power supply node Npc (VDDc). The enable control switch SW2 is connected between the gate terminal Gp2 of the P-type transistor Mp2 and the power supply node Ns (VSS). The power supply node Npc transmits the power supply voltage VDDc.

[0214] During the enable-on period (EN=H level), the enable control switches SW1 and SW2 are in the off state, so the gate voltages of the P-type transistors (output transistors) Mp1 and Mp are biased by the input voltages Vin1 and Vin2 to the gate terminals Gp1 and Gp2. This makes it possible to drive the subsequent circuit (not shown) connected to output terminal No in accordance with the input voltages Vin1 and Vin2.

[0215] During the enable-off period (EN=L level), enable control switches SW1 and SW2 are in the ON state. As a result, gate terminals Gp1 and Gp2 are connected to power supply nodes Npc (VDDC) and Ns (VSS). Consequently, P-type transistors Mp1 and Mp2 are biased by the power supply voltages VDDc and VSS, respectively. This causes the high-side P-type transistor Mp1 to be in the OFF state and the low-side P-type transistor Mp2 to be in the ON state. As a result, if the impedance of P-type transistor Mp2 is sufficiently low for the current flowing into P-type transistor Mp2 from output terminal No, the output voltage Vout of output terminal No is clamped to the power supply voltage VSS.

[0216] The current generation circuit 120P, like the current generation circuit 120N, generates current Ib when the enable signal EN is at a high level (during the enable-on period), similar to the current generation circuit 110P. On the other hand, when EN is at a low level, it does not generate current and is configured to be in a high-impedance state.

[0217] Furthermore, the current generation circuit 120P can be constructed in the same way as described for the current generation circuit 110P, by reversing the polarity of the transistors and power supply in the current generation circuits 120A to 120C exemplified in Figures 7 to 9. That is, by modifying the circuit configuration of the current generation circuits 110A to 110C described above to apply to the current generation circuit 110P, an enable function can be realized by adding an N-type transistor as a "switch transistor" that replaces the P-type transistors Mswb and Mswr in the current generation circuits 120A to 120C in Figures 7 to 9.

[0218] As a result, in output circuit 10D, which has an enable function added to output circuit 10C (Figure 13), when the enable is off, the output voltage Vout is clamped to the power supply voltage VSS by turning on the enable control switch SW2. As a result, leakage current generated in the parasitic diodes that use the back gate terminals of output transistors Mp1 and Mp2 connected to output terminal No as cathodes (N type) can be suppressed.

[0219] Similar to output circuit 10B, output circuit 10D also achieves circuit area reduction by eliminating the need to place a large-area N-type transistor M3 (Figure 1) that requires ESD countermeasures, thereby achieving the same leakage current suppression effect as the comparative example (Figure 1). Furthermore, similar to output circuit 10B, it is conceivable that enable control switches SW1 and SW2 do not need to be newly placed specifically for output circuit 10D.

[0220] Furthermore, in the output circuit 10C shown in Figure 13, it is also possible to modify the circuit by replacing the current generation circuit 110P with a current generation circuit 120P that has an enable function. In this case, while the leakage current suppression effect (in the phase where Vout > VDD) as in the output circuit 10D does not occur, the power consumption can be reduced compared to the output circuit 10A by having the current generation circuit 120P stop supplying current during the enable-off period.

[0221] In the output circuits 10C and 10D according to Embodiment 4 and its modified versions, the power supply nodes Ns (VSS) and Nsb (VSSb) are described separately, but power supply nodes Ns and Nsb may each supply different power supply voltages (VSS ≠ VSSb) or they may supply equivalent power supply voltages (VSS = VSSb). That is, power supply nodes Ns and Nsb may be electrically isolated from each other or electrically interconnected. Furthermore, the power supply voltages VSS and VSSb may both be at GND potential or negative power supply voltages (VSS < 0, VSSb < 0).

[0222] Furthermore, when VSS is a negative voltage, the power supply voltages VDD and VDDc transmitted by power supply nodes Np and Npc are not limited to positive voltages, but can also be negative voltages or even GND potential. However, as mentioned above, the degrees of freedom for power supply voltages VDD, VDDc, VSS, and VSSb must be limited to the range where the relationship VDD, VDDc > VSS, VSSb is satisfied. In addition, the voltage values ​​of power supply voltages VDD, VDDc, VSS, and VSSb must be set considering the margin of the circuit's voltage headroom.

[0223] In Embodiments 1, 2, and 4 and their modifications, configurations were described in which the high-side and low-side output transistors are of the same conductivity type (N-type or P-type). However, the back-gate control according to this embodiment can also be applied when complementary conductivity types of output transistors are used for the high-side and low-side. In this case as well, a back-gate control circuit can be provided for at least one of the high-side and low-side output transistors.

[0224] For example, it is possible to configure the output transistor on the high side as an N-type transistor and the output transistor on the low side as a P-type transistor. In this case, the high-side N-type transistor can be connected to the high-side back gate control circuits 100N and 101N shown in Figure 2 or Figure 6. Furthermore, the low-side P-type transistor can be connected to the low-side back gate control circuits 100P and 101P shown in Figure 13 or Figure 14.

[0225] Alternatively, the output transistor on the high side can be a P-type transistor, and the output transistor on the low side can be an N-type transistor. In this case, the high-side P-type transistor can be connected to the high-side back gate control circuits 100P and 101P shown in Figure 13 or Figure 14. The low-side N-type transistor can be connected to the low-side back gate control circuits 100N and 101N shown in Figure 2 or Figure 6.

[0226] In the simplest form of the back gate control circuit, the 100N and 100P, the back gate control circuit consists of a resistor (Rb) and a current generation circuit (110N, 110P). The resistor Rb is connected between the source terminal and back gate terminal of the connected output transistor (N-type, P-type) via a power supply node (Np, Ns) or output terminal No. The current generation circuit (110N, 110P) outputs a current Ib that passes through the resistor Rb, thereby generating a voltage drop (Ib·Rb) across the resistor and controlling the back gate voltage. This back gate voltage control increases the current supply capability of the output transistor by making the back gate-source voltage Vbs of the N-type output transistor a negative value, or the back gate-source voltage Vbs of the P-type output transistor a positive value.

[0227] Furthermore, in this embodiment, an example in which field-effect transistors are applied to each transistor constituting the current generation circuits 110N, 120N (and 110P, 120P) was explained using Figures 3 to 5 and Figures 7 to 9. However, since the presence or absence of a back gate is not an issue for each transistor constituting each current generation circuit, it is possible to replace these transistors with bipolar transistors.

[0228] That is, in the current generation circuits 110N and 120N shown in Figures 3 to 5 and Figures 7 to 9, and the current generation circuits 110P and 120P obtained by reversing the polarity of the transistors, each P-type transistor can also be constructed using a pnp-type bipolar transistor, and each N-type transistor can be constructed using an npn-type bipolar transistor. Note that when using bipolar transistors, the "source (terminal)" of each P-type transistor and each N-type transistor can be read as the "emitter (terminal)", the "drain (terminal)" as the "collector (terminal)", and the "gate (terminal)", which is the "control electrode", as the "base (terminal)".

[0229] <Note> The embodiments and variations described above include the following technical concepts. [Configuration 1] An output circuit for generating an output voltage (Vout) corresponding to a first input voltage (Vin1) and a second input voltage (Vin2) at an output terminal (No) to which a load is connected, A first power node (Np) that transmits a first power supply voltage (VDD) and a field-effect type first output transistor (Mn1, Mp1) connected between the output terminal and the first power supply node (Np) having a gate terminal that receives the first input voltage, A field-effect type second output transistor having a gate terminal that receives the second input voltage is connected between a second power node (Np) that transmits a second power supply voltage (VSS) lower than the first power supply voltage and the output terminal, The system includes a back gate control circuit (100N, 100P, 101N, 101P) provided for at least one of the first output transistor and the second output transistor, The aforementioned back gate control circuit is A first resistive element (Rb) is electrically connected between the back gate terminals (BGn1, BGn2, BGp1, BGp2) and source terminal (S) of the corresponding output transistors among the first and second output transistors, The system includes a current generation circuit (110N, 110P) that generates a control current (Ib) that passes through the first resistive element, The current generation circuit is an output circuit that generates the control current for the corresponding N-type output transistors (MN1, Mn2) in a direction such that a voltage drop occurs across the first resistive element such that the voltage at the back gate terminal is higher than the voltage at the source terminal, and generates the control current for the corresponding P-type output transistors (Mp1, Mp2) in a direction such that a voltage drop occurs across the first resistive element such that the voltage at the source terminal is higher than the voltage at the back gate terminal.

[0230] [Configuration 2] The output circuit according to configuration 1, wherein the current generation circuit (120N, 120P) is configured to generate the control current during the enable-on period and to stop generating the control current (Ib) during the enable-off period.

[0231] [Configuration 3] The current generation circuit (120N, 120P) is configured to generate the control current during the enable-on period, while stopping the generation of the control current (Ib) during the enable-off period. A first enable control switch (SW1) is connected between one of the first power supply node (Np) and the second power supply node (Ns) and the gate terminals (Gn1, Gp1) of the first output transistor (Mn1, Mp1), The system includes a second enable control switch (SW2) connected between the other of the first and second power supply nodes and the gate terminals (Gn2, Gp2) of the second output transistor (Mn2, Mp2), During the enable-on period, both the first enable control switch and the second enable control switch are turned off, The output circuit according to configuration 1, wherein during the enable-off period, the first enable control switch and the second enable control switch are turned on so as to keep the second output transistor in the ON state while keeping the first output transistor in the OFF state.

[0232] [Structure 4] The current generation circuit (110A) is, It has a third power supply node (Npb, Nsb) and a current generating transistor (Mpd) connected between the back gate terminals (BGn1, BGn2, BGp1, BGp2) and the internal nodes (N1, N2) connected to the first resistive element (Rb), The current generating transistor is The source terminal or emitter terminal connected to the third power node, A drain terminal or collector terminal connected to the aforementioned internal node, The output circuit according to configuration 1, having a gate terminal or base terminal to which a constant bias voltage (Vbp) is input.

[0233] [Composition 5] The current generation circuit (110B) is, It includes a third power supply node (Npb, Nsb) and a current generating transistor (Mpd) connected between the back gate terminals (BGn1, BGn2, BGp1, BGp2) and the internal nodes (N1, N2) connected to the first resistive element (Rb), The current generating transistor is The source terminal or emitter terminal connected to the third power node (Npb, Nsb), A drain terminal or collector terminal connected to the aforementioned internal node, It has a gate terminal or base terminal to which a constant bias voltage (Vbp) is input, The current generation circuit (110B) is, The system further includes a switch transistor (Mswb) connected between the third power supply node and the gate terminal or base terminal of the current generating transistor, The output circuit according to configuration 2 or 3, wherein the switch transistor is turned off during the enable-on period, while during the enable-off period, it is turned on to put the current generating transistor into a high-impedance state and stop generating the control current (Ib).

[0234] [Composition 6] The current generation circuit (120A) is, The output circuit according to configuration 1, comprising a third power supply node (Npb, Nsb) and a second resistive element (R0) connected between the back gate terminals (BGn1, BGn2, BGp1, BGp2) and the internal nodes (N1, N2) connected to the first resistive element (Rb).

[0235] [Composition 7] The current generation circuit (120B) is A third power supply node (Npb, Nsb) and a second resistor (R0) connected between the back gate terminals (BGn1, BGn2, BGp1, BGp2) and the internal nodes (N1, N2) connected to the first resistor (Rb), Between the third power supply node and the internal node, a switch transistor (Mswb) is connected in series with the second resistive element, The output circuit according to configuration 2 or 3, wherein the switch transistor is turned on during the enable-on period and turned off during the enable-off period to stop the output of the control current (Ib).

[0236] [Structure 8] The current generation circuit (110C) is It includes a current generating transistor (Mnb1) connected between a third power supply node (Npb, Nsb) and an internal node (N1, N2) connected to the back gate terminals (BGn1, BGn2, BGp1, BGp2) and the first resistor element (Rb). The current generating transistor is a drain terminal or a collector terminal connected to the third power supply node (Npb, Nsb), a source terminal or an emitter terminal connected to the internal node, and a gate terminal or a base terminal interconnected with the gate terminal of the corresponding output transistor (Mn1, Mn2, Mp1, Mp2). The output circuit according to Configuration 1

[0237] [Configuration 9] The current generating circuit (120C) is including a current generating transistor (Mnb1) and a switch transistor (Mswb) connected in series between a third power supply node (Npb, Nsb) and an internal node (N1, N2) connected to the back gate terminals (BGn1, BGn2, BGp1, BGp2) and the first resistor element (Rb). The current generating transistor is a drain terminal or a collector terminal electrically connected to the third power supply node via the switch transistor, a source terminal or an emitter terminal connected to the internal node, and a gate terminal or a base terminal interconnected with the gate terminal of the corresponding output transistor (Mn1, Mn2, Mp1, Mp2). The switch transistor is turned on during the enable - on period and turned off to stop the output of the control current (Ib) during the enable - off period. The output circuit according to Configuration 2 or 3

[0238] [Configuration 10] At least one of the first output transistor (Mn1) and the second output transistor (Mn2) is composed of an N - type transistor. The output circuit according to any one of configurations 1 to 9, wherein the value of the control current (Ib) and the resistance value of the first resistor (Rb) are determined such that the voltage at the back gate terminal (VBGn) of the N-type transistor controlled by the back gate control circuit is equal to or greater than the second power supply voltage (VSS), and is lower than either the drain voltage (Vd) of the N-type output transistor or the voltage value (Vs+Vf) obtained by adding the forward voltage (Vf) of the pn junction formed between the back gate terminal and the drain terminal or the source terminal of the N-type output transistor to the source voltage (Vs).

[0239] [Composition 11] Either the first output transistor (Mp1) or the second output transistor (Mp1) is composed of a P-type transistor. The output circuit according to any one of configurations 1 to 9, wherein the value of the control current (Ib) and the resistance value of the first resistor (Rb) are determined such that the voltage at the back gate terminal (VBGp) of the P-type transistor controlled by the back gate control circuit is less than or equal to the first power supply voltage (VDD), and is higher than either the drain voltage (Vd) of the P-type transistor or the voltage value (Vs-Vf) obtained by subtracting the forward voltage (Vf) of the pn junction formed between the back gate terminal and the drain terminal or the source terminal of the P-type transistor from the source voltage (Vs).

[0240] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of this disclosure is indicated by the claims rather than the foregoing description, and all modifications within the meaning and scope equivalent to the claims are intended. [Explanation of Symbols]

[0241] 5 Op-amps, 10, 10A, 10B, 10C, 10D, 10X Output circuits, 100N, 100P, 100X, 101N, 101P Back gate control circuits, 102 Bias circuits, 110, 110A, 110B, 110C, 110N, 110P, 120, 120A, 120B, 120C, 120N, 120P Current generation circuits, 210, 220 Output buffer circuits, 230 Power amplification module, 250 Power amplification IC, 252 Input terminals, 255 Output terminals (power amplification module), 260a, 260b Power amplifiers, 270a, 270b 90-degree lines, 300 Bias control IC, 301 Output section, 303 Control circuit, 304 Temperature sensor, 305 Non-volatile memory, BGn1, BGn2, BGp1, BGp2 back gate terminals, Cbd parasitic capacitance, Cox gate oxide capacitance, EN enable signal, ENB enable invert signal, G1~G4, Gn1, Gn2, Gp1, Gp2 gate terminals, Ib, Ibd, Ids1, Is current, Iout output current, M3, M4 N-type transistors, Mn1, Mn2, Mp1, Mp2 output transistors, Mnb1 N-type transistor (current generating transistor), Mpb P-type transistor (current generating transistor), Mswb, Mswr P-type transistor (switching transistor), N0, N1, N2, Na nodes, No output terminal (output circuit), Np, Npb, Npc, Ns, Nsb, Nsc power supply nodes, R0, R1, R2, Rb resistors, RFIN high-frequency signal, RFOUT High-frequency output signal, Rb resistor element (resistance value), SW1, SW2 enable control switches, VBGn1, VBGn2, VBGp2 back gate voltage, VDD, VDDb, VDDc, VSS, VSSb, VSSc power supply voltage, VGn1 gate voltage, VREF reference voltage, Vbp bias voltage, Vf forward voltage (pn junction), Vin1, Vin2 input voltage, Vout output voltage.

Claims

1. An output circuit for generating an output voltage corresponding to a first input voltage and a second input voltage at an output terminal to which a load is connected, A first power supply node that transmits a first power supply voltage and a field-effect type first output transistor connected between the output terminal and the first power supply node, having a gate terminal that receives the first input voltage, A field-effect type second output transistor having a gate terminal that receives the second input voltage is connected between a second power supply node that transmits a second power supply voltage lower than the first power supply voltage and the output terminal, The system comprises a back gate control circuit provided for at least one of the first output transistor and the second output transistor, The aforementioned back gate control circuit is A first resistive element electrically connected between the back gate terminal and the source terminal of the corresponding output transistor among the first and second output transistors, The circuit includes a current generation circuit that generates a control current that passes through the first resistive element, The current generation circuit is an output circuit that generates the control current in a direction such that, for the corresponding N-type output transistor, a voltage drop occurs across the first resistive element such that the voltage at the back gate terminal is higher than the voltage at the source terminal, and for the corresponding P-type output transistor, the control current is generated in a direction such that the voltage at the first resistive element is higher than the voltage at the back gate terminal.

2. The output circuit according to claim 1, wherein the current generation circuit is configured to generate the control current during the enable-on period and to stop generating the control current during the enable-off period.

3. The current generation circuit is configured to generate the control current during the enable-on period and to stop generating the control current during the enable-off period. A first enable control switch connected between one of the first power supply node and the second power supply node and the gate terminal of the first output transistor, The system comprises a second enable control switch connected between the other of the first and second power supply nodes and the gate terminal of the second output transistor, During the enable-on period, both the first enable control switch and the second enable control switch are turned off, The output circuit according to claim 1, wherein during the enable-off period, the first enable control switch and the second enable control switch are turned on so as to keep the second output transistor in the ON state while keeping the first output transistor in the OFF state.

4. The current generation circuit is The third power supply node has a current generating transistor connected between it and the internal node connected to the back gate terminal and the first resistive element, The current generating transistor is The source terminal or emitter terminal connected to the third power supply node, A drain terminal or collector terminal connected to the aforementioned internal node, The output circuit according to claim 1, having a gate terminal or a base terminal to which a constant bias voltage is input.

5. The current generation circuit is It includes a third power supply node and a current generating transistor connected between the back gate terminal and the internal node connected to the first resistive element, The current generating transistor is The source terminal or emitter terminal connected to the third power supply node, A drain terminal or collector terminal connected to the aforementioned internal node, It has a gate terminal or base terminal to which a constant bias voltage is input, The current generation circuit is The system further includes a switch transistor connected between the third power supply node and the gate terminal or the base terminal of the current generating transistor, The output circuit according to claim 2 or 3, wherein the switch transistor is turned off during the enable-on period, and turned on during the enable-off period to stop the generation of the control current by putting the current generation transistor into a high-impedance state.

6. The current generation circuit is The output circuit according to claim 1, further comprising a third power supply node and a second resistive element connected between the back gate terminal and an internal node connected to the first resistive element.

7. The current generation circuit is A third power supply node and a second resistive element connected between the back gate terminal and the internal node connected to the first resistive element, The third power supply node and the internal node include a switch transistor connected in series with the second resistive element, The output circuit according to claim 2 or 3, wherein the switch transistor is turned on during the enable-on period and turned off during the enable-off period to stop generating the control current.

8. The current generation circuit is It includes a third power supply node and a current generating transistor connected between the back gate terminal and the internal node connected to the first resistive element, The current generating transistor is A drain terminal or collector terminal connected to the third power node, The source terminal or emitter terminal connected to the aforementioned internal node, The output circuit according to claim 1, further comprising a gate terminal or base terminal interconnected with the gate terminal of the corresponding output transistor.

9. The current generation circuit is The third power supply node includes a current generating transistor and a switch transistor connected in series between the third power supply node and the internal node connected to the back gate terminal and the first resistive element, The current generating transistor is The drain terminal or collector terminal is electrically connected to the third power supply node via the switch transistor, The source terminal or emitter terminal connected to the aforementioned internal node, The gate terminal or base terminal is interconnected with the gate terminal of the corresponding output transistor, The output circuit according to claim 2 or 3, wherein the switch transistor is turned on during the enable-on period and turned off during the enable-off period to stop generating the control current.

10. At least one of the first output transistor and the second output transistor is an N-type transistor, The output circuit according to any one of claims 1 to 3, wherein the value of the control current and the resistance value of the first resistive element are determined such that the voltage at the back gate terminal of the N-type transistor controlled by the back gate control circuit is equal to or greater than the second power supply voltage, and is lower than either the drain voltage of the N-type transistor or the voltage value obtained by adding the forward voltage of the pn junction formed between the back gate terminal and the drain terminal or the source terminal of the N-type transistor to the source voltage.

11. Either the first output transistor or the second output transistor is a P-type transistor. The output circuit according to any one of claims 1 to 3, wherein the value of the control current and the resistance value of the first resistive element are determined such that the voltage at the back gate terminal of the P-type transistor controlled by the back gate control circuit is less than or equal to the first power supply voltage, and is higher than either the drain voltage of the P-type transistor or the voltage value obtained by subtracting the forward voltage of the pn junction formed between the back gate terminal and the drain terminal or the source terminal of the P-type transistor from the source voltage.

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