A multi-mosfet stacked power amplifier circuit and a driving circuit

Abstract

The application relates to the technical field of power amplification circuits, and particularly provides a multi-MOS power amplification circuit and a driving circuit, which comprises a push-pull amplification circuit, a voltage dividing resistor string arranged between a first power supply voltage and a second power supply voltage, a plurality of capacitors, a first MOS tube string comprising a plurality of first type MOS tubes which are connected in series and have the same type as a first main MOS tube, a second MOS tube string comprising a plurality of second type MOS tubes which are connected in series and have the same type as a second main MOS tube, a plurality of first unidirectional conducting devices, two ends of each first unidirectional conducting device being connected with a corresponding voltage dividing point and a source of a corresponding first type MOS tube respectively, a plurality of second unidirectional conducting devices, two ends of each second unidirectional conducting device being connected with a corresponding voltage dividing point and a source of a corresponding second type MOS tube respectively, and the circuit can effectively reduce the withstand voltage requirement of the MOS tube of the power amplification circuit.

Description

Technical Field

[0001] This application relates to the field of power amplifier circuit technology, and more specifically, to a power amplifier circuit and driving circuit with multiple MOS transistors stacked together. Background Technology

[0002] Power amplifier circuits amplify weak electrical signals and are widely used to drive loads such as loudspeakers or piezoelectric ceramic nozzles. These loads require a large continuous drain current Id. For example, the single-orifice current of a piezoelectric ceramic nozzle is typically 0.005A, and the number of nozzles is typically 256, 1024, or 2048. When the number of nozzles is 256, the total current requirement of the piezoelectric ceramic nozzle is 1.28A; when the number of nozzles is 256, the total current requirement is 5.12A; and when the number of nozzles is 256, the total current requirement is 10.24A.

[0003] Existing technologies typically employ a two-stage power amplifier. First, a first-stage power amplifier amplifies the signal to the required voltage. Then, a second-stage power amplifier amplifies the current to achieve power amplification. Current current amplification circuits (second-stage power amplifiers) usually employ a push-pull amplifier circuit. (See reference...) Figure 1 ( Figure 1 In this context, VS_IN is the voltage input terminal. Figure 1 In this context, VS_OUT is the power output terminal. Figure 1 In this context, S represents the source. Figure 1 In this context, D represents the drain electrode. Figure 1 In this circuit, G represents the gate, and the circuit consists of an NMOS transistor ( Figure 1 q1) and PMOS transistor ( Figure 1 The amplifier consists of q2), with NMOS and PMOS transistors conducting alternately to control the current during the positive and negative half-cycles of the amplified signal, respectively. This push-pull amplifier circuit requires that the source-gate breakdown voltage VDS of both the NMOS and PMOS transistors be greater than the difference between VCC_MAX and VCC_MIN. According to the VthId curve of the MOS transistor, when the MOS transistor is used as an amplifier, it must operate in the constant current region.

[0004] It is evident that existing power amplifier circuits require MOSFETs to simultaneously meet the requirements of high VDS withstand voltage, large continuous drain current Id, and VthId characteristic curve within the signal range. Therefore, existing power amplifier circuits suffer from difficulties in MOSFET selection and a limited number of usable MOSFET models.

[0005] There is currently no effective technical solution to the above problems. Summary of the Invention

[0006] The purpose of this application is to provide a power amplifier circuit and driving circuit with multiple MOSFETs stacked together, which can effectively reduce the voltage withstand requirement of the MOSFETs in the power amplifier circuit.

[0007] In a first aspect, this application provides a power amplifier circuit with multiple MOS transistors stacked together, comprising:

[0008] A push-pull amplifier circuit, comprising a first main MOSFET and a second main MOSFET of opposite types;

[0009] A voltage divider resistor string is set between a first power supply voltage and a second power supply voltage, and includes multiple first resistors connected in series to form multiple voltage divider points. The first power supply voltage is greater than the second power supply voltage.

[0010] Multiple capacitors, the number of which is the same as the number of first resistors, each capacitor corresponds to one first resistor, and each capacitor is connected in parallel with its corresponding first resistor;

[0011] The first MOSFET string has its two ends connected to the first power supply voltage and the drain of the first main MOSFET, respectively, and includes multiple first-type MOSFETs connected in series and of the same type as the first main MOSFET;

[0012] The second MOSFET string has its two ends connected to the second power supply voltage and the drain of the second main MOSFET, respectively, and includes multiple second-type MOSFETs connected in series and of the same type as the second main MOSFET;

[0013] Multiple first unidirectional conducting devices, each first unidirectional conducting device corresponding to a voltage divider point and a first type MOS transistor, each of the two ends of the first unidirectional conducting device being connected to its corresponding voltage divider point and the source of its corresponding first type MOS transistor respectively, and the conducting direction of the first unidirectional conducting device being from the voltage divider point to the first type MOS transistor;

[0014] Multiple second unidirectional conducting devices are provided, each corresponding to a voltage divider point and a second type MOSFET. The two ends of each second unidirectional conducting device are connected to the source of its corresponding voltage divider point and its corresponding second type MOSFET, respectively. The conduction direction of the second unidirectional conducting device is from the second type MOSFET to the voltage divider point.

[0015] This application provides a power amplifier circuit with multiple MOSFETs stacked together. By introducing a voltage divider resistor string, a capacitor, a first MOSFET string, a second MOSFET string, a first unidirectional conducting device, and a second unidirectional conducting device, it effectively reduces the voltage that each MOSFET in the power amplifier circuit needs to withstand while effectively amplifying the current. Therefore, this application can effectively reduce the voltage withstand value requirement of the MOSFETs in the power amplifier circuit, thereby effectively broadening the selection range of MOSFETs and effectively solving the problems of difficult MOSFET selection and limited available MOSFET models.

[0016] Optionally, the gates of the first main MOSFET and the second main MOSFET are both connected to the voltage input terminal, the sources of the first main MOSFET and the second main MOSFET are both connected to the voltage output terminal, and the gates of all first-type MOSFETs and all second-type MOSFETs are connected to the voltage output terminal.

[0017] Optionally, the number of Type I MOSFETs is the same as the number of Type II MOSFETs, with the number of Type I MOSFETs being 2-5.

[0018] The symmetry in the number of Type I and Type II MOSFETs ensures that the upper arm (composed of the first MOSFET string) and lower arm (composed of the second MOSFET string) of the push-pull amplifier circuit can provide balanced driving capability and voltage sharing characteristics during the positive and negative half-cycles. Therefore, this technical solution can make the voltage stress borne by each MOSFET uniformly distributed throughout the entire signal cycle, so as to avoid the occurrence of local overload or hot spot phenomena. By limiting the number of MOSFETs to 2-5, this technical solution effectively reduces the withstand voltage requirement of a single MOSFET while avoiding the additional parasitic effects and circuit complexity introduced by an excessive number of MOSFETs. Thus, the power amplifier circuit has good frequency response and reliability while maintaining high efficiency and stability.

[0019] Optionally, the first main MOSFET is an NMOS transistor, the drain of the first type MOSFET is connected to the first power supply voltage, and the source of the last type MOSFET is connected to the drain of the first main MOSFET.

[0020] Optionally, the second main MOSFET is a PMOS transistor, the source of the first type II MOSFET is connected to the drain of the second main MOSFET, and the drain of the last type II MOSFET is connected to the second power supply voltage.

[0021] Optionally, the number of first resistors is equal to the sum of the number of first main MOSFETs and the number of first type MOSFETs.

[0022] Optionally, all the first resistors have the same resistance value.

[0023] This technical solution creates multiple uniformly distributed voltage divider points between the first and second power supply voltages by setting all the first resistors to the same value. This allows the voltage divider resistor string to provide a uniformly distributed bias voltage, enabling the first main MOSFET, second main MOSFET, first type MOSFET, and second type MOSFET connected to these voltage divider points to obtain more stable and balanced bias conditions. This helps maintain the normal operation of the first main MOSFET, second main MOSFET, first type MOSFET, and second type MOSFET, and avoids local overvoltage or undervoltage problems caused by uneven bias voltage distribution, thereby effectively improving the stability and reliability of the power amplifier circuit.

[0024] Optionally, the first unidirectional conducting device is a unidirectional diode.

[0025] Optionally, the second unidirectional conducting device is a unidirectional diode.

[0026] Secondly, this application also provides a driving circuit, which includes a load and a power amplifier circuit with multiple MOS transistors superimposed as described in the first aspect, wherein the load is connected to a second power supply voltage and the source of a first main MOS transistor, respectively.

[0027] This application provides a driving circuit that, by introducing a voltage divider resistor string, a capacitor, a first MOSFET string, a second MOSFET string, a first unidirectional conducting device, and a second unidirectional conducting device, effectively reduces the voltage that each MOSFET in the power amplifier circuit needs to withstand while effectively amplifying the current. Therefore, this application can effectively reduce the voltage withstand value requirement of the MOSFET in the power amplifier circuit, thereby effectively broadening the selection range of MOSFETs and effectively solving the problems of difficult MOSFET selection and limited available MOSFET models.

[0028] As can be seen from the above, the power amplifier circuit and driving circuit with multiple MOSFETs stacked in this application effectively reduce the voltage that each MOSFET in the power amplifier circuit needs to withstand while effectively amplifying the current, by introducing a voltage divider resistor string, a capacitor, a first MOSFET string, a second MOSFET string, a first unidirectional conducting device, and a second unidirectional conducting device. Therefore, this application can effectively reduce the voltage withstand value requirement of the MOSFET in the power amplifier circuit, thereby effectively broadening the selection range of MOSFETs and effectively solving the problems of difficult MOSFET selection and limited available MOSFET models. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of an existing push-pull amplifier circuit.

[0030] Figure 2This is a schematic diagram of a power amplifier circuit with multiple MOS transistors stacked, provided as an embodiment of this application.

[0031] Figure 3 This is a schematic diagram of a driving circuit provided in an embodiment of this application.

[0032] Figure reference numerals: 1. Push-pull amplifier circuit; 2. Voltage divider resistor string; 3. First MOSFET string; 4. Second MOSFET string; Q1. First main MOSFET; Q2. Second main MOSFET; RL. Load; VCC_MAX. First power supply voltage; VCC_MIN. Second power supply voltage; VS_IN. Voltage input terminal; VS_OUT. Voltage output terminal. Detailed Implementation

[0033] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0034] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0035] Firstly, such as Figure 2 As shown, this application provides a power amplifier circuit with multiple MOS transistors stacked, which includes:

[0036] The push-pull amplifier circuit 1 includes a first main MOSFET Q1 and a second main MOSFET Q2 of opposite types;

[0037] Voltage divider resistor string 2, positioned between the first power supply voltage VCC_MAX and the second power supply voltage VCC_MIN, includes multiple first resistors connected in series (such as...). Figure 2 R2, R3, R4, and R5 in the equation are used to form multiple voltage divider points, and the first power supply voltage VCC_MAX is greater than the second power supply voltage VCC_MIN.

[0038] Multiple capacitors (such as) Figure 2The number of capacitors (C2, C3, C4, C5) is the same as the number of first resistors. Each capacitor corresponds to one first resistor, and each capacitor is connected in parallel with its corresponding first resistor.

[0039] The first MOSFET string 3 has its two ends connected to the first power supply voltage VCC_MAX and the drain of the first main MOSFET Q1, respectively. It includes multiple MOSFETs of the same type as the first main MOSFET Q1 connected in series (e.g., ...). Figure 2 (Q3, Q5, Q7 in the text)

[0040] The second MOSFET string 4 has its two ends connected to the second power supply voltage VCC_MIN and the drain of the second main MOSFET Q2, respectively. It includes multiple second-type MOSFETs connected in series and of the same type as the second main MOSFET Q2 (such as...). Figure 2 (Q4, Q6, Q8 in the text)

[0041] Multiple first unidirectional conduction devices (such as Figure 2 In the first unidirectional conducting device (D1, D3, D5), each first unidirectional conducting device corresponds to a voltage divider point and a first type MOS transistor. The two ends of each first unidirectional conducting device are connected to its corresponding voltage divider point and the source of its corresponding first type MOS transistor, respectively. The conduction direction of the first unidirectional conducting device is from the voltage divider point to the first type MOS transistor.

[0042] Multiple second unidirectional conduction devices (such as) Figure 2 In the diagram (D2, D4, D6), each second unidirectional conducting device corresponds to a voltage divider point and a second type MOS transistor. The two ends of each second unidirectional conducting device are connected to its corresponding voltage divider point and the source of its corresponding second type MOS transistor, respectively. The conduction direction of the second unidirectional conducting device is from the second type MOS transistor to the voltage divider point.

[0043] This application uses a voltage divider resistor string 2 between the first power supply voltage VCC_MAX and the second power supply voltage VCC_MIN to divide the voltage between them. This ensures that none of the MOSFETs in the multi-MOSFET power amplifier circuit need to withstand the voltage difference between VCC_MAX and VCC_MIN, thus making the withstand voltage of all MOSFETs less than VCC_MAX - VCC_MIN. This effectively reduces the withstand voltage requirement of individual MOSFETs, broadens the selection range of MOSFETs, and improves the design flexibility of the power amplifier circuit. This application utilizes capacitors for energy storage and the unidirectional conduction characteristic of unidirectional conducting devices to switch between two states: the first MOSFET string 3 is turned on with the first main MOSFET Q1, and the second MOSFET string 4 is turned off with the second main MOSFET Q2; and the first MOSFET string 3 is turned off with the first main MOSFET Q1, and the second MOSFET string 4 is turned on with the second main MOSFET Q2.

[0044] In this embodiment, the push-pull amplifier circuit 1 refers to the core part of the power amplifier circuit. The push-pull amplifier circuit 1 consists of a pair of MOS transistors of opposite types (one NMOS transistor and one PMOS transistor, i.e., when the first main MOS transistor Q1 is an NMOS transistor, the second main MOS transistor Q2 is a PMOS transistor, and when the first main MOS transistor Q1 is a PMOS transistor, the second main MOS transistor Q2 is an NMOS transistor). The push-pull amplifier circuit 1 is used to realize the push-pull amplification of the signal. The push-pull amplifier circuit 1 processes the positive and negative half-cycles of the signal by alternately turning on the two MOS transistors, so as to provide current amplification capability throughout the entire cycle of the signal. In this embodiment, the voltage divider resistor string 2 is composed of multiple first resistors connected in series. Since the voltage divider resistor string is positioned between the first power supply voltage VCC_MAX and the second power supply voltage VCC_MIN, the multiple first resistors connected in series can divide the power supply voltage, forming a series of intermediate voltage points (voltage divider points) between the first power supply voltage VCC_MAX and the second power supply voltage VCC_MIN. The voltage at each voltage divider point is less than the voltage difference between the first power supply voltage VCC_MAX and the second power supply voltage VCC_MIN. It should be understood that the voltage divider points in this embodiment can provide bias voltages for the first main MOSFET Q1, the second main MOSFET Q2, the first MOSFET string 3, and the second MOSFET string 4. The voltage at each point is less than the voltage difference between the first power supply voltage VCC_MAX and the second power supply voltage VCC_MIN. Therefore, this embodiment ensures that the VDS (drain-source voltage) of all MOSFETs in the first main MOSFET Q1, the second main MOSFET Q2, all MOSFETs in the first MOSFET string 3, and all MOSFETs in the second MOSFET string 4 is less than the voltage difference (VCC_MAX - VCC_MIN) between the first power supply voltage VCC_MAX and the second power supply voltage VCC_MIN. Compared to the prior art, this embodiment effectively reduces the voltage rating requirement of the MOSFETs in the power amplifier circuit. That is, this embodiment can select MOSFETs with lower voltage ratings, thereby effectively increasing the range of MOSFET models that can be used in the power amplifier circuit. The capacitor in this embodiment can store charge to provide current output and neutralize negative charges, thereby effectively improving the rate of voltage change. In this embodiment, the first MOSFET string 3 consists of multiple first-type MOSFETs connected in series between the first power supply voltage VCC_MAX and the first main MOSFET Q1. The type of the first-type MOSFETs is the same as that of the first main MOSFET Q1. Since multiple first-type MOSFETs are connected in series between the first power supply voltage VCC_MAX and the first main MOSFET Q1, this embodiment can distribute the voltage difference between the first power supply voltage VCC_MAX and the first main MOSFET Q1 across these connected first-type MOSFETs, thereby reducing the voltage across each first-type MOSFET. This allows the first MOSFET string 3 to use MOSFETs with lower withstand voltage values.In this embodiment, the second MOSFET string 4 consists of multiple second-type MOSFETs connected in series between the second power supply voltage VCC_MIN and the second main MOSFET Q2. The type of the second-type MOSFETs is the same as that of the second main MOSFET Q2. Since multiple second-type MOSFETs are connected in series between the second power supply voltage VCC_MIN and the second main MOSFET Q2, this embodiment can distribute the voltage difference between the second power supply voltage VCC_MIN and the second main MOSFET Q2 across these connected second-type MOSFETs, thereby reducing the voltage across each second-type MOSFET. This allows the second MOSFET string 4 to use MOSFETs with lower withstand voltage values. The first unidirectional conducting device in this embodiment refers to a device that introduces the voltage of the voltage divider point to the source of the first type of MOSFET. Each first unidirectional conducting device corresponds to a voltage divider point and a first type of MOSFET. The two ends of each first unidirectional conducting device are connected to its corresponding voltage divider point and the source of its corresponding first type of MOSFET, respectively. The conduction direction of all first unidirectional conducting devices is from the voltage divider point to the first type of MOSFET, so that the first type of MOSFET is turned on during the signal rising phase (positive period of the signal) and turned off during the signal falling phase (negative period of the signal). The second unidirectional conducting device in this embodiment refers to a device that connects the source voltage of the second type of MOSFET to the voltage divider point. Each second unidirectional conducting device corresponds to a voltage divider point and a second type of MOSFET. The two ends of each second unidirectional conducting device are connected to its corresponding voltage divider point and the source of its corresponding second type of MOSFET, respectively. The conduction direction of all second unidirectional conducting devices is from the second type of MOSFET to the voltage divider point, so that the second type of MOSFET is turned off during the signal rising phase and turned on during the signal falling phase.

[0045] The multi-MOSFET power amplifier circuit provided in this application effectively solves the problem of difficult MOSFET selection in the prior art through ingenious structural design. Specifically, the existing push-pull amplifier circuit 1 requires NMOS and PMOS transistors to have high withstand voltage capabilities. This application introduces a voltage divider resistor string 2, a first MOSFET string 3, and a second MOSFET string 4 to share the voltage difference between the first power supply voltage VCC_MAX and the second power supply voltage VCC_MIN, so that the voltage borne by each MOSFET is lower than the voltage difference between the first power supply voltage VCC_MAX and the second power supply voltage VCC_MIN, thereby effectively reducing the withstand voltage requirement for a single MOSFET. For example, assuming the first power supply voltage VCC_MAX is +50V and the second power supply voltage VCC_MIN is -50V, with a total voltage difference of 100V, in a conventional push-pull amplifier circuit 1, the main MOSFET needs to withstand 100V. However, in this application, if the first MOSFET string 3 consists of three first-type MOSFETs connected in series, then each first-type MOSFET and the first main MOSFET Q1 only need to withstand an average of about 25V. The second MOSFET string 4 and the second main MOSFET Q2 also share the voltage in the same way. In this embodiment, the voltage divider resistor string 2 forms multiple voltage divider points between the first power supply voltage VCC_MAX and the second power supply voltage VCC_MIN to provide suitable gate bias voltages for all MOSFETs. This embodiment utilizes a first unidirectional conducting device and a second unidirectional conducting device to precisely lock the source voltage of each first-type MOSFET and the second-type MOSFET near the corresponding voltage divider point. When the input voltage changes, these unidirectional conducting devices can ensure that the gate voltage of the MOSFET string adjusts accordingly, thereby ensuring that the MOSFETs always operate in the constant current region and effectively share the voltage.

[0046] Therefore, the multi-MOSFET stacked power amplifier circuit provided in this application, by introducing a voltage divider resistor string 2, a capacitor, a first MOSFET string 3, a second MOSFET string 4, a first unidirectional conducting device, and a second unidirectional conducting device, effectively reduces the voltage that each MOSFET in the power amplifier circuit needs to withstand while effectively amplifying the current. Thus, this application can effectively reduce the voltage rating requirements of the MOSFETs in the power amplifier circuit, thereby effectively broadening the selection range of MOSFETs and effectively solving the problems of difficult MOSFET selection and limited available MOSFET models. Furthermore, although the multi-MOSFET stacked power amplifier circuit provided in this application uses more MOSFETs than the existing push-pull amplifier circuit 1, the price of MOSFETs that simultaneously meet the requirements of high VDS voltage rating, large continuous drain current Id, and VthId characteristic curve within the signal range is higher than that of MOSFETs that simultaneously meet the requirements of large continuous drain current Id and VthId characteristic curve within the signal range. Therefore, the device cost of the multi-MOSFET stacked power amplifier circuit provided in this application is lower than that of the existing push-pull amplifier circuit 1. In other words, this application can also effectively reduce the production cost of the power amplifier circuit.

[0047] In some preferred embodiments, the gates of the first main MOSFET Q1 and the second main MOSFET Q2 are both connected to the voltage input terminal VS_IN, and the sources of the first main MOSFET Q1 and the second main MOSFET Q2 are both connected to the voltage output terminal VS_OUT. The gates of all first-type MOSFETs and all second-type MOSFETs are also connected to the voltage output terminal VS_OUT. In this embodiment, the voltage input terminal VS_IN is the interface for receiving the signal to be amplified (the signal that needs to be amplified). The signal to be amplified is applied to the gates of the first main MOSFET Q1 and the second main MOSFET Q2 in the push-pull amplifier circuit 1 to drive these two main MOSFETs to perform amplification. The voltage output terminal VS_OUT is the interface for outputting the amplified signal. This voltage output terminal VS_OUT is connected to the source of the first main MOSFET Q1 and the source of the second main MOSFET Q2. That is, in this embodiment, the source of the first main MOSFET Q1 and the source of the second main MOSFET Q2 are used as the output points of the push-pull amplifier circuit 1.

[0048] In some preferred embodiments, the number of first-type MOSFETs is the same as the number of second-type MOSFETs, with the number of first-type MOSFETs being 2-5. This embodiment ensures structural symmetry in the power amplifier circuit by setting the number of first-type and second-type MOSFETs to be the same. This symmetry is crucial for ensuring similar characteristics of the circuit during positive and negative half-cycle signal amplification, thus effectively preventing output signal distortion. Since the number of first-type and second-type MOSFETs is the same, this embodiment effectively limits the number of both types of MOSFETs to a range of 2-5. This range is set based on a comprehensive consideration of voltage sharing, power consumption management, parasitic effects, and circuit complexity in practical applications. For example, when the number of first-type and second-type MOSFETs is less than 2, the voltage that a single MOSFET needs to withstand is still relatively large; while when the number of first-type and second-type MOSFETs is more than 5, although the voltage that a single MOSFET needs to withstand can be further reduced, it will significantly increase the complexity, cost, and parasitic capacitance of the power amplifier circuit, thereby affecting the frequency response and efficiency of the power amplifier circuit.

[0049] This embodiment effectively solves the problems of circuit imbalance and performance limitations by setting the number of first-type MOSFETs and second-type MOSFETs to be the same and limiting their number to a range of 2-5. Specifically, the symmetry in the number of first-type and second-type MOSFETs ensures that the upper arm (composed of first MOSFET string 3) and lower arm (composed of second MOSFET string 4) of the push-pull amplifier circuit 1 can provide balanced driving capability and voltage sharing characteristics during the positive and negative half-cycles. Therefore, this embodiment can make the voltage stress borne by each MOSFET evenly distributed throughout the entire signal cycle, so as to avoid the occurrence of local overload or hot spots. By limiting the number of MOSFETs to a range of 2-5, this embodiment effectively reduces the voltage withstand requirement of a single MOSFET while avoiding the additional parasitic effects and circuit complexity introduced by an excessive number of MOSFETs. Thus, the power amplifier circuit has good frequency response and reliability while maintaining high efficiency and stability.

[0050] In some preferred embodiments, the first main MOSFET Q1 is an NMOS transistor. The drain of the first first-type MOSFET is connected to the first power supply voltage VCC_MAX, and the source of the last first-type MOSFET is connected to the drain of the first main MOSFET Q1. In this embodiment, the first main MOSFET Q1 is an NMOS transistor. Since the type of the first-type MOSFET is the same as that of the first main MOSFET Q1, the first-type MOSFET in this embodiment is also an NMOS transistor. In this embodiment, the drain of the first first-type MOSFET in the first MOSFET string 3 is connected to the first power supply voltage VCC_MAX. That is, this embodiment is equivalent to the starting end of the first MOSFET string 3 being directly connected to the highest potential point of the circuit. In this embodiment, the source of the last first-type MOSFET in the first MOSFET string 3 is connected to the drain of the first main MOSFET Q1, so that the voltage after voltage division by the first MOSFET string 3 is applied to the drain of the first main MOSFET Q1.

[0051] In some preferred embodiments, the second main MOSFET Q2 is a PMOS transistor. The source of the first second-type MOSFET is connected to the drain of the second main MOSFET Q2, and the drain of the last second-type MOSFET is connected to the second power supply voltage VCC_MIN. In this embodiment, the second main MOSFET Q2 is a PMOS transistor. Since the type of the second-type MOSFET is the same as that of the second main MOSFET Q2, the second-type MOSFET in this embodiment is also a PMOS transistor. When the input signal causes the second main MOSFET Q2 to conduct, current flows through the second main MOSFET Q2 and the series-connected second-type MOSFETs to the second power supply voltage VCC_MIN, ensuring that the second MOSFET string 4 can effectively share the voltage across the second main MOSFET Q2.

[0052] In some preferred embodiments, the number of first resistors is equal to the sum of the number of first main MOSFETs Q1 and the number of first type MOSFETs. Since the push-pull amplifier circuit 1 in this embodiment consists of first main MOSFETs Q1 and second main MOSFETs Q2, and the number of first type MOSFETs is the same as the number of second type MOSFETs, the number of first resistors in this embodiment is also equal to the sum of the number of second main MOSFETs Q2 and the number of second type MOSFETs. This embodiment provides a corresponding voltage divider point for each series-connected MOSFET by setting the number of first resistors (R5) to be equal to the sum of the number of first main MOSFETs Q1 and the number of first type MOSFETs, thus accurately biasing each series-connected MOSFET and precisely distributing the voltage across the entire MOSFET string. Therefore, this embodiment can ensure that the gate-source voltage or drain-source voltage of each MOSFET is within its ideal operating range, allowing the MOSFET to maintain good linearity throughout the voltage swing.

[0053] In some preferred embodiments, all the first resistors have the same resistance value. This embodiment forms multiple uniformly distributed voltage divider points between the first power supply voltage VCC_MAX and the second power supply voltage VCC_MIN by setting all the first resistors to the same value, and enables the voltage divider resistor string 2 to provide a uniformly distributed bias voltage. This allows the first main MOSFET Q1, the second main MOSFET Q2, the first type MOSFET, and the second type MOSFET connected to these voltage divider points to obtain more stable and balanced bias conditions. This helps maintain the normal operation of the first main MOSFET Q1, the second main MOSFET Q2, the first type MOSFET, and the second type MOSFET, and avoids local overvoltage or undervoltage problems caused by uneven bias voltage distribution, thereby effectively improving the stability and reliability of the power amplifier circuit.

[0054] In some preferred embodiments, the first unidirectional conducting device is a unidirectional diode. The unidirectional diode in this embodiment is a semiconductor device with unidirectional conductivity, allowing current to flow from the anode to the cathode while blocking reverse current. In practical applications, the unidirectional diode can be a common PN junction diode, Schottky diode, or fast recovery diode, and its selection can be adjusted according to the specific frequency, current, and voltage requirements of the circuit.

[0055] In some preferred embodiments, the second unidirectional conducting device is a unidirectional diode.

[0056] As can be seen from the above, the power amplifier circuit with multiple MOSFETs stacked in this application effectively reduces the voltage that each MOSFET in the power amplifier circuit needs to withstand while effectively amplifying the current, by introducing a voltage divider resistor string 2, a capacitor, a first MOSFET string 3, a second MOSFET string 4, a first unidirectional conducting device, and a second unidirectional conducting device. Therefore, this application can effectively reduce the voltage withstand requirement of the MOSFETs in the power amplifier circuit, thereby effectively broadening the selection range of MOSFETs and effectively solving the problems of difficult MOSFET selection and limited available MOSFET models.

[0057] Secondly, such as Figure 3 As shown, this application also provides a driving circuit, which includes a load and a power amplifier circuit with multiple MOS transistors superimposed as provided in the first aspect above. The load is connected to the second power supply voltage VCC_MIN and the source of the first main MOS transistor Q1, respectively.

[0058] The driving circuit provided in this application includes a load and a power amplifier circuit with multiple MOS transistors superimposed as described in the first aspect above. The principle of the driving circuit in this embodiment is the same as that of the power amplifier circuit with multiple MOS transistors superimposed as described in the first aspect above, and will not be discussed in detail here.

[0059] In some preferred embodiments, such as Figure 3 As shown, the first main MOSFET Q1 is an NMOS transistor, the second main MOSFET Q2 is a PMOS transistor, and the voltage divider resistor series 2 includes four first resistors connected in series (e.g., Figure 3 The first resistor R2 is connected in parallel with capacitor C2, the first resistor R3 is connected in parallel with capacitor C3, the first resistor R4 is connected in parallel with capacitor C4, and the first resistor R5 is connected in parallel with capacitor C5. The first MOSFET string 3 includes three first-type MOSFETs connected in series (e.g., R2, R3, R4, R5). Figure 3 (Q3, Q5, Q7), the second MOSFET string 4 includes three second-type MOSFETs connected in series (such as Q3, Q5, Q7). Figure 3 Q4, Q6, Q8), the first unidirectional conducting device (such as Q4, Q6, Q8) Figure 3 D1, D3, D5) and second unidirectional conduction devices (such as Figure 3D2, D4, and D6 are all unidirectional diodes. One end of the first unidirectional conducting device D1 is connected to the source of the first type MOSFET Q3 and the drain of the first main MOSFET Q1. The other end of the first unidirectional conducting device D1 is connected to the voltage divider point located between the first resistor R2 and the first resistor R3. One end of the first unidirectional conducting device D3 is connected to the source of the first type MOSFET Q5 and the drain of the first type MOSFET Q3. The other end of the first unidirectional conducting device D3 is connected to the voltage divider point located between the first resistor R3 and the first resistor R4. The voltage divider connection is as follows: one end of the first unidirectional conducting device D5 is connected to the source and drain of the first type MOSFET Q7 and Q5, and the other end of the first unidirectional conducting device D5 is connected to the voltage divider point located between the first resistor R4 and the first resistor R5. The conduction direction of the first unidirectional conducting device is from the voltage divider point to the first type MOSFET. One end of the second unidirectional conducting device D2 is connected to the source of the second type MOSFET Q4 and the drain of the second main MOSFET Q2, and the other end of the second unidirectional conducting device D2 is connected to the voltage divider point located between the first resistor R4 and the first resistor R5. The voltage divider point between the first resistor R4 and the first resistor R5 is connected. One end of the second unidirectional conducting device D4 is connected to the source of the second type MOSFET Q6 and the drain of the second type MOSFET Q4. The other end of the second unidirectional conducting device D4 is connected to the voltage divider point between the first resistor R3 and the first resistor R4. One end of the second unidirectional conducting device D6 is connected to the source of the second type MOSFET Q8 and the drain of the second type MOSFET Q6. The other end of the second unidirectional conducting device D6 is connected to the voltage divider point between the first resistor R2 and the first resistor R3. The conduction direction of the second unidirectional conducting device is from the second type MOSFET to the voltage divider point. The gate of the first main MOSFET Q1 and the gate of the second main MOSFET Q2 are both connected to the voltage input terminal VS_IN through the same first resistor R1. The source of the first main MOSFET Q1, the source of the second main MOSFET Q2, the gates of all first type MOSFETs Q3, Q5, and Q7, and the gates of all second type MOSFETs Q4, Q6, and Q8 are all connected to the voltage output terminal VS_OUT. When the amplifier circuit is in a static state, the first resistor R2, R3, R4, and R5 are connected in series to divide the first power supply voltage VCC_MAX and the second power supply voltage VCC_MIN, resulting in multiple voltage division points. The voltages at these voltage division points ( Figure 3In the circuit, VCC_R3, VCC_R4, and VCC_R5 are all located between VCC_MAX and VCC_MIN, and capacitors C2, C3, C4, and C5 each store a certain amount of charge. Under the action of the first unidirectional conducting device D1, D3, and D5, VCC_R3, VCC_R4, and VCC_R5 pass through the first unidirectional conducting device D1, D3, and D5 to obtain VCC_Q1, VCC_Q3, and VCC_Q5. Furthermore, the current can only flow from the terminals of VCC_R3, VCC_R4, and VCC_R5 to VCC_Q1, VCC_Q3, and VCC_Q5, and the voltage drop of the first unidirectional conducting device is limited. Under the action of the second unidirectional conducting device, the current can only flow from the terminals of VCC_Q2, VCC_Q4, and VCC_Q6 to VCC_R3, VCC_R4, and VCC_R5, and the voltage drop of the second unidirectional conducting device is also limited. When the circuit is in operation, the input signal S includes a rising phase S1 and a falling phase S2. The turn-on threshold voltages of MOSFETs Q1, Q2, Q3, Q4, Q5, Q6, Q7, and Q8 are Vth_Q1, Vth_Q2, Vth_Q3, Vth_Q4, Vth_Q5, Vth_Q6, Vth_Q7, and Vth_Q8, respectively. VCC_Q2, VCC_Q4, and VCC_Q6 are greater than VCC_MIN + Vth_Q2, VCC_MIN + Vth_Q4, and VCC_MIN + Vth_Q6, respectively. A load RL is provided between VS_OUT and VCC_MIN. Due to the energy dissipation of the load, VS_OUT = VCC_MIN when there is no VS_IN input. During the signal rise phase S1, assuming the initial input voltage VS_IN = VCC_MIN, the gate voltages of Q2, Q4, Q6 and Q8 are VS_OUT = VCC_MIN, and the drain voltages are VCC_Q2, VCC_Q4 and VCC_Q6, respectively.During the rising process of VS_IN, when the voltage VS_IN > VS_OUT + Vth_Q6, Q8 is turned off. At the same time, when VS_IN > VS_OUT + Vth_Q1, Q1 is turned on, Q3, Q5, and Q7 are turned off, Q2, Q4, and Q6 are turned off, and the voltage output is provided by C2. When the signal continues to rise to VS_IN > VS_OUT + Vth_Q4 and VS_IN > VS_OUT + Vth_Q3, Q1 and Q3 are turned on, NQ5 and Q7 are turned off, Q2 and Q4 are turned on, Q6 and Q8 are turned off. When the signal continues to rise to VS_IN > VS_OUT + Vth_Q6 and VS_IN > VS_OUT + Vth_Q5, Q1, Q3, and Q5 are turned on, Q7 is turned off, Q2 is turned on, Q4, Q6, and Q8 are turned off. When the signal rises to the maximum value (VCC_MAX), Q1, Q3, Q5, and Q7 are turned on, Q2, Q4, Q6, and Q8 are turned off, and the voltage output of VS_OUT is provided by the first power supply voltage VCC_MAX. C5 can provide an output current to accelerate the voltage change rate. When the signal S is in the falling segment S2, assume the initial voltage VS_IN = VCC_MAX. When VS_IN starts to fall, VS_IN < VCC_MAX + Vth_Q1, Q1 is turned off, VS_IN < VCC_MAX + Vth_Q2, Q2 is turned on. Under the action of D2, the current flows from VS_OUT through Q2 and D2 to VCC_R5, and the negative charge is neutralized by C4. When VS_IN drops to VS_IN < VCC_Q5 + Vth_Q7, Q7 is turned off. At the same time, when VS_IN < VCC_Q5 + Vth_Q2, Q4 is turned on. And so on. When VS_IN drops to VCC_MIN, Q1, Q3, Q5, and Q7 are turned off, Q2, Q4, Q6, and Q8 are turned on, and the voltage output is provided by the second power supply voltage VCC_MIN. C2 can provide the neutralization of the negative charge flowing from Q8 to accelerate the voltage change rate. During the process of the MOS transistors cycling on and off for the signal S, the current is amplified to meet the driving requirements of the load. At the same time, the energy storage effect of capacitors C2, C3, C4, and C5 provides current output, negative charge neutralization, and increases the voltage change rate.

[0060] As can be seen from the above, the power amplifier circuit and driving circuit with multiple MOSFETs stacked in this application, by introducing voltage divider resistor string 2, capacitors C2, C3, C4, C5, first MOSFET string 3, second MOSFET string 4, first unidirectional conducting devices D1, D3, D5 and second unidirectional conducting devices D2, D4, D6, effectively reduces the voltage that each MOSFET in the power amplifier circuit needs to withstand while effectively amplifying the current. Therefore, this application can effectively reduce the voltage withstand value requirement of the MOSFETs in the power amplifier circuit, thereby effectively broadening the selection range of MOSFETs and effectively solving the problems of difficult MOSFET selection and limited available MOSFET models.

[0061] In the embodiments provided in this application, it should be understood that relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0062] The above are merely embodiments of this application and are not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A power amplifier circuit with multiple MOS transistors stacked, characterized in that, The power amplifier circuit with multiple MOS transistors stacked includes: A push-pull amplifier circuit, comprising a first main MOSFET and a second main MOSFET of opposite types; A voltage divider resistor string is set between a first power supply voltage and a second power supply voltage, and includes multiple first resistors connected in series to form multiple voltage divider points, wherein the first power supply voltage is greater than the second power supply voltage. Multiple capacitors, the number of which is the same as the number of first resistors, each capacitor corresponds to one first resistor, and each capacitor is connected in parallel with its corresponding first resistor; The first MOS transistor string has its two ends connected to the first power supply voltage and the drain of the first main MOS transistor, respectively, and includes multiple first type MOS transistors connected in series and of the same type as the first main MOS transistor; The second MOSFET string has its two ends connected to the second power supply voltage and the drain of the second main MOSFET, respectively. It includes multiple second-type MOSFETs connected in series and of the same type as the second main MOSFET. The gates of all first-type MOSFETs and all second-type MOSFETs are connected to the voltage output terminal. Multiple first unidirectional conducting devices, each first unidirectional conducting device corresponding to a voltage divider point and a first type MOS transistor, each of the two ends of each first unidirectional conducting device being connected to its corresponding voltage divider point and the source of its corresponding first type MOS transistor, and the conducting direction of the first unidirectional conducting device being from the voltage divider point to the first type MOS transistor; Multiple second unidirectional conducting devices are provided, each of which corresponds to a voltage divider point and a second type MOS transistor. Both ends of each second unidirectional conducting device are connected to the source of its corresponding voltage divider point and its corresponding second type MOS transistor, respectively. The conduction direction of the second unidirectional conducting device is from the second type MOS transistor to the voltage divider point.

2. The power amplifier circuit with multiple MOS transistors stacked according to claim 1, characterized in that, The gates of the first main MOSFET and the second main MOSFET are both connected to the voltage input terminal, and the sources of the first main MOSFET and the second main MOSFET are both connected to the voltage output terminal.

3. The power amplifier circuit with multiple MOS transistors stacked according to claim 1, characterized in that, The number of the first type of MOSFETs is the same as the number of the second type of MOSFETs, and the number of the first type of MOSFETs is 2-5.

4. The power amplifier circuit with multiple MOS transistors stacked according to claim 1, characterized in that, The first main MOSFET is an NMOS transistor, the drain of the first first type MOSFET is connected to the first power supply voltage, and the source of the last first type MOSFET is connected to the drain of the first main MOSFET.

5. The power amplifier circuit with multiple MOS transistors stacked according to claim 1, characterized in that, The second main MOSFET is a PMOS transistor. The source of the first second type MOSFET is connected to the drain of the second main MOSFET, and the drain of the last second type MOSFET is connected to the second power supply voltage.

6. The power amplifier circuit with multiple MOS transistors stacked according to claim 1, characterized in that, The number of the first resistors is equal to the total number of the first main MOSFET and the first type of MOSFET.

7. The power amplifier circuit with multiple MOS transistors stacked according to claim 1, characterized in that, All of the first resistors have the same resistance value.

8. The power amplifier circuit with multiple MOS transistors stacked according to claim 1, characterized in that, The first unidirectional conducting device is a unidirectional diode.

9. The power amplifier circuit with multiple MOS transistors stacked according to claim 1, characterized in that, The second unidirectional conducting device is a unidirectional diode.

10. A driving circuit, characterized in that, The circuit includes a load and a power amplifier circuit with multiple MOS transistors stacked as described in any one of claims 1-9, wherein the load is connected to the second power supply voltage and the source of the first main MOS transistor, respectively.

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