Indication device

Abstract

The present invention provides a display device that can be designed with high transmittance in the optical region and minimize the occurrence of brightness deviations due to differences in wiring resistance within the optical region. [Solution] Embodiments of this specification relate to a display device, and more specifically, a display device can be provided that minimizes the occurrence of brightness deviation due to differences in wiring resistance within the optical region by differentially arranging a plurality of data connection wires, including a first connection wire and a second connection wire having lower resistance than the first connection wire, in the optical region.

Description

Technical Field

[0001] Embodiments of this specification relate to a display device.

Background Art

[0002] With the development of technology, in addition to the image display function, a display device can provide a photographing function, various sensing functions, and the like. For this purpose, the display device must include optoelectronic devices (also referred to as light receiving devices or sensors) such as cameras and sensing sensors.

[0003] Since optoelectronic devices need to receive light from the front of the display device, they must be installed in a place where light reception is advantageous. Therefore, conventionally, there was no choice but to install a camera (camera lens) and a sensing sensor so as to be exposed on the front surface of the display device. As a result, the optoelectronic device is disposed at a location where the bezels of the display panel are widened or where a notch portion or a physical hole is formed in the display area of the display panel.

[0004] That is, by providing a display device with optoelectronic devices such as a camera and a sensing sensor that receive light from the front and perform a predetermined function, the bezels on the front surface of the display device may become larger, or restrictions may occur in the front surface design of the display device. Further, when the display device includes an optoelectronic device, unexpected deterioration in image quality may occur depending on the configuration including the optoelectronic device.

Summary of the Invention

Problems to be Solved by the Invention

[0005] Embodiments of this specification can provide a display device in which an optoelectronic device disposed at the lower part of the display panel can normally receive light through a light transmission structure without the optoelectronic device being exposed on the front surface of the display device.

[0006] The embodiments of this specification provide a display device that can design the optical region with high transmittance by differential design of data connection wiring, and can minimize the occurrence of brightness deviation due to differences in wiring resistance within the optical region.

[0007] The embodiments of this specification provide a display device that ensures brightness uniformity, improves optical characteristics and yield, and enables low-power operation by differential design of data connection wiring.

[0008] Embodiments of this specification can provide a display device that can minimize the occurrence of brightness deviations by optimizing the design of the material, thickness, and length of the data connection wiring. [Means for solving the problem]

[0009] Embodiments of this specification provide a display device comprising an optical region having a plurality of transparent regions and a plurality of first light-emitting regions; a display panel disposed on the outer periphery of the optical region and including a plurality of data connection wires arranged in a first direction in at least one of the plurality of transparent regions, the general region having a plurality of second light-emitting regions; and an optical electronic device disposed below the display panel and superimposed on the optical region, wherein the plurality of data connection wires include at least one first connection wire disposed in the first region and the second region of the optical region, and at least one second connection wire disposed in the first region and having a lower resistance than the first connection wire.

[0010] Embodiments of this specification can provide a display device comprising: a substrate including a plurality of transparent regions and a plurality of light-emitting regions; a transistor layer disposed on the substrate and including at least one transistor and a plurality of interlayer insulating films; a plurality of planarization layers disposed on the transistor layer; a plurality of data sub-wirings disposed on any one of the plurality of planarization layers in the plurality of light-emitting regions and electrically connected to at least one of at least one first connection wiring and at least one second connection wiring; and a light-emitting layer disposed on the plurality of planarization layers and including a plurality of light-emitting elements corresponding to each of the plurality of light-emitting regions.

[0011] According to embodiments of this specification, it is possible to provide a display device in which an optical electronic device located at the bottom of the display panel can receive light normally through a light-transmitting structure, without the optical electronic device being exposed on the front of the display device.

[0012] According to embodiments of this specification, a display device can be provided that, by designing the data connection wiring with differential design, allows for the design of the optical region with high transmittance and minimizes the occurrence of brightness deviations due to differences in wiring resistance within the optical region.

[0013] According to embodiments of this specification, by ensuring brightness uniformity through differential design of data connection wiring, it is possible to provide a display device that improves optical characteristics and yield, and enables low-power operation.

[0014] According to embodiments of this specification, a display device can be provided that minimizes the occurrence of brightness deviations by optimizing the design of the material, thickness, and length of the data connection wiring. [Brief explanation of the drawing]

[0015] [Figure 1a] This is a diagram illustrating a display device according to an embodiment of this specification. [Figure 1b] This is a diagram illustrating a display device according to an embodiment of this specification. [Figure 1c]This is a diagram illustrating a display device according to an embodiment of this specification. [Figure 1d] This is a diagram illustrating a display device according to an embodiment of this specification. [Figure 1e] This is a diagram illustrating a display device according to an embodiment of this specification. [Figure 2] This is a diagram illustrating the system configuration of a display device according to the embodiments of this specification. [Figure 3] This figure illustrates an example of a subpixel according to the embodiments of this specification. [Figure 4] This figure illustrates the arrangement of subpixels in the general region and the optical region according to embodiments of this specification. [Figure 5a] This diagram illustrates the arrangement of signal wiring in a display panel according to an embodiment of this specification. [Figure 5b] This diagram illustrates the arrangement of signal wiring in a display panel according to an embodiment of this specification. [Figure 6] This is a diagram illustrating the optical region according to the embodiments of this specification. [Figure 7] This is a diagram illustrating the optical region according to the embodiments of this specification. [Figure 8] This figure illustrates embodiments of a display device according to the embodiments of this specification, showing various combinations of the first and second connection wirings. [Figure 9] This figure illustrates embodiments of a display device according to the embodiments of this specification, showing various combinations of the first and second connection wirings. [Figure 10] This figure illustrates embodiments of a display device according to the embodiments of this specification, showing various combinations of the first and second connection wirings. [Figure 11] This figure illustrates embodiments of a display device according to the embodiments of this specification, showing various combinations of the first and second connection wirings. [Figure 12]In the display device according to the embodiment of the present specification, it is a diagram for explaining embodiments by various combinations of a first connection wiring and a second connection wiring. [Figure 13] In the display device according to the embodiment of the present specification, it is a diagram for explaining embodiments by various combinations of a first connection wiring and a second connection wiring. [Figure 14] It is a diagram for explaining an embodiment of the display device according to the embodiment of the present specification. [Figure 15] It is a diagram for explaining an embodiment of the display device according to the embodiment of the present specification. [Figure 16] It is a diagram for explaining an embodiment of the display device according to the embodiment of the present specification. [Figure 17] It is a diagram for explaining an embodiment of the display device according to the embodiment of the present specification. [Figure 18] It is a diagram for explaining an embodiment of the display device according to the embodiment of the present specification.

Mode for Carrying Out the Invention

[0016] Hereinafter, some embodiments of the present specification will be described in detail with reference to exemplary drawings. When adding reference numerals to the components of each drawing, for the same components, even if they are shown on other drawings, the same numerals may be used as much as possible. In addition, when explaining the present invention, if it is determined that a specific explanation of a related known configuration or function may obscure the gist of the present specification, the detailed explanation thereof will be omitted. When terms such as "including", "having", "consisting of" mentioned in the present specification are used, other parts may be added unless "only" is used. When a component is expressed in the singular, it can include the case of including a plurality unless there are particularly explicit descriptions.

[0017] Furthermore, when describing the components of this specification, terms such as 1st, 2nd, A, B, (a), (b), etc., may be used. These terms are used solely to distinguish a component from other components, and do not limit the nature, order, sequence, or number of the component.

[0018] In descriptions of the positional relationships of components, when it is stated that two or more components are “linked,” “joined,” or “connected,” it should be understood that while two or more components can be directly “linked,” “joined,” or “connected,” it is also possible for two or more components to be further “interposed” with other components before being “linked,” “joined,” or “connected.” Here, the other components may be included in at least one of the two or more components that are “linked,” “joined,” or “connected” to each other.

[0019] In descriptions of temporal relationships concerning constituent elements, operating methods, or manufacturing methods, when temporal order or sequential relationships are described using phrases such as "after," "following," "next," or "before," unless "immediately" or "directly" is used, this can include cases that are not continuous.

[0020] On the other hand, if numerical values ​​or corresponding information (e.g., levels) relating to components are mentioned, even without further explicit mention, these numerical values ​​or corresponding information may be interpreted as including a range of errors that can occur due to various factors (e.g., process factors, internal or external shocks, noise, etc.).

[0021] Various embodiments of this specification will be described in detail below with reference to the attached drawings.

[0022] Figures 1a to 1e are diagrams illustrating the display device 100 according to the embodiments of this specification.

[0023] Referring to Figures 1a to 1e, the display device 100 according to the embodiments herein may include a display panel 110 for displaying an image and / or at least one optical electronic device 11, 12.

[0024] The display panel 110 may include a display area DA where an image is displayed and a non-display area NDA where no image is displayed.

[0025] Multiple subpixels may be arranged in the display area DA, and various signal lines for driving these multiple subpixels may be arranged therein.

[0026] The non-display area (NDA) may be an area outside the display area (DA). Various signal lines may be placed in the NDA, and various drive circuits may be connected to it. The NDA may be bent so that it is not visible from the front, or it may be covered by a case (not shown). The NDA is also called a bezel or bezel area.

[0027] Referring to Figures 1a to 1d, in the display device 100 according to the embodiments herein, at least one electronic device 11 and / or 12 may be an electronic component located below the display panel 110 (i.e., on the opposite side of the viewing surface).

[0028] External light can enter the front (viewing surface) of the display panel 110, pass through the display panel 110, and be transmitted to at least one optical electronic device 11, 12 located below the display panel 110.

[0029] At least one electronic device 11 and / or 12 may be a device that receives external light transmitted through the display panel 110 and performs a predetermined function in accordance with the received external light. For example, at least one optical electronic device 11 and / or 12 may include at least one of an imaging device such as a camera (image sensor), a proximity sensor, and a sensing sensor such as an illuminance sensor.

[0030] Referring to Figures 1a to 1e, in the display panel 110 according to the embodiments herein, the display area DA may include a general area NA and at least one optical area OA1, OA2. Here, the general area NA may be located outside the at least one optical area OA1, OA2.

[0031] At least one optical region OA1 and / or OA2 may be a region that overlaps with at least one optical electronic device 11 and / or 12, respectively.

[0032] As illustrated in Figure 1a, the display area DA may include a general area NA and a first optical area OA1. Here, at least a portion of the first optical area OA1 can be superimposed on the first optical electronic device 11.

[0033] Figure 1a shows a structure in which the first optical region OA1 is circular, but the shape of the first optical region OA1 according to the embodiments herein is not limited to this.

[0034] For example, as shown in Figure 1b, the shape of the first optical region OA1 can be an octagon, but it may also consist of various other polygonal shapes.

[0035] As illustrated in Figure 1c, the display area DA may include a general area NA, a first optical area OA1, and a second optical area OA2. In the example of Figure 1c, the general area NA may be located between the first optical area OA1 and the second optical area OA2. Here, at least a portion of the first optical area OA1 may overlap with the first optical electronic device 11, and at least a portion of the second optical area OA2 may overlap with the second optical electronic device 12.

[0036] In the example shown in Figure 1d, the display area DA may include a general area NA, a first optical area OA1, and a second optical area OA2. In the example of Figure 1d, the general area NA does not necessarily have to be placed between the first optical area OA1 and the second optical area OA2. That is, the first optical area OA1 and the second optical area OA2 may be in contact with each other. Here, at least a portion of the first optical area OA1 can be superimposed on the first optical electronic device 11, and at least a portion of the second optical area OA2 can be superimposed on the second optical electronic device 12.

[0037] In the example shown in Figure 1e, the display panel 110 further includes a hall region H surrounded by a general region NA, in which the second optical electronic device 12 is located, and in the hall region H, the second optical electronic device 12 may be located at the top of the display panel 110. However, embodiments of this specification are not limited thereto, and the hall region H may be a second optical region OA2 in which the second optical electronic device 12 is located at the bottom of the display panel 110 as a display region DA.

[0038] The display area DA on the display panel 110 may include a first optical area OA1 and a general area NA.

[0039] In the example shown in Figure 1e, a general area NA is positioned between the first optical area OA1 and the hall area H, the hall area H is positioned on a virtual centerline that vertically divides the display panel 110, and the first optical area OA1 may be positioned to the left or right of the virtual centerline, separated from the hall area H.

[0040] Figure 1e shows that the size of the first optical region OA1 and the size of the hole region H are the same, but this is not limited to this. For example, the size of the first optical region OA1 and the size of the hole region H may be different. For example, the size of the first optical region OA1 may be smaller than the size of the hole region H.

[0041] At least one optical region OA1 and / or OA2 may have both an image display structure and a light transmission structure formed thereon. That is, since at least one optical region OA1 and / or OA2 is a part of the display region DA, at least one optical region OA1 and / or OA2 must have subpixels for image display. Furthermore, at least one optical region OA1 and / or OA2 must have a light transmission structure formed thereon to allow light to pass through at least one electronic device 11 and / or 12.

[0042] In the following, the image display structure may be referred to as the light-emitting region, and the light-transmitting structure may be referred to as the light-transmitting region.

[0043] At least one optical electronic device 11 and / or 12 is a device that requires light reception, is located below the display panel 110 (on the opposite side of the viewing surface), and is capable of receiving light that has passed through the display panel 110.

[0044] At least one optical electronic device 11 and / or 12 is not exposed on the front (viewing surface) of the display panel 110, so that when the user looks at the front of the display device 100, the optical electronic devices 11 and / or 12 are not visible to the user.

[0045] For example, the first optical electronic device 11 may be a sensing sensor such as a proximity sensor or an illuminance sensor, and the second optical electronic device 12 may be a camera. For example, the sensing sensor may be an infrared sensor that detects infrared rays.

[0046] Conversely, the first optical electronic device 11 may be a camera, and the second optical electronic device 12 may be a sensing sensor.

[0047] For the sake of clarity, the following explanation will use the example that the first optical electronic device 11 is a sensing sensor and the second optical electronic device 12 is a camera. Here, "camera" can mean either a camera lens or an image sensor.

[0048] If the second optical electronic device 12 is a camera, the camera is located below the display panel 110, but it may also be a front camera that photographs the front of the display panel 110. Therefore, the user may take pictures through a camera that is not visible on the viewing surface of the display panel 110 while looking at the viewing surface.

[0049] The general region NA and at least one optical region OA1 and / or OA2 are regions on which an image can be displayed, but the general region NA is a region on which a light-transmitting structure does not need to be formed, while at least one optical region OA1 and / or OA2 is a region on which a light-transmitting structure should be formed.

[0050] Therefore, at least one optical region OA1 and / or OA2 should have a transmittance above a certain level, while the general region NA may have no light transmittance or a low transmittance below a certain level.

[0051] For example, at least one optical region OA1 and / or OA2 and the general region NA may differ from each other in terms of resolution, subpixel arrangement structure, number of subpixels per unit area, electrode structure, wiring structure, electrode arrangement structure, or wiring arrangement structure.

[0052] For example, the number of subpixels per unit area in at least one optical region OA1 and / or OA2 may be less than the number of subpixels per unit area in the general region NA. That is, the resolution of at least one optical region OA1 and / or OA2 may be lower than the resolution of the general region NA. Here, the number of subpixels per unit area is a unit for measuring resolution and can also be called PPI (Pixels Per Inch), which means the number of pixels in one inch.

[0053] For example, the number of subpixels per unit area in the first optical region OA1 may be less than the number of subpixels per unit area in the general region NA. The number of subpixels per unit area in the second optical region OA2 may be greater than or equal to the number of subpixels per unit area in the first optical region OA1.

[0054] The first optical region OA1 and the second optical region OA2 can each have various shapes, such as a circle, ellipse, square, hexagon, or octagon. The first optical region OA1 and the second optical region OA2 may have the same shape or different shapes.

[0055] Referring to Figure 1c, when the first optical region OA1 and the second optical region OA2 are in contact, the entire optical region including the first optical region OA1 and the second optical region OA2 can have various shapes, such as circular, elliptical, square, hexagonal, or octagonal.

[0056] For the sake of explanation, in the following examples, we will assume that the first optical region OA1 and the second optical region OA2 are both circular.

[0057] In the embodiments of this specification, the display device 100 does not require a notch or hole to be formed in the display panel 110 for the exposure of a camera or sensing sensor, and therefore, a reduction in the area of ​​the display area DA may not occur.

[0058] As a result, a notch or camera hole for exposing the camera or sensing sensor does not need to be formed in the display panel 110, which can reduce the size of the bezel area, eliminate design constraints, and potentially increase design flexibility.

[0059] In the display device 100 according to the embodiments herein, at least one optical electronic device 11 and / or 12 must be able to receive light normally and perform a predetermined function normally, even though at least one optical electronic device 11 and / or 12 is positioned hidden behind the display panel 110.

[0060] Furthermore, in the display device 100 according to the embodiments of this specification, even though at least one optical electronic device 11 and / or 12 is positioned hidden behind the display panel 110 and overlapping with the display area DA, normal image display must be possible in at least one optical area OA1 and / or OA2 that overlaps with the at least one optical electronic device 11 and / or 12 within the display area DA.

[0061] Figure 2 is a diagram illustrating the system configuration of the display device 100 according to the embodiment of this specification.

[0062] Referring to Figure 2, the display device 100 is a component for displaying an image and may include a display panel 110 and a display driving circuit.

[0063] The display driving circuit is a circuit for driving the display panel 110 and may include a data driving circuit 220, a gate driving circuit 230, and a display controller 240, etc.

[0064] The display panel 110 may include a display area DA on which an image is displayed and a non-display area NDA on which no image is displayed. The non-display area NDA may be the outer area of ​​the display area DA, or it may also be called the bezel area. All or part of the non-display area NDA may be an area visible from the front of the display device 100, or an area that is bent and not visible from the front of the display device 100.

[0065] The display panel 110 may include a substrate SUB and a plurality of subpixels SP arranged on the substrate SUB. Furthermore, the display panel 110 may further include various types of signal wiring to drive the plurality of subpixels SP.

[0066] The display device 100 according to the embodiments of this specification may be a liquid crystal display device or the like, or a self-emissive display device in which the display panel 110 emits light itself. If the display device 100 according to the embodiments of this specification is a self-emissive display device, each of the plurality of subpixels SP may include a light-emitting element.

[0067] For example, the display device 100 according to the embodiments of this specification may be an organic light-emitting display device in which the light-emitting element is realized by an organic light-emitting diode (OLED). Another example is the display device 100 according to the embodiments of this specification, which may be an inorganic light-emitting display device in which the light-emitting element is realized by an inorganic-based light-emitting diode. Yet another example is the display device 100 according to the embodiments of this specification, which may be a quantum dot display device in which the light-emitting element is realized by a quantum dot, which is a semiconductor crystal that emits light itself.

[0068] The structure of each of the multiple subpixels SP may vary depending on the type of display device 100. For example, if the display device 100 is a self-emissive display device that emits light from the subpixels SP itself, each subpixel SP may include a light-emitting element that emits light itself, at least one transistor, and at least one capacitor.

[0069] For example, some types of signal wiring may include multiple data wirings DL that transmit data signals (also called data voltages or image signals) and multiple gate wirings GL that transmit gate signals (also called scan signals SCAN).

[0070] Multiple data paths DL and multiple gate paths GL can intersect each other. Each of the multiple data paths DL can be arranged extending in a first direction. Each of the multiple gate paths GL can be arranged extending in a second direction.

[0071] Here, the first direction may be the column direction and the second direction may be the row direction. Alternatively, the first direction may be the row direction and the second direction may be the column direction.

[0072] For the sake of explanation, in the following examples, the first direction will be the column direction and the second direction will be the row direction.

[0073] At least one data wiring DL that overlaps with at least one optical region OA1 and / or OA2 among a plurality of data wirings DL may include at least one of the following wirings: data connection wiring (first connection wiring DCL1, second connection wiring DCL2) and data sub-wiring.

[0074] The data connection wiring (first connection wiring DCL1, second connection wiring DCL2) and data sub-wiring will be specifically explained with reference to the following embodiment Figures 6 to 18.

[0075] The data drive circuit 220 is a circuit for driving multiple data lines DL and can output data signals to multiple data lines DL. The gate drive circuit 230 is a circuit for driving multiple gate lines GL and can output gate signals (i.e., scan signals SCAN) to multiple gate lines GL.

[0076] The controller 240 is a device for controlling the data drive circuit 220 and the gate drive circuit 230, and can control the drive timing for multiple data lines DL and the drive timing for multiple gate lines GL.

[0077] The controller 240 can supply a data drive control signal DCS to the data drive circuit 220 to control the data drive circuit 220, and can supply a gate drive control signal GCS to the gate drive circuit 230 to control the gate drive circuit 230.

[0078] The controller 240 can receive input image data from the host system 250 and, based on the input image data, supply image data DATA to the data drive circuit 220.

[0079] The data drive circuit 220 can supply data signals to multiple data wirings DL in accordance with the drive timing control of the controller 240.

[0080] The data drive circuit 220 receives digital image data DATA from the controller 240, converts the received image data DATA into an analog data signal, and outputs it to multiple data wirings DL.

[0081] The gate drive circuit 230 can supply gate signals to multiple gate wirings GL in accordance with the timing control of the controller 240. The gate drive circuit 230 is supplied with various gate drive control signals GCS, a first gate voltage corresponding to the turn-on level voltage, and a second gate voltage corresponding to the turn-off level voltage, generates gate signals, and can supply the generated gate signals to multiple gate wirings GL.

[0082] For example, the data drive circuit 220 may be connected to the display panel 110 by tape automated bonding (TAB), connected to the bonding pad of the display panel 110 by chip-on-glass (COG) or chip-on-panel (COP) technology, or implemented using chip-on-film (COF) technology.

[0083] The gate drive circuit 230 can be connected to the display panel 110 by tape automated bonding (TAB), by the bonding pad of the display panel 110 by chip-on-glass (COG) or chip-on-panel (COP) method, or by the display panel 110 according to the chip-on-film (COF) method. Alternatively, the gate drive circuit 230 may be of the gate-in-panel (GIP) type and formed in the non-display area (NDA) of the display panel 110. The gate drive circuit 230 may be placed on the substrate SUB or connected to the substrate SUB. That is, in the case of the GIP type, the gate drive circuit 230 can be placed in the non-display area (NDA) of the substrate SUB. In the case of the chip-on-glass (COG) type, chip-on-film (COF) type, etc., the gate drive circuit 230 can be connected to the substrate SUB.

[0084] On the other hand, at least one of the data drive circuit 220 and gate drive circuit 230 may be placed in the display area DA of the display panel 110. For example, at least one of the data drive circuit 220 and gate drive circuit 230 may be placed so as not to overlap with the subpixel SP, or it may be placed so as to partially or entirely overlap with the subpixel SP.

[0085] The data drive circuit 220 may be connected to one side of the display panel 110 (for example, the top or bottom). Depending on the drive method, panel design method, etc., the data drive circuit 220 may be connected to both sides of the display panel 110 (for example, the top and bottom), or to two or more of the four sides of the display panel 110.

[0086] The gate drive circuit 230 may be connected to one side of the display panel 110 (for example, the left or right side). Depending on the drive method, panel design method, etc., the gate drive circuit 230 may be connected to both sides of the display panel 110 (for example, the left and right sides), or to two or more of the four sides of the display panel 110.

[0087] The controller 240 can be implemented as a separate component from the data drive circuit 220, or it can be implemented as an integrated circuit by integrating it with the data drive circuit 220.

[0088] The controller 240 may be a timing controller used in conventional display technology, a control device that can perform other control functions in addition to the timing controller, a control device different from the timing controller, or a circuit within the control device. The controller 240 can be implemented as various circuits or electronic components such as an IC (Integrated Circuit), FPGA (Field Programmable Gate Array), ASIC (Application Specific Integrated Circuit), or processor.

[0089] The controller 240 can be mounted on a printed circuit board, a flexible printed circuit board, etc., and can be electrically connected to the data drive circuit 220 and the gate drive circuit 230 via the printed circuit board, flexible printed circuit board, etc.

[0090] The controller 240 can send and receive signals with the data drive circuit 220 according to at least one predetermined interface. For example, the interface may include an LVDS (Low Voltage Differential Signaling) interface, an EPI (Embedded Clock Point-Point Interface), or an SPI (Serial Peripheral Interface).

[0091] The display device 100 according to the embodiments of this specification may include, in addition to an image display function, a touch sensor TS and a touch sensing circuit that senses the touch sensor TS to detect whether a touch has occurred by a touch object such as a finger or a pen, or to detect the touch position, in order to further provide a touch sensing function.

[0092] The touch sensing circuit may include a touch drive circuit 260 that drives and senses a touch sensor TS, generates and outputs touch sensing data, and a touch controller 270 that can detect a touch or determine the touch position using the touch sensing data.

[0093] The touch sensor TS may include multiple touch electrodes. The touch sensor TS may further include multiple touch wirings for electrically connecting the multiple touch electrodes to the touch drive circuit 260.

[0094] The touch sensor TS may exist outside the display panel 110 in the form of a touch panel, or it may exist inside the display panel 110. When the touch sensor TS exists outside the display panel 110 in the form of a touch panel, the touch sensor TS is called an external type. When the touch sensor TS is an external type, the touch panel and the display panel 110 can be manufactured separately and joined during the assembly process. An external type touch panel may include a touch panel substrate and multiple touch electrodes on the touch panel substrate.

[0095] If the touch sensor TS is located inside the display panel 110, the touch sensor may be formed on the substrate SUB during the manufacturing process of the display panel 110, along with signal wiring and electrodes related to display driving.

[0096] The touch drive circuit 260 can supply a touch drive signal to at least one of the multiple touch electrodes, sense at least one of the multiple touch electrodes, and generate touch sensing data.

[0097] The touch sensing circuit can perform touch sensing using either a self-capacitance sensing method or a mutual-capacitance sensing method.

[0098] When a touch sensing circuit performs touch sensing using a self-capacitance sensing method, the touch sensing circuit can perform touch sensing based on the capacitance between each touch electrode and the touch object (e.g., finger, pen, etc.).

[0099] According to the self-capacitance sensing method, each of the multiple touch electrodes can perform both the role of a driving touch electrode and a sensing touch electrode. The touch driving circuit 260 can drive all or some of the multiple touch electrodes and sense all or some of the multiple touch electrodes.

[0100] When a touch sensing circuit performs touch sensing using a mutual capacitance sensing method, the touch sensing circuit can perform touch sensing based on the capacitance between the touch electrodes.

[0101] In the mutual capacitance sensing method, multiple touch electrodes are divided into driving touch electrodes and sensing touch electrodes. The touch driving circuit 260 can drive the driving touch electrodes and sense the sensing touch electrodes.

[0102] The touch drive circuit 260 and the touch controller 270 included in the touch sensing circuit may be implemented as separate devices or as a single device. Furthermore, the touch drive circuit 260 and the data drive circuit 220 may be implemented as separate devices or as a single device.

[0103] The display device 100 may further include a power supply circuit that supplies various power sources to the display driving circuit and / or touch sensing circuit.

[0104] The display device 100 according to the embodiments of this specification may be a mobile terminal such as a smartphone or tablet, or it may be a monitor or television (TV) of various sizes, and is not limited thereto, and may be a display of various types and sizes capable of displaying information or images.

[0105] As described above, the display area DA in the display panel 110 may include a general area NA and at least one optical area OA1 and / or OA2.

[0106] The general region NA and at least one optical region OA1 and / or OA2 are regions on which an image can be displayed. However, the general region NA is a region on which a light-transmitting structure does not need to be formed, while at least one optical region OA1 and / or OA2 are regions on which a light-transmitting structure should be formed.

[0107] Figure 3 is a diagram illustrating an example of a subpixel SP according to the embodiments of this specification.

[0108] Referring to Figure 3, each of the subpixels SP located in the general area NA, the first optical area OA1, and the second optical area OA2 within the display area DA of the display panel 110 may include a light-emitting element ED located in the light-emitting area on the substrate SUB, a drive transistor DRT for driving the light-emitting element ED, a scan transistor SCT for transmitting a data voltage VDATA to the first node N1 of the drive transistor DRT, and a storage capacitor Cst for maintaining a constant voltage for one frame.

[0109] The drive transistor DRT may include a first node N1 to which a data voltage is applied, a second node N2 electrically connected to the light-emitting element ED, and a third node N3 to which the drive voltage ELVDD is applied from the drive voltage wiring DVL.

[0110] The first node N1 of the drive transistor DRT may also be the gate node of the drive transistor DRT and can be electrically connected to the source node or drain node of the scan transistor SCT.

[0111] The second node N2 of the drive transistor DRT may be the source node or drain node of the drive transistor DRT and can be electrically connected to the pixel electrode PE of the light-emitting element ED.

[0112] The third node N3 of the drive transistor DRT may be the drain node or source node of the drive transistor DRT.

[0113] A storage capacitor Cst can be connected between the first node N1 and the second node N2 of the drive transistor DRT. The storage capacitor Cst is charged with an amount of charge corresponding to the voltage difference across its terminals and plays the role of maintaining the voltage difference across its terminals for a predetermined frame time. Thus, the corresponding subpixel SP can emit light during the predetermined frame time.

[0114] The scan transistor SCT is controlled on and off by a gate signal (i.e., a scan signal SCAN) and can be connected between the first node N1 of the drive transistor DRT and the data trace DL.

[0115] The scan transistor SCT is turned on by a gate signal of the turn-on level voltage supplied from the gate wiring GL, and can transmit the data voltage VDATA supplied from the data wiring DL to the first node N1 of the drive transistor DRT.

[0116] The scan transistor (SCT) and the drive transistor (DRT) may be either n-type or p-type transistors.

[0117] Here, if the scan transistor SCT is an n-type transistor, the turn-on level voltage of the gate signal may be a high-level voltage. If the scan transistor SCT is a p-type transistor, the turn-on level voltage of the gate signal may be a low-level voltage.

[0118] The light-emitting element ED may include a pixel electrode PE, a light-emitting layer EL, and a common electrode CE. A base voltage ELVSS can be applied to the common electrode CE.

[0119] For example, the pixel electrode PE may be the anode electrode and the common electrode CE may be the cathode electrode. Conversely, the pixel electrode PE may be the cathode electrode and the common electrode CE may be the anode electrode. In the following explanation, for the sake of clarity, we will assume that the pixel electrode PE is the anode electrode and the common electrode CE is the cathode electrode.

[0120] For example, the light-emitting element ED may be an organic light-emitting diode (OLED), an inorganic light-emitting diode, or a quantum dot light-emitting element. In this case, if the light-emitting element ED is an organic light-emitting diode, the light-emitting layer EL in the light-emitting element ED may include an organic light-emitting layer containing organic material.

[0121] The storage capacitor Cst may be an intentionally designed external capacitor located outside the drive transistor DRT, rather than a parasitic capacitor (e.g., Cgs, Cgd) that is an internal capacitor located between the gate node and the source node (or drain node) of the drive transistor DRT.

[0122] Since the circuit elements (especially the light-emitting elements ED) within each subpixel SP are vulnerable to external moisture and oxygen, a sealing layer ENCAP can be placed on the display panel 110 to prevent external moisture and oxygen from penetrating the circuit elements (especially the light-emitting elements ED). The sealing layer ENCAP can be placed in a manner that covers the light-emitting elements ED.

[0123] The subpixel SP structure shown in Figure 3 is merely an example and can be modified in various ways to include one or more transistors or one or more capacitors.

[0124] Figure 4 is a diagram illustrating the arrangement of subpixels SP in the general region NA and optical regions OA1 and OA2 according to the embodiments of this specification.

[0125] Referring to Figure 4, multiple subpixels SP may be arranged in each of the general area NA, the first optical area OA1, and the second optical area OA2 included in the display area DA.

[0126] For example, multiple subpixels SP may include a red subpixel (Red SP) that emits red light, a green subpixel (Green SP) that emits green light, and a blue subpixel (Blue SP) that emits blue light.

[0127] As a result, the general region NA, the first optical region OA1, and the second optical region OA2 can each contain multiple emission regions EA of red subpixels Red SP, multiple emission regions EA of green subpixels Green SP, and multiple emission regions EA of blue subpixels Blue SP.

[0128] In the following, the emission region EA included in the first optical region OA1 and the second optical region OA2 will be referred to as the first emission region EA1, and the emission region EA included in the general region NA will be referred to as the second emission region EA2.

[0129] Referring to Figure 4, the general region NA may not include a transmission region TA (i.e., a light transmission structure) and may contain multiple emission regions EA.

[0130] However, the first optical region OA1 and the second optical region OA2 may include not only multiple light-emitting regions EA, but also multiple transmission regions TA.

[0131] In other words, the first optical region OA1 may include a plurality of light-emitting regions EA and a plurality of first transmission regions TA1, and the second optical region OA2 may include a plurality of light-emitting regions EA and a plurality of second transmission regions TA2.

[0132] Multiple light-emitting regions EA and multiple light-transmitting regions TA1 and TA2 can be distinguished by their light transmission potential. That is, multiple light-emitting regions EA may be regions where light transmission is impossible, while multiple light-transmitting regions TA1 and TA2 may be regions where light transmission is possible.

[0133] Furthermore, multiple light-emitting regions EA and multiple transmission regions TA1 and TA2 can be distinguished by the presence or absence of a specific metal layer. For example, cathode electrodes CE may be formed in multiple light-emitting regions EA, while cathode electrodes CE may not be formed in multiple transmission regions TA1 and TA2. A light shield layer may be formed in multiple light-emitting regions EA, while light shield layers may not be formed in multiple transmission regions TA1 and TA2. The cathode electrode CE may be a common electrode.

[0134] Since the first optical region OA1 includes a plurality of first transmission regions TA1, and the second optical region OA2 also includes a plurality of second transmission regions TA2, the first optical region OA1 and the second optical region OA2 can be defined as regions through which light (e.g., external light) can pass.

[0135] The transmittance (transmittance) of the first optical region OA1 and the transmittance (transmittance) of the second optical region OA2 may be the same.

[0136] In this case, the first transmission region TA1 of the first optical region OA1 and the second transmission region TA2 of the second optical region OA2 may be the same in shape or size. Alternatively, even if the first transmission region TA1 of the first optical region OA1 and the second transmission region TA2 of the second optical region OA2 are different in shape or size, the ratio of the first transmission region TA1 within the first optical region OA1 and the ratio of the second transmission region TA2 within the second optical region OA2 may be equal.

[0137] In contrast, the transmittance (transmittance) of the first optical region OA1 and the transmittance (transmittance) of the second optical region OA2 may be different.

[0138] In this case, the first transmission region TA1 of the first optical region OA1 and the second transmission region TA2 of the second optical region OA2 may differ in shape and size. Alternatively, even if the first transmission region TA1 of the first optical region OA1 and the second transmission region TA2 of the second optical region OA2 are the same in shape or size, the ratio of the first transmission region TA1 within the first optical region OA1 and the ratio of the second transmission region TA2 within the second optical region OA2 may differ from each other.

[0139] For example, if the first optical electronic device 11 onto which the first optical region OA1 is superimposed is a camera, and the second optical electronic device 12 onto which the second optical region OA2 is superimposed is a sensing sensor, the camera may require a larger amount of light than the sensing sensor.

[0140] Therefore, the transmittance (transmittance) of the first optical region OA1 may be higher than the transmittance (transmittance) of the second optical region OA2.

[0141] In this case, the first transmission region TA1 of the first optical region OA1 may be larger in size than the second transmission region TA2 of the second optical region OA2. Alternatively, even if the first transmission region TA1 of the first optical region OA1 and the second transmission region TA2 of the second optical region OA2 are the same size, the proportion of the first transmission region TA1 within the first optical region OA1 may be larger than the proportion of the second transmission region TA2 within the second optical region OA2.

[0142] As shown in Figure 4, in the embodiments of this specification, the transparent regions TA1 and TA2 are also called transparent regions, and transmittance is sometimes referred to as transparency.

[0143] Furthermore, as shown in Figure 4, in the embodiments of this specification, it is assumed that the first optical region OA1 and the second optical region OA2 are located at the upper end of the display region DA of the display panel 110 and are arranged side by side.

[0144] Referring to Figure 4, the horizontal display area where the first optical area OA1 and the second optical area OA2 are located can be called the first horizontal display area HA1, and the horizontal display area where neither the first optical area OA1 nor the second optical area OA2 are located can be defined as the second horizontal display area HA2.

[0145] Referring to Figure 4, the first horizontal display area HA1 can include the general area NA, the first optical area OA1, and the second optical area OA2. The second horizontal display area HA2 can include only the general area NA.

[0146] Figures 5a and 5b are diagrams illustrating the arrangement of signal wiring in the display panel 110 according to the embodiments of this specification.

[0147] Specifically, Figure 5a shows the signal wiring layout in the first optical region OA1 and the general region NA according to the embodiments of this specification, and Figure 5b shows the signal wiring layout in the second optical region OA2 and the general region NA according to the embodiments of this specification.

[0148] The first horizontal display area HA1 shown in Figures 5a and 5b is a part of the first horizontal display area HA1 in the display panel 110, and the second horizontal display area HA2 is a part of the second horizontal display area HA2 in the display panel 110.

[0149] The first optical region OA1 shown in Figure 5a is a part of the first optical region OA1 in the display panel 110, and the second optical region OA2 shown in Figure 5b is a part of the second optical region OA2 in the display panel 110.

[0150] Referring to Figures 5a and 5b, the first horizontal display area HA1 can include a general area NA, a first optical area OA1, and a second optical area OA2. The second horizontal display area HA2 can include a general area NA.

[0151] The display panel 110 may have various types of horizontal lines HL1 and HL2, and various types of vertical lines VLn, VL1 and VL2.

[0152] In the embodiments of this specification, the transverse and longitudinal directions refer to two intersecting directions, and the transverse and longitudinal directions may differ depending on the viewing direction. For example, in the embodiments of this specification, the transverse direction may refer to the direction in which a gate trace GL is positioned as it extends, and the longitudinal direction may refer to the direction in which a data trace DL is positioned as it extends. Thus, the transverse and longitudinal directions are given as examples.

[0153] Referring to Figures 5a and 5b, the horizontal lines on the display panel 110 may include a first horizontal line HL1 located in the first horizontal display area HA1 and a second horizontal line HL2 located in the second horizontal display area HA2.

[0154] The horizontal lines on the display panel 110 may be gate wiring GL. That is, the first horizontal line HL1 and the second horizontal line HL2 may be gate wiring GL. Depending on the structure of the subpixel SP, the gate wiring GL can include various types of gate wiring.

[0155] Referring to Figures 5a and 5b, the vertical lines arranged on the display panel 110 may include a general vertical line VLn that is arranged only in the general area NA, a first vertical line VL1 that passes through both the first optical area OA1 and the general area NA, and a second vertical line VL2 that passes through both the second optical area OA2 and the general area NA.

[0156] The vertical lines arranged on the display panel 110 may include data wiring DL, drive voltage wiring DVL, etc., and may further include reference voltage wiring, initialization voltage wiring, etc. That is, the general vertical line VLn, the first vertical line VL1, and the second vertical line VL2 may include data wiring DL, drive voltage wiring DVL, etc., and may further include reference voltage wiring, initialization voltage wiring, etc.

[0157] In embodiments of this specification, the term “lateral” in the second transverse line HL2 simply means that the signal is transmitted from left (or right) to right (or left), and does not mean that the second transverse line HL2 extends in a straight line only in the exact transverse direction. That is, although the second transverse line HL2 is shown as straight in Figures 5a and 5b, the second transverse line HL2 may, in contrast, include bent or curved portions. Similarly, the first transverse line HL1 may also be bent or include curved portions.

[0158] In embodiments of this specification, the term “vertical” in a general vertical line VLn means that the signal is transmitted from top (or bottom) to bottom (or top), and does not mean that a general vertical line VLn extends in a straight line only in the exact vertical direction. That is, although a general vertical line VLn is shown as straight in Figures 5a and 5b, a general vertical line VLn may, however, include bent or curved portions. Similarly, the first vertical line VL1 and the second vertical line VL2 may also be bent or include curved portions.

[0159] Referring to Figures 4 and 5a, the first optical region OA1 included in the first transverse region HA1 can include a plurality of light-emitting regions EA and a plurality of first transmission regions TA1. The outer regions of the plurality of transmission regions TA1 within the first optical region OA1 can include a plurality of light-emitting regions EA.

[0160] Referring to Figure 5a, in order to improve the transmittance of the first optical region OA1, the first transverse line HL1 passing through the first optical region OA1 can pass through while avoiding multiple first transmission regions TA1 within the first optical region OA1.

[0161] Therefore, each of the first transverse lines HL1 passing through the first optical region OA1 may include curved or bent sections that bypass the outer edges of the multiple transmission regions TA1 within the first optical region OA1.

[0162] As a result, the first transverse line HL1 located in the first transverse region HA1 and the second transverse line HL2 located in the second transverse region HA2 may differ from each other in shape, length, etc. That is, the first transverse line HL1 passing through the first optical region OA1 and the second transverse line HL2 not passing through the first optical region OA1 may differ from each other in shape, length, etc.

[0163] Furthermore, in order to improve the transmittance of the first optical region OA1, the first vertical line VL1 passing through the first optical region OA1 can pass through while avoiding multiple first transmission regions TA1 within the first optical region OA1.

[0164] Therefore, each of the first vertical lines VL1 passing through the first optical region OA1 may include curved sections or bent sections that bypass the outer edges of the multiple first transmission regions TA1 within the first optical region OA1.

[0165] As a result, the first vertical line VL1 that passes through the first optical region OA1 and the general vertical line VLn that does not pass through the first optical region OA1 but is located in the general region NA may differ from each other in shape, length, etc.

[0166] Referring to Figure 5a, the first transmission region TA1, which is included in the first optical region OA1 within the first transverse region HA1, can be arranged in the diagonal direction.

[0167] Referring to Figure 5a, in the first optical region OA1 within the first lateral region HA1, multiple light-emitting regions EA can be arranged between two horizontally adjacent transmission regions TA1. In the first optical region OA1 within the first lateral region HA1, multiple light-emitting regions EA can be arranged between two vertically adjacent transmission regions TA1.

[0168] Referring to Figure 5a, all first transverse lines HL1 located in the first transverse region HA1, i.e., first transverse lines HL1 passing through the first optical region OA1, may include at least one curved or bent section that bypasses the outer edge of the first transmission region TA1.

[0169] Referring to Figure 5b, the second optical region OA2 contained within the first transverse region HA1 can include multiple emission regions EA and multiple second transmission regions TA2. Within the second optical region OA2, the outer regions of the multiple second transmission regions TA2 can include multiple emission regions EA.

[0170] The positions and arrangement of the multiple light-emitting regions EA and multiple transmission regions TA2 within the second optical region OA2 may be the same as the positions and arrangement of the multiple light-emitting regions EA and multiple first transmission regions TA1 within the first optical region OA1 in Figure 5a.

[0171] In contrast, as shown in Figure 5b, the positions and arrangement of the multiple light-emitting regions EA and the multiple second transmission regions TA2 within the second optical region OA2 may differ from the positions and arrangement of the multiple light-emitting regions EA and the multiple first transmission regions TA1 within the first optical region OA1 in Figure 5a.

[0172] For example, referring to Figures 4 and 5b, within the second optical region OA2, multiple second transmission regions TA2 can be arranged in the lateral direction (left-right direction). A light-emitting region EA does not necessarily need to be placed between two adjacent second transmission regions TA2 in the lateral direction (left-right direction). Furthermore, multiple light-emitting regions EA within the second optical region OA2 may be placed between adjacent second transmission regions TA2 in the vertical direction (up-down direction). That is, multiple light-emitting regions EA can be placed between rows of two transmission regions.

[0173] The first transverse line HL1 can pass through the second optical region OA2 and the surrounding general region NA within the first transverse region HA1 in the same manner as in Figure 5a.

[0174] In contrast, as shown in Figure 5b, the first transverse line HL1 can pass through the second optical region OA2 and the surrounding general region NA within the first transverse region HA1 in a different manner than shown in Figure 5a.

[0175] This is because the positions and arrangement of the multiple light-emitting regions EA and the multiple second transmission regions TA2 within the second optical region OA2 in Figure 5b are different from the positions and arrangement of the multiple light-emitting regions EA and the multiple first transmission regions TA1 within the first optical region OA1 in Figure 5a.

[0176] Referring to Figure 5b, when the first horizontal line HL1 passes through the second optical region OA2 within the first horizontal region HA1 and the surrounding general region NA, it can pass in a straight line between multiple vertically adjacent transmission regions TA2 without any curved or bent sections.

[0177] In other words, a first horizontal line HL1 may have a curved or bent section within the first optical region OA1, but may not have a curved or bent section within the second optical region OA2.

[0178] To improve the transmittance of the second optical region OA2, the second vertical line VL2 passing through the second optical region OA2 can pass through while avoiding multiple second transmission regions TA2 within the second optical region OA2.

[0179] Therefore, each of the second longitudinal lines VL2 passing through the second optical region OA2 may include curved or bent sections that bypass the outer edges of each of the multiple second transmission regions TA2.

[0180] As a result, the second longitudinal line VL2 that passes through the second optical region OA2 and the general longitudinal line VLn that does not pass through the second optical region OA2 but is located in the general region NA may have different shapes, lengths, etc.

[0181] As shown in Figure 5a, the first transverse line HL1 passing through the first optical region OA1 may have a curved section or a bent section that bypasses the outer edges of the multiple first transmission regions TA1 within the first optical region OA1.

[0182] Therefore, the length of the first transverse line HL1 that passes through the first optical region OA1 and the second optical region OA2 may be slightly longer than the length of the second transverse line HL2 that does not pass through the first optical region OA1 and the second optical region OA2, but is located only in the general region NA.

[0183] As a result, the resistance of the first transverse line HL1 that passes through the first optical region OA1 and the second optical region OA2 (hereinafter also referred to as the first resistance) may be slightly greater than the resistance of the second transverse line HL2 that does not pass through the first optical region OA1 and the second optical region OA2 and is located only in the general region NA (hereinafter also referred to as the second resistance).

[0184] Referring to Figures 5a and 5b, depending on the light transmission structure, the first optical region OA1 which overlaps at least a portion with the first optical electronic device 11 includes a plurality of first transmission regions TA1, and the second optical region OA2 which overlaps at least a portion with the second optical electronic device 12 includes a plurality of second transmission regions TA2. Therefore, the first optical region OA1 and the second optical region OA2 may have fewer subpixels per unit area compared to the general region NA.

[0185] The number of subpixels SP to which the first transverse line HL1, which passes through the first optical region OA1 and the second optical region OA2, is connected, and the number of subpixels SP to which the second transverse line HL2, which does not pass through the first optical region OA1 and the second optical region OA2 but is located only in the general region NA, is connected, may be different from each other.

[0186] The number of subpixels SP (first number) to which the first transverse line HL1 passing through the first optical region OA1 and the second optical region OA2 is connected may be less than the number of subpixels SP (second number) to which the second transverse line HL2, which is located only in the general region NA and does not pass through the first optical region OA1 and the second optical region OA2, is connected.

[0187] The difference between the first number and the second number can vary depending on the difference between the resolutions of the first optical region OA1 and the second optical region OA2 and the resolution of the general region NA. For example, the larger the difference between the resolutions of the first optical region OA1 and the second optical region OA2 and the resolution of the general region NA, the larger the difference between the first number and the second number may be.

[0188] As mentioned above, the number of subpixels SP to which the first transverse line HL1, which passes through the first optical region OA1 and the second optical region OA2, is connected (the first number) is less than the number of subpixels SP to which the second transverse line HL2, which does not pass through the first optical region OA1 and the second optical region OA2 and is located only in the general region NA, is connected (the second number). Therefore, the area in which the first transverse line HL1 overlaps with other surrounding electrodes or wiring may be smaller than the area in which the second transverse line HL2 overlaps with other surrounding electrodes or wiring.

[0189] Therefore, the parasitic capacitance formed by the first transverse wire HL1 with other surrounding electrodes or wiring (hereinafter referred to as the first capacitance) may be significantly smaller than the parasitic capacitance formed by the second transverse wire HL2 with other surrounding electrodes or wiring (hereinafter referred to as the second capacitance).

[0190] Considering the relative magnitudes of the first and second resistances (first resistance ≥ second resistance) and the relative magnitudes of the first and second capacitances (first capacitance ≪ second capacitance), the RC (Resistance-Capacitance) value of the first horizontal line HL1 passing through the first optical region OA1 and the second optical region OA2 (hereinafter also referred to as the first RC value) may be the smallest possible value compared to the RC (Resistance-Capacitance) value of the second horizontal line HL2 located only in the general region NA without passing through the first and second optical regions OA1 and OA2 (hereinafter also referred to as the second RC value) (first RC value ≪ second RC value).

[0191] Due to the difference between the first RC value of the first horizontal line HL1 and the second RC value of the second horizontal line HL2 (hereinafter referred to as the RC load deviation), the signal transfer characteristics via the first horizontal line HL1 and the signal transfer characteristics via the second horizontal line HL2 may be different.

[0192] In the following, for the sake of explanation, at least one of the first optical region OA1 and the second optical region OA2 may be referred to as optical region OA, and at least one of the multiple first transmission regions TA1 within the first optical region OA1 and the multiple second transmission regions TA2 within the second optical region OA2 may be referred to as transmission region TA.

[0193] Figures 6 and 7 are diagrams illustrating the optical region OA according to embodiments of this specification.

[0194] Specifically, Figure 6 shows a plan view of the optical region OA according to an embodiment of this specification, and Figure 7 shows a plan view in which only the first region A1 is represented in the plan view of Figure 6.

[0195] Referring to Figures 6 and 7, the optical region OA can comprise a plurality of transmission regions TA and a plurality of first emission regions EA1.

[0196] In Figures 6 and 7, for the sake of explanation, the optical region OA is shown as having only the first light-emitting regions EA1 in odd-numbered rows and only the transmission regions TA in even-numbered rows. However, the embodiments of this specification are not limited thereto, and at least one additional transmission region TA may be arranged between the first light-emitting regions EA1 arranged in a row.

[0197] Each of the multiple first light-emitting regions EA1 may contain at least one subpixel from among a first color (e.g., green) subpixel SP1, a second color (e.g., blue) subpixel SP2, and a third color (e.g., red) subpixel SP3.

[0198] For example, among a plurality of first light-emitting regions EA1, a second-color subpixel SP2 may be arranged in the first-1 light-emitting region, a third-color subpixel SP3 may be arranged in the first-2 light-emitting region adjacent to the first-1 light-emitting region, and a first-color subpixel SP1 may be arranged at the interface between the first-1 and first-2 light-emitting regions; however, the embodiments described herein are not limited thereto.

[0199] The shapes and sizes of at least two of the subpixels SP1 of the first color, SP2 of the second color, and SP3 of the third color may be the same or different from each other.

[0200] As shown in the examples in Figures 6 and 7, the subpixel SP2 of the second color can be formed with a larger area than the subpixel SP1 of the first color and the subpixel SP3 of the third color, taking into consideration the lifetime and luminescence efficiency of the light-emitting material for each color; however, the embodiments specified herein are not limited thereto.

[0201] As illustrated in the examples in Figures 6 and 7, in order to improve transmittance in the optical region (OA), it is necessary to reduce the use of low-transmittance wiring such as metal wiring in the transmissive region (TA). In other words, it is necessary to consider methods for applying high-transmittance wiring to the transmissive region (TA).

[0202] However, high-transmittance wiring has higher resistance compared to existing wiring (such as low-transmittance wiring or metal wiring), and due to the structural characteristics of the circular optical region OA, applying high-transmittance wiring to the entire transmission region TA can result in a large resistance difference between the long wiring in the center and the short wiring at the edges, which can cause brightness deviation problems.

[0203] Therefore, the display device 100 according to the embodiment of this specification applies high-transmittance wiring on multiple transparent regions TA, but by applying high-transmittance wiring in a differential manner, taking into account the resistance difference between the central region and the edge region, the problem of brightness deviation due to the wiring resistance difference is minimized, and the transmittance can be improved in the multiple transparent regions TA.

[0204] The following section provides a specific example of applying high-transparency wiring in a differential configuration.

[0205] For example, since the light-emitting region EA does not require consideration of transmittance, the data wiring DL (e.g., data sub-wiring DSL and second connection wiring DCL2) can be formed from metallic materials such as titanium (Ti), aluminum (Al), or copper (Cu).

[0206] On the other hand, since the transmittance of the transparent region TA must be taken into consideration, the data connection wiring DCL (e.g., the first connection wiring DCL1) can be formed from a transparent conductive oxide (TCO) material.

[0207] Specifically, the multiple data wirings DL may include multiple data connection wirings arranged in a first direction in at least one of the multiple transmission regions TA in the region superimposed with the optical region OA, and multiple data sub-wirings DSL arranged in the first direction in the multiple first emission regions EA1 and electrically connected to the corresponding at least one data connection wiring.

[0208] Multiple data connection lines may include at least one first connection line DCL1 located in the first region A1 and the second region A2 of the optical region OA, and at least one second connection line DCL2 located in the first region A1 and having a lower resistance than the first connection line DCL1. For example, multiple data connection lines may include at least one of at least one first connection line DCL1 and at least one second connection line DCL2.

[0209] For example, the first connection wiring DCL1 may be a high-transmittance wiring with a transmittance of 80% to 99%, and as an example, the first connection wiring DCL1 may include at least one transparent conductive oxide (TCO) material from among ITO (Indium Tin Oxide), IGZO (Indium Gallium Zinc Oxide), and IZO (Indium Zinc Oxide). Therefore, the first connection wiring DCL1 can have a higher transmittance than either the second connection wiring DCL2 or the data sub-wiring DSL.

[0210] The second connection wiring DCL2 and data sub-wiring DSL may be wirings with a surface resistance of 0.01 to 0.05, and as an example, the second connection wiring DCL2 and data sub-wiring DSL may include aluminum (Al). That is, the second connection wiring DCL2 and data sub-wiring DSL may be wirings made of the same material. In other words, like the second connection wiring DCL2, the data sub-wiring DSL may have a lower resistance than the first connection wiring DCL1.

[0211] However, the embodiments described herein are not limited thereto, and at least one of the multiple data sub-wirings DSLs may contain the same material as the first connection wiring DCL1.

[0212] For example, the first connection wiring DCL1 can be formed on a different layer from the second connection wiring DCL2 and the data sub-wiring DSL, while the second connection wiring DCL2 and the data sub-wiring DSL can be formed on the same layer and from the same material.

[0213] In the examples shown in Figures 6 and 7, the first region A1 is the region located in the center of the optical region OA, and the second region A2 may be the regions located on the first side (e.g., the left side) and the second side (e.g., the right side) of the first region A1, respectively.

[0214] In other words, the display device 100 according to the embodiment of this specification arranges a first connection wiring DCL1, which is a high-transmittance / high-resistance wiring, and a second connection wiring DCL2, which is a low-resistance wiring, in a differential arrangement in the first region A1 corresponding to the center of the optical region OA, and arranges the first connection wiring DCL1, which is a high-transmittance / high-resistance wiring, in the second region A2 corresponding to the edge of the optical region OA, thereby minimizing the difference in wiring resistance between the center, where the wiring length is long, and the edge, where the wiring length is short.

[0215] According to embodiments of this specification, the display device 100 can be designed so that the wiring widths of at least one of the multiple data connection wirings located in the first region A1 and at least one of the multiple data connection wirings located in the second region A2 are different from each other, in order to minimize the difference in wiring resistance between the central part and the edge part.

[0216] For example, the wiring widths can be designed to be differential such that at least one of the multiple data connection wirings located in the first region A1 has a wider wiring width than at least one of the multiple data connection wirings located in the second region A2.

[0217] To give a more specific example, the display device 100 can be designed such that the wiring width of the first connecting wiring DCL1 located in the centerline region CL, which has the longest wiring length, is the largest, and the wiring width of the first connecting wiring DCL1 gradually decreases as it moves away from the centerline region CL.

[0218] According to embodiments of this specification, the display device 100 can be designed such that, in order to minimize the difference in wiring resistance between the central part and the edge part, at least one of the multiple data connection wires located in the first region A1 and at least one of the multiple data connection wires located in the second region A2 have different wiring lengths.

[0219] In the display device 100 according to the embodiment of the present disclosure, the wiring arranged in the second region A2 may be wiring having curves or bends (angular turns), in which case the wiring having curves or bends may include a zigzag pattern (i.e., "DP" in Figure 6).

[0220] Specifically, the wiring having curves or bends located in the second region A2 may include at least one of the following: power wiring, power connection wiring, low-potential wiring, data connection wiring (DCL), and data sub-wiring (DSL).

[0221] For example, at least one data connection cable (DCL) located in the second region A2 among multiple data connection cables (DCL) may have a curve or bend in order to design the length of the data connection cable differently. Alternatively, at least one data connection cable (DCL) located in the second region A2 may have a zigzag pattern (DP).

[0222] As another example, in order to minimize resistance between the central and edge regions of the optical region OA, at least one of the multiple data sub-wiring DSLs located in the second region A2 may be a wiring that has a curve or a bent portion. Alternatively, at least one data sub-wiring DSL located in the second region A2 may be a wiring that has a zigzag pattern (not shown).

[0223] Referring to Figure 7, the first region A1 is divided into an upper region UA, an intermediate region CA, and a lower region LA. In the first region A1, the first connection wiring DCL1 is located in the intermediate region CA, and the second connection wiring DCL2 may be located in at least one of the upper region UA ​​and the lower region LA.

[0224] In the first region A1, the first connection wiring DCL1 can be located in at least one of the upper region UA ​​and the lower region LA, so that at least one of the upper region UA ​​and the lower region LA may have a mixed arrangement of the first connection wiring DCL1 and the second connection wiring DCL2.

[0225] In other words, the display device 100 according to the embodiment of this specification has the first connection wiring DCL1 and the second connection wiring DCL2 differentially arranged to minimize the resistance difference between the center and edge of the optical region OA, but the second connection wiring DCL2 can be arranged only in the upper region UA ​​and / or lower region LA of the first region A1 to minimize the decrease in transmittance in the transparent region TA.

[0226] Figures 8 to 13 illustrate embodiments of the display device 100 according to this embodiment, showing various combinations of the first connection wiring DCL1 and the second connection wiring DCL2.

[0227] Specifically, Figures 8 to 13 illustrate embodiments of various combinations of the first connection wiring DCL1 and the second connection wiring DCL2 in the centerline region CL shown in Figure 7.

[0228] Referring to Figures 8 to 13, in the first region A1, the first connection wiring DCL1 may be located in at least one transparent region TA situated in at least one of the upper region UA, the intermediate region CA, and the lower region LA, and the second connection wiring DCL2 may be located in at least one transparent region TA situated in at least one of the upper region UA ​​and the lower region LA.

[0229] As shown in the examples in Figures 8 to 13, a first connection wiring DCL1 can be placed in each of the multiple intermediate transparent regions TA_C located in the intermediate region CA.

[0230] As shown in the example in Figure 8, a second connection wiring DCL2 can be placed in each of the first to third upper transparent regions TA_U1, TA_U2, and TA_U3 located in the upper region UA, and in the first to third lower transparent regions TA_L1, TA_L2, and TA_L3 located in the lower region LA.

[0231] In the example shown in Figure 9, a second connection wiring DCL2 may be placed in each of the first upper transparent region TA_U1, the third upper transparent region TA_U3, the first lower transparent region TA_L1, and the third lower transparent region TA_L3, while a first connection wiring DCL1 may be placed in each of the second upper transparent region TA_U2 and the second lower transparent region TA_L2.

[0232] In the example shown in Figure 10, a second connection wiring DCL2 may be placed in each of the first upper transparent region TA_U1, the second upper transparent region TA_U2, the first lower transparent region TA_L1, and the second lower transparent region TA_L2, while a first connection wiring DCL1 may be placed in each of the third upper transparent region TA_U3 and the third lower transparent region TA_L3.

[0233] In the example shown in Figure 11, a second connection wiring DCL2 may be placed in each of the second upper transparent region TA_U2 and the second lower transparent region TA_L2, and a first connection wiring DCL1 may be placed in each of the first upper transparent region TA_U1, the third upper transparent region TA_U3, the first lower transparent region TA_L1, and the third lower transparent region TA_L3.

[0234] In the example shown in Figure 12, a second connection wiring DCL2 may be placed in each of the second upper transparent region TA_U2, the third upper transparent region TA_U3, the second lower transparent region TA_L2, and the third lower transparent region TA_L3, and a first connection wiring DCL1 may be placed in each of the first upper transparent region TA_U1 and the first lower transparent region TA_L1.

[0235] In the example shown in Figure 13, a first connection wiring DCL1 may be placed in each of the first to third upper transparent regions TA_U1, TA_U2, and TA_U3, and a second connection wiring DCL2 may be placed in each of the first to third lower transparent regions TA_L1, TA_L2, and TA_L3.

[0236] Figures 14 to 18 are diagrams illustrating embodiments of the display device 100 according to the embodiments of this specification.

[0237] Specifically, Figure 14 shows a cross-sectional view of the non-transparent region NTA of the optical region OA provided in the display device 100 according to the embodiment of this specification, and Figures 15 and 16 show cross-sectional views of the transparent region TA of the optical region OA.

[0238] Furthermore, Figure 17 shows a cross-sectional view of the connection relationship between the first connection wiring DCL1 and the data sub-wiring DSL when the data connection wiring placed in the transparent region TA is the first connection wiring DCL1, and Figure 18 shows a cross-sectional view of the connection relationship between the second connection wiring DCL2 and the data sub-wiring DSL when the data connection wiring placed in the transparent region TA is the second connection wiring DCL2.

[0239] More specifically, Figure 17 shows a cross-sectional view when the first connecting wiring DCL1 is placed in at least one transparent region TA adjacent to the non-transparent region NTA containing the first light-emitting region, and Figure 18 shows a cross-sectional view when the second connecting wiring DCL2 is placed in at least one transparent region TA adjacent to the non-transparent region NTA containing the first light-emitting region.

[0240] Referring to Figures 14 to 16, the display device 100 according to the embodiments of this specification may include an opaque region NTA and a transmissive region TA within the optical region OA. The opaque region NTA may include a first light-emitting region EA1.

[0241] In the examples shown in Figures 14 to 16, for the sake of explanation, an example is shown where the transmission region TA of the optical region OA overlaps with the first optical electronic device 11; however, the transmission region TA of the optical region OA may also overlap with the second optical electronic device 12.

[0242] Furthermore, in the examples shown in Figures 14 to 16, the first optical electronic device 11 is shown overlapping the transmission region TA, but the first optical electronic device 11 may also overlap at least a portion of the non-transmission region NTA included in the optical region OA.

[0243] The opaque region NTA and the transparent region TA may include the substrate SUB, the transistor layer TRL, the planarization layer PLN, the light-emitting element layer EDL, the encapsulation layer ENCAP, the touch sensor layer TSL, and the protective layer PAC.

[0244] First, the stacked structure of the opaque NTA will be explained with reference to Figure 14.

[0245] The substrate SUB may include a first substrate SUB1, an intermediate insulating film IPD, and a second substrate SUB2. The intermediate insulating film IPD may be located between the first substrate SUB1 and the second substrate SUB2. By composing the substrate SUB with the first substrate SUB1, the intermediate insulating film IPD, and the second substrate SUB2, moisture penetration can be prevented. For example, the first substrate SUB1 and the second substrate SUB2 may be polyimide (PI) substrates. The intermediate insulating film IPD may include an inorganic material. For example, the intermediate insulating film IPD may include silicon nitride (SiNx) or silicon oxide (SiOx).

[0246] The transistor layer TRL, placed on the substrate SUB, can be configured with various patterns ACT, SD1, GATE, various insulating films MBUF, ABUF1, ABUF2, GI, ILD1, ILD2, ILD3, PAS0, and various metal patterns TM, GM, ML1, ML2 for forming transistors such as the drive transistor DRT.

[0247] According to the embodiment, at least one additional insulating film can be placed between the second interlayer insulating film ILD2 and the third interlayer insulating film ILD3 and / or between the third interlayer insulating film ILD3 and the passivation layer PAS0.

[0248] The following section provides a more detailed explanation of the stacked structure of the transistor layer (TRL).

[0249] The multi-buffer layer MBUF may be placed on the second substrate SUB2, and the first active buffer layer ABUF1 may be placed on the multi-buffer layer MBUF.

[0250] A first metal layer ML1 and a second metal layer ML2 can be placed on the first active buffer layer ABUF1. Here, the first metal layer ML1 and the second metal layer ML2 can function as a light shield.

[0251] A second active buffer layer ABUF2 can be placed on the first metal layer ML1 and the second metal layer ML2. The active layer ACT of the drive transistor DRT can be placed on the second active buffer layer ABUF2.

[0252] The gate insulating film GI can be placed while covering the active layer ACT.

[0253] The gate electrode GATE of the drive transistor DRT can be placed on the gate insulating film GI. In this case, the gate material layer GM can be placed on the gate insulating film GI together with the gate electrode GATE of the drive transistor DRT at a position different from the formation position of the drive transistor DRT.

[0254] A first interlayer insulating film ILD1 can be placed while covering the gate electrode GATE and the gate material layer GM. A metal pattern TM can be placed on the first interlayer insulating film ILD1. A second interlayer insulating film ILD2 can be placed while covering the metal pattern TM on the first interlayer insulating film ILD1.

[0255] A third interlayer insulating film ILD3 can be placed on a second interlayer insulating film ILD2, and two first source-drain electrode patterns SD1 can be placed on the third interlayer insulating film ILD3. One of the two first source-drain electrode patterns SD1 may be the source node of the drive transistor DRT, and the other may be the drain node of the drive transistor DRT.

[0256] The two first source-drain electrode patterns SD1 can be connected to one side and the other side of the active layer ACT via the contact holes of the third interlayer insulating film ILD3, the second interlayer insulating film ILD2, the first interlayer insulating film ILD1, and the gate insulating film GI. In the active layer ACT, the portion overlapping with the gate electrode GATE may be a channel region. One of the two first source-drain electrode patterns SD1 may be connected to one side of the channel region in the active layer ACT, and the other of the two first source-drain electrode patterns SD1 may be connected to the other side of the channel region in the active layer ACT.

[0257] The passivation layer PAS0 can be positioned while covering the two first source-drain electrode patterns SD1.

[0258] A planarization layer PLN can be placed on a transistor layer TRL. The planarization layer PLN may include a first planarization layer PLN1 and a second planarization layer PLN2.

[0259] The first planarization layer PLN1 can be placed on the passivation layer PAS0. The second source-drain electrode pattern SD2 can be placed on the first planarization layer PLN1. The second source-drain electrode pattern SD2 can be connected to one of the two first source-drain electrode patterns SD1 (corresponding to node N2 in Figure 4) via a contact hole in the first planarization layer PLN1.

[0260] According to the embodiment, the data connection wiring DCL can be placed on the first source-drain electrode pattern SD1 and the second source-drain electrode pattern SD2, and below the first planarization layer PLN1. That is, the data connection wiring DCL can be placed between the source-drain electrode patterns (e.g., SD1 and SD2) and the planarization layer (e.g., PLN1).

[0261] According to the embodiment, the data connection wiring DCL may be located below the first source-drain electrode pattern SD1 and the second source-drain electrode pattern SD2, and between the second interlayer insulating film ILD2 and the third interlayer insulating film ILD3.

[0262] A data sub-wiring DSL can be placed on the first planarization layer PLN1.

[0263] The second planarization layer PLN2 can be positioned over the second source-drain electrode pattern SD2 and the data sub-wiring DSL. The light-emitting element layer EDL can be positioned on multiple planarization layers, particularly the second planarization layer PLN2, and may include light-emitting elements ED corresponding to each of the multiple light-emitting regions EA.

[0264] For example, the light-emitting element layer EDL may include a light-emitting element ED formed by a pixel electrode PE, a light-emitting layer EL, and a common electrode CE. The light-emitting layer EL may include an organic film.

[0265] The pixel electrode PE may be placed on the second planarization layer PLN2 and electrically connected to the second source-drain electrode pattern SD2 through contact holes in the second planarization layer PLN2.

[0266] The bank can be positioned while covering the pixel electrode PE. The bank may have an open portion corresponding to the light-emitting region of the subpixel SP. A portion of the pixel electrode PE can be exposed in the open portion of the bank. The light-emitting layer EL can be positioned in and around the open portion of the bank. This allows the light-emitting layer EL to be positioned on the pixel electrode PE exposed through the open portion of the bank.

[0267] A common electrode CE can be placed on the light-emitting layer EL. For example, the common electrode CE may be a cathode electrode.

[0268] The sealing layer ENCAP can be placed on the aforementioned light-emitting element layer EDL.

[0269] The ENCAP sealing layer can have a single-layer or multi-layer structure. For example, as shown in Figure 14, the ENCAP sealing layer may include a lower sealing layer PAS1, an intermediate sealing layer PCL, and an upper sealing layer PAS2.

[0270] However, the display device 100 according to the embodiments of this specification is not limited thereto and may include only the intermediate sealing layer PCL.

[0271] The lower sealing layer PAS1 and the upper sealing layer PAS2 are inorganic films, and the intermediate sealing layer PCL may be an organic or inorganic film. The intermediate sealing layer PCL can serve as a planarization layer.

[0272] The lower sealing layer PAS1 is placed on the common electrode CE and may be positioned closest to the light-emitting element ED. The lower sealing layer PAS1 can be formed from an inorganic insulating material that can be deposited at low temperatures. For example, the lower sealing layer PAS1 may be silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). Since the lower sealing layer PAS1 is deposited in a low-temperature atmosphere, during the deposition process, the lower sealing layer PAS1 can prevent damage to the light-emitting layer EL, which contains organic materials that are vulnerable to high-temperature atmospheres.

[0273] The intermediate sealing layer PCL can act as a buffer to alleviate the stress between layers caused by warping of the display device 100, and can also enhance the planarization performance. For example, the intermediate sealing layer PCL can be made of an organic insulating material such as acrylic resin, epoxy resin, polyimide, polyethylene, or silicon oxycarbon (SiOC). For example, the intermediate sealing layer PCL can be formed by an inkjet method.

[0274] For reference, the display panel 110 may have one or more dams at or near the endpoints of the inclined surface of the sealing layer ENCAP in order to prevent the sealing layer ENCAP from collapsing. One or more dams may be located at the boundary point between the display area DA and the non-display area NDA, or near the boundary point.

[0275] An interlayer sealing layer (PCL) containing organic matter can only be located inside the innermost primary dam. That is, the interlayer sealing layer (PCL) does not have to be present on top of all dams. In contrast, an interlayer sealing layer (PCL) containing organic matter can be located on top of at least the primary dam, or only up to the top of the primary dam. That is, the interlayer sealing layer (PCL) can extend only up to the top of the primary dam. Alternatively, the interlayer sealing layer (PCL) may extend past the top of the primary dam to the top of the secondary dam.

[0276] The upper sealing layer PAS2 can be formed on the substrate SUB on which the intermediate sealing layer PCL is formed, so as to cover the upper and side surfaces of the intermediate sealing layer PCL and the lower sealing layer PAS1, respectively. The upper sealing layer PAS2 can minimize or block the penetration of external moisture or oxygen into the lower sealing layer PAS1 and the intermediate sealing layer PCL. For example, the upper sealing layer PAS2 can be formed from an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3).

[0277] The touch sensor layer TSL can be placed on the aforementioned sealing layer ENCAP.

[0278] A touch buffer film T-BUF can be placed on the sealing layer ENCAP, and a touch sensor TS can be placed on the touch buffer film T-BUF. The touch sensor TS may include a touch sensor metal TSM and a bridge metal BRG located in different layers. A touch interlayer insulating film T-ILD can be placed between the touch sensor metal TSM and the bridge metal BRG.

[0279] For example, it includes a first touch sensor metal TSM, a second touch sensor metal TSM, and a third touch sensor metal TSM that are arranged adjacent to each other. The first touch sensor metal TSM and the second touch sensor metal TSM must be electrically connected to each other. However, if there is a third touch sensor metal TSM between the first touch sensor metal TSM and the second touch sensor metal TSM, the first touch sensor metal TSM and the second touch sensor metal TSM can be electrically connected via a bridge metal BRG in another layer. The bridge metal BRG can be insulated from the third touch sensor metal TSM by a touch layer interlayer insulating film T-ILD.

[0280] When forming the touch sensor layer TSL, chemical solutions (such as developers or etching solutions) or external moisture used in the process may occur. By disposing a touch buffer film T-BUF and arranging the touch sensor layer TSL thereon, it is possible to prevent chemicals, moisture, etc. from penetrating into the light-emitting layer EL containing organic substances in the manufacturing process of the touch sensor layer TSL. Thereby, the touch buffer film T-BUF can prevent damage to the light-emitting layer EL that is vulnerable to chemical solutions or moisture.

[0281] The touch buffer film T-BUF can be formed at a low temperature of a certain temperature (for example, 100 degrees (°C)) or lower and is formed of an organic insulating material having a low dielectric constant of 1 to 3 in order to prevent damage to the light-emitting layer EL containing organic substances that are vulnerable to high temperatures. For example, the touch buffer film T-BUF can be formed of a material such as acrylic, epoxy, or siloxane. Depending on the warping of the display device 100, the encapsulation layer ENCAP may be damaged, and the touch sensor metal located on the touch buffer film T-BUF may be damaged. Even if the display device 100 is warped, the touch buffer film T-BUF having planarization performance with an organic insulating material can prevent damage to the encapsulation layer ENCAP and / or cracking of the metals TSM and BRG constituting the touch sensor TS.

[0282] The protective layer PAC can be arranged while covering the touch sensor TS. The protective layer PAC may be an organic insulating film.

[0283] According to the example of FIG. 15, in any one of the plurality of transmission regions TA, the first connection wiring DCL1 is arranged on the second interlayer insulating film ILD2, and the third interlayer insulating film ILD3 may be arranged on the second interlayer insulating film ILD2 while covering the first connection wiring DCL1.

[0284] According to the example of FIG. 16, in another one of the plurality of transmission regions TA, the second connection wiring DCL2 is arranged on the first planarization layer PLN1, and the second planarization layer PLN2 may be arranged on the first planarization layer PLN1 while covering the second connection wiring DCL2.

[0285] Referring to FIG. 17, within at least one non-transmission region NTA, the data sub-wiring DSL overlapping with the first light-emitting region EA1 is arranged on the first planarization layer PLN1, and the first connection wiring DCL1 overlapping with at least one transmission region TA adjacent to at least one non-transmission region NTA may be arranged on any one of the plurality of interlayer insulating films, for example, on the second interlayer insulating film ILD2.

[0286] According to the example of FIG. 17, the data sub-wiring DSL and the first connection wiring DCL1 arranged in different layers can be electrically connected through a connection pattern CP arranged on the passivation layer PAS0.

[0287] Referring to FIG. 18, the data sub-wiring DSL overlapping with the first light-emitting region EA1 within at least one non-transmission region NTA and the second connection wiring DCL2 overlapping with at least one transmission region TA adjacent to at least one non-transmission region NTA can be arranged on the first planarization layer PLN1.

[0288] For example, the data sub-wiring DSL and the second connection wiring DCL2 can be formed on the same layer, specifically, on one of a plurality of planarization layers, for example, on the first planarization layer PLN1, by a single manufacturing process using the same material in at least one of a plurality of transparent regions TA.

[0289] The embodiments of this specification described above can be briefly summarized as follows.

[0290] A display device according to an embodiment of this specification includes a display panel comprising an optical region having a plurality of transparent regions and a plurality of first light-emitting regions, and a plurality of data connection wires arranged in a first direction in a general region having a plurality of second light-emitting regions and in at least one of the plurality of transparent regions, and an optical electronic device arranged below the display panel and superimposed on the optical region, wherein the plurality of data connection wires may include at least one first connection wire arranged in the first region and the second region of the optical region, and at least one second connection wire arranged in the first region and having a lower resistance than the first connection wire.

[0291] The second region may be a region located on the first and second sides of the first region, respectively.

[0292] The first region is divided into an upper region, an intermediate region, and a lower region, and at least one second connecting wire may be located in at least one of the upper region and the lower region.

[0293] At least one first connecting wire can be placed in the intermediate region.

[0294] At least one first connecting wire can be located in at least one of the upper and lower regions.

[0295] The widths of at least one of the multiple data connection wires located in the first region and at least one of the multiple data connection wires located in the second region may differ from each other.

[0296] At least one of the multiple data connection wires located in the first region may have a wider wiring width than at least one of the multiple data connection wires located in the second region.

[0297] The lengths of at least one of the multiple data connection wires located in the first region and at least one of the multiple data connection wires located in the second region may differ from those of the other.

[0298] Of the multiple data connection wires, at least one data connection wire located in the second region may have a curve or bend, and the wire having a curve or bend may include a zigzag pattern. The wire having a curve or bend located in the second region may include any of the following: power wires, power connection wires, low-potential wires, data connection wires, and data sub-wires.

[0299] The display panel may include at least one connection pattern in which, in a plurality of first light-emitting regions, a plurality of data sub-wirings arranged in a first direction and at least one of the plurality of data sub-wirings arranged in different layers electrically connects the corresponding wiring among the at least one first connection wiring.

[0300] Multiple data sub-routes may have lower resistance than the first connection routing.

[0301] At least one of the first connecting wires may be a wire with high light transmittance.

[0302] The display panel may further include a substrate, a transistor layer disposed on the substrate and comprising at least one transistor and a plurality of interlayer insulating films, and a plurality of planarization layers disposed on the transistor layer.

[0303] The plurality of data sub-wiring can be disposed on any one of the plurality of planarization layers.

[0304] At least one first connection wiring can be disposed on any one of the plurality of interlayer insulating films.

[0305] At least one second connection wiring can be disposed on any one of the plurality of planarization layers.

[0306] The display device according to the embodiment of the present specification includes a substrate including a plurality of transmissive regions and a plurality of light-emitting regions, a transistor layer disposed on the substrate and including at least one transistor and a plurality of interlayer insulating films, a plurality of planarization layers disposed on the transistor layer, and in the plurality of light-emitting regions, disposed on any one of the plurality of planarization layers, a plurality of data sub-wirings electrically connected to at least one of at least one first connection wiring and at least one second connection wiring, and a light-emitting element layer including a plurality of light-emitting elements corresponding to each of the plurality of light-emitting regions.

[0307] At least one first connection wiring may be disposed on any one of the plurality of interlayer insulating films in at least one of the plurality of transmissive regions.

[0308] At least one second connection wiring may be disposed on any one of the plurality of planarization layers in at least one of the plurality of transmissive regions.

[0309] The display device according to the embodiments herein includes an optical region comprising a plurality of transparent regions and a plurality of first light-emitting regions; a display panel disposed around the optical region and comprising a plurality of data connection wirings arranged in a first direction in at least one of the regions of the plurality of transparent regions and a general region comprising a plurality of second light-emitting regions; and an optical electronic device disposed below the display panel and superimposed on the optical region, wherein the plurality of data connection wirings comprises at least one first connection wiring arranged in the first region and the second region of the optical region, and at least one second connection wiring arranged in the first region, wherein at least one of the plurality of data connection wirings arranged in the second region is a wiring having a curve or a bent portion, and the wiring having a curve or a bent portion may include a zigzag pattern.

[0310] The display device according to the embodiments of this specification includes a substrate including an optical region including a plurality of transparent regions and a plurality of light-emitting regions; a transistor layer disposed on the substrate and including at least one transistor and a plurality of interlayer insulating films; a plurality of planarization layers disposed on the transistor layer; a plurality of data sub-wirings disposed on any of the plurality of planarization layers in the plurality of light-emitting regions and electrically connected to at least one of a plurality of data connection wirings, specifically at least one first connection wiring and at least one second connection wiring; and a light-emitting layer disposed on the plurality of planarization layers and including a plurality of light-emitting elements corresponding to each of the plurality of light-emitting regions, wherein the optical region includes a first region and a second region, and at least one of the plurality of data sub-wirings disposed in the second region may have a curve or a refraction portion.

[0311] The above description is merely illustrative of the technical concept of this specification, and any person with ordinary skill in the art to which this specification belongs will be able to make various modifications and variations without departing from the essential characteristics of this specification. Furthermore, the embodiments disclosed herein are for illustrative purposes only and not to limit the technical concept of this specification, and the scope of the technical concept of this specification is not limited by such embodiments. [Explanation of Symbols]

[0312] OA: Optical area EA1: First luminescence region TA: Transparent area DCL1: First connection wiring DCL2: Second connection wiring DSL: Data Subwire DP: Zigzag Pattern SP1: Subpixel of the first color SP2: Second color subpixel SP3: Third subpixel color

Claims

1. A display panel comprising an optical region including a plurality of transparent regions and a plurality of first light-emitting regions, a general region disposed outside the optical region and having a plurality of second light-emitting regions, and a plurality of data connection wirings arranged in a first direction in at least one of the plurality of transparent regions, and An optical electronic device positioned below the display panel and superimposed on the optical region. Includes, A display device wherein the plurality of data connection lines include at least one first connection line located in a first region and a second region of the optical region, and at least one second connection line located in the first region and having a lower resistance than the first connection line.

2. The display device according to claim 1, wherein the second region is a region located on the first side and the second side of the first region, respectively.

3. The first region is divided into an upper region, an intermediate region, and a lower region. The display device according to claim 1, wherein the at least one second connection wiring is arranged in at least one of the upper region and the lower region.

4. The display device according to claim 3, wherein the at least one first connection wiring is located in the intermediate region.

5. The display device according to claim 3, wherein the at least one first connection wiring is arranged in at least one of the upper region and the lower region.

6. The display device according to claim 1, wherein at least one data connection wiring located in the first region and at least one data connection wiring located in the second region of the plurality of data connection wirings have different wiring widths.

7. The display device according to claim 1, wherein at least one of the plurality of data connection wirings located in the first region has a wiring width greater than at least one of the plurality of data connection wirings located in the second region.

8. The display device according to claim 1, wherein at least one data connection wiring located in the first region and at least one data connection wiring located in the second region of the plurality of data connection wirings have different wiring lengths.

9. The display device according to claim 1, wherein at least one of the plurality of data connection wires located in the second region is a wire having a curve or a bent portion.

10. The display device according to claim 9, wherein the wiring having the curve or bent portion includes a zigzag pattern.

11. The display device according to claim 1, wherein at least one of the plurality of data connection wirings is disposed between the planarization layer and the source-drain electrode pattern.

12. The display device according to claim 1, wherein at least one of the plurality of data connection wirings is located below the source-drain electrode pattern.

13. The display device according to claim 12, wherein at least one of the plurality of data connection wirings is arranged between a plurality of interlayer insulating films.

14. The aforementioned display panel is In the plurality of first light-emitting regions, a plurality of data sub-wirings are arranged in the first direction and are located in layers different from the at least one first connection wiring, and At least one connection pattern that electrically connects at least one of the plurality of data sub-wirings to the corresponding wiring among the at least one first connection wiring. The display device according to claim 1, including the following:

15. The display device according to claim 14, wherein the plurality of data sub-wirings have lower resistance than the first connection wiring.

16. The display device according to claim 1, wherein the at least one first connection wiring has high light transmittance.

17. The aforementioned display panel is substrate, A transistor layer disposed on the substrate, comprising at least one transistor and a plurality of interlayer insulating films, and Multiple planarization layers arranged on the transistor layer It further includes, The display device according to claim 14, wherein the plurality of data sub-wirings are arranged on any one of the plurality of planarization layers.

18. The at least one first connection wiring is, The display device according to claim 17, which is disposed on any one of the plurality of interlayer insulating films.

19. The display device according to claim 17, wherein the at least one second connecting wiring is arranged on any one of the plurality of planar layers.

20. A substrate including multiple transparent regions and multiple light-emitting regions, A transistor layer disposed on the substrate, comprising at least one transistor and a plurality of interlayer insulating films, Multiple planarizing layers arranged on the transistor layer, In the plurality of light-emitting regions, a plurality of data sub-wirings are arranged on any one of the plurality of planarization layers and electrically connected to at least one of the plurality of data connection wirings, at least one of the at least one first connection wirings and at least one of the at least one second connection wirings, and A light-emitting layer disposed on the plurality of planarization layers, including a plurality of light-emitting elements corresponding to each of the plurality of light-emitting regions. A display device that includes a display device.

21. The display device according to claim 20, wherein the at least one first connection wiring is arranged on one of the multiple interlayer insulating films in at least one of the multiple transparent regions.

22. The display device according to claim 20, wherein the at least one second connecting wiring is arranged on one of the planarization layers in at least one of the plurality of transparent regions.

23. A display panel comprising an optical region including a plurality of transparent regions and a plurality of first light-emitting regions, a general region disposed outside the optical region and having a plurality of second light-emitting regions, and a plurality of data connection wirings arranged in a first direction in at least one of the plurality of transparent regions, and An optical electronic device positioned below the display panel and superimposed on the optical region. Includes, The plurality of data connection lines include at least one first connection line located in the first and second regions of the optical region, and at least one second connection line located in the first region. A display device in which the wiring arranged in the second region is wiring having curves or bends.

24. The display device according to claim 23, wherein the wiring having the curve or bent portion includes a zigzag pattern.

25. The display device according to claim 23, wherein the wiring having the curve or bend arranged in the second region includes any of the following: power wiring, power connection wiring, low-potential wiring, data connection wiring, and data sub-wiring.

26. The display device according to claim 23, wherein the wiring having the curve or bend arranged in the second region includes the data connection wiring.

27. The display device according to claim 23, wherein the wiring having the curve or bend arranged in the second region includes data subwiring.

28. The display device according to claim 23, wherein the wiring having the curve or bend arranged in the second region includes the data connection wiring and the data sub-wiring.

Images