Light detection device and electronic equipment

Abstract

It enables precise focus adjustment over a wide illumination range and improves the image quality of captured images. [Solution] The photodetector comprises a plurality of photoelectric conversion elements, a first floating diffusion region shared by the plurality of photoelectric conversion elements and holding charge transferred from the plurality of photoelectric conversion elements, a plurality of transfer circuits for transferring charge accumulated in the plurality of photoelectric conversion elements to the first floating diffusion region, a first semiconductor region arranged between two adjacent photoelectric conversion elements among the plurality of photoelectric conversion elements and transferring charge overflowing from one of the two photoelectric conversion elements to the other, a second floating diffusion region and a capacitor for holding charge overflowing from the plurality of photoelectric conversion elements, and a pixel circuit for reading the charge held in the first floating diffusion region and the second floating diffusion region, or for reading separately the charge accumulated in some of the plurality of photoelectric conversion elements and the charge accumulated in the remaining photoelectric conversion elements.

Description

Technical Field

[0001] The present disclosure relates to a photodetection device and an electronic device.

Background Art

[0002] A solid-state imaging device that detects an image plane phase difference and adjusts focus by providing a plurality of photoelectric conversion units in one pixel is known. In this type of pixel, when one photoelectric conversion unit is saturated, the excess charge overflowing from that photoelectric conversion unit can be transferred to other photoelectric conversion units to prevent a deterioration in image quality.

[0003] Patent Document 1 discloses a structure that prevents charge overflowing from each photoelectric conversion unit of two pixels that detect an image plane phase difference from flowing into a floating diffusion (also referred to as a floating diffusion region).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, the solid-state imaging device of Patent Document 1 has not made any improvements to increase the amount of charge that can be accumulated in the photoelectric conversion units within a pixel, and thus cannot perform focus adjustment over a wide illumination range. On the other hand, although a solid-state imaging device having a function of switching the conversion efficiency of photoelectric conversion has also been proposed, since the signal-to-noise ratio changes significantly when switching the conversion efficiency, there is a risk that the image quality of the captured image will deteriorate.

[0006] Therefore, the present disclosure provides a photodetection device and an electronic device that can accurately perform focus adjustment over a wide illumination range and improve the image quality of the captured image.

Means for Solving the Problems

[0007] To solve the above problems, according to this disclosure, a plurality of photoelectric conversion elements, each accumulating charge according to the amount of incident light, A first floating diffusion region shared by the plurality of photoelectric conversion elements and holding the charge transferred from the plurality of photoelectric conversion elements, A plurality of transfer circuits that transfer the charge accumulated in the plurality of photoelectric conversion elements to the first floating diffusion region, Among the plurality of photoelectric conversion elements, a first semiconductor region is arranged between two adjacent photoelectric conversion elements and transfers the charge overflowing from one of the two photoelectric conversion elements to the other; A second floating diffusion region and a capacitor that hold the charge overflowing from the plurality of photoelectric conversion elements, The device includes a pixel circuit that reads out the charge held in the first floating diffusion region and the second floating diffusion region, or reads out separately the charge accumulated in some of the photoelectric conversion elements and the charge accumulated in the remaining photoelectric conversion elements. A light detection device is provided.

[0008] Among the plurality of photoelectric conversion elements and the plurality of transfer circuits, each has a corresponding photoelectric conversion element and transfer circuit, and comprises a plurality of pixels that share the pixel circuit, The pixel circuit may switch between aggregating and reading the charges photoelectrically converted by the multiple photoelectric conversion elements in the multiple pixels, reading the charges photoelectrically converted by the multiple photoelectric conversion elements separately, or reading separately the charges accumulated in some of the photoelectric conversion elements and the charges accumulated in the remaining photoelectric conversion elements.

[0009] The plurality of photoelectric conversion elements include a first photoelectric conversion element and a second photoelectric conversion element arranged adjacent to the first photoelectric conversion element. The plurality of transfer circuits include a first transistor that transfers the charge of the first photoelectric conversion element to the first floating diffusion region, and a second transistor that transfers the charge of the second photoelectric conversion element to the first floating diffusion region. The first semiconductor region is positioned between the first photoelectric conversion element and the second photoelectric conversion element, and may transfer any overflowing charge from one of the first or second photoelectric conversion elements to the other.

[0010] The first transistor has a smaller potential barrier than the second transistor. The first transistor may have a smaller potential variation than the second transistor.

[0011] The first transistor may have substantially the same size as the second transistor.

[0012] The first transistor may have a larger size than the second transistor.

[0013] The distance between the gate electrode of the first transistor and the source region or drain region may be greater than the distance between the gate electrode of the second transistor and the source region or drain region.

[0014] The aforementioned plurality of photoelectric conversion elements are arranged in a plurality of rectangular regions in a plan view. The plurality of transfer circuits may be arranged so as to overlap the corners of the plurality of rectangular regions in a plan view.

[0015] The semiconductor layer comprises the plurality of photoelectric conversion elements arranged The first transistor may have a first gate extending in the depth direction of the semiconductor layer.

[0016] The second transistor has a second gate that extends in the depth direction of the semiconductor layer, The gate length of the first gate in the depth direction of the semiconductor layer may be longer than the gate length of the second gate.

[0017] The plurality of transfer circuits may be arranged along a surface opposite to the light incident surface, and may include a semiconductor layer having the plurality of photoelectric conversion elements and the first semiconductor region arranged inside the opposite surface.

[0018] A first transfer path for transferring charges from the first photoelectric conversion element to the first floating diffusion region, A second transfer path for transferring charges from the second photoelectric conversion element to the first floating diffusion region, A second semiconductor region or an insulating region having the same conductivity type as the first semiconductor region and a low impurity concentration or a conductivity type opposite to that of the first semiconductor region, which separates the first transfer path and the second transfer path, may be provided.

[0019] A third transfer path for transferring charges from the first photoelectric conversion element to the first floating diffusion region and also for transferring charges from the second photoelectric conversion element to the first floating diffusion region is provided, The first transistor and the second transistor may be arranged at one end of the third transfer path, and the first floating diffusion region may be arranged at the other end.

[0020] A third transistor for transferring charges overflowing from the plurality of photoelectric conversion elements and the first floating diffusion region to the second floating diffusion region may be provided.

[0021] A third floating diffusion region for holding at least a part of the charges overflowing from the plurality of photoelectric conversion elements, A third transistor for transferring at least a part of the stored charges in the second floating diffusion region to the first floating diffusion region, A fourth transistor for transferring at least a part of the stored charges in the third floating diffusion region to the second floating diffusion region may be provided.

[0022] A third floating diffusion region for holding at least a part of the charges overflowing from the plurality of photoelectric conversion elements, A third transistor for transferring at least a part of the stored charges in the third floating diffusion region to the first floating diffusion region, A fourth transistor that transfers at least a portion of the retained charge in the second floating diffusion region to the third floating diffusion region, The system may also include a fifth transistor that transfers the charge overflowing from the plurality of photoelectric conversion elements to the second floating diffusion region without passing through the first floating diffusion region.

[0023] A third floating diffusion region that holds at least a portion of the charge overflowing from the plurality of photoelectric conversion elements, A third transistor that transfers at least a portion of the retained charge in the third floating diffusion region to the first floating diffusion region, A fourth transistor that transfers at least a portion of the retained charge in the second floating diffusion region to the third floating diffusion region, The system may also include a fourth transfer path that transfers at least a portion of the charge overflowing from the plurality of photoelectric conversion elements to the second floating diffusion region without passing through the first floating diffusion region.

[0024] The fourth transfer path may have a third semiconductor region positioned between at least one of the plurality of photoelectric conversion elements and the second floating diffusion region, and having a potential barrier lower than the potential barriers of the first and second transistors.

[0025] A first substrate including the plurality of photoelectric conversion elements, the first floating diffusion region, and the fourth semiconductor region on which the first semiconductor region is arranged, The system comprises a second substrate laminated on the first substrate, on which the second floating diffusion region is arranged, Of the first substrate, the fourth semiconductor region contains an impurity of the first conductivity type. Of the first substrate, regions other than the fourth semiconductor region may contain at least one of the following: impurities of the second conductivity type, impurities of the first conductivity type at a lower concentration than the fourth semiconductor region, or insulating regions.

[0026] Furthermore, according to this disclosure, a photodetector that outputs image data, The system comprises a signal processing unit that performs signal processing on the aforementioned image data, Electronic devices will be provided. [Brief explanation of the drawing]

[0027] [Figure 1] A block diagram showing the configuration of the electronic device according to the first embodiment. [Figure 2] A block diagram showing the configuration of the light detection device according to the first embodiment. [Figure 3A] A diagram showing the first example of a stacked structure for an image processing system. [Figure 3B] A figure showing a second example of a stacked structure for an image processing system. [Figure 4] A circuit diagram showing the configuration of a large pixel and a pixel circuit according to the first embodiment. [Figure 5] A plan view showing the layout of the large pixels and pixel circuits according to the first embodiment. [Figure 6] A cross-sectional view of a transfer transistor according to the first embodiment. [Figure 7] A diagram showing the potential barrier of a large pixel according to the first embodiment. [Figure 8] A plan view showing the layout of the large pixels and pixel circuits according to the second embodiment. [Figure 9] A diagram showing the potential barrier of a large pixel according to the second embodiment. [Figure 10] A waveform diagram showing the relationship between the signal level and signal-to-noise ratio of a pixel signal in a light detection device. [Figure 11A] A cross-sectional view of the first transfer transistor according to the third embodiment. [Figure 11B] A cross-sectional view of the second transfer transistor according to the third embodiment. [Figure 12] A circuit diagram showing the configuration of a large pixel and a pixel circuit according to the fourth embodiment. [Figure 13] A plan view showing the layout of the large pixels and pixel circuits according to the fourth embodiment. [Figure 14] A plan view showing the layout of the large pixels and pixel circuits according to the fifth embodiment. [Figure 15] A plan view showing the layout of the large pixels and pixel circuits according to the sixth embodiment. [Figure 16] Cross-sectional view of two transfer transistors according to the sixth embodiment. [Figure 17] A plan view showing the layout of the large pixels and pixel circuits according to the seventh embodiment. [Figure 18] Cross-sectional view of two transfer transistors according to the seventh embodiment. [Figure 19] A plan view showing the layout of the large pixels and pixel circuits according to the eighth embodiment. [Figure 20] Cross-sectional view of a large pixel and pixel circuit according to the eighth embodiment. [Figure 21] A plan view showing the layout of the large pixels and pixel circuits according to the ninth embodiment. [Figure 22] Cross-sectional view of a large pixel and pixel circuit according to the ninth embodiment. [Figure 23] A plan view showing the layout of a large pixel and pixel circuit according to the tenth embodiment. [Figure 24] Cross-sectional view of a large pixel and pixel circuit according to the tenth embodiment. [Figure 25] A circuit diagram showing the configuration of a large pixel and a pixel circuit according to the 11th embodiment. [Figure 26] A plan view showing the layout of the large pixels and pixel circuits according to the eleventh embodiment. [Figure 27] Cross-sectional view of a large pixel and pixel circuit according to the eleventh embodiment. [Figure 28] A diagram showing the potential barrier of a large pixel according to the 11th embodiment. [Figure 29] A circuit diagram showing the configuration of a large pixel and a pixel circuit according to the 12th embodiment. [Figure 30] A plan view showing the layout of the large pixels and pixel circuits according to the twelfth embodiment. [Figure 31] Cross-sectional view of a large pixel and pixel circuit according to the twelfth embodiment. [Figure 32] A diagram showing the potential barrier of a large pixel according to the twelfth embodiment. [Figure 33] A circuit diagram showing the configuration of a large pixel and a pixel circuit according to the 13th embodiment. [Figure 34] A plan view showing the layout of the large pixels and pixel circuits according to the 13th embodiment. [Figure 35A] A first cross-sectional view of a large pixel and pixel circuit according to the 13th embodiment. [Figure 35B] A second cross-sectional view of a large pixel and pixel circuit according to the 13th embodiment. [Figure 36] A plan view showing the layout of the large pixels and pixel circuits according to the 14th embodiment. [Figure 37A] A plan view showing a large pixel and a first layer of a pixel circuit according to the 15th embodiment. [Figure 37B] A plan view showing a large pixel and a second layer of the pixel circuit according to the 15th embodiment. [Figure 38] Cross-sectional view of a large pixel and pixel circuit according to the 15th embodiment. [Figure 39A] A plan view showing the large pixels and the first layer of the pixel circuit according to the 16th embodiment. [Figure 39B] A plan view showing a large pixel and a second layer of a pixel circuit according to the 16th embodiment. [Figure 40] Cross-sectional view of a large pixel and pixel circuit according to the 16th embodiment. [Figure 41] Cross-sectional view of a large pixel and pixel circuit according to the 17th embodiment. [Figure 42] A block diagram showing an example of a general configuration of a vehicle control system. [Figure 43] An explanatory diagram showing an example of the installation location of the external information detection unit and the imaging unit. [Modes for carrying out the invention]

[0028] Embodiments of the photodetector and electronic equipment will be described below with reference to the drawings. While the main components of the photodetector and electronic equipment will be described below, there may be components and functions not shown or described. The following description does not exclude any components or functions not shown or described.

[0029] (First Embodiment) Figure 1 is a block diagram showing the configuration of an electronic device 1 equipped with a light detection device 10 according to a first embodiment of the present disclosure. The electronic device 1 is a device that generates image data based on the amount of incident light (for example, a solid-state imaging device), and comprises a light detection device 10, an imaging lens 2, a recording unit 3, and a control unit 4. Examples of electronic devices 1 include sensing devices, cameras mounted on industrial robots, or in-vehicle cameras, but the specific application and configuration of the electronic device 1 are arbitrary.

[0030] The light detection device 10 converts incident light into photoelectric data to generate image data containing grayscale information. The light detection device 10 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor.

[0031] The light detection device 10 can detect the phase difference (image plane phase difference) of incident light between multiple light-receiving positions. The light detection device 10 may also have a function to bring the multiple light-receiving positions into a focused state where the phases of the incident light are aligned by adjusting the phase difference of the incident light. In this specification, the above focusing method is also called image plane phase difference autofocus (ZAF).

[0032] The imaging lens 2 focuses the incident light and guides it to the photodetector 10. The recording unit 3 records the image data input from the photodetector 10 via the transmission line 5. The recording unit 3 may be located on a server connected via a network. The control unit 4 controls the imaging timing of the photodetector 10 via the control line 6. The electronic device 1 may have a signal processing unit 7 that performs image processing or machine learning processing on the image data output by the photodetector 10.

[0033] Figure 2 is a block diagram showing the configuration of a photodetector 10 according to the first embodiment of the present disclosure. The photodetector 10 comprises a pixel array unit 11, a row drive circuit 12, a control circuit 13, and a column signal processing circuit 14.

[0034] The pixel array section 11 has multiple large pixels 20 arranged in a first direction X and a second direction Y. In this specification, the left-right (horizontal) direction in Figure 2 is referred to as the first direction X, and the up-down (vertical) direction in Figure 2 is referred to as the second direction Y. A group of multiple large pixels 20 arranged along the first direction X is referred to as a pixel row, and a group of multiple large pixels 20 arranged along the second direction Y is referred to as a pixel column.

[0035] Each large pixel 20 has multiple photoelectric conversion elements that generate an electric charge corresponding to the amount of incident light. The large pixel 20 also contains multiple small pixels (also simply called pixels) each having a photoelectric conversion element. Multiple small pixels within a single large pixel 20 share a single pixel circuit. The pixel circuit generates a pixel signal Vimg based on the charges of the multiple photoelectric conversion elements. Note that the small pixels and pixel circuit are not shown in Figure 2.

[0036] The row drive circuit 12 is composed of a shift register, an address decoder, and the like. The row drive circuit 12 drives each large pixel 20 of the pixel array section 11 either all large pixels simultaneously or in units of pixel rows. The row drive circuit 12 sweeps out charge and reads out signals from each large pixel 20 and pixel circuit.

[0037] During charge sweeping, unwanted charges are swept away (reset) from multiple photoelectric conversion elements in the large pixel 20. This allows the multiple photoelectric conversion elements within the large pixel 20 to begin new exposure. The operation of discarding the charges from multiple photoelectric conversion elements and starting new exposure (starting charge accumulation) is also called electronic shutter operation. The photodetector 10 may perform a global shutter operation, in which the electronic shutter operation is performed simultaneously on all large pixels. Global shutter operation has the advantage that there is no timing difference in exposure for each large or small pixel.

[0038] During signal readout, a pixel signal Vimg based on the charge accumulated by multiple photoelectric conversion elements within the large pixel 20 is read out from the pixel circuit. The period from the operation of the electronic shutter to the readout of the signal is also called the exposure period. During signal readout, a pixel signal Vimg corresponding to the amount of light incident on the large pixel 20 during the exposure period is read out from the pixel circuit.

[0039] The control circuit 13 is composed of a timing generator and the like that generates various timing signals. Based on the various timing signals, the control circuit 13 controls the readout and sweep timing of the row drive circuit 12, and the drive control of the column signal processing circuit 14, etc.

[0040] The column signal processing circuit 14 receives pixel signals Vimg from each large pixel 20 and pixel circuit in the pixel array section 11. The column signal processing circuit 14 performs predetermined signal processing on the pixel signals Vimg. These predetermined signal processing methods include, for example, analog-to-digital conversion of the pixel signals Vimg and noise reduction processing superimposed on the pixel signals Vimg. For noise reduction processing on the pixel signals Vimg, for example, CDS (Correlated Double Sampling) is used.

[0041] The light detection device 10 can be composed of, for example, a stacked chip made by stacking multiple chips. Figure 3A shows a first example of the stacked structure of the light detection device 10. The light detection device 10 in Figure 3A has a two-layer structure composed of a pixel chip b1 and a logic chip b2 bonded together in that order. These chips are joined by vias or the like. Note that the pixel chip b1 and the logic chip b2 may be joined by Cu-Cu bonding or bumps in addition to vias.

[0042] The pixel chip b1 contains, for example, multiple large pixels 20 within the pixel array section 11, as well as pixel circuits and the like. The logic chip b2 contains, for example, a row drive circuit 12, a control circuit 13, and a column signal processing circuit 14.

[0043] Figure 3B shows a second example of the stacked structure of the photodetector 10. The photodetector 10a in Figure 3B has a three-layer structure formed by bonding a first pixel chip b3, a second pixel chip b4, and a logic chip b2 in that order. For example, multiple large pixels 20 are arranged on the first pixel chip b3. Pixel circuits are arranged on the second pixel chip b4. By arranging the pixel circuits on the second pixel chip b4, the photodetector 10a can increase the ratio of the area of ​​the photoelectric conversion element to the total chip area, thereby improving sensitivity and enabling miniaturization of the chip.

[0044] Furthermore, the components placed on each chip are not limited to those described above. The photodetector 10 may also be composed of four or more stacked chips, or it may be composed of a single flat chip.

[0045] Figure 4 is a circuit diagram showing the configuration of a large pixel 20 and a pixel circuit 21 according to the first embodiment of this disclosure. Figure 5 is a plan view showing the layout of the large pixel 20 and the pixel circuit 21 according to the first embodiment of this disclosure. The large pixel 20 has a plurality of photoelectric conversion elements PD, a plurality of transfer transistors (transfer circuits) TG, a floating diffusion region (first floating diffusion region) FD1, a transfer region (first semiconductor region) TRN, a conversion efficiency transistor (third transistor) FDG, and a floating diffusion region (second floating diffusion region) FD2. Figure 4 also shows a capacitor Cp connected to the floating diffusion region FD2.

[0046] The multiple photoelectric conversion elements PD include a photoelectric conversion element (first photoelectric conversion element) PD1 and a photoelectric conversion element (second photoelectric conversion element) PD2, which are arranged adjacent to each other. The multiple transfer transistors TG include a transfer transistor (first transistor) TG1 corresponding to the photoelectric conversion element PD1 and a transfer transistor (second transistor) TG2 corresponding to the photoelectric conversion element PD2. The large pixel 20 also includes a small pixel 22a having a photoelectric conversion element PD1 and a transfer transistor TG1, and a small pixel 22b having a photoelectric conversion element PD2 and a transfer transistor TG2.

[0047] The pixel circuit 21 includes an output transistor RST, an amplifier transistor AMP, and a selection transistor SEL. The pixel circuit 21 outputs a pixel signal Vimg to the column signal processing circuit 14 via a vertical signal line VSL.

[0048] The components shown in Figure 4 can be arranged in either the large pixel 20 or the pixel circuit 21 at will. At least some of the components of the pixel circuit 21 (for example, the amplifier transistor AMP) may be included in the large pixel 20. Also, at least some of the components of the large pixel 20 (for example, the conversion efficiency transistor FDG and the floating diffusion region FD2) may be included in the pixel circuit 21. The capacitor Cp may be included in either the large pixel 20 or the pixel circuit 21.

[0049] The transfer transistors TG1 and TG2, the conversion efficiency transistor FDG, the emission transistors RST and RST, the amplifier transistor AMP, and the selection transistor SEL in Figure 4 are, for example, NMOS (N channel Metal-Oxide-Semiconductor) transistors. Some or all of these transistors may be PMOS (P channel Metal-Oxide-Semiconductor) transistors. As described above, the polarity of the transistors described herein is arbitrary.

[0050] The photoelectric conversion elements PD1 and PD2 are, for example, photodiodes, and each accumulates a charge corresponding to the amount of incident light. The photoelectric conversion elements PD1 and PD2 each have an anode and a cathode. Either the anode or cathode of photoelectric conversion element PD1 (e.g., the cathode) is connected to the source of transfer transistor TG1, and the other (e.g., the anode) is connected to a predetermined reference voltage node VSS, such as the ground voltage. Either the anode or cathode of photoelectric conversion element PD2 (e.g., the cathode) is connected to the source of transfer transistor TG2, and the other (e.g., the anode) is connected to the reference voltage node VSS.

[0051] The drains of transfer transistors TG1 and TG2 are connected to the floating diffusion region FD1. Transfer transistor TG1 turns on when a predetermined voltage is applied to its gate and transfers the charge stored in photoelectric conversion element PD1 to the floating diffusion region FD1. Transfer transistor TG2 turns on when a predetermined voltage is applied to its gate and transfers the charge stored in photoelectric conversion element PD2 to the floating diffusion region FD1. As shown in Figure 5, transfer transistors TG1 and TG2 according to the first embodiment of this disclosure have substantially the same surface area (size).

[0052] The floating diffusion region FD1 is shared by multiple photoelectric conversion elements PD and holds the charge transferred from multiple photoelectric conversion elements PD (photoelectric conversion elements PD1 and PD2 in Figure 4). The floating diffusion region FD1 is connected to the gate of the amplifier transistor AMP and to the source of the conversion efficiency transistor FDG.

[0053] The photoelectric conversion elements PD1, PD2, and the floating diffusion region FD1 are semiconductor regions into which impurities of a first conductivity type (e.g., N-type) are implanted. An element isolation region ISO is positioned between the photoelectric conversion elements PD1, PD2, and the floating diffusion region FD1. The element isolation region ISO has, for example, a Shallow Trench Isolation (STI) including an insulating region. The element isolation region ISO may also have a configuration in which semiconductor regions into which impurities of a second conductivity type (e.g., P-type) are implanted.

[0054] As shown in Figure 5, the transfer region TRN is positioned between the photoelectric conversion elements PD1 and PD2. The transfer region TRN transfers the overflow charge (hereinafter also referred to as overflow charge) from one of the photoelectric conversion elements PD1 or PD2 to the other.

[0055] The transfer region TRN may be, for example, a semiconductor region in which a first-type impurity is implanted and whose impurity concentration is lower than that of the photoelectric conversion elements PD1 and PD2. Alternatively, the transfer region TRN may be a region in which a second-type impurity is implanted and whose impurity concentration is lower than that of the second-type semiconductor region within the element isolation region ISO.

[0056] The drain of the conversion efficiency transistor FDG is connected to the floating diffusion region FD2. The conversion efficiency transistor FDG turns on when a predetermined voltage is applied to its gate, transferring the overflow charge from the multiple photoelectric conversion elements PD to the floating diffusion region FD2.

[0057] The floating diffusion region FD2 holds the charge overflowing from multiple photoelectric conversion elements PD. Furthermore, the floating diffusion region FD2 is connected to the source of the emission transistor RST.

[0058] Capacitor Cp holds at least a portion of the charge held in the floating diffusion region FD2. One end of capacitor Cp is connected to the floating diffusion region FD2, and the other end is connected to a predetermined high-voltage node MIMVDD, such as the power supply voltage.

[0059] Capacitor Cp is, for example, a Lateral Overflow Integration Capacitor (LOFIC). Capacitor Cp may have, for example, a Metal-Insulator-Metal (MIM) capacitance. Capacitor Cp may also have a Metal-Oxide Semiconductor (MOS) capacitance. Because capacitor Cp has a large capacitance, the floating diffusion region FD2 and capacitor Cp can hold more charge than the floating diffusion region FD1.

[0060] The discharge transistor RST controls the sweeping of charge from the large pixel 20 and the pixel circuit 21. The drain of the discharge transistor RST is connected to a predetermined high-voltage node VDD, such as the power supply voltage. The discharge transistor RST turns on when a predetermined voltage is applied to its gate and discharges the charge from the large pixel 20 and the pixel circuit 21 to the high-voltage node VDD.

[0061] The amplifier transistor AMP is used as the input to a source follower circuit. The source of the amplifier transistor AMP is connected to the drain of the selection transistor SEL, and the drain is connected to the high-voltage node VDD. The voltage of the stray diffusion region FD1 is also applied to the gate of the amplifier transistor AMP. The amplifier transistor AMP supplies a current to the selection transistor SEL based on the voltage of the stray diffusion region FD1.

[0062] The source of the selection transistor SEL is connected to the vertical signal line VSL. The selection transistor SEL turns on when a predetermined voltage is applied to its gate and outputs a pixel signal Vimg based on the voltage of the floating diffusion region FD1 to the column signal processing circuit 14 in Figure 2 via the vertical signal line VSL.

[0063] Figure 5 illustrates the first transfer path Ps1 through the transfer transistor TG1, which transfers charge from the photoelectric conversion element PD1 to the floating diffusion region FD1. It also illustrates the second transfer path Ps2 through the transfer transistor TG2, which transfers charge from the photoelectric conversion element PD2 to the floating diffusion region FD1. Furthermore, it illustrates the third transfer path Ps3 through the transfer region TRN, which transfers charge between the photoelectric conversion elements PD1 and PD2.

[0064] The element isolation region ISO in Figure 5 includes an element isolation region (second semiconductor region, or insulating region) ISOa located between the transfer transistors TG1 and TG2 and the floating diffusion region FD1. The element isolation region ISOa separates paths Ps1 and Ps2.

[0065] Figure 6 is a cross-sectional view of a transfer transistor TG1 according to the first embodiment of this disclosure. Figure 6 shows a cross-section along the line A-A' in Figure 5. Figure 6 also shows a semiconductor layer 30 on which a plurality of photoelectric conversion elements PD are arranged. The transfer transistor TG1 has an electrode 31 arranged on the surface of the semiconductor layer 30 and a semiconductor region 32 arranged within the semiconductor layer 30. The electrode 31 is the gate electrode of the transfer transistor TG1. The semiconductor region 32 is either the drain region or the source region of the transfer transistor TG1 (for example, the drain region). Note that in Figure 6, the other of the drain region or source region is not shown. A semiconductor region 33 is also arranged within the semiconductor layer 30 so as to face the electrode 31.

[0066] The semiconductor layer 30 includes, for example, silicon (Si). The semiconductor region 32 is a region into which a first conductivity type impurity is implanted. Furthermore, when a predetermined voltage is applied to the electrode 31, charge is transferred from the photoelectric conversion element PD1 to the semiconductor region 32. The semiconductor region 32 may be formed integrally with the floating diffusion region FD1.

[0067] The semiconductor region 33 is a region into which impurities of the second conductivity type are implanted, and is located separately from the semiconductor region 32. The semiconductor region 33 is used to form the potential barrier of the transfer transistor TG1. Increasing the impurity concentration in the semiconductor region 33 can increase the potential barrier of the transfer transistor TG1. In this specification, the semiconductor region 33 is also referred to as the back gate region.

[0068] The cross-sectional structure of the transfer transistor TG2 is the same as in Figure 6.

[0069] Figure 7 shows the potential barrier of the large pixel 20 according to the first embodiment of this disclosure. Figure 7 illustrates the potential barrier when the transfer transistors TG1 and TG2 are off. Between the photoelectric conversion element PD1 and the floating diffusion region FD1 is a potential barrier of transfer transistor TG1 (i.e., path Ps1). Between the photoelectric conversion element PD2 and the floating diffusion region FD1 is a potential barrier of transfer transistor TG2 (i.e., path Ps2). Between the photoelectric conversion elements PD1 and PD2 is a potential barrier of transfer region TRN (i.e., path Ps3).

[0070] In the example shown in Figure 7, the transfer transistors TG1 and TG2 have approximately the same potential barrier when they are off. However, transfer transistors TG1 and TG2 may have different potential barriers when they are off. Furthermore, the potential barrier of the transfer region TRN is lower than the potential barriers of transfer transistors TG1 and TG2 when they are off.

[0071] The operation of the large pixel 20 and pixel circuit 21 in Figure 4 will be described below. The transfer transistors TG1 and TG2, the conversion efficiency transistor FDG, the output transistor RST, the amplifier transistor AMP, and the selection transistor SEL are controlled, for example, by applying a predetermined voltage to the gate from the row drive circuit 12 in Figure 2.

[0072] During the exposure period, the photoelectric conversion elements PD1 and PD2 accumulate charge in proportion to the amount of incident light. During the exposure period, the transfer transistors TG1 and TG2 are off and do not transfer the charge accumulated by the photoelectric conversion elements PD1 and PD2 to the floating diffusion region FD1.

[0073] During the exposure period, the emission transistor RST and the selection transistor SEL are off. Also, during the exposure period, the conversion efficiency transistor FDG is on.

[0074] When the illuminance of the incident light is high, the photoelectric conversion element PD1 or PD2 (for example, photoelectric conversion element PD1) becomes saturated. The potential barrier of the transfer region TRN is lower than the potential barriers of the transfer transistors TG1 and TG2 in the off state. Therefore, the overflow charge from the saturated photoelectric conversion element PD1 exceeds the potential barrier of the transfer region TRN and overflows into the photoelectric conversion element PD2.

[0075] When both photoelectric conversion elements PD1 and PD2 become saturated, the overflow charge exceeds the potential barrier of transfer transistors TG1 and TG2 and spills into the floating diffusion region FD1. Furthermore, the overflow charge is transferred to the floating diffusion region FD2 and capacitor Cp by the conversion efficiency transistor FDG.

[0076] In other words, the floating diffusion region FD2 and the capacitor Cp can hold the overflow charge that spills out from the photoelectric conversion elements PD1 and PD2 during the exposure period.

[0077] After the exposure period ends, a readout period begins in which charge is read from the large pixel 20 and the pixel circuit 21.

[0078] During the readout period, the pixel circuit 21 can aggregate and read out the charge photoelectrically converted by multiple photoelectric conversion elements PD within the large pixel 20. Alternatively, the pixel circuit 21 can read out the charge photoelectrically converted by multiple photoelectric conversion elements PD separately, or it can read out the charge accumulated in some of the photoelectric conversion elements PD and the charge accumulated in the remaining part of the photoelectric conversion elements PD separately.

[0079] First, we will explain the case where the charges of multiple photoelectric conversion elements PD are aggregated and read out. The pixel circuit 21 can output a reset-level pixel signal Vimg before transferring the accumulated charge of the photoelectric conversion elements PD to the floating diffusion region FD1 by turning off the conversion efficiency transistor FDG and turning on the selection transistor SEL. The pixel signal Vimg before charge transfer can be used for CDS for the high conversion efficiency (HCG) pixel signal Vimg described later.

[0080] Next, the pixel circuit 21 can transfer the charge accumulated by the photoelectric conversion elements PD1 and PD2 to the floating diffusion region FD1 by turning on the transfer transistors TG1 and TG2 while the conversion efficiency transistor FDG is in the off state. The pixel circuit 21 can output a pixel signal Vimg having a signal level corresponding to the accumulated charge of the photoelectric conversion elements PD1 and PD2 by turning on the selection transistor SEL.

[0081] In this specification, the pixel signal Vimg corresponding to the accumulated charge of the photoelectric conversion elements PD1 and PD2 is also referred to as the high-efficiency (HCG) pixel signal Vimg.

[0082] Furthermore, by turning on the conversion efficiency transistor FDG, transfer transistors TG1 and TG2, the charge accumulated in the photoelectric conversion elements PD1 and PD2, and the overflow charge held by the floating diffusion region FD2 and capacitor Cp are transferred to the floating diffusion region FD1. The pixel circuit 21 can output a pixel signal Vimg having a signal level corresponding to the accumulated charge in the photoelectric conversion elements PD1 and PD2 and the overflow charge overflowing from the photoelectric conversion elements PD1 and PD2 by turning on the selection transistor SEL.

[0083] In this specification, the pixel signal Vimg corresponding to the accumulated charge and overflow charge of the photoelectric conversion elements PD1 and PD2 is also referred to as the low conversion efficiency (SLCG) pixel signal Vimg.

[0084] The pixel circuit 21 can discharge charge from the large pixel 20 and the pixel circuit 21 by turning on the discharge transistor RST, and the voltages of the photoelectric conversion elements PD1 and PD2 can be reset to the voltage level before exposure. The pixel circuit 21 can output a pixel signal Vimg at the reset level after charge discharge by turning on the selection transistor SEL. The pixel signal Vimg at the reset level after charge discharge can be used for CDS for the low conversion efficiency (SLCG) pixel signal Vimg.

[0085] As described above, by turning on the conversion efficiency transistor FDG, the charge transferred to the floating diffusion region FD1 and the overflow charge held in the floating diffusion region FD2 and capacitor Cp can be read out. By reading out the charge and overflow charge of multiple photoelectric conversion elements PD, the pixel circuit 21 can read out a charge exceeding the saturation charge amount of the multiple photoelectric conversion elements PD. This expands the dynamic range of the pixel signal Vimg. In this specification, the above drive is also called LOFIC drive.

[0086] The pixel circuit 21 can aggregate the charge of multiple photoelectric elements PD by simultaneously turning on multiple transfer transistors TG. This method can be used for the LOFIC drive described above, and the pixel circuit 21 can aggregate and read out the charge even when the amount of incident light is low and the charge accumulated in each of the multiple photoelectric elements PD is small.

[0087] Next, we will explain the case where the charges of multiple photoelectric conversion elements PD are read out separately. The pixel circuit 21 can transfer the charge of the photoelectric conversion element PD1 to the floating diffusion region FD1 by turning on the transfer transistor TG1 while the conversion efficiency transistor FDG and the transfer transistor TG2 are in the off state. The pixel circuit 21 can output a pixel signal Vimg having a signal level corresponding to the accumulated charge of the photoelectric conversion element PD1 by turning on the selection transistor SEL.

[0088] Next, with the conversion efficiency transistor FDG and transfer transistor TG1 in the off state, the transfer transistor TG2 and selection transistor SEL are turned on, thereby enabling the output of a pixel signal Vimg having a signal level corresponding to the accumulated charge of the photoelectric conversion element PD2.

[0089] As described above, the pixel circuit 21 can separately read out the charge photoelectrically converted by multiple photoelectric conversion elements PD by turning on some of the transfer transistors TG and turning off the remaining ones. This allows the pixel circuit 21 to output a pixel signal Vimg for each of the multiple small pixels and acquire grayscale information for each small pixel.

[0090] Furthermore, if the photoelectric conversion elements PD1 and PD2 are not saturated, the photodetector 10 can obtain the phase difference of the incident light received by the photoelectric conversion elements PD1 and PD2 by comparing the pixel signal Vimg corresponding to the accumulated charge of the photoelectric conversion element PD1 with the pixel signal Vimg corresponding to the accumulated charge of the photoelectric conversion element PD2.

[0091] The light detection device 10 can determine whether the photoelectric conversion elements PD1 and PD2 are in focus by determining whether there is a phase difference in the incident light to the photoelectric conversion elements PD1 and PD2. By adjusting the phase difference between the photoelectric conversion elements PD1 and PD2, the light detection device 10 can achieve autofocus.

[0092] Thus, the photodetector 10 according to the first embodiment of this disclosure includes a plurality of photoelectric conversion elements PD, a transfer transistor TG arranged for each photoelectric conversion element PD, and floating diffusion regions FD1, FD2, and a capacitor Cp shared by the plurality of photoelectric conversion elements PD.

[0093] The photodetector 10 can switch between aggregating and reading out the charges of multiple photoelectric conversion elements PD, or reading them out separately, by controlling multiple transfer transistors TG.

[0094] When charge is aggregated and read out, the pixel signal Vimg can be amplified even when the amount of incident light is low, allowing for the output of clear image data. Furthermore, when the amount of incident light is high, the saturation signal amount (Qs) can be expanded by holding overflow charge in the capacitor Cp. As a result, the photodetector 10 can expand its dynamic range.

[0095] When the charges are read out separately, a pixel signal Vimg can be output for each small pixel, enabling the generation of high-resolution image data. Furthermore, autofocus can be achieved by detecting the image plane phase difference.

[0096] In other words, the light detection device 10 can perform accurate focus adjustment over a wide illumination range and improve the image quality of the captured image.

[0097] (Second embodiment) A second embodiment of this disclosure describes a method for further increasing the saturation signal amount. Figure 8 is a plan view showing the layout of the large pixel 20a and pixel circuit 21a according to the second embodiment of this disclosure. Figure 9 is a diagram showing the potential barrier of the large pixel 20a according to the second embodiment of this disclosure. The circuit diagrams of the large pixel 20a and pixel circuit 21a are the same as the circuit diagram in Figure 4. The large pixel 20a according to the second embodiment of this disclosure has transfer transistors TG1a and TG2a, respectively, corresponding to the transfer transistors TG1 and TG2 in Figure 5.

[0098] As shown in Figure 9, the potential barrier of the off-state transfer transistor TG2a is greater than that of the transfer transistor TG2 in Figure 7. The potential barrier of the transfer transistor TG2a can be increased by strengthening the negative bias of the transfer transistor TG2a in the off-state, or by injecting a higher concentration of impurities into the back gate region of the transfer transistor TG2a (i.e., the semiconductor region 33 in Figure 6).

[0099] The transfer transistor TG2a has a large potential barrier. On the other hand, the potential barrier of the off-state transfer transistor TG1a is smaller than that of the off-state transfer transistor TG2a. Therefore, when the photoelectric conversion element PD2 becomes saturated, the overflow charge is transferred to the floating diffusion region FD1 via the transfer region TRN (path Ps3), the photoelectric conversion element PD1, and the transfer transistor TG1a (path Ps1).

[0100] As described above, the large pixel 20a in Figure 8 differs from the large pixel 20 in Figure 5 in that it does not use the path Ps2 in Figure 5 for the transfer of overflow charge.

[0101] Furthermore, as shown in Figure 8, the transfer transistor TG1a has a larger size than the transfer transistor TG2a. Increasing the size of the transfer transistor TG1a allows for an increase in the back gate region of the transfer transistor TG1a (i.e., the semiconductor region 33 in Figure 6). This makes it possible to suppress potential variations due to the discrete dopant effect in the transfer transistor TG1a.

[0102] In the large pixel 20a, the transfer of overflow charge can be performed using path Ps1, which has a small potential variation, instead of path Ps2, which has a large potential variation. In the large pixel 20a, the transfer of overflow charge can be limited by the potential of the transfer transistor TG1a. As a result, the saturation signal amount of the photoelectric conversion element PD can be made larger than that of the large pixel 20 in Figure 5.

[0103] Figure 10 is a waveform diagram showing the relationship between the signal level and the signal-to-noise ratio (hereinafter also referred to as S / N) of the pixel signal Vimg in the photodetector 10. The horizontal axis of Figure 10 represents the signal level of the pixel signal Vimg, and the vertical axis represents the signal-to-noise ratio of the pixel signal Vimg. Also in Figure 10, waveform W shows the pixel signal Vimg with high conversion efficiency. HCG And the waveform W shows the pixel signal Vimg with low conversion efficiency. SLCG And, this is illustrated in the diagram.

[0104] The signal-to-noise ratio (S / N) of a high-efficiency pixel signal Vimg improves monotonically with increasing signal level until the photoelectric converter PD saturates. However, once the photoelectric converter PD saturates, the S / N of the high-efficiency pixel signal Vimg no longer improves even if the signal level increases. Therefore, the photodetector 10 acquires a low-efficiency pixel signal Vimg at the signal level where the photoelectric converter PD saturates (the transition point in Figure 10).

[0105] In this specification, the degree of decrease in the S / N ratio from the high-conversion-efficiency pixel signal Vimg to the low-conversion-efficiency pixel signal Vimg at the splice shown in Figure 10 is also referred to as the splice S / N step. In the photodetector 10, if the splice S / N step is large, the image quality of the image data deteriorates.

[0106] In the large pixel 20a shown in Figure 8, the overflow charge of the photoelectric conversion elements PD1 and PD2 is transferred to the floating diffusion region FD1 via a path Ps1 with small potential variation. This improves the signal-to-noise ratio (S / N) of the low-conversion-efficiency pixel signal Vimg and reduces the transition S / N step. In other words, the photodetector 10 using the large pixel 20a shown in Figure 8 can improve the image quality of the image data.

[0107] Another approach is to eliminate the difference in potential barriers between transfer transistors TG1 and TG2, and instead increase the size of both transfer transistors TG1 and TG2. Similar to the large pixel 20a in Figure 8, this can reduce potential variation.

[0108] However, this method has a problem in that it increases the size of multiple transfer transistors TG, making it difficult to secure sufficient size for the photoelectric conversion element PD, and thus reducing the saturation charge amount of the photoelectric conversion element PD.

[0109] In contrast, with the large pixel 20a in Figure 8, there is no need to increase the size of the transfer transistor TG2, so a sufficient size can be secured for the photoelectric conversion element PD compared to the method described above.

[0110] In the large pixels 20a in Figures 8 and 9, the size of the transfer transistor TG1a is increased, and the potential barrier of the transfer transistor TG2a is increased. However, this is not limited to this, and the size of the transfer transistor TG2a may also be increased, and the potential barrier of the transfer transistor TG1a may also be increased.

[0111] The large pixel 20a in Figure 8 may have a configuration that includes three or more photoelectric conversion elements PD and three or more transfer transistors TG. In this case, by increasing the size of one of the transfer transistors TG and increasing the potential barrier of the other transfer transistors TG, the saturation signal amount of the photoelectric conversion element PD can be increased in the same way as described above.

[0112] Thus, in the large pixel 20a according to the second embodiment of this disclosure, the size of one of the multiple transfer transistors TG is increased, thereby increasing the potential barrier of the other transfer transistors TG. As a result, overflow charge can be transferred in a path with small potential variation, the saturation signal amount can be increased compared to the large pixel 20 according to the first embodiment, and the image quality can be improved.

[0113] Furthermore, in the large pixel 20a according to the second embodiment, it is not necessary to increase the size of multiple transfer transistors TG; it is sufficient to increase the size of just one transfer transistor TG. As a result, in the large pixel 20a, a sufficient size can be secured for the photoelectric conversion element PD, and the saturation signal amount of the photoelectric conversion element PD can be increased.

[0114] (Third embodiment) Several methods can be considered to reduce the potential variation of the transfer transistor TG. Figure 11A is a cross-sectional view of the transfer transistor TG1b according to the third embodiment of this disclosure. Figure 11B is a cross-sectional view of the transfer transistor TG2b according to the third embodiment of this disclosure. The transfer transistors TG1b and TG2b in Figures 11A and 11B correspond to the transfer transistors TG1 and TG2 in Figure 5, respectively.

[0115] The transfer transistor TG1b in Figure 11A differs from the transfer transistor TG1 in Figure 6 in that the distance between the electrode 31 and the semiconductor region 32 is larger. This allows the size of the semiconductor region 33a, which is the back gate region, to be larger in the transfer transistor TG1b than in the semiconductor region 33 in Figure 6. In the transfer transistor TG1b in Figure 11A, the potential variation due to the discrete dopant effect can be suppressed by increasing the size of the semiconductor region 33a.

[0116] The cross-sectional structure of the transfer transistor TG2b according to the third embodiment of this disclosure is the same as that shown in Figure 6. That is, the distance between the electrode 31 and the semiconductor region 32 is greater in the transfer transistor TG1b than in the transfer transistor TG2b. Also, the size of the semiconductor region 33a is larger than the semiconductor region 33b which is the back gate region of the transfer transistor TG2b.

[0117] In a third embodiment of this disclosure, the potential barrier of the off-state transfer transistor TG2b is increased, similar to the second embodiment, thereby expanding the saturation signal and reducing the transition S / N step, thereby improving the image quality of the image data. The semiconductor region 33b in Figure 11B has a higher impurity concentration than, for example, the semiconductor region 33a in Figure 11A.

[0118] Furthermore, the size of the transfer transistor TG1b may be larger than that of the transfer transistor TG2b, or it may be approximately the same size.

[0119] Thus, in the third embodiment of this disclosure, the potential variation of the transfer transistor TG1b can be suppressed by positioning the semiconductor region 32 at a greater distance from the electrode 31.

[0120] (Fourth embodiment) Figure 12 is a circuit diagram showing the configuration of a large pixel 20b and a pixel circuit 21b according to the fourth embodiment of this disclosure. Figure 13 is a plan view showing the layout of the large pixel 20b and the pixel circuit 21b according to the fourth embodiment of this disclosure. The pixel circuit 21b (or large pixel 20b) in Figure 12 differs from the pixel circuit 21 (or large pixel 20) in Figure 4 in that it further includes a floating diffusion region (second floating diffusion region) FD3 and a conversion efficiency transistor (fourth transistor) FCG.

[0121] In Figure 12, the source of the conversion efficiency transistor (third transistor) FDG is connected to the floating diffusion region (first floating diffusion region) FD1, and the drain is connected to the floating diffusion region (third floating diffusion region) FD2. When the conversion efficiency transistor FDG is ON, it transfers at least a portion of the charge held in the floating diffusion region FD1 to the floating diffusion region FD2.

[0122] The floating diffusion region FD2 holds at least a portion of the overflow charge that spills out from the multiple photoelectric conversion elements PD during the exposure period.

[0123] The source of the conversion efficiency transistor FCG in Figure 12 is connected to the floating diffusion region FD2, and the drain is connected to the floating diffusion region FD3. When the conversion efficiency transistor FCG is ON, it transfers at least a portion of the charge held in the floating diffusion region FD2 to the floating diffusion region FD3. The conversion efficiency transistor FCG is, for example, an NMOS transistor. The conversion efficiency transistor FCG is controlled by applying a predetermined voltage to its gate from the row drive circuit 12.

[0124] The floating diffusion region FD3 holds overflow charge during the exposure period. The floating diffusion region FD3 is connected to the source of the emission transistor RST and one end of the capacitor Cp. The floating diffusion region FD3 and the capacitor Cp can hold more charge than the floating diffusion regions FD1 and FD2.

[0125] The operation of the large pixel 20b and pixel circuit 21b in Figure 12 is described below. During the exposure period, the transfer transistors TG1a and TG2a, the emission transistor RST, and the selection transistor SEL are turned off, and the conversion efficiency transistors FDG and FCG are turned on. This transfers the overflow charge to the floating diffusion regions FD2 and FD3 and the capacitor Cp.

[0126] The pixel circuit 21b can detect image plane phase difference or perform LOFIC driving during the readout period. First, an example of image plane phase difference detection will be explained. First, when reading the charge of the photoelectric conversion element PD1, the conversion efficiency transistor FDG and the transfer transistor TG1a are turned on while the conversion efficiency transistor FCG and the transfer transistor TG2a are turned off. This allows the charge of the photoelectric conversion element PD1 to be read into the floating diffusion regions FD1 and FD2. By turning on the selection transistor SEL, a pixel signal Vimg containing information about the phase of the incident light to the photoelectric conversion element PD1 can be output.

[0127] Similarly, when reading the charge from the photoelectric conversion element PD2, if the conversion efficiency transistor FDG, transfer transistor TG2a, and selection transistor SEL are turned on while the conversion efficiency transistor FCG and transfer transistor TG1a are turned off, a pixel signal Vimg containing information about the phase of the incident light from the photoelectric conversion element PD2 can be output.

[0128] The image plane phase difference can be detected by comparing the pixel signals Vimg, which contain information about the phase of the incident light from the photoelectric conversion elements PD1 and PD2. While the above example describes reading the charges from the photoelectric conversion elements PD1 and PD2 in that order, the charges may also be read in the reverse order.

[0129] Next, an example of LOFIC driving will be explained. First, with the conversion efficiency transistor FCG, transfer transistors TG1a and TG2a turned off, the conversion efficiency transistor FDG and the selection transistor SEL can be turned on to read the reset level potentials of the floating diffusion regions FD1 and FD2. This makes it possible to output the reset level pixel signal Vimg used for CDS for the medium conversion efficiency (MCG) pixel signal Vimg described later.

[0130] With the conversion efficiency transistors FCG and FDG, and the transfer transistors TG1a and TG2a turned off, the potential of the reset level of the floating diffusion region FD1 can be read out by turning on the selection transistor SEL. This allows the output of a pixel signal Vimg corresponding to the reset level of the high conversion efficiency (HCG) pixel signal Vimg.

[0131] With the conversion efficiency transistors FCG and FDG turned off, the stored charge of the photoelectric conversion elements PD1 and PD2 can be transferred to the floating diffusion region FD1 by turning on the transfer transistors TG1a and TG2a. By turning on the selection transistor SEL, the charge can be read from the floating diffusion region FD1, and a high conversion efficiency (HCG) pixel signal Vimg, which has a signal level corresponding to the stored charge of the photoelectric conversion elements PD1 and PD2, can be output.

[0132] With the conversion efficiency transistor FCG turned off, the accumulated charge of the photoelectric conversion elements PD1 and PD2 can be transferred to the floating diffusion regions FD1 and FD2 by turning on the conversion efficiency transistor FDG, transfer transistors TG1a and TG2a. By turning on the selection transistor SEL, a pixel signal Vimg with medium conversion efficiency (MCG) having a signal level corresponding to the held charge in the floating diffusion regions FD1 and FD2 can be output.

[0133] By turning on the conversion efficiency transistors FCG and FDG, the transfer transistors TG1a and TG2a, and the selection transistor SEL, a low conversion efficiency (SLCG) pixel signal Vimg can be output, which has a signal level corresponding to the accumulated charge and overflow charge of the photoelectric conversion elements PD1 and PD2.

[0134] When the discharge transistor RST is turned on, charge can be discharged from the large pixel 20b and the pixel circuit 21b. After charge discharge, by turning on the selection transistor SEL, a reset-level pixel signal Vimg corresponding to the low conversion efficiency (SLCG) pixel signal Vimg can be output.

[0135] The large pixel 20 and pixel circuit 21 in Figure 4 can output two types of pixel signals Vimg with different conversion efficiencies (i.e., HCG and SLCG). On the other hand, the large pixel 20b and pixel circuit 21b in Figure 12 can output three types of pixel signals Vimg with different conversion efficiencies (i.e., HCG, MCG, and SLCG). In this specification, the driving of the large pixel 20 and pixel circuit 21 in Figure 4 is also referred to as two-stage conversion efficiency switching drive. The driving of the large pixel 20b and pixel circuit 21b in Figure 12 is also referred to as three-stage conversion efficiency switching drive.

[0136] In two-stage conversion efficiency drive, increasing the conversion efficiency of the high-efficiency (HCG) pixel signal Vimg leads to a problem of worsening the transition S / N step. In contrast, in three-stage conversion efficiency drive, by providing a medium-efficiency (MCG) pixel signal Vimg, the conversion efficiency of the high-efficiency (HCG) pixel signal Vimg can be increased without worsening the transition S / N step. As a result, the large pixel 20b and pixel circuit 21b in Figure 12 can improve low-light characteristics.

[0137] Figure 13 shows an example in which the size of the transfer transistor TG1a is larger than the size of the transfer transistor TG2a, similar to the large pixel 20a in the second embodiment. However, it is not limited to this, and the sizes of the transfer transistors TG1a and TG2a may be substantially the same. The three-stage conversion efficiency drive configuration of the fourth embodiment of this disclosure can be applied to any of the first to third embodiments.

[0138] (Fifth embodiment) Figure 14 is a plan view showing the layout of a large pixel 20c and a pixel circuit 21c according to a fifth embodiment of the present disclosure. The large pixel 20c in Figure 14 has transfer transistors TG1c and TG2c, which correspond to the transfer transistors TG1a and TG2a in Figure 13, respectively. The transfer transistors TG1c and TG2c in Figure 14 differ from the transfer transistors TG1a and TG2a in Figure 13 in their placement and shape.

[0139] In Figure 14, multiple photoelectric conversion elements PD (i.e., photoelectric conversion elements PD1 and PD2) are arranged in multiple rectangular regions in a plan view. Furthermore, multiple transfer transistors TG (i.e., transfer transistors TG1c and TG2c) are arranged to overlap the corners of the above-mentioned rectangular regions in a plan view. Transfer transistors TG1c and TG2c have, for example, a roughly trapezoidal shape.

[0140] More specifically, among the multiple corners of the rectangular region where the photoelectric conversion elements PD are arranged, the transfer transistors TG are placed in the corners near other photoelectric conversion elements PD and the floating diffusion region FD1. In the large pixel 20c of Figure 14, the transfer transistors TG can be placed closer to the floating diffusion region FD1 than in the layouts shown in Figure 13, etc.

[0141] In the large pixel 20c shown in Figure 14, the size of the floating diffusion region FD1 can be reduced. This improves the conversion efficiency of the retained charge in the floating diffusion region FD1, thereby improving low-light characteristics.

[0142] Furthermore, the large pixel 20c in Figure 14 lacks the element isolation region ISOa shown in Figure 13, etc. That is, the transfer transistors TG1c, TG2c, and the floating diffusion region FD1 are not separated by the element isolation region ISO. Therefore, the charges of the photoelectric conversion elements PD1 and PD2 are transferred via a common path (third transfer path) Ps4.

[0143] As shown in Figure 14, transfer transistors TG1c and TG2c are located at one end of path Ps4, and a floating diffusion region FD1 is located at the other end. Path Ps4 contains, for example, photoelectric conversion elements PD1 and PD2, and impurities of the same conductivity type as the floating diffusion region FD1.

[0144] Figure 14 shows an example where the size of transfer transistor TG1c is made larger than the size of transfer transistor TG2c in order to suppress potential variation. However, this is not the only option, and the sizes of transfer transistors TG1c and TG2c may be approximately the same.

[0145] Thus, in the fifth embodiment of this disclosure, by arranging the transfer transistors TG at the corners of the rectangular region where the photoelectric conversion element PD is arranged, the arrangement of the floating diffusion region FD1 and the multiple transfer transistors TG can be brought closer together. This reduces the size of the floating diffusion region FD1 and improves the low-light characteristics. The layout according to the fifth embodiment can be applied to any of the first to fourth embodiments.

[0146] (Sixth embodiment) Figure 15 is a plan view showing the layout of the large pixel 20d and pixel circuit 21d according to the sixth embodiment of this disclosure. Figure 16 is a cross-sectional view of the transfer transistors TG1d and TG2c according to the sixth embodiment of this disclosure. Figure 16 shows a cross-section along the line B-B' in Figure 15. The transfer transistor TG1d corresponds to the transfer transistor TG1c in Figure 14.

[0147] As shown in Figure 16, the transfer transistor TG1d has an electrode (first gate) 31a having a protrusion that extends in the depth direction of the semiconductor layer 30. In this specification, a transistor having the above-mentioned protrusion is also referred to as a vertical transistor. The protrusion of the electrode 31a extends to a position deeper than, for example, the bottom of the element isolation region ISO that separates the transfer transistors TG1d and TG2c.

[0148] The transfer transistor TG2c does not have the aforementioned protrusion, meaning it is not a vertical transistor. Note that in Figure 16, the drain region, source region, and back gate region of the transfer transistors TG1d and TG2c are not shown.

[0149] By making the transfer transistor TG1d a vertical transistor, potential variation can be suppressed, and the saturation signal amount can be increased. In this method, as shown in Figure 15, potential variation can be suppressed without increasing the size of the transfer transistor TG1d. As a result, the size of the large pixel 20d can be reduced compared to the large pixel 20c in Figure 14. Furthermore, by not making the transfer transistor TG2c a vertical transistor, it is possible to prevent the control line capacitance connected to the transfer transistor TG2c from becoming large, thereby suppressing a decrease in the driving speed of the large pixel 20d. The transfer transistor TG1d according to the sixth embodiment can be applied to any of the first to fifth embodiments.

[0150] (Seventh Embodiment) Figure 17 is a plan view showing the layout of the large pixel 20e and pixel circuit 21e according to the seventh embodiment of the present disclosure. Figure 18 is a cross-sectional view of the transfer transistors TG1d and TG2d according to the seventh embodiment of the present disclosure. Figure 18 shows a cross-section along the line B-B' in Figure 17. The transfer transistor TG2d corresponds to the transfer transistor TG2c in Figure 14.

[0151] As shown in Figure 18, the transfer transistor TG2d has an electrode (second gate) 31b with a protrusion extending in the depth direction of the semiconductor layer 30. In other words, the transfer transistor TG2d is a vertical transistor. The length of the protrusion (gate length) of electrode 31b is longer than the length of the protrusion of electrode 31a.

[0152] By making the transfer transistor TG2d a vertical transistor, the charge transfer capability between the photoelectric conversion element PD2 and the floating diffusion region FD1 can be improved. In addition, the protrusion of electrode 31b extends to a shallower position than the protrusion of electrode 31a. As a result, the control line capacitance connected to transfer transistor TG2d can be made smaller than the control line capacitance connected to transfer transistor TG1d. In other words, an increase in the control line capacitance of transfer transistor TG2d can be prevented, and a decrease in the driving speed of the large pixel 20e can be suppressed.

[0153] (Eighth embodiment) Figure 19 is a plan view showing the layout of the large pixel 40 and pixel circuit 41 according to the eighth embodiment of the present disclosure. Figure 20 is a cross-sectional view of the large pixel 40 and pixel circuit 41 according to the eighth embodiment of the present disclosure. Figure 20 shows a cross-section along the line C-C' in Figure 19.

[0154] The large pixel 40 in Figure 20 differs from the large pixel 20 in Figure 5 in that it has a structure in which multiple photoelectric conversion elements PDs are embedded inside a semiconductor substrate (i.e., a semiconductor layer 30). In this specification, the structure of the large pixel 40 is also called an embedded PD structure. The circuit diagrams of the large pixel 40 and the pixel circuit 41 are the same as those in Figure 12.

[0155] In the large pixel 40, light is incident from the lower side of Figure 20. An on-chip lens (OCL) and a color filter CF are arranged on the light incident surface side of the semiconductor layer 30. The OCL lens focuses the incident light onto multiple photoelectric conversion elements PD inside the semiconductor layer 30.

[0156] The color filter CF transmits or blocks light of a predetermined wavelength from the light incident on the large pixel 40. For example, the color filter CF can be a color filter that transmits visible light, or an infrared (IR Pass) filter that transmits infrared (near-infrared) light. By changing the color filter CF placed on the large pixel 40, the function of the large pixel 40 can be changed.

[0157] A floating diffusion region FD1, etc., is arranged on the surface of the semiconductor layer 30 opposite to the light incident surface. Multiple transfer transistors TG are also arranged along the surface opposite to the light incident surface. The capacitor Cp is arranged, for example, at a distance from the surface of the semiconductor layer 30 opposite to the light incident surface.

[0158] Multiple photoelectric conversion elements (PDs) and a transfer region (TRN) are arranged inside the semiconductor layer 30, on the side opposite to the light incident surface.

[0159] Adjacent large pixels 40 can be separated by placing FFTI (Full Trench Isolation) in the semiconductor layer 30. Figure 20 also illustrates the element isolation region ISOa, which is located between the photoelectric conversion elements PD1 and PD2 and the floating diffusion region FD1. Note that the illustration of the element isolation region ISOa is omitted in Figure 19.

[0160] In the large pixel 40 according to the eighth embodiment of this disclosure, the size of the large pixel 40 can be reduced by embedding the photoelectric conversion element PD and the transfer region TRN within the semiconductor layer 30.

[0161] Furthermore, in the large pixel 40 of Figure 19, the size of the transfer transistor TG1 is larger than the size of the transfer transistor TG2. As a result, as shown in Figure 20, the distance d1 between the photoelectric conversion element PD1 and the floating diffusion region FD1 on the surface of the semiconductor layer 30 opposite to the light incident surface can be increased compared to the distance d2 between the photoelectric conversion element PD2 and the floating diffusion region FD1. This suppresses the potential variation of the transfer transistor TG1, similar to the large pixel 20a in Figure 8, and increases the saturation signal amount of the photoelectric conversion element PD.

[0162] (Ninth embodiment) Figure 21 is a plan view showing the layout of the large pixel 40a and pixel circuit 41a according to the ninth embodiment of the present disclosure. Figure 22 is a cross-sectional view of the large pixel 40a and pixel circuit 41a according to the ninth embodiment of the present disclosure. Figure 22 shows a cross-section along the line D-D' in Figure 21. In the large pixel 40a of Figure 21, the transfer transistors TG1 and TG2 are arranged adjacent to each other, closer than in the large pixel 40 of Figure 19.

[0163] Furthermore, the large pixel 40a in Figure 22 lacks the element isolation region ISOa shown in Figure 20. That is, the transfer transistors TG1 and TG2 and the floating diffusion region FD1 are not separated by the element isolation region ISO. Therefore, the charge of the photoelectric conversion elements PD1 and PD2 is transferred by a common path Ps4. As shown in Figure 21, transfer transistors TG1 and TG2 are located at one end of path Ps4, and the floating diffusion region FD1 is located at the other end. More specifically, the drain region or source region of transfer transistors TG1 and TG2 is located at one end of path Ps4.

[0164] In the large pixel 40a shown in Figure 21, transfer transistors TG1 and TG2 can be positioned close to the floating diffusion region FD1, thereby reducing the size of the floating diffusion region FD1. This improves the conversion efficiency of the retained charge in the floating diffusion region FD1, thereby improving low-light characteristics.

[0165] The large pixel 40a in Figure 21 has a floating diffusion region FD3 and a conversion efficiency transistor FCG. That is, the large pixel 40a has a three-stage conversion efficiency drive configuration. Alternatively, the floating diffusion region FD3 and the conversion efficiency transistor FCG may be omitted from the large pixel 40a, resulting in a two-stage conversion efficiency drive configuration.

[0166] In the example shown in Figure 22, the transfer transistor TG2 and the photoelectric converter PD2 are located on the left side of Figure 22, while the transfer transistor TG1 and the photoelectric converter PD1 are located on the right side of Figure 22. The photoelectric converter PD2 is positioned closer to the floating diffusion region FD3 than the photoelectric converter PD1.

[0167] Thus, in the large pixel 40a according to the ninth embodiment of this disclosure, the element isolation region ISOa is omitted, and the transfer transistors TG1 and TG2 are placed close to each other. This reduces the size of the floating diffusion region FD1 and improves the low-light characteristics.

[0168] (Tenth embodiment) Figure 23 is a plan view showing the layout of the large pixel 40b and pixel circuit 41b according to the tenth embodiment of the present disclosure. Figure 24 is a cross-sectional view of the large pixel 40b and pixel circuit 41b according to the tenth embodiment of the present disclosure.

[0169] The large pixel 40b in Figure 23 differs from the large pixel 40a in Figure 21 in that the size of the transfer transistor TG2a is larger than the size of the transfer transistor TG2a. As a result, similar to the large pixel 40 in Figure 19, the potential variation of the transfer transistor TG1a can be suppressed, and the saturation signal amount of the photoelectric conversion element PD can be increased.

[0170] Furthermore, the large pixel 40b in Figure 23 can reduce the size of the floating diffusion region FD1 compared to the large pixel 40 in Figure 19. This improves low-light performance.

[0171] (11th embodiment) Figure 25 is a circuit diagram showing the configuration of the large pixel 40c and pixel circuit 41c according to the 11th embodiment of this disclosure. Figure 26 is a plan view showing the layout of the large pixel 40c and pixel circuit 41c according to the 11th embodiment of this disclosure. Figure 27 is a cross-sectional view of the large pixel 40c and pixel circuit 41c according to the 11th embodiment of this disclosure. Figure 28 is a diagram showing the potential barrier of the large pixel 40c according to the 11th embodiment of this disclosure.

[0172] The large pixels 40c and pixel circuits 41c in Figures 25 and 27 differ from the large pixels 20 and pixel circuits 21 in Figure 4 in that they further include a transfer region (third semiconductor region) TRNa, a floating diffusion region (second floating diffusion region) FD3, and a conversion efficiency transistor (fourth transistor) FCG. The transfer region TRNa and floating diffusion region FD3 are located, for example, in the large pixel 40c. The conversion efficiency transistor FCG is located, for example, in the pixel circuit 41c.

[0173] The floating diffusion region FD3 holds overflow charge during the exposure period. The floating diffusion region FD3 is connected to the drain of the conversion efficiency transistor FCG and one end of the capacitor Cp. The floating diffusion region FD3 and the capacitor Cp can hold more charge than the floating diffusion regions FD1 and FD2.

[0174] The transfer region TRNa directly transfers the overflow charge that spills out from the photoelectric conversion element PD (photoelectric conversion element PD1 in Figure 25) to the floating diffusion region FD3.

[0175] The source of the conversion efficiency transistor FCG in Figure 25 is connected to the floating diffusion region FD2. When the conversion efficiency transistor FCG is ON, it transfers the retained charge from the floating diffusion region FD3 to the floating diffusion region FD2. The conversion efficiency transistor FCG is, for example, an NMOS transistor. The conversion efficiency transistor FCG is controlled by applying a predetermined voltage to its gate from the row drive circuit 12.

[0176] In Figure 25, the source of the conversion efficiency transistor (third transistor) FDG is connected to the floating diffusion region (first floating diffusion region) FD1, and the drain is connected to the floating diffusion region (third floating diffusion region) FD2. When the conversion efficiency transistor FDG is on, it transfers at least a portion of the charge held in the floating diffusion region FD2 to the floating diffusion region FD1.

[0177] The floating diffusion region FD2 holds at least a portion of the overflow charge that spills from the multiple photoelectric conversion elements PD during the exposure period. The floating diffusion region FD2 is also connected to the source of the emission transistor RST.

[0178] The transfer region TRNa is positioned between the floating diffusion region FD3 and the photoelectric conversion element PD1. More specifically, as shown in Figure 27, the large pixel 40c has an embedded PD structure. Furthermore, the transfer region TRNa is positioned inward from the surface of the semiconductor layer 30 opposite to the light incident surface. In the example in Figure 27, the photoelectric conversion element PD1 is positioned closer to the floating diffusion region FD3 than the photoelectric conversion element PD2.

[0179] The transfer region TRNa may be a semiconductor region where, for example, a first conductivity type (e.g., N-type) impurity is implanted and the impurity concentration is lower than that of the transfer region TRN. Alternatively, the transfer region TRNa may be a region where a second conductivity type (e.g., P-type) impurity is implanted and the impurity concentration is higher than that of the transfer region TRN.

[0180] As shown in Figure 28, the potential barrier of the transfer region TRNa is greater than the potential barrier of the transfer region TRN, and smaller than the potential barrier of the off-state transfer transistor TG2 (and transfer transistor TG1). As a result, the overflow charge of the multiple photoelectric conversion elements PD is transferred to the floating diffusion region FD3 via the transfer region TRNa.

[0181] Figure 27 illustrates a path (fourth transfer path) Ps5 that transfers the charge overflowing from multiple photoelectric conversion elements PD to the floating diffusion region FD3. The transfer region TRNa comprises at least a portion of path Ps5.

[0182] The operation of the large pixel 40c and pixel circuit 41c in Figure 25 is described below. During the exposure period, the transfer transistors TG1 and TG2, the emission transistor RST, and the selection transistor SEL are turned off. During the exposure period, the transfer region TRNa transfers the overflow charge to the floating diffusion region FD3 and the capacitor Cp.

[0183] During the readout period, the image plane phase difference can be detected by turning on multiple transfer transistors TG at multiple timings.

[0184] Next, an example of LOFIC driving will be explained. First, with the conversion efficiency transistor FCG, transfer transistors TG1 and TG2 turned off, the conversion efficiency transistor FDG and the selection transistor SEL can be turned on to output a reset-level pixel signal Vimg used for CDS for the medium conversion efficiency (MCG) pixel signal Vimg. Also, with the conversion efficiency transistors FCG and FDG, and transfer transistors TG1 and TG2 turned off, the selection transistor SEL can be turned on to output a reset-level pixel signal Vimg corresponding to the high conversion efficiency (HCG) pixel signal Vimg.

[0185] With the conversion efficiency transistors FCG and FDG turned off, the accumulated charge of the photoelectric conversion elements PD1 and PD2 can be transferred to the floating diffusion region FD1 by turning on the transfer transistors TG1 and TG2. By turning on the selection transistor SEL, the charge can be read from the floating diffusion region FD1, and a high conversion efficiency (HCG) pixel signal Vimg, which has a signal level corresponding to the accumulated charge of the photoelectric conversion elements PD1 and PD2, can be output.

[0186] With the conversion efficiency transistor FCG turned off, the accumulated charge of the photoelectric conversion elements PD1 and PD2 can be transferred to the floating diffusion regions FD1 and FD2 by turning on the conversion efficiency transistor FDG, transfer transistors TG1 and TG2. By turning on the selection transistor SEL, a pixel signal Vimg with medium conversion efficiency (MCG) having a signal level corresponding to the held charge in the floating diffusion regions FD1 and FD2 can be output.

[0187] By turning on the conversion efficiency transistors FCG and FDG, the transfer transistors TG1 and TG2, and the selection transistor SEL, a low conversion efficiency (SLCG) pixel signal Vimg can be output, having a signal level corresponding to the accumulated charge of the photoelectric conversion elements PD1 and PD2 and the overflow charge accumulated in the capacitor Cp.

[0188] When the discharge transistor RST is turned on, charge can be discharged from the large pixel 40c and the pixel circuit 41c. After charge discharge, by turning on the selection transistor SEL, a reset-level pixel signal Vimg corresponding to the low conversion efficiency (SLCG) pixel signal Vimg can be output.

[0189] In the large pixel 40c shown in Figure 25, it is not necessary to transfer the overflow charge of multiple photoelectric conversion elements PD to the floating diffusion region FD1 via the off-state transfer transistor TG. Therefore, the design of the transfer transistor TG can be simplified.

[0190] (12th embodiment) Figure 29 is a circuit diagram showing the configuration of a large pixel 40d and a pixel circuit 41d according to the twelfth embodiment of this disclosure. Figure 30 is a plan view showing the layout of the large pixel 40d and the pixel circuit 41d according to the twelfth embodiment of this disclosure. Figure 31 is a cross-sectional view of the large pixel 40d and the pixel circuit 41d according to the twelfth embodiment of this disclosure. Figure 32 is a diagram showing the potential barrier of the large pixel 40d according to the twelfth embodiment of this disclosure.

[0191] The large pixel 40d and pixel circuit 41d in Figure 29 differ from the large pixel 40c and pixel circuit 41c in Figure 25 in that they have an overflow gate transistor (5th transistor) OFG instead of a transfer region TRNa.

[0192] The overflow gate transistor (OFG) transfers the overflow charge from multiple photoelectric conversion elements (PDs) to the floating diffusion region (FD3) without passing through the floating diffusion region (FD1). The overflow gate transistor (OFG) is, for example, an NMOS transistor. The source of the overflow gate transistor (OFG) is connected to either the anode or cathode (for example, the cathode) of the photoelectric conversion element (PD1), and the drain is connected to the floating diffusion region (FD3).

[0193] By applying a predetermined bias voltage to the gate of the overflow gate transistor OFG, a transfer region TRNb can be formed between the floating diffusion region FD3 and the photoelectric conversion element PD1. The transfer region TRNb is, for example, the channel region of the overflow gate transistor OFG. Figure 31 illustrates the formed transfer region TRNb.

[0194] As shown in Figure 32, the potential barrier of the transfer region TRNb is set to be greater than the potential barrier of the transfer region TRN, but smaller than the potential barrier of the off-state transfer transistor TG2 (and transfer transistor TG1). As a result, the overflow charge of the multiple photoelectric conversion elements PD is transferred to the floating diffusion region FD3 via the transfer region TRNb.

[0195] The potential barrier of the transfer region TRNb can be controlled by the bias voltage applied to the gate of the overflow gate transistor OFG. Alternatively, the potential barrier of the transfer region TRNb may be controlled by adjusting the impurity concentration in the back gate region of the overflow gate transistor OFG.

[0196] The operation of the large pixel 40d and the pixel circuit 41d is the same as that of the large pixel 40c and the pixel circuit 41c in Figure 25.

[0197] In the large pixel 40d shown in Figure 29, the potential barrier of the transfer region TRNb can be controlled by an overflow gate transistor OFG. This suppresses potential variations in the transfer region TRNb and expands the saturation signal amount.

[0198] (13th embodiment) Figure 33 is a circuit diagram showing the configuration of the large pixel 40e and pixel circuit 41e according to the thirteenth embodiment of this disclosure. Figure 34 is a plan view showing the layout of the large pixel 40e and pixel circuit 41e according to the thirteenth embodiment of this disclosure.

[0199] The large pixel 40e in Figure 33 has four small pixels 22a, 22b, 22c, and 22d. The four small pixels 22a to 22d each have a photoelectric conversion element PD1, PD2, PD3, and PD4. In addition, the small pixels 22a to 22d each have a transfer transistor TG1, TG2, TG3, and TG4.

[0200] As shown in Figure 34, the four small pixels 22a to 22d are arranged in the horizontal and vertical directions of Figure 34. Each of the four small pixels 22a to 22d has a lens OCL. In this specification, the structure of the large pixel 40e in Figure 34 is also referred to as a 2×2OCL structure.

[0201] The transfer transistors TG1 to TG4 are arranged, for example, at the corners of the rectangular region where the photoelectric conversion elements PD1 to PD4 are located in a plan view, facing each other. This makes it possible to reduce the size of the floating diffusion region FD1 and improve the conversion efficiency of the charge held in the floating diffusion region FD1.

[0202] Photoelectric conversion elements PD1 and PD2 are adjacent to each other horizontally in Figure 34. Photoelectric conversion elements PD3 and PD4 are adjacent to each other horizontally in Figure 34. Photoelectric conversion elements PD1 and PD4 are adjacent to each other vertically in Figure 34. Photoelectric conversion elements PD2 and PD3 are adjacent to each other vertically in Figure 34.

[0203] A transfer region TRN is positioned between two adjacent photoelectric conversion elements PD in the horizontal or vertical direction in Figure 34. That is, a large pixel 40e has four transfer regions TRN. The potential barrier of the transfer region TRN in Figure 34 is the same as in Figure 7.

[0204] Figures 35A and 35B are cross-sectional views of a large pixel 40d and a pixel circuit 41d according to the thirteenth embodiment of this disclosure. Figure 35A shows a cross-section of the line E-E' in Figure 34. Figure 35A shows photoelectric conversion elements PD1 and PD4, transfer transistors TG1 and TG4, and amplifier transistor AMP. Figure 35A also shows RDTI (Rear Deep Trench Isolation) which separates two adjacent large pixels 40e. Figure 35B shows photoelectric conversion elements PD1 and PD4 and a transfer region TRN.

[0205] The large pixel 40e can detect the lateral and vertical phase differences of the image plane, as shown in Figure 34. To detect the lateral phase difference, first, transfer transistors TG1 and TG4 are turned on simultaneously to read out the charges of photoelectric elements PD1 and PD4 simultaneously. Next, transfer transistors TG2 and TG3 are turned on simultaneously to read out the charges of photoelectric elements PD2 and PD3 simultaneously. By comparing the pixel signals Vimg based on the charges of photoelectric elements PD1 and PD4 with the pixel signals Vimg based on the charges of photoelectric elements PD2 and PD3, the lateral phase difference of the image plane can be detected.

[0206] In detecting the vertical phase difference on the image plane, first, transfer transistors TG1 and TG2 are turned on simultaneously to read out the charges of photoelectric elements PD1 and PD2 simultaneously. Next, transfer transistors TG3 and TG4 are turned on simultaneously to read out the charges of photoelectric elements PD3 and PD4 simultaneously. By comparing the pixel signals Vimg based on the charges of photoelectric elements PD1 and PD2 with the pixel signals Vimg based on the charges of photoelectric elements PD3 and PD4, the vertical phase difference on the image plane can be detected.

[0207] The charge readout may be performed in the reverse order described above. Furthermore, the large pixel 40e can be driven using LOFIC, similar to the large pixel 20 in Figure 4 and the large pixel 20b in Figure 12, allowing for an expansion of the saturation signal amount.

[0208] (14th embodiment) Figure 36 is a plan view showing the layout of a large pixel 40f and a pixel circuit 41f according to the 14th embodiment of this disclosure. The large pixel 40f in Figure 36 has a transfer transistor TG1d, which is a vertical transistor. The structure of the transfer transistor TG1d is the same as in Figure 16. This makes it possible to suppress potential variation without increasing the size of the transfer transistor TG1d.

[0209] Figure 36 shows an example where one of the four transfer transistors TG1d in a large pixel 40f is a vertical transistor. However, the large pixel 40f may have a configuration with multiple vertical transistors. For example, two transfer transistors TG (e.g., transfer transistors TG1d and TG3) arranged diagonally to each other may be vertical transistors.

[0210] Also, similar to Figure 18, some of the four transfer transistors TG may be vertical transistors with long gate lengths, while the remaining ones may be vertical transistors with short gate lengths.

[0211] (15th embodiment) The photoelectric conversion elements PD, transistors, and floating diffusion regions within the large pixels and pixel circuits may be arranged in multiple layers. Figure 37A is a plan view showing the layout of the first layer (first substrate) L1 of the large pixel 40g and pixel circuit 41g according to the 15th embodiment of this disclosure. Figure 37B is a plan view showing the layout of the second layer (second substrate) L2 of the large pixel 40g and pixel circuit 41g according to the 15th embodiment of this disclosure. Figure 38 is a cross-sectional view of the large pixel 40g and pixel circuit 41g according to the 15th embodiment of this disclosure. Figure 38 shows the cross-section along the G-G' line in Figures 37A and 37B.

[0212] The first layer L1 and the second layer L2 are stacked in this order from the light incident surface side of the light detection device 10. In this specification, the configuration of the large pixel 40g is also referred to as a two-stage pixel configuration.

[0213] In the first layer L1 of Figure 37A, for example, multiple transfer transistors TG, a conversion efficiency transistor FDG, and floating diffusion regions FD1 and FD2 are arranged. In addition, photoelectric conversion elements PD1 and PD2 (not shown in Figure 37A) are arranged in the first layer L1. As for the multiple transfer transistors TG, for example, a large-sized transfer transistor TG1a and a small-sized transfer transistor TG2a are arranged.

[0214] The floating diffusion regions FD1 and FD2, and the photoelectric conversion elements PD1 and PD2, are separated by STIs. Alternatively, a semiconductor region implanted with a second conductivity type (e.g., P-type) impurity may be placed instead of the STIs.

[0215] In Figure 37B, the second layer L2 includes, for example, an emission transistor RST, an amplifier transistor AMP, a selection transistor SEL, a conversion efficiency transistor FCG, and a floating diffusion region FD3. Note that a capacitor Cp, not shown in Figures 37B and 38, may also be placed in the second layer L2.

[0216] An insulating film, such as a silicon oxide film (SiO2), is placed between the transfer transistor TG on the first layer L1 and the transistor on the second layer L2. Furthermore, a charge transfer path, such as one made of silicon (Si), is placed between the transistors on the second layer L2.

[0217] In the large pixel 40g and pixel circuit 41g, the pixel size can be reduced by dividing the components into a first layer L1 and a second layer L2.

[0218] Furthermore, by limiting the region of high concentration of the first conductivity type (e.g., N-type) (the fourth semiconductor region) located in the first layer L1 to only multiple photoelectric conversion elements PD (and transfer region TRN) and floating diffusion regions FD1 and FD2, the transfer destination of the overflow charge of the photoelectric conversion elements PD can be restricted to the floating diffusion regions FD1 and FD2. Therefore, even if the potential barrier of the transfer transistor TG1 is increased, there is no risk of overflow charge spilling into regions other than the floating diffusion regions FD1 and FD2. This allows for an increase in the saturated signal amount.

[0219] The above-described layout of the first layer L1 can be realized, for example, by injecting high concentrations of first conductivity type impurities into multiple photoelectric conversion elements PD, floating diffusion regions FD1 and FD2, and injecting second conductivity type impurities into other regions of the first layer L1, making them insulating regions, or injecting low concentrations of first conductivity type impurities.

[0220] (16th Embodiment) A two-stage pixel configuration may include vertical transistors as shown in Figure 16. Figure 39A is a plan view showing the layout of the first layer L1 of the large pixel 40h and pixel circuit 41h according to the 16th embodiment of this disclosure. Figure 39B is a plan view showing the layout of the second layer L2 of the large pixel 40h and pixel circuit 41h according to the 16th embodiment of this disclosure. Figure 40 is a cross-sectional view of the large pixel 40h and pixel circuit 41h according to the 16th embodiment of this disclosure.

[0221] In Figure 39A, the transfer transistors TG consist of a vertical transistor, TG1d, and a non-vertical transfer transistor, TG2. Note that, as in Figure 18, transfer transistor TG2 may be constructed as a vertical transistor with a short gate. This allows for the suppression of potential variation without increasing the size of transfer transistor TG1d.

[0222] (Embodiment 17) The large pixel and pixel circuit may consist of three or more layers. Figure 41 is a cross-sectional view of a large pixel 40i and pixel circuit 41i according to the 17th embodiment of the present disclosure. The large pixel 40i and pixel circuit 41i have a three-stage pixel configuration including a first layer L1, a second layer L2, and a third layer (third substrate) L3. The first layer L1, the second layer L2, and the third layer L3 are stacked in this order from the light incident surface side.

[0223] The third layer L3 contains, for example, one or more logic transistors LTr. Figure 41 illustrates a junction (for example, a Cu-Cu junction) located between the first layer L1 and the second layer L2.

[0224] As described above, a three-stage pixel configuration allows for the inclusion of logic transistors (LTr) that form logic circuits and the like.

[0225] (Examples of application) The technology disclosed herein can be applied to a variety of products. For example, the technology disclosed herein may be implemented as a device mounted on any type of mobile vehicle, such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, robots, construction machinery, or agricultural machinery (tractors).

[0226] Figure 42 is a block diagram showing a schematic configuration example of a vehicle control system 7000, which is an example of a mobile control system to which the technology described herein can be applied. The vehicle control system 7000 comprises a plurality of electronic control units connected via a communication network 7010. In the example shown in Figure 42, the vehicle control system 7000 comprises a drive system control unit 7100, a body system control unit 7200, a battery control unit 7300, an external information detection unit 7400, an internal information detection unit 7500, and an integrated control unit 7600. The communication network 7010 connecting these plurality of control units may be an in-vehicle communication network compliant with any standard such as CAN (Controller Area Network), LIN (Local Interconnect Network), LAN (Local Area Network), or FlexRay®.

[0227] Each control unit comprises a microcomputer that performs calculations according to various programs, a storage unit that stores programs executed by the microcomputer or parameters used in various calculations, and a drive circuit that drives various controlled devices. Each control unit is equipped with a network interface for communication with other control units via the communication network 7010, and a communication interface for communication with devices or sensors inside or outside the vehicle via wired or wireless communication. Figure 42 illustrates the functional configuration of the integrated control unit 7600, which includes a microcomputer 7610, a general-purpose communication interface 7620, a dedicated communication interface 7630, a positioning unit 7640, a beacon receiver 7650, an in-vehicle equipment interface 7660, an audio / image output unit 7670, an in-vehicle network interface 7680, and a storage unit 7690. Other control units similarly include a microcomputer, a communication interface, and a storage unit.

[0228] The drivetrain control unit 7100 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 7100 functions as a control device for generating driving force for the vehicle, such as an internal combustion engine or a drive motor; a driving force transmission mechanism for transmitting driving force to the wheels; a steering mechanism for adjusting the steering angle of the vehicle; and a braking device for generating braking force for the vehicle. The drivetrain control unit 7100 may also function as a control device such as ABS (Antilock Brake System) or ESC (Electronic Stability Control).

[0229] A vehicle state detection unit 7110 is connected to the drivetrain control unit 7100. The vehicle state detection unit 7110 includes, for example, a gyro sensor for detecting the angular velocity of the vehicle's axial rotational motion, an acceleration sensor for detecting the vehicle's acceleration, or at least one of the sensors for detecting the amount of operation of the accelerator pedal, the amount of operation of the brake pedal, the steering angle of the steering wheel, the engine speed, or the rotational speed of the wheels. The drivetrain control unit 7100 performs calculations using signals input from the vehicle state detection unit 7110 and controls the internal combustion engine, drive motor, electric power steering system, brake system, etc.

[0230] The body system control unit 7200 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 7200 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 7200 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 7200 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0231] The battery control unit 7300 controls the secondary battery 7310, which is the power source for the drive motor, according to various programs. For example, the battery control unit 7300 receives information such as battery temperature, battery output voltage, or remaining battery capacity from the battery device equipped with the secondary battery 7310. The battery control unit 7300 uses these signals to perform calculations and controls the temperature of the secondary battery 7310 or the cooling device provided in the battery device.

[0232] The external information detection unit 7400 detects information from outside the vehicle equipped with the vehicle control system 7000. For example, at least one of the imaging unit 7410 and the external information detection unit 7420 is connected to the external information detection unit 7400. The imaging unit 7410 includes at least one of the following: a ToF (Time Of Flight) camera, a stereo camera, a monocular camera, an infrared camera, and other cameras. The external information detection unit 7420 includes at least one of the following: an environmental sensor for detecting the current weather or climate, or an ambient information detection sensor for detecting other vehicles, obstacles, or pedestrians around the vehicle equipped with the vehicle control system 7000.

[0233] The environmental sensor may be at least one of the following: a raindrop sensor for detecting rain, a fog sensor for detecting fog, a sunshine sensor for detecting the degree of sunlight, and a snow sensor for detecting snowfall. The ambient information detection sensor may be at least one of the following: an ultrasonic sensor, a radar device, and a LIDAR (Light Detection and Ranging, Laser Imaging Detection and Ranging) device. These imaging unit 7410 and external information detection unit 7420 may be provided as independent sensors or devices, or as a device in which multiple sensors or devices are integrated.

[0234] Here, Figure 43 shows examples of the installation locations of the imaging unit 7410 and the external information detection unit 7420. The imaging units 7910, 7912, 7914, 7916, and 7918 are installed, for example, at least one of the following locations on the vehicle 7900: the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the passenger compartment. The imaging unit 7910 installed on the front nose and the imaging unit 7918 installed on the upper part of the windshield inside the passenger compartment mainly acquire images of the front of the vehicle 7900. The imaging units 7912 and 7914 installed on the side mirrors mainly acquire images of the sides of the vehicle 7900. The imaging unit 7916 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 7900. The imaging unit 7918 installed on the upper part of the windshield inside the passenger compartment is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0235] Figure 43 shows an example of the imaging range of each imaging unit 7910, 7912, 7914, and 7916. Imaging range a shows the imaging range of imaging unit 7910 located on the front nose, imaging ranges b and c show the imaging ranges of imaging units 7912 and 7914 located on the side mirrors, respectively, and imaging range d shows the imaging range of imaging unit 7916 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 7910, 7912, 7914, and 7916, an overhead view image of the vehicle 7900 can be obtained.

[0236] The external information detection units 7920, 7922, 7924, 7926, 7928, and 7930, which are installed on the front, rear, sides, corners, and the upper part of the windshield inside the vehicle 7900, may be, for example, ultrasonic sensors or radar devices. The external information detection units 7920, 7926, and 7930, which are installed on the front nose, rear bumper, back door, and the upper part of the windshield inside the vehicle 7900, may be, for example, LIDAR devices. These external information detection units 7920 to 7930 are mainly used to detect preceding vehicles, pedestrians, or obstacles.

[0237] Returning to Figure 42, the explanation continues. The external information detection unit 7400 causes the imaging unit 7410 to capture images of the area outside the vehicle and receives the captured image data. The external information detection unit 7400 also receives detection information from the connected external information detection unit 7420. If the external information detection unit 7420 is an ultrasonic sensor, radar device, or LIDAR device, the external information detection unit 7400 emits ultrasonic waves or electromagnetic waves and receives information on the received reflected waves. Based on the received information, the external information detection unit 7400 may perform object detection processing such as detecting people, vehicles, obstacles, signs, or characters on the road surface, or distance detection processing. Based on the received information, the external information detection unit 7400 may perform environmental recognition processing to recognize rainfall, fog, or road surface conditions. Based on the received information, the external information detection unit 7400 may calculate the distance to an object outside the vehicle.

[0238] Furthermore, the external information detection unit 7400 may perform image recognition processing or distance detection processing to recognize people, vehicles, obstacles, signs, or characters on the road surface based on the received image data. The external information detection unit 7400 may perform distortion correction or alignment processing on the received image data, and may also synthesize image data captured by different imaging units 7410 to generate an overhead view image or a panoramic image. The external information detection unit 7400 may also perform viewpoint transformation processing using image data captured by different imaging units 7410.

[0239] The in-vehicle information detection unit 7500 detects information inside the vehicle. The in-vehicle information detection unit 7500 is connected to, for example, a driver status detection unit 7510 that detects the driver's state. The driver status detection unit 7510 may include a camera that images the driver, a biosensor that detects the driver's biometric information, or a microphone that collects sounds inside the vehicle. The biosensor is installed, for example, on the seat or steering wheel and detects the biometric information of a passenger sitting in the seat or a driver holding the steering wheel. Based on the detection information input from the driver status detection unit 7510, the in-vehicle information detection unit 7500 may calculate the driver's level of fatigue or concentration, or determine whether the driver is dozing off. The in-vehicle information detection unit 7500 may perform processing such as noise cancellation on the collected audio signals.

[0240] The integrated control unit 7600 controls the overall operation of the vehicle control system 7000 according to various programs. An input unit 7800 is connected to the integrated control unit 7600. The input unit 7800 is implemented by a device that can be operated by the passenger, such as a touch panel, buttons, a microphone, a switch, or a lever. The integrated control unit 7600 may also receive data obtained by voice recognition of voice input from the microphone. The input unit 7800 may be a remote control device using infrared or other radio waves, or an external device such as a mobile phone or PDA (Personal Digital Assistant) that is compatible with the operation of the vehicle control system 7000. The input unit 7800 may be a camera, in which case the passenger can input information by gesture. Alternatively, data obtained by detecting the movement of a wearable device worn by the passenger may be input. Furthermore, the input unit 7800 may include, for example, an input control circuit that generates an input signal based on the information input by the passenger using the above input unit 7800 and outputs it to the integrated control unit 7600. Passengers and others can input various data or instruct the vehicle control system 7000 to perform processing operations by operating this input unit 7800.

[0241] The memory unit 7690 may include a ROM (Read Only Memory) for storing various programs executed by a microcomputer, and a RAM (Random Access Memory) for storing various parameters, calculation results, or sensor values. The memory unit 7690 may also be implemented using a magnetic storage device such as an HDD (Hard Disk Drive), a semiconductor storage device, an optical storage device, or a magneto-optical storage device.

[0242] The general-purpose communication interface 7620 is a general-purpose communication interface that mediates communication between the vehicle and various devices present in the external environment 7750. The general-purpose communication interface 7620 may implement cellular communication protocols such as GSM (Global System of Mobile communications), WiMAX (registered trademark), LTE (registered trademark) (Long Term Evolution), or LTE-A (LTE-Advanced), or other wireless communication protocols such as wireless LAN (also known as Wi-Fi (registered trademark)) or Bluetooth (registered trademark). The general-purpose communication interface 7620 may connect to devices (e.g., application servers or control servers) located on an external network (e.g., the Internet, a cloud network, or a carrier-specific network) via, for example, a base station or access point. The general-purpose communication interface 7620 may also connect to terminals located near the vehicle (e.g., terminals for drivers, pedestrians, or shops, or MTC (Machine Type Communication) terminals) using, for example, P2P (Peer To Peer) technology.

[0243] The dedicated communication I / F 7630 is a communication I / F that supports communication protocols designed for use in vehicles. The dedicated communication I / F 7630 may implement standard protocols such as WAVE (Wireless Access in Vehicle Environment), which is a combination of, for example, the lower-layer IEEE802.11p and the upper-layer IEEE1609, DSRC (Dedicated Short Range Communications), or a cellular communication protocol. The dedicated communication I / F 7630 typically performs V2X communication, which is a concept that includes one or more of vehicle-to-vehicle communication, vehicle-to-infrastructure communication, vehicle-to-home communication, and vehicle-to-pedestrian communication.

[0244] The positioning unit 7640 receives GNSS signals (e.g., GPS signals from GPS (Global Positioning System) satellites) from GNSS (Global Navigation Satellite System) satellites, for example, and performs positioning to generate position information including the latitude, longitude, and altitude of the vehicle. Note that the positioning unit 7640 may also identify the current position by exchanging signals with a wireless access point, or may acquire position information from a terminal such as a mobile phone, PHS, or smartphone having a positioning function.

[0245] The beacon receiver 7650 receives radio waves or electromagnetic waves transmitted from, for example, a wireless station installed on the road, and acquires information such as the current position, traffic congestion, road closure, or travel time. Note that the function of the beacon receiver 7650 may be included in the dedicated communication I / F 7630 described above.

[0246] The in-vehicle device I / F 7660 is a communication interface that mediates the connection between the microcomputer 7610 and various in-vehicle devices 7760 present in the vehicle. The in-vehicle device I / F 7660 may establish a wireless connection using a wireless communication protocol such as a wireless LAN, Bluetooth (registered trademark), NFC (Near Field Communication), or WUSB (Wireless USB). Also, the in-vehicle device I / F 7660 may establish a wired connection such as USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), or MHL (Mobile High-definition Link) via connection terminals (and cables if necessary) not shown in the figure. The in-vehicle devices 7760 may include, for example, at least one of a mobile device or wearable device owned by a passenger, or an information device carried into or attached to the vehicle. Also, the in-vehicle devices 7760 may include a navigation device that performs route search to an arbitrary destination. The in-vehicle device I / F 7660 exchanges control signals or data signals with these in-vehicle devices 7760.

[0247] The in-vehicle network I / F 7680 is an interface that mediates communication between the microcomputer 7610 and the communication network 7010. The in-vehicle network I / F 7680 transmits and receives signals, etc., in accordance with a predetermined protocol supported by the communication network 7010.

[0248] The microcomputer 7610 of the integrated control unit 7600 controls the vehicle control system 7000 according to various programs based on information acquired via at least one of the general-purpose communication I / F 7620, dedicated communication I / F 7630, positioning unit 7640, beacon receiver 7650, in-vehicle equipment I / F 7660, and in-vehicle network I / F 7680. For example, the microcomputer 7610 may calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on acquired in-vehicle and out-of-vehicle information and output control commands to the drive system control unit 7100. For example, the microcomputer 7610 may perform coordinated control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including vehicle collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning. Furthermore, the microcomputer 7610 may perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on the acquired information about the vehicle's surroundings.

[0249] The microcomputer 7610 may generate three-dimensional distance information between the vehicle and surrounding structures, people, and other objects based on information acquired via at least one of the general-purpose communication I / F 7620, dedicated communication I / F 7630, positioning unit 7640, beacon receiver 7650, in-vehicle equipment I / F 7660, and in-vehicle network I / F 7680, and create local map information including surrounding information of the vehicle's current location. Furthermore, the microcomputer 7610 may predict dangers such as vehicle collision, proximity of pedestrians, or entry into a closed road based on the acquired information, and generate a warning signal. The warning signal may, for example, be a signal to generate a warning sound or illuminate a warning lamp.

[0250] The audio-image output unit 7670 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying the vehicle's occupants or those outside the vehicle. In the example in Figure 42, the output devices are exemplified as an audio speaker 7710, a display unit 7720, and an instrument panel 7730. The display unit 7720 may include, for example, at least one of an onboard display and a head-up display. The display unit 7720 may also have an AR (Augmented Reality) display function. The output device may be other devices other than these, such as headphones, wearable devices such as glasses-type displays worn by occupants, projectors, or lamps. If the output device is a display device, the display device visually displays the results obtained from various processes performed by the microcomputer 7610 or information received from other control units in various formats such as text, images, tables, and graphs. If the output device is an audio output device, the audio output device converts the audio signal, consisting of reproduced audio data or sound data, into an analog signal and outputs it audibly.

[0251] In the example shown in Figure 42, at least two control units connected via the communication network 7010 may be integrated into a single control unit. Alternatively, each control unit may be composed of multiple control units. Furthermore, the vehicle control system 7000 may include other control units not shown. Also, in the above description, some or all of the functions performed by one control unit may be assigned to other control units. In other words, as long as information is transmitted and received via the communication network 7010, predetermined calculation processing may be performed by any of the control units. Similarly, a sensor or device connected to one control unit may be connected to another control unit, and multiple control units may transmit and receive detection information to each other via the communication network 7010.

[0252] In the vehicle control system 7000 described above, the light detection device 10 according to this embodiment, as described with reference to Figure 2, can be applied to the imaging unit 7410 in the application example shown in Figure 42. This enables the autofocus function of the imaging unit 7410 while expanding the dynamic range and generating clear image data even in dark places.

[0253] Furthermore, this technology can take the following configuration. (1) Multiple photoelectric conversion elements, each accumulating charge corresponding to the amount of incident light, A first floating diffusion region shared by the plurality of photoelectric conversion elements and holding the charge transferred from the plurality of photoelectric conversion elements, A plurality of transfer circuits that transfer the charge accumulated in the plurality of photoelectric conversion elements to the first floating diffusion region, Among the plurality of photoelectric conversion elements, a first semiconductor region is arranged between two adjacent photoelectric conversion elements and transfers the charge overflowing from one of the two photoelectric conversion elements to the other; A second floating diffusion region and a capacitor that hold the charge overflowing from the plurality of photoelectric conversion elements, The device includes a pixel circuit that reads out the charge held in the first floating diffusion region and the second floating diffusion region, or reads out separately the charge accumulated in some of the photoelectric conversion elements and the charge accumulated in the remaining photoelectric conversion elements. Light detection device. (2) Among the plurality of photoelectric conversion elements and the plurality of transfer circuits, the plurality of pixels each have a corresponding photoelectric conversion element and the transfer circuit, and share the pixel circuit, The pixel circuit can switch between aggregating and reading the charges photoelectrically converted by the multiple photoelectric conversion elements in the multiple pixels, reading the charges photoelectrically converted by the multiple photoelectric conversion elements separately, or reading separately the charges accumulated in some of the photoelectric conversion elements and the charges accumulated in the remaining photoelectric conversion elements. (1) The light detection device described above. (3) The plurality of photoelectric conversion elements include a first photoelectric conversion element and a second photoelectric conversion element arranged adjacent to the first photoelectric conversion element, The plurality of transfer circuits include a first transistor that transfers the charge of the first photoelectric conversion element to the first floating diffusion region, and a second transistor that transfers the charge of the second photoelectric conversion element to the first floating diffusion region. The first semiconductor region is positioned between the first photoelectric conversion element and the second photoelectric conversion element, and transfers the charge overflowing from one of the first or second photoelectric conversion element to the other of the first or second photoelectric conversion element. The light detection device described in (1) or (2). (4) The first transistor has a smaller potential barrier than the second transistor, The first transistor has a smaller potential variation than the second transistor. (3) The light detection device described above. (5) The first transistor has substantially the same size as the second transistor. (3) or (4) the light detection device described above. (6) The first transistor has a larger size than the second transistor. (3) or (4) the light detection device described above. (7) The distance between the gate electrode of the first transistor and the source region or drain region is greater than the distance between the gate electrode of the second transistor and the source region or drain region. (3) The light detection device described in any one of items (6). (8) The plurality of photoelectric conversion elements are arranged in a plurality of rectangular regions in a plan view, The plurality of transfer circuits are arranged so as to overlap the corners of the plurality of rectangular regions in a plan view. (3) The light detection device described in any one of items (7). (9) A semiconductor layer on which the plurality of photoelectric conversion elements are arranged The first transistor has a first gate extending in the depth direction of the semiconductor layer, (3) The light detection device described in any one of items (8). (10) The second transistor has a second gate that extends in the depth direction of the semiconductor layer, The gate length of the first gate in the depth direction of the semiconductor layer is longer than the gate length of the second gate. (9) The light detection device described above. (11) The plurality of transfer circuits are arranged along the surface opposite to the light incident surface, and the semiconductor layer comprises the plurality of photoelectric conversion elements and the first semiconductor region arranged inward from the opposite surface, (3) The light detection device described in any one of items (10). (12) A first transfer path for transferring charge from the first photoelectric conversion element to the first floating diffusion region, A second transfer path for transferring charge from the second photoelectric conversion element to the first floating diffusion region, The first transfer path and the second transfer path are separated by a second semiconductor region or insulating region having the same conductivity type as the first semiconductor region and a low impurity concentration, or having the opposite conductivity type to the first semiconductor region. (3) The light detection device described in any one of items (11). (13) A third transfer path is provided for transferring charge from the first photoelectric conversion element to the first floating diffusion region and for transferring charge from the second photoelectric conversion element to the first floating diffusion region, The first transistor and the second transistor are located at one end of the third transfer path, and the first floating diffusion region is located at the other end. (3) The light detection device described in any one of items (11). (14) comprising the plurality of photoelectric conversion elements and a third transistor that transfers the charge overflowing from the first floating diffusion region to the second floating diffusion region, (3) The light detection device described in any one of items (13). (15) A third floating diffusion region that holds at least a portion of the charge overflowed from the plurality of photoelectric conversion elements, A third transistor that transfers at least a portion of the retained charge in the second floating diffusion region to the first floating diffusion region, A fourth transistor configured to transfer at least a part of the stored charge in the third floating diffusion region to the second floating diffusion region. (3) The photodetection device according to any one of (3) to (13). (16) A third floating diffusion region configured to hold at least a part of the charge overflowing from the plurality of photoelectric conversion elements. A third transistor configured to transfer at least a part of the stored charge in the third floating diffusion region to the first floating diffusion region. A fourth transistor configured to transfer at least a part of the stored charge in the second floating diffusion region to the third floating diffusion region. A fifth transistor configured to transfer the charge overflowing from the plurality of photoelectric conversion elements to the second floating diffusion region without passing through the first floating diffusion region. (3) The photodetection device according to any one of (3) to (13). (17) A third floating diffusion region configured to hold at least a part of the charge overflowing from the plurality of photoelectric conversion elements. A third transistor configured to transfer at least a part of the stored charge in the third floating diffusion region to the first floating diffusion region. A fourth transistor configured to transfer at least a part of the stored charge in the second floating diffusion region to the third floating diffusion region. A fourth transfer path configured to transfer at least a part of the charge overflowing from the plurality of photoelectric conversion elements to the second floating diffusion region without passing through the first floating diffusion region. (3) The photodetection device according to any one of (3) to (13). (18) The fourth transfer path is disposed between at least one of the plurality of photoelectric conversion elements and the second floating diffusion region, and has a third semiconductor region having a potential barrier lower than the potential barriers of the first transistor and the second transistor. (17) The photodetection device according to (17). (19) A first substrate including a fourth semiconductor region in which the plurality of photoelectric conversion elements, the first floating diffusion region, and the first semiconductor region are disposed. A second substrate laminated on the first substrate and in which the second floating diffusion region is disposed. Of the first substrate, the fourth semiconductor region contains an impurity of the first conductivity type. Of the first substrate, the regions other than the fourth semiconductor region include at least one of the following: impurities of the second conductivity type, impurities of the first conductivity type at a lower concentration than the fourth semiconductor region, or insulating regions. A light detection device as described in any one of items (1) through (18). (20) A light detection device according to any one of items (1) to (19) that outputs image data, The system comprises a signal processing unit that performs signal processing on the aforementioned image data, electronic equipment.

[0254] The aspects of this disclosure are not limited to the individual embodiments described above, but include various modifications that a person skilled in the art could conceive, and the effects of this disclosure are not limited to those described above. In other words, various additions, modifications, and partial deletions are possible, as long as they do not depart from the conceptual idea and spirit of this disclosure derived from the claims and their equivalents. [Explanation of Symbols]

[0255] 1 Electronic device, 2 Imaging lens, 3 Recording unit, 4 Control unit, 5 Transmission line, 6 Control line, 7 Signal processing unit, 10, 10a Light detection device, 11 Pixel array unit, 12 Row drive circuit, 13 Control circuit, 14 Column signal processing circuit, 20, 20a, 20b, 20c, 20d, 20e, 40, 40a, 40b, 40c, 40d, 40e, 40f, 40g, 40h, 40i Large pixels, 21, 21a, 21b, 21c, 21d, 21e, 41, 41a, 41b, 41c, 41d, 41e, 41f, 41g, 41h, 41i Pixel circuit, 22a, 22b, 22c, 22d Small pixels, 30 Semiconductor layer, 31, 31a, 31b Electrode, 32, 33, 33a, 33b semiconductor area

Claims

1. Multiple photoelectric conversion elements, each accumulating charge corresponding to the amount of incident light, A first floating diffusion region shared by the plurality of photoelectric conversion elements and holding the charge transferred from the plurality of photoelectric conversion elements, A plurality of transfer circuits for transferring the charge accumulated in the plurality of photoelectric conversion elements to the first floating diffusion region, Among the plurality of photoelectric conversion elements, a first semiconductor region is arranged between two adjacent photoelectric conversion elements and transfers the charge overflowing from one of the two photoelectric conversion elements to the other. A second floating diffusion region and a capacitor that hold the charge overflowing from the plurality of photoelectric conversion elements, The system includes a pixel circuit that reads out the charge held in the first floating diffusion region and the second floating diffusion region, or reads out separately the charge accumulated in some of the photoelectric conversion elements and the charge accumulated in the remaining photoelectric conversion elements. Light detection device.

2. Among the plurality of photoelectric conversion elements and the plurality of transfer circuits, each has a corresponding photoelectric conversion element and transfer circuit, and comprises a plurality of pixels that share the pixel circuit, The pixel circuit can switch between aggregating and reading the charges photoelectrically converted by the multiple photoelectric conversion elements in the multiple pixels, reading the charges photoelectrically converted by the multiple photoelectric conversion elements separately, or reading separately the charges accumulated in some of the photoelectric conversion elements and the charges accumulated in the remaining photoelectric conversion elements. The light detection device according to claim 1.

3. The plurality of photoelectric conversion elements include a first photoelectric conversion element and a second photoelectric conversion element arranged adjacent to the first photoelectric conversion element. The plurality of transfer circuits include a first transistor that transfers the charge of the first photoelectric conversion element to the first floating diffusion region, and a second transistor that transfers the charge of the second photoelectric conversion element to the first floating diffusion region. The first semiconductor region is positioned between the first photoelectric conversion element and the second photoelectric conversion element, and transfers the charge overflowing from one of the first or second photoelectric conversion element to the other of the first or second photoelectric conversion element. The light detection device according to claim 1.

4. The first transistor has a smaller potential barrier than the second transistor. The first transistor has a smaller potential variation than the second transistor. The light detection device according to claim 3.

5. The first transistor has substantially the same size as the second transistor. The light detection device according to claim 3.

6. The first transistor has a larger size than the second transistor. The light detection device according to claim 3.

7. The distance between the gate electrode of the first transistor and the source region or drain region is greater than the distance between the gate electrode of the second transistor and the source region or drain region. The light detection device according to claim 3.

8. The aforementioned plurality of photoelectric conversion elements are arranged in a plurality of rectangular regions in a plan view. The plurality of transfer circuits are arranged so as to overlap the corners of the plurality of rectangular regions in a plan view. The light detection device according to claim 3.

9. The semiconductor layer comprises the plurality of photoelectric conversion elements arranged The first transistor has a first gate extending in the depth direction of the semiconductor layer, The light detection device according to claim 3.

10. The second transistor has a second gate that extends in the depth direction of the semiconductor layer, The gate length of the first gate in the depth direction of the semiconductor layer is longer than the gate length of the second gate. The light detection device according to claim 9.

11. ） The plurality of transfer circuits are arranged along the surface opposite to the light incident surface, and the semiconductor layer comprises the plurality of photoelectric conversion elements and the first semiconductor region arranged inward from the opposite surface, The light detection device according to claim 3.

12. A first transfer path for transferring charge from the first photoelectric conversion element to the first floating diffusion region, A second transfer path for transferring charge from the second photoelectric conversion element to the first floating diffusion region, The first transfer path and the second transfer path are separated by a second semiconductor region or insulating region having the same conductivity type as the first semiconductor region and a low impurity concentration, or having the opposite conductivity type to the first semiconductor region. The light detection device according to claim 3.

13. The system includes a third transfer path that transfers charge from the first photoelectric conversion element to the first floating diffusion region and from the second photoelectric conversion element to the first floating diffusion region, The first transistor and the second transistor are arranged at one end of the third transfer path, and the first floating diffusion region is arranged at the other end. The light detection device according to claim 3.

14. The system comprises the plurality of photoelectric conversion elements and a third transistor that transfers the charge overflowing from the first floating diffusion region to the second floating diffusion region. The light detection device according to claim 3.

15. A third floating diffusion region that holds at least a portion of the charge overflowing from the plurality of photoelectric conversion elements, A third transistor that transfers at least a portion of the retained charge in the second floating diffusion region to the first floating diffusion region, A fourth transistor that transfers at least a portion of the retained charge in the third floating diffusion region to the second floating diffusion region, The light detection device according to claim 3.

16. A third floating diffusion region that holds at least a portion of the charge overflowing from the plurality of photoelectric conversion elements, A third transistor that transfers at least a portion of the retained charge in the third floating diffusion region to the first floating diffusion region, A fourth transistor that transfers at least a portion of the retained charge in the second floating diffusion region to the third floating diffusion region, The system includes a fifth transistor that transfers the charge overflowing from the plurality of photoelectric conversion elements to the second floating diffusion region without passing through the first floating diffusion region. The light detection device according to claim 3.

17. A third floating diffusion region that holds at least a portion of the charge overflowing from the plurality of photoelectric conversion elements, A third transistor that transfers at least a portion of the retained charge in the third floating diffusion region to the first floating diffusion region, A fourth transistor that transfers at least a portion of the retained charge in the second floating diffusion region to the third floating diffusion region, The system includes a fourth transfer path that transfers at least a portion of the charge overflowing from the plurality of photoelectric conversion elements to the second floating diffusion region without passing through the first floating diffusion region. The light detection device according to claim 3.

18. The fourth transfer path is disposed between at least one of the plurality of photoelectric conversion elements and the second floating diffusion region, and has a third semiconductor region having a potential barrier lower than the potential barriers of the first and second transistors. The light detection device according to claim 17.

19. A first substrate including the plurality of photoelectric conversion elements, the first floating diffusion region, and the fourth semiconductor region on which the first semiconductor region is arranged, The system comprises a second substrate laminated on the first substrate, on which the second floating diffusion region is arranged, Of the first substrate, the fourth semiconductor region contains an impurity of the first conductivity type. Of the first substrate, the regions other than the fourth semiconductor region include at least one of the following: an impurity of the second conductivity type, an impurity of the first conductivity type at a lower concentration than the fourth semiconductor region, or an insulating region. The light detection device according to claim 1.

20. A light detection device according to claim 1 that outputs image data, The system comprises a signal processing unit that performs signal processing on the aforementioned image data, electronic equipment.

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