Photodetector and electronic equipment

Abstract

To provide an optical detection device and electronic equipment that can achieve both improved performance and high integration. [Solution] An embodiment of the photodetector of the present disclosure comprises a first substrate and a second substrate. The first substrate has a photoelectric conversion unit that generates electric charge by photoelectric conversion of light, a charge storage unit that stores electric charge, and a first junction surface. The second substrate has a semiconductor layer, through vias, a second junction surface, and a first wiring layer. The semiconductor layer includes an element formation surface on which a semiconductor element included in a readout circuit that outputs a first signal based on electric charge is provided, and through holes extending in a first direction from the element formation surface. The through vias are inserted through the through holes and are electrically connected to the charge storage unit. The second junction surface is located on the opposite side from the element formation surface when viewed from the semiconductor layer and is bonded to the first junction surface. The first wiring layer is located between the semiconductor layer and the second junction surface.

Description

Technical Field

[0001] The present disclosure relates to a photodetection device and an electronic device having a plurality of semiconductor layers stacked on one another.

Background Art

[0002] For example, Non-Patent Document 1 discloses a three-layer-structured CMOS image sensor in which a top wafer including a photodiode and a transfer gate, a mid wafer including pixel transistors, and a bottom wafer including a logic circuit are stacked.

Prior Art Documents

Patent Documents

[0003]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In such a photodetection device, it is required to achieve high integration without degrading the photodetection performance.

[0005] Therefore, it is desirable to provide a photodetection device and an electronic device that can achieve both performance improvement and high integration.

Means for Solving the Problems

[0006] A photodetector according to one embodiment of the present disclosure comprises a first substrate and a second substrate. The first substrate has a photoelectric conversion unit that generates electric charge by photoelectric conversion of light, a charge storage unit that stores electric charge, and a first junction surface. The second substrate has a semiconductor layer, through vias, a second junction surface, and a first wiring layer. The semiconductor layer includes an element formation surface on which a semiconductor element included in a readout circuit that outputs a first signal based on electric charge is provided, and through holes extending in a first direction from the element formation surface. The through vias are inserted through the through holes and are electrically connected to the charge storage unit. The second junction surface is located on the opposite side from the element formation surface when viewed from the semiconductor layer and is bonded to the first junction surface. The first wiring layer is located between the semiconductor layer and the second junction surface.

[0007] An electronic device according to one embodiment of the present disclosure is equipped with a semiconductor device according to the above embodiment as a photodetector.

[0008] In a photodetector and electronic device according to one embodiment of the present disclosure, a wiring layer is provided on the second substrate on the side opposite to the element formation surface when viewed from the semiconductor layer. This reduces wiring congestion on the element formation surface side. Furthermore, the electrical connection between the semiconductor element and the portion of the semiconductor layer surrounding the through-via, which is connected to the charge storage portion and penetrates the semiconductor layer, can be made via the first wiring layer. As a result, parasitic capacitance between the through-via and the semiconductor surrounding the through-via can be reduced due to the Miller effect. Consequently, the photoelectric conversion efficiency is improved. [Brief explanation of the drawing]

[0009] [Figure 1] This is a block diagram showing an example of the functional configuration of an imaging device according to one embodiment of the present disclosure. [Figure 2] Figure 1 is an equivalent circuit diagram of the pixel sharing unit. [Figure 3] Figure 1 is a schematic diagram showing an example of a stacked cross-sectional configuration of the imaging device. [Figure 4] This is a schematic diagram showing a magnified view of a part of the imaging device shown in Figure 3. [Figure 5A]It is a first schematic diagram of a horizontal cross-section representing a part of the imaging device shown in FIG. 3. [Figure 5B] It is a second schematic diagram of a horizontal cross-section representing a part of the imaging device shown in FIG. 3. [Figure 6A] It is a schematic cross-sectional diagram for explaining one step of the manufacturing method of the connection part in the imaging device shown in FIG. 3. [Figure 6B] It is a schematic cross-sectional diagram representing the step following FIG. 6A. [Figure 6C] It is a schematic cross-sectional diagram representing the step following FIG. 6B. [Figure 6D] It is a schematic cross-sectional diagram representing the step following FIG. 6C. [Figure 6E] It is a schematic cross-sectional diagram representing the step following FIG. 6D. [Figure 6F] It is a schematic cross-sectional diagram representing the step following FIG. 6E. [Figure 6G] It is a schematic cross-sectional diagram representing the step following FIG. 6F. [Figure 6H] It is a schematic cross-sectional diagram representing the step following FIG. 6G. [Figure 6I] It is a schematic cross-sectional diagram representing the step following FIG. 6H. [Figure 6J] It is a schematic cross-sectional diagram representing the step following FIG. 6I. [Figure 6K] It is a schematic cross-sectional diagram representing the step following FIG. 6J. [Figure 6L] It is a schematic cross-sectional diagram representing the step following FIG. 6K. [Figure 7A] It is a schematic diagram showing a cross-sectional configuration example of the second substrate as the first modification example of the present disclosure. [Figure 7B] It is a schematic diagram showing a cross-sectional configuration example of the second substrate as the second modification example of the present disclosure. [Figure 7C] It is a schematic diagram showing a cross-sectional configuration example of the second substrate as the third modification example of the present disclosure. [Figure 7D] It is a schematic diagram showing a cross-sectional configuration example of the second substrate as the fourth modification example of the present disclosure. [Figure 7E] It is a schematic diagram showing a cross-sectional configuration example of the second substrate as the fifth modification example of the present disclosure. [Figure 8]It is a schematic diagram showing a cross-sectional configuration example of an imaging device as a sixth modification of the present disclosure. [Figure 9] It is a schematic diagram showing a cross-sectional configuration example of an imaging device as a seventh modification of the present disclosure. [Figure 10A] It is a cross-sectional schematic diagram for explaining one step of a manufacturing method of the imaging device shown in FIG. 9. [Figure 10B] It is a cross-sectional schematic diagram showing the steps following FIG. 10A. [Figure 10C] It is a cross-sectional schematic diagram showing the steps following FIG. 10B. [Figure 10D] It is a cross-sectional schematic diagram showing the steps following FIG. 10C. [Figure 10E] It is a cross-sectional schematic diagram showing the steps following FIG. 10D. [Figure 11] It is a block diagram showing a configuration example of an electronic device having the imaging device shown in FIG. 1. [Figure 12A] It is a schematic diagram showing an example of an overall configuration of an optical detection system using the imaging device shown in FIG. 1 and the like. [Figure 12B] It is a diagram showing an example of a circuit configuration of the optical detection system shown in FIG. 12A. [Figure 13] It is a diagram showing an example of a schematic configuration of an endoscopic surgery system. [Figure 14] It is a block diagram showing an example of a functional configuration of a camera head and a CCU. [Figure 15] It is a block diagram showing an example of a schematic configuration of a vehicle control system. [Figure 16] It is an explanatory diagram showing an example of installation positions of an outside-vehicle information detection unit and an imaging unit.

Embodiments for Carrying Out the Invention

[0010] Hereinafter, embodiments for carrying out the present disclosure will be described in detail with reference to the drawings. The description will be made in the following order. 1. Embodiment 2. Modification 3. Application Example 4. Application Example

[0011] <1. Embodiment> [Functional configuration of imaging device 1] Figure 1 is a block diagram showing an example of the overall configuration of an imaging device 1, which is a specific example of a photodetector according to an embodiment of the present disclosure. The imaging device 1 is a device that receives incident light and converts it into photoelectric light. The imaging device 1 generates a signal by converting the received light into photoelectric light. The imaging device 1 captures incident light (image light) from the subject, for example, through an optical lens system. The imaging device 1 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor and captures an image of the subject.

[0012] The imaging device 1 has a pixel array section 240 in which a plurality of pixels P are arranged in a matrix. That is, the pixel array section 240 is a region in which pixels P are repeatedly arranged in an array. Each of the plurality of pixels P has a photoelectric conversion section. The imaging device 1 has, for example, an input section 210, a row drive section 220, a timing control section 230, a column signal processing section 250, an image signal processing section 260, and an output section 270 in the peripheral region of the pixel array section 240.

[0013] In the imaging device 1, pixel sharing units 40, each containing multiple pixels P, are repeatedly arranged in an array. More specifically, the pixel sharing units 40, each containing multiple pixels P, are repeatedly arranged in both the row and column directions as repeating units. In the example shown in Figure 1, the pixel sharing unit 40 contains four pixels (pixel Pa, pixel Pb, pixel Pc, and pixel Pd). Pixels Pa to Pd are arranged, for example, in a 2x2 arrangement. Each of the pixels Pa to Pd has, for example, a photodiode PD as a photoelectric conversion unit.

[0014] In the imaging device 1, a readout circuit 45 (see Figure 2 below), described later, is provided for each pixel sharing unit 40. The readout circuit includes semiconductor elements such as an amplification transistor and a reset transistor. The readout circuit outputs a pixel signal based on the charge photoelectrically converted by the photoelectric conversion unit of each pixel P. The pixel sharing unit 40 is a unit that shares one readout circuit, and multiple pixels P (pixels Pa to Pd in ​​Figure 1) of the pixel sharing unit 40 share one readout circuit. In the pixel array unit 240, one readout circuit is provided for every four pixels (pixels Pa to Pd). By operating the readout circuit in a time-division manner, the pixel signals of each pixel Pa to Pd are read out.

[0015] As shown in Figure 1, the imaging device 1 is provided with multiple row drive signal lines Lread (row selection lines, reset control lines, etc.) and multiple vertical signal lines (column readout lines) Lsig. For example, row drive signal lines Lread are wired to each pixel row of the pixel array unit 240, which consists of multiple pixels P arranged horizontally (row direction). Also, vertical signal lines Lsig are wired to each pixel column of the pixel array unit 240, which consists of multiple pixels P arranged vertically (column direction). The row drive signal lines Lread transmit signals to drive each transistor of the pixel sharing unit 40, for example. Pixel signals can be read out from each of the pixels Pa to Pd included in the pixel sharing unit 40 via the vertical signal lines Lsig.

[0016] The row drive unit 220 is composed of a shift register, an address decoder, and the like. The row drive unit 220 generates drive signals for driving pixels P and outputs these drive signals to each pixel sharing unit 40 of the pixel array unit 240 via the row drive signal line Lread. The row drive unit 220 generates signals such as TRGs for controlling transfer transistors, SELs for controlling selection transistors, and RSTs for controlling reset transistors, and outputs the TRGs, SELs, and RSTs signals to each of the pixel sharing units 40 via the row drive signal line Lread.

[0017] As described above, the row drive signal line Lread transmits drive signals (such as signals TRGs, signals SELs, and signals RSTs) from the pixels P. The row drive unit 220 is a row address control unit that selectively scans each pixel P in the pixel array unit 240 and drives, for example, multiple pixels P arranged in the pixel array unit 240 in row units. The pixel signal of each pixel P selected and scanned by the row drive unit 220 is output to the column signal processing unit 250 via the vertical signal line Lsig connected to each pixel P.

[0018] The column signal processing unit 250 includes, for example, a load circuit connected to the vertical signal line Lsig. The load circuit, together with the amplification transistor of the readout circuit, constitutes a source follower circuit. The column signal processing unit 250 may also include an amplification circuit that amplifies the pixel signal read out from the pixel sharing unit 40 via the vertical signal line Lsig. Furthermore, the column signal processing unit 250 may include a noise processing unit that removes noise components from the pixel signal.

[0019] Furthermore, the column signal processing unit 250 includes an analog-to-digital converter (ADC). The ADC includes, for example, a comparator unit and a counter unit. The comparator unit compares the analog signal to be converted with a reference signal to be compared with it. The counter unit measures the time until the comparison result from the comparator unit is inverted.

[0020] The ADC of the column signal processing unit 250 converts the pixel signal, which is an analog signal output from the pixel sharing unit 40, into a digital signal. The ADC may perform A / D conversion on the pixel signal before noise processing by the noise processing unit, or on the pixel signal after noise processing by the noise processing unit. The column signal processing unit 250 may also include a horizontal scanning circuit that controls scanning of the readout column.

[0021] The timing control unit 230 supplies timing control signals to the row drive unit 220 and the column signal processing unit 250 based on a reference clock signal and timing control signals input to the imaging device 1 from an external source, for example. The timing control signals are, for example, vertical synchronization signals and horizontal synchronization signals. The timing control unit 230 has, for example, a timing generator that generates various timing signals, and performs drive control of the row drive unit 220 and the column signal processing unit 250, etc., based on the generated timing signals.

[0022] The image signal processing unit 260 is a circuit that performs various signal processing on the pixel signal. The image signal processing unit 260 may also include a processor and memory. For example, the image signal processing unit 260 performs signal processing on the AD-converted pixel signal, such as black level adjustment and tone curve correction processing to adjust the gradation. Characteristic data of the tone curve indicating the amount of gradation correction may be stored in advance in the internal memory of the image signal processing unit 260.

[0023] The input unit 210 and the output unit 270 are responsible for exchanging signals with the outside. For example, the reference clock signal, timing control signal, and characteristic data mentioned above are input to the input unit 210 from outside the imaging device 1. The output unit 270 can output, for example, the pixel signal after signal processing by the image signal processing unit 260, or the pixel signal before signal processing by the image signal processing unit, to the outside.

[0024] Figure 2 is an equivalent circuit diagram showing one example configuration of a pixel sharing unit 40 of an imaging device 1 according to an embodiment of the present disclosure. The pixel sharing unit 40 includes a plurality of pixels P (Pa to Pd), one readout circuit 45 connected to the plurality of pixels P, and a vertical signal line Lsig connected to the readout circuit 45. Below, an example in which four pixels P (Pa to Pd) share one readout circuit 45 will be described, as shown in Figures 1 and 2. Each of the four pixels Pa to Pd has a photoelectric conversion unit, which is a photodiode PD (PD1 to PD4), a transfer transistor TR (TR1 to TR4), and a floating diffusion FD (FD1 to FD4).

[0025] The readout circuit 45 includes, for example, a reset transistor RST, an FD conversion gain switching transistor FDG, an amplification transistor AMP, and a selection transistor SEL. The pixel sharing unit 40 operates one readout circuit 45 in a time-division manner, sequentially outputting the pixel signals of the four pixels Pa to Pd included in the pixel sharing unit 40 to the vertical signal line Lsig. In this manner, one readout circuit 45 is connected to four pixels Pa to Pd, and the pixel signals of the four pixels Pa to Pd are output in a time-division manner by one readout circuit 45. This configuration is referred to as multiple pixels P sharing one readout circuit 45.

[0026] The photoelectric conversion unit, photodiodes PD1 to PD4, converts incident light into electric charge. Photodiodes PD1 to PD4 perform photoelectric conversion to generate charge according to the amount of light received. The cathodes of photodiodes PD1 to PD4 are electrically connected to the sources of transfer transistors TR1 to TR4, and the anodes of photodiodes PD1 to PD4 are electrically connected to a reference potential line (e.g., ground GND).

[0027] Transfer transistors TR1 to TR4 are electrically connected to photodiodes PD1 to PD4. Transfer transistors TR1 to TR4 are, for example, n-type CMOS (Complementary Metal Oxide Semiconductor) transistors. The drains of transfer transistors TR1 to TR4 are electrically connected to floating diffusions FD1 to FD4, and the gates of transfer transistors TR1 to TR4 are electrically connected to drive signal lines. These drive signal lines are part of a plurality of row drive signal lines Lread (see Figure 1) connected to one pixel sharing unit 40. Transfer transistors TR1 to TR4 are controlled by signals TRG1 to TRG4, respectively, and transfer the charge that has been photoelectrically converted and stored in photodiodes PD1 to PD4 to floating diffusions FD1 to FD4.

[0028] Floating diffusion regions FD1 to FD4 are n-type diffusion layer regions formed within the p-type semiconductor layer. Floating diffusion regions FD1 to FD4 are charge holding regions, holding the charge transferred from photodiodes PD1 to PD4. Floating diffusion regions FD1 to FD4 can also be described as charge storage regions that accumulate the charge transferred from photodiodes PD1 to PD4. Floating diffusion regions FD1 to FD4 store the transferred charge and convert it into a voltage corresponding to the capacitance of floating diffusion regions FD1 to FD4. The charge converted by photodiodes PD1 to PD4 is transferred to floating diffusion regions FD1 to FD4 by transfer transistors TR1 to TR4, and converted into a voltage corresponding to the capacitance of floating diffusion regions FD1 to FD4.

[0029] The four floating diffusion transistors FD1 to FD4 contained in the pixel sharing unit 40 are electrically connected to each other and to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG. The drain of the FD conversion gain switching transistor FDG is connected to the source of the reset transistor RST, and the gate of the FD conversion gain switching transistor FDG is connected to the drive signal line. This drive signal line is part of the multiple row drive signal lines Lread connected to the pixel sharing unit 40. The drain of the reset transistor RST is connected to the power line VDD, and the gate of the reset transistor RST is connected to the drive signal line. This drive signal line is part of the multiple row drive signal lines Lread connected to the pixel sharing unit 40. The gate of the amplification transistor AMP is connected to the floating diffusion transistors FD1 to FD4, the drain of the amplification transistor AMP is connected to the power line VDD, and the source of the amplification transistor AMP is connected to the drain of the selection transistor SEL. The source of the selection transistor SEL is connected to the vertical signal line 543, and the gate of the selection transistor SEL is connected to the drive signal line. This drive signal line is part of a plurality of row drive signal lines Lread connected to a pixel sharing unit 40.

[0030] When the transfer transistors TR1 to TR4 are turned on, they transfer the charge from the photodiodes PD1 to PD4 to the floating diffusion transistors FD1 to FD4. The reset transistor RST resets the potential of the floating diffusion transistors FD1 to FD4 to a predetermined potential. When the reset transistor RST is turned on, it resets the potential of the floating diffusion transistors FD1 to FD4 to the potential of the power line VDD. The selection transistor SEL controls the output timing of the pixel signal from the readout circuit 45. The amplification transistor AMP generates a signal with a voltage corresponding to the level of charge held in the floating diffusion transistors FD1 to FD4 as the pixel signal. The amplification transistor AMP is connected to the vertical signal line Lsig via the selection transistor SEL. In the column signal processing unit 250, the amplification transistor AMP, together with the load circuit connected to the vertical signal line Lsig, constitutes a source follower. When the selector transistor SEL is turned ON, the amplifying transistor AMP outputs the voltages of the floating diffusions FD1 to FD4 to the column signal processing unit 250 via the vertical signal line Lsig. The reset transistor RST, the amplifying transistor AMP, and the selector transistor SEL are, for example, N-type CMOS transistors.

[0031] The FD conversion gain switching transistor FDG is used to change the gain of charge-to-voltage conversion in floating diffusion transistors FD1 to FD4. Generally, when shooting in dark places, the pixel signal is small. Based on Q=CV, when performing charge-to-voltage conversion, if the capacitance of floating diffusion transistors FD1 to FD4 (FD capacitance C) is large, the voltage V when converted by the amplification transistor AMP will be small. On the other hand, in bright places, the pixel signal is large, so if the FD capacitance C is not large enough, floating diffusion transistors FD1 to FD4 will not be able to accept the charge from photodiodes PD1 to PD4. Furthermore, it is desirable that the FD capacitance C be large so that the voltage V when converted by the amplification transistor AMP does not become too large (in other words, to keep it small). Considering these factors, when the FD conversion gain switching transistor FDG is turned on, the gate capacitance of the FD conversion gain switching transistor FDG increases, so the overall FD capacitance C increases. On the other hand, when the FD conversion gain switching transistor FDG is turned off, the overall FD capacitance C decreases. In this way, by switching the FD conversion gain switching transistor FDG on and off, the FD capacitance C can be varied, and the conversion efficiency can be switched. The FD conversion gain switching transistor FDG is, for example, an N-type CMOS transistor.

[0032] It is also possible to omit the FD conversion gain switching transistor FDG. In this case, for example, the readout circuit 45 is composed of three transistors, for example, an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST. The readout circuit 45 has at least one pixel transistor, such as an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FDG.

[0033] The selection transistor SEL may be located between the power line VDD and the amplification transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically connected to the drain of the amplification transistor AMP, and the gate of the selection transistor SEL is electrically connected to the row drive signal line Lread. The source of the amplification transistor AMP (the output terminal of the readout circuit 45) is electrically connected to the row drive signal line Lread, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST. Note that the number of pixels P that share one readout circuit 45 may be other than 4. For example, two or eight pixels p may share one readout circuit 45.

[0034] [Schematic configuration of imaging device 1] Figure 3 is a stacked cross-sectional view showing an example of the schematic configuration of the imaging device 1. Figure 3 is a schematic representation to make the positional relationships of the components easier to understand, and may differ from the actual cross-section. The imaging device 1 has a structure in which three substrates, namely a first substrate 101, a second substrate 102, and a third substrate 103, are stacked in order. The first substrate 101, the second substrate 102, and the third substrate 103 are each composed of a semiconductor substrate, such as a silicon (Si) substrate. In this specification, the stacking direction of the first substrate 101, the second substrate 102, and the third substrate 103 is defined as the Z-axis direction. The Z-axis direction coincides with the direction of incidence of light from the subject. The left-right direction of the paper perpendicular to the Z-axis direction is defined as the X-axis direction, and the direction perpendicular to the Z-axis and the X-axis is defined as the Y-axis direction. In subsequent figures, directions may be indicated based on the direction of the arrows in Figure 3.

[0035] The first substrate 101 has a light-receiving layer 110 and a wiring section 111. The second substrate 102 has a semiconductor layer 120, a wiring section 121 and a wiring section 122. The third substrate 103 has a semiconductor layer 130 and a wiring section 131. The light-receiving layer 110, the semiconductor layer 120, and the semiconductor layer 130 have first surfaces 11S1, 12S1, 13S1 and second surfaces 11S2, 12S2, 13S2. Both the first surfaces 11S1, 12S1, 13S1 and the second surfaces 11S2, 12S2, 13S2 extend along the XY plane.

[0036] Each of the first surfaces 11S1, 12S1, and 13S1 is an element formation surface on which semiconductor elements such as transistors are provided. Each of the first surfaces 11S1, 12S1, and 13S1 is provided with, for example, the gate electrode, gate oxide film, source and drain regions of a transistor. For example, the first surface 11S1 of the light-receiving layer 110 is provided with a transfer transistor TR and a floating diffusion FD. Also, the first surface 12S1 of the semiconductor layer 120 is provided with an amplification transistor AMP and a selection transistor SEL.

[0037] In the first substrate 101, a wiring portion 111 is laminated on the first surface 11S1 of the light-receiving layer 110. In the second substrate 102, a wiring portion 121 is laminated on the first surface 12S1 of the semiconductor layer 120, and a wiring portion 122 is laminated on the second surface 12S2 of the second substrate 102. Furthermore, in the third substrate 103, a wiring portion 131 is laminated on the first surface 13S1 of the semiconductor layer 130. The wiring portions 111, 121, 122, and 131 each include, for example, a conductive film and an insulating film, and have a plurality of wirings and vias, etc. Each of the wiring portions 111, 121, 122, and 131 includes, for example, two or more layers of wiring. Each of the wiring portions 122 and 131 may each include three or more layers of wiring.

[0038] The wiring sections 111, 121, 122, and 131 have a configuration in which, for example, one or more wiring layers are laminated with an interlayer insulating layer (interlayer insulating film) in between. Specifically, in the wiring section 111, for example, wiring layers 11M1, 11M2, and 11M3 are embedded in the interlayer insulating layer 11Z, laminated in order from the side of the joint surface 101S1 (described later). In the wiring section 121, for example, wiring layers 21M1, 21M2, and 21M3 are embedded in the interlayer insulating layer 21Z, laminated in order from the side of the joint surface 102S1 (described later). In the wiring section 122, for example, wiring layers 22M1 and 22M2 are embedded in the interlayer insulating layer 22Z, laminated in order from the side of the joint surface 102S2 (described later). Furthermore, in the wiring section 131, wiring layers 31M1, 31M2, 31M3, 31M4, and 31M5 are embedded in the interlayer insulating layer 31Z, for example, by being laminated in order from the side of the joint surface 103S1 (described later). In this specification, the wiring layers included in the wiring sections 111, 121, 122, and 131 may be collectively referred to as wiring layer M. Also, in this specification, the interlayer insulating layer included in the wiring sections 111, 121, 122, and 131 may be collectively referred to as interlayer insulating layer Z.

[0039] Each wiring layer M of wiring sections 111, 121, 122, and 131 is formed using, for example, aluminum (Al), copper (Cu), tungsten (W), polysilicon (Poly-Si), etc. Each interlayer insulating layer Z of wiring sections 111, 121, 122, and 131 is formed by a single layer film made of one of the following: silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON), or a multilayer film made of two or more of these.

[0040] The first substrate 101 and the second substrate 102 are stacked such that the first surface 11S1, which is an element formation surface where elements such as transistors are formed by bonding between electrodes, and the second surface 12S2, which is opposite to the element formation surface, face each other. In other words, the first substrate 101 and the second substrate 102 are bonded such that the front surface of the first substrate 101 and the back surface of the second substrate 102 face each other. This bonding method is called face-to-back bonding. Specifically, the bonding surface 101S1, which is the front surface of the first substrate 101 and is the side of the wiring portion 111 opposite to the light-receiving layer 110, is bonded to the bonding surface 102S2, which is the back surface of the second substrate 102 and is the side of the wiring portion 122 opposite to the semiconductor layer 120. The bonding surface 101S1 is a specific example of the "first bonding surface" as one aspect of this disclosure, and the bonding surface 102S2 is a specific example of the "second bonding surface" as one aspect of this disclosure. The first substrate 101 and the second substrate 102 may be joined to each other by a so-called hybrid bond. That is, the wiring layer 11M1 as a first pad exposed on the bonding surface 101S1 and the wiring layer 22M1 as a second pad exposed on the bonding surface 102S2 are joined to form a first bonding terminal pair, and the interlayer insulating layer 11Z exposed on the bonding surface 101S1 and the interlayer insulating layer 22Z exposed on the bonding surface 102S2 are joined. When both the wiring layer 11M1 and the wiring layer 22M1 are made of copper (Cu), the bond between the wiring layer 11M1 and the wiring layer 22M1 is sometimes called a Cu-Cu bond. The electrodes used for bonding may be made of metal materials other than copper (Cu), such as nickel (Ni), cobalt (Co), tin (Sn), etc., or may be made of other materials. Furthermore, for example, a metal oxide film containing a metal element such as Ta (tantalum), Hf (hafnium), W (tungsten), or Al (aluminum) may be provided on the second surface 12S2, which is the back surface of the semiconductor layer 120, as an anti-reflective film or light-shielding film.

[0041] On the other hand, the second substrate 102 and the third substrate 103 are stacked such that their first surfaces 12S1 and 13S1, on which elements such as transistors are formed, face each other through electrode bonding. In other words, the second substrate 102 and the third substrate 103 are bonded together such that their respective surfaces face each other. This bonding method is called face-to-face bonding. Specifically, the bonding surface 102S1 of the second substrate 102, which is the surface opposite to the semiconductor layer 120 of the wiring portion 121, is bonded to the bonding surface 103S1 of the third substrate 103, which is the surface opposite to the semiconductor layer 130 of the wiring portion 131. The second substrate 102 and the third substrate 103 may also be bonded to each other by a so-called hybrid bonding. In other words, the wiring layer 21M1, which serves as an electrode exposed on the bonding surface 102S1, and the wiring layer 31M1, which serves as an electrode exposed on the bonding surface 103S1, are bonded together, and the interlayer insulating layer 21Z, which serves as an electrode exposed on the bonding surface 102S1, is bonded together with the interlayer insulating layer 31Z, which serves as an electrode exposed on the bonding surface 103S1. When both the wiring layer 21M1 and the wiring layer 31M1 are made of copper (Cu), the bond between the wiring layer 21M1 and the wiring layer 31M1 is sometimes called a Cu-Cu bond. The electrodes used for bonding may be made of metal materials other than copper (Cu), such as nickel (Ni), cobalt (Co), tin (Sn), or other materials.

[0042] In the imaging device 1, the photodiode PD, transfer transistor TR1, and floating diffusion FD described above are arranged on the first substrate 101, and the readout circuit 45 is arranged on the second substrate 102. Since the photodiode PD and the readout circuit 45 are arranged on separate substrates, the photodiode PD can be made sufficiently large compared to the case where the photodiode PD and the readout circuit 45 are arranged on the same substrate. This makes it possible to acquire images with a wide dynamic range. The first substrate 101 may have a color filter CF on the light incident side of the photodiode PD, that is, on the side opposite to the wiring section 111 when viewed from the photodiode PD. Furthermore, an on-chip lens OCL may be provided on the second surface 11S2 of the first substrate 101. The third substrate 103 may have, for example, the row drive unit 220, timing control unit 230, column signal processing unit 250, and image signal processing unit 260 described above. The third substrate 103 may also have the input unit 210 and output unit 270 described above.

[0043] As schematically shown in Figure 3, the floating diffusion FD of the pixel P on the first substrate 101 is electrically connected to the amplification transistor AMP of the readout circuit 45 on the second substrate 102 via the wiring layers 11M1 to 11M3 of the wiring section 111 and the wiring layer 22M1 of the wiring section 122. The charge photoelectrically converted by the photodiode PD on the first substrate 101 is output to the floating diffusion FD and the readout circuit 45 on the second substrate 102 via the transfer transistor TR.

[0044] Furthermore, through-via TSVs are provided on the second substrate 102. In the imaging device 1, a through-via TSV is provided for each pixel P, or for each of multiple pixels P. The through-via TSV penetrates the semiconductor layer 120 in the Z-axis direction. The upper end of the through-via TSV is connected to the wiring layer 22M1, and the lower end of the through-via TSV is connected to the wiring layer 21M3. Therefore, the wiring layer 22M1 and the wiring layer 21M3 are electrically connected by the through-via TSV. In addition, the wiring layer 21M3 is connected to the gate electrode of the amplification transistor AMP via via 21V. In the imaging device 1, a through-via TSV is arranged for each readout circuit 45, or for each of multiple readout circuits 45. The readout circuit 45 provided on the second substrate 102 is electrically connected to the wiring section 111 and the floating diffusion FD of the light-receiving layer 110 via the through-via TSV and the wiring section 122. Through-beam vias (TSVs) are made of materials such as tungsten (W), aluminum (Al), cobalt (Co), molybdenum (Mo), and ruthenium (Ru). However, through-beam vias (TSVs) may also be formed from other metallic materials.

[0045] [Detailed configuration of imaging device 1] Figure 4 is an enlarged schematic cross-sectional view of a portion of the second substrate 102 of the imaging device 1 shown in Figure 3. As shown in Figure 4, the first surface 12S1 of the semiconductor layer 120, which serves as the element formation surface, is provided with semiconductor elements such as an amplification transistor AMP and a selection transistor SEL. The semiconductor layer 120 is provided with a through hole 23K that penetrates the semiconductor layer 120 in the Z-axis direction. A through via TSV is inserted through the through hole 23K in the Z-axis direction. The upper end of the through via TSV is connected to an electrode pad 25, which is part of the wiring layer 22M1. The electrode pad 25 is exposed on the second bonding surface 102S2 and is bonded to a portion of the wiring layer 11M1, which serves as the first pad and is exposed on the first bonding surface 101S1. Note that the electrode pad 25 is a specific example corresponding to one embodiment of the "wiring" and "second pad" respectively in this disclosure.

[0046] The semiconductor layer 120 includes a semiconductor region 23p of a first conductivity type (e.g., p-type) and a well region 23nw of a second conductivity type (n-type) surrounding the through-via TSV. The well region 23nw includes a high-concentration region 23n+ in which the impurity concentration of n-type is higher than that of the surrounding area. Each of the amplification transistor AMP and the selection transistor SEL includes, for example, an n-type source-drain region S / D near the first surface 12S1. Furthermore, each of the amplification transistor AMP and the selection transistor SEL includes gate electrodes AMPG and SELG. The wiring layer 22M2 includes at least a portion of a connection portion 24 that electrically connects the high-concentration region 23n+ of the well region 23nw and the source-drain region S / D of the amplification transistor AMP.

[0047] More specifically, the connection section 24 includes a first pillar 24P1, a second pillar 24P2, and a beam 24B. The first pillar 24P1 is connected to the source-drain region S / D of the amplification transistor AMP and extends in the Z-axis direction from the source-drain region S / D of the amplification transistor AMP to at least the second surface 12S2, which is the back surface opposite to the first surface 12S1 of the semiconductor layer 120. The second pillar 24P2 is connected to the high-density region 23n+ of the well region 23nw and extends in the Z-axis direction from at least the second surface 12S2 of the semiconductor layer 23. The wiring layer 22M2 includes as part of the connection section 24 a beam 24B which extends along the second junction surface 102S2 to electrically connect the first pillar 24P1 and the second pillar 24P2. Therefore, in the second substrate 102 of the embodiment shown in Figure 4, the beam 24B of the connection portion 24 is provided on a different layer from the layer on which the wiring layer 22M1 is provided.

[0048] In the connection section 24, the constituent materials of beam 24B, the first pillar 24P1, and the second pillar P2 are the same. These constituent materials of beam 24B, the first pillar 24P1, and the second pillar P2 are similar to those of through-via TSVs, for example, tungsten (W), aluminum (Al), cobalt (Co), molybdenum (Mo), ruthenium (Ru), etc. However, beam 24B, the first pillar 24P1, and the second pillar P2 may be formed from other metallic materials.

[0049] Furthermore, the beam 24B, the first pillar P1, and the second pillar P2 in the connection portion 24 may be formed integrally. That is, the connection portion 24 may be formed collectively from the same type of material.

[0050] The second substrate 102 further includes insulating layers 23Z1, 23Z2, and 23Z3. Insulating layer 23Z1 is interposed in the gap between the first pillar P1 and the semiconductor region 23p surrounding the first pillar P1. Insulating layer 23Z2 is interposed in the gap between the second pillar P2 and the well region 23nw surrounding the second pillar P2. Furthermore, insulating layer 23Z3 is interposed in the gap between the through-via TSV and the well region 23nw surrounding the through-via TSV.

[0051] As previously mentioned, the second substrate 102 further has a wiring layer 21M3 on the side opposite to the second junction surface 102S2 when viewed from the semiconductor layer 120. The wiring layer 21M3 electrically connects the through-through via TSV and the gate electrode AMPG of the amplification transistor AMP. Note that the wiring layer 21M3 is a specific example corresponding to one embodiment of the "third wiring layer" of this disclosure.

[0052] Furthermore, the layout of the imaging device 1 along the XY plane is shown in Figures 5A and 5B. Figures 5A and 5B correspond to the horizontal cross-sections at positions Lv1 and Lv2 in the Z-axis direction shown in Figure 3, respectively. However, the example configuration of the stacked cross-section in Figure 3 and the example configuration of the horizontal cross-section shown in Figures 5A and 5B do not strictly match. Figures 5A and 5B show a state in which two pixel sharing units 40, each composed of four pixels Pa to Pd, are arranged in both the X-axis direction and the Y-axis direction.

[0053] As shown in Figure 5A, the photodiodes PD1 to PD4 for each pixel P are provided in the active region surrounded by the pixel separation section 51. Transfer transistors TR1 to TR4 are provided in the active region so as to overlap with the photodiodes PD1 to PD4 in the Z-axis direction. Contact sections FDC are positioned at the center of the four pixels Pa to Pd, and are connected to each of the floating diffusions FD1 to FD4.

[0054] As shown in Figure 5B, wiring layers 11M1 and 22M1 are provided on the junction surface between the first substrate 101 and the second substrate 102 so as to surround the active regions of the four pixels Pa to Pd. A through-via TSV is positioned in the center of the four pixels Pa to Pd. The through-via TSV is electrically connected to the contact portion FDC, also shown in Figure 5A, via wiring layers 11M1 and 22M1 (electrode pad 25). A well region 23nw is also provided surrounding the through-via TSV. Furthermore, a connection portion 24 (shown as beam 24B in Figure 5B) is provided that electrically connects the high-density region 23n+ (not shown in Figure 5B) of the well region 23nw to the source-drain region S / D (not shown in Figure 5B) of the amplification transistor AMP provided in the semiconductor region 23p.

[0055] [Manufacturing method of imaging device 1] Next, the manufacturing method of the imaging device 1 will be described. Here, the manufacturing method of the connection portion 24 and its surrounding area on the second substrate 102 will be explained with reference to Figures 6A to 6L.

[0056] First, as shown in Figure 6A, a laminated structure is prepared having a semiconductor layer 120 on which an amplifying transistor AMP and a selection transistor SEL are provided on the first surface 12S1, and a wiring section 121 that covers the first surface 12S1 and on which a wiring layer 21M3 and vias 21V are formed.

[0057] Next, as shown in Figure 6B, a photoresist pattern PR1 is selectively formed on the insulating layer 22Z. The photoresist pattern PR1 has openings K1 and K2 at the locations where the first pillar 24P1 and the second pillar 24P2 should be formed, respectively. After forming the photoresist pattern PR1, the insulating layer 22Z and the semiconductor region 23p of the semiconductor layer 120 are selectively removed sequentially by etching (e.g., RIE) using the photoresist pattern PR1 as a mask. This forms holes H1 and H2 that reach the high-concentration region 23n+ provided on the first surface 12S1.

[0058] Next, as shown in Figure 6C, after removing the photoresist pattern PR1, insulating layers 23Z1 and 23Z2 are formed along the inner walls of holes H1 and H2, respectively. A method for forming the insulating layers 23Z1 and 23Z2 can be, for example, ALD (atomic layer deposition). This is because even if holes H1 and H2 have a high aspect ratio, insulating layers 23Z1 and 23Z2 with high homogeneity in terms of film quality and thickness can be formed along the inner walls of holes H1 and H2.

[0059] Next, etching is performed to remove the insulating layers 23Z1 and 23Z2 deposited on the bottom surfaces of holes H1 and H2, respectively. This exposes the high-concentration region 23n+. After that, as shown in Figure 6D, a metal layer 24M is formed to fill holes H1 and H2 and cover the insulating layer 22Z. The metal layer 24M may be obtained, for example, by forming a barrier layer using at least one of Ta, Ti, W, N, and Co, followed by forming a conductive layer containing at least one of W, Co, Ru, Cu, Al, and Mo.

[0060] Next, as shown in Figure 6E, a photoresist pattern PR2 is selectively formed on the insulating layer 22Z. The photoresist pattern PR2 is formed only in the region where the connection portion 24 should be formed.

[0061] Next, an etching process (e.g., RIE) using the photoresist pattern PR2 as a mask is performed to selectively remove the insulating layer 22Z and a portion of the metal layer 24M in the areas not covered by the photoresist pattern PR2. This forms the beam 24B as the wiring layer 22M2, as shown in Figure 6F. As a result, the connection portion 24 is obtained.

[0062] Next, as shown in Figure 6G, holes H3 are formed at the locations where through-via TSVs are to be formed. Holes H3 can be formed, for example, by selectively forming a photoresist pattern having an opening at the locations where through-via TSVs are to be formed, and then using that photoresist pattern as a mask for etching (e.g., RIE). By forming holes H3, through-holes 23K are formed in the semiconductor region 23P of the semiconductor layer 120.

[0063] Next, as shown in Figure 6H, an impurity layer 23D is formed to cover the inner wall surface of hole H3 and the insulating layer 22Z. The impurity layer 23D is, for example, P2O5 containing the n-type impurity P (phosphorus). The impurity layer 23D is formed, for example, by the ALD method. Alternatively, an SiO2 film may be formed to cover the inner wall surface of hole H3, and then the P2O5 film may be formed. After that, the n-type impurity P (phosphorus) is diffused into the p-type semiconductor region 23p by heat treatment, and an n-type well region 23nw is formed around the inner wall surface of hole H3 in a self-aligned manner.

[0064] Next, as shown in Figure 6I, the impurity layer 23D is removed by wet etching. Then, as shown in Figure 6J, an insulating layer 22Z3 is formed to cover the inner wall surface of the hole H3 and the insulating layer 22Z. One example of a method for forming the insulating layer 23Z3 is the ALD method.

[0065] Next, as shown in Figure 6K, etching is performed to sequentially remove the insulating layer 23Z3 deposited on the bottom surface of hole H3 and the insulating layer 21Z located below hole H3. This exposes the wiring layer 21M3.

[0066] Subsequently, as shown in Figure 6L, a through-via TSV is formed by providing conductive material to fill hole H3 using a CVD method or the like.

[0067] Finally, the second substrate 102 is completed by forming the wiring layer 22M1.

[0068] [Effects of Imaging Device 1] In the imaging device 1 of this embodiment, wiring layers 22M1 and 22M2 are provided on the second substrate 102 on the side opposite to the first surface 12S1, which is the element formation surface, when viewed from the semiconductor layer 120. This reduces congestion of the wiring layers M on the first surface 12S1 side. Consequently, the degree of freedom in the planar layout of each wiring layer M is improved, and high integration of the readout circuit 45 and other components becomes easier. Furthermore, in the semiconductor layer 120, the electrical connection between the high-density region 23n+ of the well region 23nw surrounding the through-through via TSV and the amplification transistor AMP can be made via the beam 23B contained in the wiring layer 22M2. As a result, parasitic capacitance between the through-through via TSV and the well region 23nw surrounding the through-through via TSV can be reduced due to the Miller effect. Consequently, in the imaging device 1, the photoelectric conversion efficiency of the photodiodes PD1 to PD4 is improved, and high photodetection performance is obtained. Therefore, according to the imaging device 1 of this embodiment, it is possible to achieve both improved imaging performance and high integration. In particular, in the imaging device 1, the first pillar 24P1 and the second pillar 24P2, which extend in the Z-axis direction, are used to electrically connect the high-density region 23n+ around the through-via TSV with the source-drain region S / D of the amplification transistor AMP. This prevents an increase in the occupied area in the XY plane, which is advantageous for high integration.

[0069] In particular, in the imaging device 1, an insulating layer 23Z1 is provided around the first pillar 24P1, so it is not necessary to provide a well region 23nw around the source-drain region S / D of the amplification transistor AMP. For this reason, the manufacturing process of the second substrate 102 is simpler compared to, for example, the second substrate 102-1 and the second substrate 102-2, which are described later as first and second modifications.

[0070] Furthermore, in the imaging device 1, the connection section 24 has a structure in which the first pillar 24P1, the second pillar 24P2, and the beam 24B are integrated. This reduces the number of manufacturing steps and allows for higher accuracy in the positioning and dimensional precision of the connection section 24. Therefore, compared to, for example, the second substrate 102-3 as a third modified example described later, the parasitic capacitance formed between the through-via TSV and the connection section 24 can be reduced.

[0071] Modifications 1 to 6 of this disclosure are described below. In each of the following modifications, components common to the above embodiment are denoted by the same reference numerals.

[0072] <2. Variant> (2-1. First variation) Figure 7A shows an example of the cross-sectional configuration of the second substrate 102-1 as a first modified example of the present disclosure, and corresponds to Figure 4 of the above embodiment. In the second substrate 102 of the above embodiment, an insulating layer 23Z1 is provided around the first pillar 24P1 and an insulating layer 23Z2 is provided around the second pillar 24P2. However, in the present disclosure, as shown in the second substrate 102-1, a well region 23nw may be provided around each of the first pillar 24P1 and the second pillar 24P2 so as to be in contact with each of the first pillar 24P1 and the second pillar 24P2.

[0073] According to the second substrate 102-1 of this modified example, compared to the second substrate 102 of the above embodiment, the contact between the first pillar 24P1 and the second pillar 24P2 and the well region 23nw makes it possible to reduce the electrical resistance between the high-concentration region 23n+ around the through-via TSV and the source-drain region S / D of the amplification transistor AMP.

[0074] (2-2. Second variation) Figure 7B shows an example of the cross-sectional configuration of the second substrate 102-2 as a second modification of the present disclosure, and corresponds to Figure 4 of the above embodiment. In the second substrate 102-2 of this modification, a high-concentration region 23n+ is provided on the second surface 12S2. Specifically, the first pillar 24P1 is connected to the high-concentration region 23n+ which is connected to the well region 23nw connected to the source-drain region S / D of the amplification transistor AMP. The second pillar 24P2 is connected to the high-concentration region 23n+ provided on the second surface 12S2 of the well region 23nw surrounding the through-via TSV.

[0075] In the second substrate 102-2 of this modified example, there is no need to drill holes in the semiconductor layer 120 to provide the first pillar 24P1 and the second pillar 24P2, thus simplifying the manufacturing process. As a result, variations in the characteristics of multiple pixels P4 and variations in the characteristics of multiple pixel sharing units 40 can be reduced.

[0076] (2-3~2-5. Variations of the 3rd to 5th variations) Figures 7C to 7E show examples of cross-sectional configurations of the second substrates 102-3 to 102-5 as third to fifth modifications of the present disclosure, and correspond to Figure 4 of the above embodiment. In the second substrates 102-3 to 102-5 as third to fifth modifications, the beam 24B of the connection portion 24 is provided as a wiring layer 22M1 instead of a wiring layer 22M2. The constituent material of the beam 24B is different from the constituent material of the first pillar 24P1 and the constituent material of the second pillar 24P2, respectively. The electrode pad 25 included in the wiring layer 22M1 is a wiring that is electrically connected to the upper end in the Z-axis direction of the through-via TSV and is located at the same level as the beam 24B. The constituent material of the beam 24B may be the same as, for example, the constituent material of the electrode pad 25. Except for these points, the configurations of the second substrates 102-3 to 102-5 are substantially the same as the configurations of the second substrates 102, 102-1, and 102-2, respectively.

[0077] According to the second substrates 102-3 to 102-5, which are the third to fifth modifications of this disclosure, the electrical resistance of the connection portion 24 can be reduced compared to the second substrates 102, 102-1, and 102-2, respectively. This is because a low-resistance material such as copper (Cu) can be used as the constituent material of the beam 24B, and the thickness (cross-sectional area) of the beam 24B can be made relatively large.

[0078] (2-6. Sixth variation) Figure 8 shows an example of the configuration of a stacked cross-section of the imaging device 1A as a sixth modification of the present disclosure, and corresponds to Figure 3 of the above embodiment. In the imaging device 1A as the sixth modification, the second substrate 102 further has a wiring layer 22M3 located between the wiring layer 22M2 and the second bonding surface 102S2. Except for this point, the configuration of the imaging device 1A is substantially the same as the configuration of the imaging device 1 of the above embodiment. According to the imaging device 1A of this modification, since a wiring layer 22M3 is further provided on the second surface 12S2 side opposite to the element formation surface of the semiconductor layer 120, in addition to the wiring layers 22M1 and 22M2, congestion of the wiring layers M on the first surface 12S1 side can be further alleviated. Therefore, the degree of freedom of the planar layout of each wiring layer M is further improved, and high integration of the readout circuit 45 and the like becomes easier.

[0079] (2-7. Seventh variation) Figure 9 shows an example of the configuration of a stacked cross-section of the imaging device 1B as a seventh modification of the present disclosure, and corresponds to Figure 3 of the above embodiment. The imaging device 1B as the seventh modification further includes a fourth substrate 104. That is, the imaging device 1B has a structure in which four substrates, the first substrate 101, the second substrate 102, the third substrate 103, and the fourth substrate 104, are stacked in order. The fourth substrate 104, like the third substrate 103, is a logic substrate on which logic circuits are provided. For example, an analog-to-digital (AD) conversion circuit can be placed on the third substrate 103, and an ISP (Image Signal Processing) / DSP (Digital Signal Processing) circuit can be placed on the fourth substrate 104. The circuits provided on the third substrate 103 and the circuits provided on the fourth substrate 104 may be electrically connected, for example, via a through-through via TSV2. In that case, the thickness of the through-through via TSV2 can be made larger than the thickness of the through-through via TSV provided on the second substrate 102.

[0080] In imaging device 1B, the third substrate 103 has a bonding surface 103S2 on the side opposite to the second substrate 102. The bonding surface 103S2 is a specific example of the "third bonding surface" as one aspect of this disclosure. The bonding surface 103S2 is bonded to the bonding surface 104S1 (described later) of the fourth substrate 104. In imaging device 1B, the third substrate 103 further has a wiring section 132 in addition to the semiconductor layer 130 and the wiring section 131. The wiring section 132 is located on the side opposite to the wiring section 131 when viewed from the semiconductor layer 130, and is provided on the second surface 13S2 of the semiconductor layer 130. Of the wiring section 132, the surface opposite to the second surface 13S2 of the semiconductor layer 130 is the bonding surface 103S2. The wiring section 132 has a configuration in which one or more wiring layers are laminated with an interlayer insulating layer (interlayer insulating film) in between. Specifically, the wiring section 132 has a structure in which wiring layers 32M1 and 32M2, which are stacked sequentially from the side of the joint surface 103S2, are embedded in the interlayer insulating layer 32Z. Some of the wiring layers 32M1 are third pads exposed to the joint surface 103S2. The wiring layer 32M1 as the third pad is joined to the wiring layer 41M1 as the fourth pad, which will be described later, to form a second joint terminal pair.

[0081] The third substrate 103 is provided with through-vias TSV2. The through-vias TSV2 penetrate the semiconductor layer 130 in the Z-axis direction. The upper end of the through-vias TSV2 is connected to the wiring layer 31M5, and the lower end of the through-vias TSV2 is connected to the wiring layer 32M2. Therefore, the wiring layer 31M5 and the wiring layer 32M2 are electrically connected by the through-vias TSV2. The through-vias TSV2 are made of, for example, tungsten (W), aluminum (Al), cobalt (Co), molybdenum (Mo), ruthenium (Ru), etc. However, the through-vias TSV2 may be formed from other metallic materials.

[0082] In the imaging device 1B, the fourth substrate 104 has a bonding surface 104S1 that is bonded to the bonding surface 103S2 of the third substrate 103. The bonding surface 104S1 is a specific example of the "fourth bonding surface" as an embodiment of the present disclosure. The fourth substrate 104 has a semiconductor layer 140 and a wiring portion 141. The semiconductor layer 140 has a first surface 14S1 and a second surface 14S2. Both the first surface 14S1 and the second surface 14S2 extend along the XY plane. The first surface 14S1 is an element formation surface on which semiconductor elements such as transistors are provided. For example, the gate electrode, gate oxide film, source and drain regions of a transistor are provided on the first surface 14S1. Of the wiring portion 141, the surface of the semiconductor layer 140 opposite to the first surface 14S1 is the bonding surface 104S1. The wiring section 141 has a configuration in which one or more wiring layers are laminated with an interlayer insulating layer (interlayer insulating film) in between. Specifically, the wiring section 141 has a structure in which wiring layers 41M1, 41M2, 41M3, 41M4, and 41M5, which are laminated in order from the side of the joint surface 104S1, are embedded in the interlayer insulating layer 41Z. Some of the wiring layers 41M1 are electrode pads exposed on the joint surface 104S1 (for convenience, referred to as fourth electrode pads). The wiring layers 41M1 as electrode pads are joined to the wiring layers 32M1 as electrode pads to form a joint terminal pair. The arrangement pitch of the multiple wiring layers 41M1 as fourth pads is preferably wider than the arrangement pitch of the multiple wiring layers 11M1 as first pads exposed on the joint surface 101S1 and the arrangement pitch of the multiple wiring layers 22M1 as second pads exposed on the joint surface 102S2. In other words, the arrangement pitch of the multiple second joint terminal pairs formed by the wiring layer 41M1 and the wiring layer 32M1 is greater than the arrangement pitch of the multiple first joint terminal pairs formed by the wiring layer 11M1 and the wiring layer 22M1, respectively.

[0083] The third substrate 103 and the fourth substrate 104 may be joined to each other by a so-called hybrid junction. That is, the wiring layer 32M1, which serves as an electrode exposed on the junction surface 103S2, and the wiring layer 41M1, which serves as an electrode exposed on the junction surface 104S1, are joined, and the interlayer insulating layer 32Z, which serves as an electrode exposed on the junction surface 103S2, and the interlayer insulating layer 41Z, which serves as an electrode exposed on the junction surface 104S1, are joined. When both the wiring layer 32M1 and the wiring layer 41M1 are made of copper (Cu), the joining of the wiring layer 32M1 and the wiring layer 41M1 is sometimes called a Cu-Cu junction.

[0084] Thus, in the imaging device 1B, the logic board is divided into two parts and stacked, which reduces the area occupied by the third board 103 in the XY plane compared to the imaging device 1. Therefore, the imaging device 1B is more suitable for achieving both high resolution and high functionality, as well as miniaturization.

[0085] The imaging device 1B can be manufactured, for example, as follows. First, as shown in Figure 10A, the bonding surface 102S1 of the second substrate 102 before the formation of the through-via TSV and the bonding surface 103S1 of the third substrate 103 before the formation of the through-via TSV2 are joined by hybrid bonding. At this stage, the wiring section 132 is not provided.

[0086] Next, as shown in Figure 10B, through holes are formed at predetermined positions in the semiconductor layer 130, and then an interlayer insulating layer 32Z is ​​formed to fill the through holes and cover the second surface 13S2 of the semiconductor layer 130. Furthermore, through vias TSV2 are formed so as to pass through the through holes formed in the semiconductor layer 130.

[0087] Next, as shown in Figure 10C, a wiring section 132 is formed on the second surface 13S2 of the semiconductor layer 130, including wiring layers 32M1 and 32M2 embedded in the interlayer insulating layer 32Z. At this time, a portion of the wiring layer 32M2 is made to be in contact with the lower end of the through-via TSV2. Furthermore, after preparing the fourth substrate 104, the bonding surface 103S2 of the third substrate 103 and the bonding surface 104S1 of the fourth substrate 104 are bonded by hybrid bonding.

[0088] Next, as shown in Figure 10D, through holes are formed at predetermined positions in the semiconductor layer 120, and then an interlayer insulating layer 22Z is ​​formed to fill the through holes and cover the second surface 12S2 of the semiconductor layer 120. Furthermore, through-via TSVs are formed so as to pass through the through holes formed in the semiconductor layer 120.

[0089] Next, as shown in Figure 10E, a wiring section 122 is formed on the second surface 12S2 of the semiconductor layer 120, including wiring layers 22M1 to 22M3 embedded in the interlayer insulating layer 22Z. At this time, some of the wiring layers 22M3 are made to be in contact with the upper end of the through-via TSV.

[0090] Furthermore, after preparing the first substrate 101, the bonding surface 102S2 of the second substrate 102 and the bonding surface 101S1 of the first substrate 101 are bonded by hybrid bonding. After that, the imaging device 1B is completed by forming a color filter CF, an on-chip lens OCL, and the like.

[0091] <3. Application Examples> (Application Example 1) The above-mentioned imaging device 1 can be applied to any type of electronic device equipped with an imaging function, such as camera systems like digital still cameras and video cameras, or mobile phones with imaging capabilities. Figure 11 shows a schematic configuration of the electronic device 1000.

[0092] The electronic device 1000 includes, for example, a lens group 1001, an imaging device 1, a DSP (Digital Signal Processor) circuit 1002, a frame memory 1003, a display unit 1004, a recording unit 1005, an operation unit 1006, and a power supply unit 1007, all of which are interconnected via a bus line 1008.

[0093] The lens group 1001 captures incident light (image light) from the subject and forms an image on the imaging surface of the imaging device 1. The imaging device 1 converts the amount of incident light formed on the imaging surface by the lens group 1001 into an electrical signal on a pixel-by-pixel basis and supplies it as a pixel signal to the DSP circuit 1002.

[0094] The DSP circuit 1002 is a signal processing circuit that processes signals supplied from the imaging device 1. The DSP circuit 1002 outputs image data obtained by processing the signals from the imaging device 1. The frame memory 1003 temporarily holds the image data processed by the DSP circuit 1002 on a frame-by-frame basis.

[0095] The display unit 1004 consists of a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and records the video or still image data captured by the imaging device 1 onto a recording medium such as a semiconductor memory or a hard disk.

[0096] The operation unit 1006 outputs operation signals for various functions possessed by the electronic device 1000 in accordance with user operations. The power supply unit 1007 appropriately supplies various power sources to the DSP circuit 1002, frame memory 1003, display unit 1004, recording unit 1005, and operation unit 1006.

[0097] (Application Example 2) Figure 12A schematically shows an example of the overall configuration of a photodetection system 2000 equipped with an imaging device 1. Figure 12B shows an example of the circuit configuration of the photodetection system 2000. The photodetection system 2000 includes a light-emitting device 2001 as a light source that emits infrared light L2, and a photodetection device 2002 as a light-receiving unit having a photoelectric conversion element. The imaging device 1 described above can be used as the photodetection device 2002. The photodetection system 2000 may further include a system control unit 2003, a light source drive unit 2004, a sensor control unit 2005, a light source side optical system 2006, and a camera side optical system 2007.

[0098] The photodetector 2002 can detect light L1 and light L2. Light L1 is light reflected from ambient light from the outside by the subject (object to be measured) 2100 (Figure 12A). Light L2 is light that has been emitted by the light-emitting device 2001 and then reflected by the subject 2100. Light L1 is, for example, visible light, and light L2 is, for example, infrared light. Light L1 is detectable in the photoelectric conversion unit of the photodetector 2002, and light L2 is detectable in the photoelectric conversion region of the photodetector 2002. Image information of the subject 2100 can be obtained from light L1, and distance information between the subject 2100 and the photodetector system 2000 can be obtained from light L2. The photodetector system 2000 can be mounted on, for example, electronic devices such as smartphones or mobile devices such as cars. The light-emitting device 2001 can be, for example, a semiconductor laser, a surface-emitting semiconductor laser, or a vertical-cavity surface-emitting laser (VCSEL). The detection method for light L2 emitted from the light-emitting device 2001 by the photodetector 2002 can, for example, be the iTOF method, but is not limited to this. In the iTOF method, the photoelectric conversion unit can measure the distance to the subject 2100 by, for example, the time-of-flight (TOF). The detection method for light L2 emitted from the light-emitting device 2001 by the photodetector 2002 can also be, for example, the structured light method or the stereo vision method. For example, in the structured light method, the distance between the photodetector 2000 and the subject 2100 can be measured by projecting a predetermined pattern of light onto the subject 2100 and analyzing the degree of distortion of the pattern. In the stereo vision method, for example, the distance between the photodetector 2000 and the subject can be measured by using two or more cameras to acquire two or more images of the subject 2100 from two or more different viewpoints. The light-emitting device 2001 and the photodetector 2002 can be synchronized and controlled by the system control unit 2003.

[0099] <4. Application Examples> (Examples of application to endoscopic surgical systems) The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology disclosed herein may be applied to an endoscopic surgical system.

[0100] Figure 13 shows an example of a schematic configuration of an endoscopic surgical system to which the technology described herein (the technology) may be applied.

[0101] Figure 13 illustrates a surgeon (physician) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgical system 11000. As shown in the figure, the endoscopic surgical system 11000 consists of an endoscope 11100, other surgical instruments 11110 such as an insufflation tube 11111 and an energy treatment device 11112, a support arm device 11120 for supporting the endoscope 11100, and a cart 11200 equipped with various devices for endoscopic surgery.

[0102] The endoscope 11100 consists of a barrel 11101, the tip of which is inserted into the body cavity of the patient 11132 for a predetermined length, and a camera head 11102 connected to the base end of the barrel 11101. In the illustrated example, the endoscope 11100 is shown as a so-called rigid endoscope having a rigid barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible endoscope having a flexible barrel.

[0103] An opening into which an objective lens is fitted is provided at the tip of the endoscope tube 11101. A light source device 11203 is connected to the endoscope 11100, and the light generated by the light source device 11203 is guided to the tip of the endoscope tube by a light guide extending inside the endoscope tube 11101, and is irradiated through the objective lens towards the object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a straight-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0104] The camera head 11102 contains an optical system and an image sensor. Reflected light from the object being observed (observation light) is focused onto the image sensor by the optical system. The image sensor converts the observation light into electrical signals, generating an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. This image signal is transmitted as RAW data to the camera control unit (CCU) 11201.

[0105] The CCU11201 consists of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and other components, and comprehensively controls the operation of the endoscope 11100 and the display device 11202. Furthermore, the CCU11201 receives image signals from the camera head 11102 and performs various image processing operations on these image signals, such as development processing (demosaic processing), to display the image based on those image signals.

[0106] The display device 11202 displays an image based on an image signal that has been processed by the CCU 11201, under control from the CCU 11201.

[0107] The light source device 11203 consists of a light source such as an LED (light-emitting diode) and supplies illumination light to the endoscope 11100 when photographing the surgical area, etc.

[0108] The input device 11204 is an input interface for the endoscopic surgical system 11000. The user can input various information and instructions to the endoscopic surgical system 11000 via the input device 11204. For example, the user can input instructions to change the imaging conditions (type of light, magnification, focal length, etc.) of the endoscope 11100.

[0109] The treatment instrument control device 11205 controls the drive of the energy treatment instrument 11112 for purposes such as tissue cauterization, incision, or vascular sealing. The insufflation device 11206 delivers gas into the patient's body cavity via the insufflation tube 11111 to inflate the body cavity of the patient 11132 for the purpose of securing a field of view by the endoscope 11100 and securing the operator's working space. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various formats such as text, images, or graphs.

[0110] The light source device 11203, which supplies illumination light to the endoscope 11100 when photographing the surgical area, can be configured as a white light source consisting of, for example, an LED, a laser light source, or a combination thereof. When the white light source is configured as a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so the white balance of the captured image can be adjusted in the light source device 11203. In this case, it is also possible to time-divisionally capture images corresponding to each of the RGB light sources by irradiating the observation target with laser light from each RGB laser light source and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter on the image sensor.

[0111] Furthermore, the light source device 11203 may be controlled to change the intensity of the light it outputs at predetermined time intervals. By controlling the drive of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity, images can be acquired in time-division order, and these images can be combined to generate high dynamic range images without so-called black crushing and white clipping.

[0112] Furthermore, the light source device 11203 may be configured to supply light in a predetermined wavelength range corresponding to special light observation. In special light observation, for example, so-called narrow-band imaging is performed, in which a predetermined tissue such as blood vessels on the surface of the mucosa is imaged with high contrast by irradiating with narrow-band light compared to the irradiation light used in normal observation (i.e., white light), utilizing the wavelength dependence of light absorption in body tissue. Alternatively, fluorescence observation may be performed in special light observation, in which an image is obtained from fluorescence generated by irradiation with excitation light. In fluorescence observation, fluorescence can be obtained by irradiating body tissue with excitation light and observing the fluorescence from the body tissue (autofluorescence observation), or by locally injecting a reagent such as indocyanine green (ICG) into body tissue and irradiating the body tissue with excitation light corresponding to the fluorescence wavelength of the reagent to obtain a fluorescence image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0113] Figure 14 is a block diagram showing an example of the functional configuration of the camera head 11102 and CCU 11201 shown in Figure 13.

[0114] The camera head 11102 includes a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with one another.

[0115] The lens unit 11401 is an optical system provided at the connection point with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and then incident on the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses, including a zoom lens and a focus lens.

[0116] The imaging unit 11402 may consist of one image sensor (a so-called single-chip system) or multiple image sensors (a so-called multi-chip system). If the imaging unit 11402 is configured as a multi-chip system, for example, each image sensor may generate image signals corresponding to RGB, and these signals may be combined to obtain a color image. Alternatively, the imaging unit 11402 may be configured to have a pair of image sensors for acquiring image signals for the right eye and left eye, respectively, corresponding to 3D (dimensional) display. By performing 3D display, the surgeon 11131 can more accurately grasp the depth of the biological tissue in the surgical area. In addition, if the imaging unit 11402 is configured as a multi-chip system, multiple lens units 11401 may be provided corresponding to each image sensor.

[0117] Furthermore, the imaging unit 11402 does not necessarily have to be located in the camera head 11102. For example, the imaging unit 11402 may be located inside the lens barrel 11101, directly behind the objective lens.

[0118] The drive unit 11403 is composed of actuators and, under control from the camera head control unit 11405, moves the zoom lens and focus lens of the lens unit 11401 along the optical axis by a predetermined distance. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted as appropriate.

[0119] The communication unit 11404 consists of communication devices for sending and receiving various types of information with the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 as RAW data to the CCU 11201 via the transmission cable 11400.

[0120] Furthermore, the communication unit 11404 receives control signals from the CCU 11201 to control the drive of the camera head 11102 and supplies them to the camera head control unit 11405. These control signals include information regarding imaging conditions, such as information to specify the frame rate of the captured image, information to specify the exposure value at the time of imaging, and / or information to specify the magnification and focus of the captured image.

[0121] The imaging conditions such as frame rate, exposure value, magnification, and focus may be specified by the user as appropriate, or they may be automatically set by the control unit 11413 of the CCU11201 based on the acquired image signal. In the latter case, the endoscope 11100 will be equipped with so-called AE (Auto Exposure), AF (Auto Focus), and AWB (Auto White Balance) functions.

[0122] The camera head control unit 11405 controls the drive of the camera head 11102 based on the control signal received from the CCU 11201 via the communication unit 11404.

[0123] The communication unit 11411 consists of a communication device for sending and receiving various types of information with the camera head 11102. The communication unit 11411 receives image signals transmitted from the camera head 11102 via the transmission cable 11400.

[0124] Furthermore, the communication unit 11411 transmits control signals to the camera head 11102 to control the driving of the camera head 11102. Image signals and control signals can be transmitted via telecommunications, optical communications, etc.

[0125] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data transmitted from the camera head 11102.

[0126] The control unit 11413 performs various controls related to imaging the surgical area, etc., by the endoscope 11100, and the display of the images obtained from imaging the surgical area, etc. For example, the control unit 11413 generates control signals to control the driving of the camera head 11102.

[0127] Furthermore, the control unit 11413 displays the captured image showing the surgical area on the display device 11202 based on the image signal processed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical instruments such as forceps, specific biological sites, bleeding, mist when using the energy treatment device 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When the control unit 11413 displays the captured image on the display device 11202, it may use the recognition results to superimpose various surgical support information onto the image of the surgical area. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced, and the surgeon 11131 can proceed with the surgery with confidence.

[0128] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable compatible with electrical signal communication, an optical fiber compatible with optical communication, or a composite cable thereof.

[0129] In the illustrated example, communication was performed via a wired connection using the transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may be performed wirelessly.

[0130] The above describes an example of an endoscopic surgical system to which the technology described herein may be applied. The technology described herein can be applied to the imaging unit 11402 of the configuration described above. By applying the technology described herein to the imaging unit 11402, the detection accuracy is improved.

[0131] While an endoscopic surgical system has been described here as an example, the technology described herein may also be applied to other systems, such as microsurgical systems.

[0132] (Examples of applications to mobile devices) The technology disclosed herein can be applied to a variety of products. For example, the technology disclosed herein may be implemented as a device mounted on any type of mobile vehicle, such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, robots, construction machinery, or agricultural machinery (tractors).

[0133] Figure 15 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0134] The vehicle control system 12000 comprises multiple electronic control units connected via a communication network 12001. In the example shown in Figure 15, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0135] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0136] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0137] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0138] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0139] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0140] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking system based on information from inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0141] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0142] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0143] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example in Figure 15, the output devices are exemplified as an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0144] Figure 16 shows an example of the installation position of the imaging unit 12031.

[0145] In Figure 16, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0146] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0147] Figure 16 shows an example of the imaging range of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0148] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0149] For example, the microcomputer 12051, based on distance information obtained from imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to vehicle 12100). In particular, it can extract the nearest object on the vehicle 12100's path that is traveling in approximately the same direction as vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, where the vehicle drives autonomously without driver intervention, can be performed.

[0150] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, heavy vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0151] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0152] The above describes an example of a mobile object control system to which the technology of this disclosure may be applied. The technology of this disclosure can be applied to the imaging unit 12031 of the configuration described above. Specifically, the imaging devices according to the above embodiments and their modified examples 1 to 7 can be applied to the imaging unit 12031. By applying the technology of this disclosure to the imaging unit 12031, high-definition images with low noise can be obtained, so that high-precision control using the captured images can be performed in the mobile object control system.

[0153] The present disclosure has been described above with reference to embodiments and their modifications 1 to 6, application examples, and application examples. However, the present disclosure is not limited to the above embodiments, and various modifications are possible. The effects described herein are merely illustrative. The effects of the present disclosure are not limited to those described herein. The present disclosure may have effects other than those described herein.

[0154] Furthermore, for example, this disclosure can take the following configuration. In a photodetector having the following configuration, a wiring layer is provided on the second substrate on the side opposite to the element formation surface when viewed from the semiconductor layer. This reduces wiring congestion on the element formation surface side. Also, the electrical connection between the semiconductor element and the portion of the semiconductor layer surrounding the through-via, which is connected to the charge storage portion and penetrates the semiconductor layer, can be made via the first wiring layer. As a result, parasitic capacitance between the through-via and the semiconductor surrounding the through-via can be reduced due to the Miller effect. Consequently, the photoelectric conversion efficiency is improved. Thus, it is possible to achieve both improved performance and high integration. <1> A first substrate having a photoelectric conversion unit that generates electric charge by photoelectric conversion of light, a charge storage unit that stores the electric charge, and a first junction surface, A second substrate having an element formation surface on which a semiconductor element included in a readout circuit that outputs a first signal based on the charge is provided, a semiconductor layer including a through hole extending in a first direction from the element formation surface, a through via inserted through the through hole and electrically connected to the charge storage portion, a second junction surface located on the opposite side from the element formation surface as seen from the semiconductor layer and bonded to the first junction surface, and a first wiring layer located between the semiconductor layer and the second junction surface. Equipped with Light detection device. <2> The semiconductor layer includes a semiconductor region of a first conductivity type and a well region of a second conductivity type different from the first conductivity type that surrounds the through via. The well region includes a high-concentration region where the concentration of the second conductivity type impurity is higher than that of the surrounding area. The semiconductor element is provided in the semiconductor region and includes the source-drain region of the second conductivity type. The first wiring layer includes at least a portion of a connection that electrically connects the high-concentration region of the well region and the source-drain region of the semiconductor element. the above <1> The described light detection device. <3> The connection portion includes a first pillar that is connected to the source and drain regions of the semiconductor element and extends in the first direction from the source and drain regions of the semiconductor element to at least the back surface of the semiconductor layer opposite to the element formation surface. the above <2> The described light detection device. <4> The connecting portion further includes a second pillar that is connected to the high-concentration region of the well region and extends in the first direction from the high-concentration region of the well region to at least the back surface of the semiconductor layer. the above <3> The described light detection device. <5> The first wiring layer includes, as part of the connection, a beam extending along the second joint surface to electrically connect the first pillar and the second pillar. the above <4> The described light detection device. <6> The constituent materials of the beam, the first pillar, and the second pillar are the same. the above <5> The described light detection device. <7> The beam, the first pillar, and the second pillar are integrally formed. the above <5> or <6> The described light detection device. <8> The constituent material of the beam is different from the constituent material of the first pillar and the constituent material of the second pillar, respectively. the above <5> The described light detection device. <9> The first wiring layer further includes wiring that is electrically connected to the first direction end of the through via and is located at the same level as the beam. the above <8> The described light detection device. <10> The second substrate is A first insulating layer interposed between the first pillar and the semiconductor region, A second insulating layer interposed between the second pillar and the well region It further possesses the above <4> from <9> A light detection device as described in any one of the following. <11> The first substrate further has a first pad that is electrically connected to the charge storage unit and exposed on the first bonding surface, The second substrate is electrically connected to the through-via and further has a second pad exposed on the second bonding surface and bonded to the first pad. the above <1> from <10> A light detection device as described in any one of the following. <12> The second substrate further comprises a second wiring layer located between the first wiring layer and the second bonding surface. the above <1> from <11> A light detection device as described in any one of the following. <13> The second substrate further has a third wiring layer on the side opposite to the second junction surface when viewed from the semiconductor layer, The third wiring layer electrically connects the through-via and the gate electrode of the semiconductor element. the above <2> The described light detection device. <14> Equipped with a light detection device, The aforementioned light detection device is A first substrate having a photoelectric conversion unit that generates electric charge by photoelectric conversion of light, a charge storage unit that stores the electric charge, and a first junction surface, A second substrate having an element formation surface on which a semiconductor element included in a readout circuit that outputs a first signal based on the charge is provided, a semiconductor layer including a through hole extending in a first direction from the element formation surface, a through via inserted through the through hole and electrically connected to the charge storage portion, a second junction surface located on the opposite side from the element formation surface as seen from the semiconductor layer and bonded to the first junction surface, and a first wiring layer located between the semiconductor layer and the second junction surface. Equipped with electronic equipment. <15> The system further comprises a third substrate provided on the side opposite to the first substrate as viewed from the second substrate, and having a first signal processing unit that is electrically connected to the semiconductor element. the above <1> from <13> A light detection device as described in any one of the following. <16> The system further comprises a fourth board having a second signal processing unit that is electrically connected to the first signal processing unit, and is located on the side opposite to the second board when viewed from the third board. The third substrate further has a second through-via, The second through via electrically connects the first signal processing unit and the second signal processing unit. the above <15> The described light detection device. <17> The diameter of the second through via is greater than the diameter of the first through via. the above <16> The described light detection device. <18> The third substrate has a third bonding surface, The fourth substrate has a fourth bonding surface that is bonded to the third bonding surface, The arrangement pitch of the multiple second connector terminal pairs, formed by joining multiple third pads exposed on the third connector surface and multiple fourth pads exposed on the fourth connector surface, is greater than the arrangement pitch of the multiple first connector terminal pairs, formed by joining multiple first pads exposed on the first connector surface and multiple second pads exposed on the second connector surface. the above <16> or <17> The described light detection device. [Explanation of Symbols]

[0155] 1...Imaging device, 23p...Semiconductor region, 23nw...Well region, 23n+...High-density region, 24...Connection section, 24B...Beam, 24P1...First pillar, 24P2...Second pillar, 40...Pixel sharing unit, 45...Readout circuit, 101...First substrate, 102...Second substrate, 103...Third substrate, 110...Photodetector layer, 120,130...Semiconductor layer, 111,121,122,131...Wiring section, 101S1,102S1,102S2,103S1...Bonding surface, 210...Input section, 2 20... Row drive unit, 230... Timing control unit, 240... Pixel array unit, 250... Column signal processing unit, 260... Image signal processing unit, 270... Output unit 270, TR (TR1~TR4)... Transfer transistor, TG... Transfer gate, RST... Reset transistor, AMP... Amplifier transistor, SEL... Selection transistor, FDG... FD transfer transistor, PD... Photodiode, FD... Floating diffusion, P (Pa~Pd)... Pixel, TSV... Through via.

Claims

1. A first substrate having a photoelectric conversion unit that generates electric charge by photoelectric conversion of light, a charge storage unit that stores the electric charge, and a first bonding surface, A second substrate having an element formation surface on which a semiconductor element included in a readout circuit that outputs a first signal based on the charge is provided, a semiconductor layer including a through hole extending in a first direction from the element formation surface, a through via inserted through the through hole and electrically connected to the charge storage portion, a second bonding surface located on the opposite side from the element formation surface as seen from the semiconductor layer and bonded to the first bonding surface, and a first wiring layer located between the semiconductor layer and the second bonding surface. Equipped with Light detection device.

2. The semiconductor layer includes a semiconductor region of a first conductivity type and a well region of a second conductivity type different from the first conductivity type that surrounds the through via. The well region includes a high-concentration region where the impurity concentration of the second conductivity type is higher than that of the surrounding area. The semiconductor element is provided in the semiconductor region and includes the source-drain region of the second conductivity type. The first wiring layer includes at least a portion of a connection that electrically connects the high-concentration region of the well region and the source-drain region of the semiconductor element. The light detection device according to claim 1.

3. The connection portion is connected to the source and drain regions of the semiconductor element and includes a first pillar that extends in the first direction from the source and drain regions of the semiconductor element to at least the back surface of the semiconductor layer opposite to the element formation surface. The light detection device according to claim 2.

4. The connecting portion further includes a second pillar that is connected to the high-concentration region of the well region and extends in the first direction from the high-concentration region of the well region to at least the back surface of the semiconductor layer. The photodetector according to claim 3.

5. The first wiring layer includes, as part of the connection portion, a beam extending along the second joint surface to electrically connect the first pillar and the second pillar. The photodetector according to claim 4.

6. The constituent materials of the beam, the first pillar, and the second pillar are the same. The photodetector according to claim 5.

7. The beam, the first pillar, and the second pillar are formed integrally. The photodetector according to claim 5.

8. The constituent material of the beam is different from the constituent material of the first pillar and the constituent material of the second pillar, respectively. The photodetector according to claim 5.

9. The first wiring layer further includes wiring that is electrically connected to the first direction end of the through via and is located at the same level as the beam. The light detection device according to claim 8.

10. The aforementioned second substrate is A first insulating layer interposed between the first pillar and the semiconductor region, A second insulating layer interposed between the second pillar and the well region Furthermore, it has The photodetector according to claim 4.

11. The first substrate further has a first pad that is electrically connected to the charge storage portion and exposed on the first bonding surface, The second substrate is electrically connected to the through-via and further has a second pad that is exposed on the second bonding surface and bonded to the first pad. The light detection device according to claim 1.

12. The second substrate further comprises a second wiring layer located between the first wiring layer and the second bonding surface. The light detection device according to claim 1.

13. The second substrate further has a third wiring layer on the side opposite to the second bonding surface when viewed from the semiconductor layer, The third wiring layer electrically connects the through-via to the gate electrode of the semiconductor element. The light detection device according to claim 2.

14. Equipped with a light detection device, The aforementioned light detection device is A first substrate having a photoelectric conversion unit that generates electric charge by photoelectric conversion of light, a charge storage unit that stores the electric charge, and a first bonding surface, A second substrate having an element formation surface on which a semiconductor element included in a readout circuit that outputs a first signal based on the charge is provided, a semiconductor layer including a through hole extending in a first direction from the element formation surface, a through via inserted through the through hole and electrically connected to the charge storage portion, a second bonding surface located on the opposite side from the element formation surface as seen from the semiconductor layer and bonded to the first bonding surface, and a first wiring layer located between the semiconductor layer and the second bonding surface. Equipped with electronic equipment.

15. The system further comprises a third substrate provided on the side opposite to the first substrate as viewed from the second substrate, and having a first signal processing unit that is electrically connected to the semiconductor element. The light detection device according to claim 1.

16. The system further comprises a fourth board having a second signal processing unit that is electrically connected to the first signal processing unit, and is located on the side opposite to the second board when viewed from the third board. The third substrate further has a second through-via, The second through via electrically connects the first signal processing unit and the second signal processing unit. The light detection device according to claim 15.

17. The diameter of the second through via is greater than the diameter of the first through via. The light detection device according to claim 16.

18. The third substrate has a third bonding surface, The fourth substrate has a fourth bonding surface that is bonded to the third bonding surface, The arrangement pitch of the multiple second connector terminal pairs, formed by joining multiple third pads exposed on the third connector surface and multiple fourth pads exposed on the fourth connector surface, is greater than the arrangement pitch of the multiple first connector terminal pairs, formed by joining multiple first pads exposed on the first connector surface and multiple second pads exposed on the second connector surface. The light detection device according to claim 16.

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