Semiconductor devices, imaging devices, radiation imaging systems, equipment, and methods for manufacturing semiconductor devices.

Abstract

In semiconductor devices, there has been a need for technologies that are advantageous in reducing the electrical resistance of connections between conductive components such as vias and plugs. [Solution] A semiconductor device comprising: a semiconductor layer; an insulating layer laminated on the semiconductor layer; a conductive through-via extending through the semiconductor layer and into the interior of the insulating layer, having a recess at its end on the insulating layer side; and a conductive connecting member disposed in the insulating layer, the part of which of its side surface abuts the inner surface of the recess of the through-via, wherein the part of the side surface of the connecting member abutting the through-via extends from the insulating layer side to the semiconductor layer side with respect to the extension line of the interface between the insulating layer and the semiconductor layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, a method for manufacturing a semiconductor device, and the like.

Background Art

[0002] Patent Document 1 discloses a technique for improving the reliability of an image sensor having an organic photoelectric conversion layer. The image sensor described in Patent Document 1 includes a contact via penetrating a substrate and a lower contact plug penetrating a part of an interlayer insulating layer and protruding into the contact via. The lower contact plug protruding into the contact via has a structure that contacts the contact via only on the substrate side rather than on the interface between the substrate and the interlayer insulating layer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a semiconductor device exemplified by an image sensor, it is required to reduce the electrical resistance at the connection part between conductive members such as vias and plugs. In the image sensor described in Patent Document 1, although it has a structure in which the lower contact plug protrudes into the contact via only on the substrate side rather than on the interface between the substrate and the interlayer insulating layer, a technique for further reducing the electrical resistance of the connection part has been demanded.

Means for Solving the Problems

[0005] A first aspect of the present invention is a semiconductor device comprising: a semiconductor layer; an insulating layer laminated on the semiconductor layer; a conductive through-via extending through the semiconductor layer and into the interior of the insulating layer, having a recess at its end on the insulating layer side; and a conductive connecting member disposed in the insulating layer, the part of which of its side surface abuts the inner surface of the recess of the through-via, wherein the part of the side surface of the connecting member abutting the through-via extends from the insulating layer side to the semiconductor layer side with respect to the extension of the interface between the insulating layer and the semiconductor layer.

[0006] Furthermore, a second aspect of the present invention is a method for manufacturing a semiconductor device, comprising the steps of: preparing a second substrate comprising a semiconductor layer on which a semiconductor element is formed and an element isolation region for separating the semiconductor element, wherein an insulating layer is provided so as to cover the semiconductor layer and the element isolation region; forming a first opening in the second substrate that penetrates the insulating layer and reaches a part of the element isolation region; filling the first opening with a conductive material to form a conductive connecting member; forming a second opening in the second substrate that penetrates the semiconductor layer and the element isolation region and reaches a part of the insulating layer, exposing a part of the connecting member; and filling the second opening with a conductive material to form a conductive through-via, wherein a conductive through-via that penetrates the semiconductor layer and extends into the interior of the insulating layer and has a recess at its end on the insulating layer side, and a conductive connecting member disposed in the insulating layer, with a part of its side surface in contact with the inner surface of the recess of the through-via, is formed to create an electrical connection structure. [Effects of the Invention]

[0007] According to the present invention, in semiconductor devices, it is possible to provide a technique that is advantageous for reducing the electrical resistance of connection points between conductive members such as vias and plugs. [Brief explanation of the drawing]

[0008] [Figure 1] A schematic cross-sectional view showing the stacked structure of the photoelectric conversion device according to Embodiment 1. [Figure 2]A schematic cross-sectional view showing a magnified view of the vicinity of the connection between the through via and the connecting member. [Figure 3] A schematic cross-sectional view showing an enlarged view of the vicinity of the connection between the through via and the connecting member for Modification Example 1. [Figure 4] A schematic cross-sectional view showing an enlarged view of the vicinity of the connection between the through via and the connecting member in the second modified example. [Figure 5] This schematic cross-sectional view shows an enlarged view of the vicinity of the connection between the through via and the connecting member in the third modification. [Figure 6] A schematic cross-sectional view illustrating one stage in the manufacturing process of the first circuit board. [Figure 7] A schematic cross-sectional view illustrating the procedure for forming a connecting member. [Figure 8] A schematic cross-sectional view illustrating the procedure for forming a wiring structure including a junction electrode E12. [Figure 9] A schematic cross-sectional view illustrating the procedure for joining the first circuit board and the sensor board. [Figure 10] A schematic cross-sectional diagram illustrating the procedure for thinning the second semiconductor substrate SL2SUB as needed to form the second semiconductor layer SL2. [Figure 11] A schematic cross-sectional view illustrating the procedure for forming an opening TH for creating a through via. [Figure 12] A schematic cross-sectional diagram illustrating the procedure for depositing an insulating film to cover the sidewall of the opening TH. [Figure 13] A schematic cross-sectional view illustrating the procedure for filling an opening TH with conductive material to form a through via. [Figure 14] A schematic cross-sectional view illustrating the procedure for forming a junction electrode E21 on a through via. [Figure 15] A schematic cross-sectional diagram illustrating the procedure for integrating the sensor board 11, the first circuit board 21, and the second circuit board 31. [Figure 16](a) Schematic diagram for explaining the device according to Embodiment 2. (b) Schematic diagram showing an example of the photoelectric conversion system according to Embodiment 2. (c) Schematic diagram showing an example of the in-vehicle photoelectric conversion system according to Embodiment 2. [Figure 17] (a) Schematic diagram showing the device as a radiation imaging system according to Embodiment 3. (b) Schematic diagram showing the configuration of a transmission electron microscope as a radiation imaging system according to Embodiment 3.

Mode for Carrying Out the Invention

[0009] Referring to the drawings, a semiconductor device, a method for manufacturing a semiconductor device, etc. according to an embodiment of the present invention will be described. The embodiments shown below are illustrative, and for example, those skilled in the art can appropriately modify and implement the details of the configuration without departing from the gist of the present invention.

[0010] In the drawings referred to in the following description of the embodiments, unless otherwise specified, elements denoted by the same reference numerals have the same functions. In the drawings, when a plurality of the same elements are arranged, the assignment of reference numerals and their descriptions may be omitted.

[0011] Also, for the convenience of illustration and description, the drawings may be schematically represented. Therefore, the shapes, sizes, arrangements, etc. of the elements shown in the drawings may not necessarily exactly match the actual objects. Also, the description of "XX or more and YY or less" or "XX to YY" representing a numerical range means a numerical range including the endpoints XX (lower limit) and YY (upper limit) unless otherwise specified. When the numerical ranges are described stepwise, the upper and lower limits of each numerical range can be arbitrarily combined.

[0012] In the following description, for example, when referring to the X plus direction, it refers to the same direction as that pointed by the X-axis arrow in the illustrated orthogonal coordinate system, and when referring to the X minus direction, it refers to the direction opposite by 180 degrees to the direction pointed by the X-axis arrow in the illustrated orthogonal coordinate system. Also, when simply referring to the X direction, it refers to a direction parallel to the X axis regardless of the difference from the direction pointed by the X-axis arrow in the illustration. The same applies to directions other than X. In the following description, terms indicating specific directions and positions (for example, "up", "down", "right", "left", and other terms including these terms) are used as necessary. The use of these terms is for facilitating the understanding of the embodiments with reference to the drawings, and the technical scope of the present invention is not limited by the meanings of these terms.

[0013] In the following description, although the terms "layer" and "film" such as an insulating layer and an insulating film may be used, unless otherwise specified, they do not mean technically different aspects.

[0014] The relationship of "substantially equal" used in the following description will be described. Although it is an equal relationship in design, a slight difference may occur due to manufacturing errors. This "substantially equal" includes the slight difference caused by this manufacturing error.

[0015] [Embodiment 1] (Configuration of the photoelectric conversion device) The configuration of the photoelectric conversion device according to Embodiment 1 will be described with reference to the drawings. FIG. 1 is a schematic cross-sectional view for showing the stacked structure of the photoelectric conversion device according to the present embodiment. The illustrated photoelectric conversion device 100 is configured as a stacked type photoelectric conversion device. The photoelectric conversion device 100 may be, for example, a back-illuminated type photoelectric conversion device, but the photoelectric conversion device according to the present invention may also be configured as a front-illuminated type photoelectric conversion device.

[0016] The photoelectric conversion device 100 is configured, for example, by laminating a plurality of substrates including a sensor substrate 11, a first circuit substrate 21, and a second circuit substrate 31, and electrically connecting these plurality of substrates.

[0017] The sensor substrate 11, the first circuit board 21, and the second circuit board 31 may each be chips diced from a wafer, but these substrates are not limited to chips. For example, each substrate may be a wafer. Also, multiple substrates may be stacked in wafer form and then diced, or multiple chips may be stacked or bonded together after being formed into chips.

[0018] The sensor substrate 11 has a pixel array region on which a plurality of photoelectric conversion elements 201 are arranged. The sensor substrate 11 also has a first semiconductor layer SL1 having the photoelectric conversion elements 201 and an insulating layer IL11 including a multilayer wiring structure. The insulating layer IL11 may be formed as an interlayer insulating layer in the multilayer wiring structure electrically connected to the photoelectric conversion elements 201.

[0019] The first circuit board 21 has a second semiconductor layer SL2 on which a plurality of semiconductor elements (e.g., transistors) constituting a circuit such as a first signal processing unit and element isolation regions 210 that separate the semiconductor elements are arranged. Furthermore, the first circuit board 21 has an insulating layer IL12 including a multilayer wiring structure and an insulating layer IL21 including a wiring structure.

[0020] The insulating layer IL12 may be formed as an interlayer insulating layer in a multilayer wiring structure that electrically connects the sensor substrate 11 and the first signal processing unit. The insulating layer IL12 includes an insulating film 216 and an insulating layer 218. The insulating layer IL21 may be formed as an interlayer insulating layer in a wiring structure that electrically connects the first signal processing unit and the second circuit board 31. The insulating layer IL12 and the insulating layer IL21 are laminated on opposite sides with the second semiconductor layer SL2 in between. The second semiconductor layer SL2 has a silicide layer 211 at its interface with the insulating layer IL12 (insulating layer 218).

[0021] The first circuit board 21 includes through-vias 219 that penetrate the second semiconductor layer SL2 in order to electrically connect the wiring pattern 217 formed in the insulating layer IL12 with the wiring provided on the second circuit board 31. The through-vias 219, made of a conductive material, penetrate at least a portion of the insulating layer IL21 and the second semiconductor layer SL2, and extend to at least a portion (inside) of the insulating layer IL12. The wiring pattern 217 and the through-vias 219 are connected by a connecting member 215 made of a conductive material. The connecting member 215 penetrates at least a portion of the insulating layer IL12 and extends into the recess of the through-vias 219. The connection portion between the through-vias 219 and the connecting member 215 and its surrounding structure will be described in detail later.

[0022] The second circuit board 31 has a second circuit region on which circuits such as a second signal processing unit, a vertical scanning circuit, a horizontal scanning circuit, and a readout circuit are arranged. The second circuit board 31 also has a third semiconductor layer SL3 on which a plurality of semiconductor elements (e.g., transistors) constituting the second signal processing unit and other circuits are arranged, and an insulating layer IL22 including a multilayer wiring structure. The insulating layer IL22 may be formed as an interlayer insulating layer of the multilayer wiring structure electrically connected to the second circuit board 21.

[0023] Between the first semiconductor layer SL1 of the sensor substrate 11 and the second semiconductor layer SL2 of the first circuit board 21, there is a first insulating layer IL1, which consists of insulating layers IL11 and IL12 connected together. Between the second semiconductor layer SL2 of the first circuit board 21 and the third semiconductor layer SL3 of the second circuit board 31, there is a second insulating layer IL2, which consists of insulating layers IL21 and IL22 connected together.

[0024] The sensor substrate 11 and the first circuit board 21 are joined such that the first insulating layer IL11 and the insulating layer IL12 are adjacent to each other. At the joint between the sensor substrate 11 and the first circuit board 21, a bonding electrode E11 located on the insulating layer IL11 and a bonding electrode E12 located on the insulating layer IL12 form a metal joint, electrically and mechanically connecting the sensor substrate 11 and the first circuit board 21. Specifically, the first insulating layer IL1 has a wiring structure (electrical connection structure) that electrically connects the photoelectric conversion element 201 formed on the first semiconductor layer SL1 and the first circuit region formed on the first circuit board 21.

[0025] The first circuit board 21 includes an insulating layer IL21 formed on the side opposite to the insulating layer IL12 relative to the semiconductor layer SL2. At the junction between the first circuit board 21 and the second circuit board 31, a junction electrode E21 located in the insulating layer IL21 and a junction electrode E22 located in the insulating layer IL22 form a metal junction, electrically and mechanically connecting the first circuit board 21 and the second circuit board 31. In other words, the second insulating layer IL2 has a wiring structure (electrical connection structure) formed therein that electrically connects the first circuit region formed on the first circuit board 21 and the second circuit region formed on the second circuit board 31.

[0026] (Regarding through-vias and connecting members) Next, we will describe a characteristic feature of this embodiment, namely the structure that reduces the electrical resistance of the connection between the through-via 219 and the connecting member 215. Figure 2 is a schematic cross-sectional view showing an enlarged view of the connection portion and its vicinity between the through-via 219 and the connecting member 215. In this figure, the main surface of the first circuit board 21 or the second semiconductor layer SL2 is parallel to the XY plane, and the normal direction to the main surface of the first circuit board 21 or the second semiconductor layer SL2 is the Z direction. The layer structure schematically shown in Figure 2 can be confirmed by observing a cross-sectional sample of the photoelectric converter 100 or the first circuit board 21 using an appropriate analyzer or analytical method such as TEM or SEM.

[0027] In the second circuit board 21, the through-via 219 and the connecting member 215 electrically connect the wiring pattern 217 arranged in the insulating layer IL12 and the junction electrode E21 arranged in the insulating layer IL21. The wiring pattern 217 may be formed of, for example, copper or aluminum, but may also be formed of other materials.

[0028] The through via 219 may be formed of, for example, tungsten, but may also be formed of other conductive materials such as aluminum or copper. The through via 219 may be formed as a two-layer structure having a conductive core material 2192 and a conductive coating material 2191 covering it. The core material 2192, which is the center or base of the through via 219, can be formed of a metallic material such as tungsten, aluminum, or copper, or other alloy materials, and the coating material 2191 can be formed as a barrier metal using, for example, Ti, TiN, etc.

[0029] A silicide layer 211 is formed on the Z-positive side (insulating layer IL12 side) of the second semiconductor layer SL2. In the portion of the second semiconductor layer SL2 where the silicide layer 211 is not present, an element isolation region 210 can be provided to separate semiconductor elements from each other. Through-through vias 219 must be positioned to avoid the silicide layer 211, but positioning the through-through vias 219 to penetrate the element isolation region 210, as shown in Figure 2, is advantageous in simplifying the circuit layout and process.

[0030] A connecting member 215 that connects the wiring pattern 217 and the through via 219 may be formed as a two-layer structure having a conductive core material 2152 and a conductive covering material 2151 that covers it. The core material 2152, which is the center or base of the connecting member 215, can be formed from a metallic material such as tungsten, aluminum, or copper, or other alloy material, and the covering material 2151 can be formed as a barrier metal using, for example, Ti, TiN, etc. The connecting member 215 may be, for example, a plug.

[0031] For the sake of explanation, the dimension of the through via 219 in the Z direction will be called the height of the through via 219, and the diameter in a cross-section parallel to the XY plane will be called the width of the through via 219. Similarly, the dimension of the connecting member 215 in the Z direction will be called the height of the connecting member 215, and the diameter in a cross-section parallel to the XY plane will be called the width of the connecting member 215.

[0032] The configuration in which the through-via 219 is electrically connected to the wiring pattern 217 via the connecting member 215 allows for a reduction in the height of the through-via 219, or in other words, a reduction in the depth of the through-hole formed to form the through-via 219. This is advantageous for the stable formation of fine through-vias 219. Furthermore, such a structure is advantageous in that it does not cause etching damage to the wiring pattern 217 when the through-hole for forming the through-via 219 is formed by etching. In order to reduce the height of the through-via 219, it is preferable that the second semiconductor layer SL2 is thinner than the other semiconductor layers. For example, it is preferable that the second semiconductor layer SL2 is thinner than either the first semiconductor layer SL1 or the third semiconductor layer SL3.

[0033] The through via 219 may have a tapered shape, with its width decreasing towards the connecting member. Similarly, the connecting member 215 may also have a tapered shape, with its width decreasing towards the through via. At the connection point between the through via 219 and the connecting member 215, the width of the through via 219 is greater than the width of the connecting member 215. By adopting this configuration, the requirements for the precision of the alignment of the through via 219 with respect to the connecting member 215 during manufacturing can be relaxed.

[0034] A recess is formed at the upper end (the end in the Z-positive direction) of the through via 219, and the lower end (the end in the Z-negative direction) of the connecting member 215 extends into this recess, thereby firmly connecting the through via 219 and the connecting member 215. Specifically, the side surface of the recess in the through via 219 and the side surface of the lower end of the connecting member 215 are joined, and the bottom surface of the recess in the through via 219 and the front surface of the lower end of the connecting member 215 are joined.

[0035] As shown in the figure, in the direction normal to the main surface of the first circuit board 21 or the second semiconductor layer SL2 (Z direction), the position of the upper end of the through via 219 is P1, the position of the interface between the insulating layer IL12 and the second semiconductor layer SL2 is P2, and the position of the lower end of the connecting member 215 is P3.

[0036] As is clear from the positional relationship between P1 and P2 shown in the diagram, the upper end of the through via 219 is located on the side of the insulating layer IL12 rather than on the extension of the interface between the insulating layer IL12 and the second semiconductor layer SL2. In other words, the through via 219 penetrates the second semiconductor layer SL2 and extends at least a portion of it into the insulating layer IL12.

[0037] Furthermore, as can be seen from the positional relationship between P2 and P3, the lower end of the connecting member 215 is located on the side of the second semiconductor layer SL2, rather than on the extension line of the interface between the insulating layer IL12 and the second semiconductor layer SL2. In other words, the connecting member 215 penetrates a portion of the insulating layer IL12, and at least a portion of it extends into the second semiconductor layer SL2.

[0038] According to this embodiment, the side surface of the recess of the through via 219 and the side surface of the lower end of the connecting member 215 are joined over a wide area, from P1 on the insulating layer IL12 side to P3 on the second semiconductor layer SL2 side. In other words, the through via 219 and the connecting member 215 are joined over a wide area, with their sides straddling the interface (P2) between the insulating layer IL12 and the second semiconductor layer SL2. To put it another way, a portion of the side surface of the connecting member 215 that is in contact with the through via 219 extends from the insulating layer IL12 side to the semiconductor layer SL2 side, relative to the extension of P2, which is the interface between the insulating layer IL12 and the semiconductor layer SL2.

[0039] Thus, not only the tip surface of the through via 219 and the tip surface of the connecting member 215, but also the inner surface of the recess of the through via 219 and the side surface of the lower end of the connecting member 215 are joined over a wide area. For this reason, according to this embodiment, poor conductivity and resistance variations at the connection between the connecting member 215 and the through via 219 can be significantly reduced.

[0040] The coating material 2151 on the connecting member 215 can be formed by a film deposition technique (film deposition method) with low anisotropy of deposition rate, such as CVD. The coating material 2191 on the through via 219 can be formed by a film deposition technique with high anisotropy of deposition rate (directivity of material), such as sputtering. With such a manufacturing method, the film thickness of each part can be configured to satisfy the relationships TB12>TB22>TS22 and TB12>TS12. Note that TS12 is the thickness of the coating material 2151 on the side surface of the connecting member 215, and TB22 is the thickness of the coating material 2191 on the upper surface of the through via 219, i.e., the part that abuts the insulating layer 218. Also, TS22 is the thickness of the coating material 2191 on the side surface of the through via 219. TB12 is the total film thickness of the coating material 2151 and the coating material 2191 at the bottom surface of the recess of the through via 219. For example, the film thickness of TS12 can be 5nm to 30nm, TS22 can be 5nm to 60nm, TB22 can be 5nm to 90nm, and TB12 can be 10nm to 120nm.

[0041] As described above, the connecting member 215 has a conductive core material 2152 and a conductive covering material 2151 that covers the core material 2152. The thickness TS12 of the covering material 2151 that covers the side surface of the core material 2152 is approximately equal to the thickness (TB12-TB22) of the covering material that covers the end surface of the core material 2152 on the through via side. The through via 219 has a conductive core material 2192 and a conductive covering material 2191 that covers the core material 2192. The thickness TS22 of the covering material 2191 that covers the side surface of the core material 2192 is smaller than the thickness TB22 of the covering material 2191 that covers the tip surface on the insulating layer 218 side of the core material 2192 or the bottom surface of the recess.

[0042] Furthermore, the manufacturing method and configuration of the covering material 2151 for the connecting member 215 and the covering material 2191 for the through via 219 may differ. Examples of such modifications are described below.

[0043] (Modification 1) Figure 3 is a schematic cross-sectional view of Modification 1, showing an enlarged view of the connection between the through via 219 and the connecting member 215 and its vicinity. Details common to the configuration shown in Figure 2 are omitted from the explanation.

[0044] The coating material 2151 on the connecting member 215 is formed by a film deposition technique with low deposition rate anisotropy, such as CVD. The coating material 2191 on the through via 219 is also formed by a film deposition technique with low deposition rate anisotropy, such as CVD. With this manufacturing method, the film thickness of each part can be configured to satisfy the relationships TB13 > TB23 ≈ TS23 and TB13 > TS13. Note that TS13 is the thickness of the coating material 2151 on the side surface of the connecting member 215, and TB23 is the thickness of the coating material 2191 on the upper surface of the through via 219, i.e., the part that abuts the insulating layer 218. Also, TS23 is the thickness of the coating material 2191 on the side surface of the through via 219. TB13 is the total film thickness of the coating material 2151 and the coating material 2191 at the bottom surface of the recess of the through via 219. For example, the film thickness of TS13 can be 5nm to 30nm, TS23 can be 5nm to 30nm, TB23 can be 5nm to 30nm, and TB13 can be 10nm to 60nm.

[0045] (Modification 2) Figure 4 is a schematic cross-sectional view showing an enlarged view of the connection between the through via 219 and the connecting member 215 and its vicinity in Modification 2. Details common to the embodiment shown in Figure 2 are omitted from the explanation.

[0046] The coating material 2151 of the connecting member 215 is formed using a film deposition technique with anisotropic deposition rate, such as sputtering, so that the deposition rate (directivity of the material) is large in the Z direction. The coating material 2191 of the through via 219 is formed using a film deposition technique with small anisotropy in deposition rate, such as CVD. With this manufacturing method, the film thickness of each part can be configured to satisfy the relationships TB14>TB24≈TS24 and TB14>TS14. Note that TS14 is the thickness of the coating material 2151 on the side surface of the connecting member 215, and TB24 is the thickness of the coating material 2191 on the upper surface of the through via 219, i.e., the part that abuts the insulating layer 218. Also, TS24 is the thickness of the coating material 2191 on the side surface of the through via 219. TB14 is the total film thickness of the coating material 2151 and the coating material 2191 at the bottom surface of the recess of the through via 219. For example, the film thickness of TS14 can be 5nm to 60nm, TS24 can be 5nm to 30nm, TB24 can be 5nm to 30nm, and TB14 can be 10nm to 120nm.

[0047] (Modification 3) Figure 5 is a schematic cross-sectional view of Modification 3, showing an enlarged view of the connection between the through via 219 and the connecting member 215 and its vicinity. Details common to the embodiment shown in Figure 2 are omitted from the explanation.

[0048] The coating material 2151 of the connecting member 215 is formed using a film deposition technique with anisotropic deposition rate, such as sputtering, so that the deposition rate in the Z direction is increased. The coating material 2191 of the through via 219 is formed using a film deposition technique with anisotropic deposition rate, such as sputtering, so that the deposition rate in the Z direction is increased. With this manufacturing method, the film thickness of each part can be configured to satisfy the relationships TB15>TB25>TS25 and TB15>TS15. Note that TS15 is the thickness of the coating material 2151 on the side surface of the connecting member 215, and TB25 is the thickness of the coating material 2191 on the upper surface of the through via 219, i.e., the part that abuts the insulating layer 218. Also, TS25 is the thickness of the coating material 2191 on the side surface of the through via 219. TB15 is the total film thickness of the coating material 2151 and the coating material 2191 at the bottom surface of the recess of the through via 219. For example, the film thickness of TS15 can be 5nm to 60nm, TS25 can be 5nm to 60nm, TB25 can be 5nm to 90nm, and TB15 can be 10nm to 180nm.

[0049] (Regarding the manufacturing method) The manufacturing method of the photoelectric converter according to this embodiment will be described with reference to Figures 6 to 15. Figures 6 to 15 are schematic cross-sectional views illustrating each stage of the manufacturing process of the photoelectric converter. First, the manufacturing procedure of the first circuit board 21 (Figure 1) will be described.

[0050] As shown in Figure 6, a transistor including a silicide layer 211 and, for example, an element isolation region 210 in which an oxide film is embedded in grooves, and a second semiconductor substrate SL2SUB for forming the second semiconductor layer SL2 are formed. Furthermore, an insulating layer 218 and an insulating film 216 are formed sequentially on the second semiconductor substrate SL2SUB. The insulating layer 218 may be, for example, a silicon nitride film. The insulating film 216 may be, for example, a silicon oxide film. The thickness of the insulating layer 218 can be 10 nm to 100 nm. An insulating film (not shown) may be formed between the insulating layer 218 and the second semiconductor substrate SL2SUB.

[0051] Next, as shown in Figure 7, the first aperture OP21 and the second aperture OP22 are formed by etching the insulating film 216. The first aperture OP21 penetrates the insulating layer 218 and reaches a predetermined depth (P3 in Figure 2) within the element isolation region 210, while the etching conditions for the second aperture OP22 are adjusted so that etching stops at the position where the silicide layer 211 is exposed.

[0052] Next, conductive material is filled into the first opening OP21 to form a connecting member 215, and conductive material is filled into the second opening OP22 to form a contact plug 230 (Figure 1). Here, the connecting member 215 is formed to penetrate the insulating layer 218 and reach a predetermined depth (P3 in Figure 2) within the element isolation region 210.

[0053] The connecting member 215 and the contact plug 230 may be formed from, for example, barrier metals such as Ti and TiN, and tungsten, but may also be formed from other materials such as aluminum or copper, or a combination thereof. The connecting member 215 connected to the through via 219 can be formed simultaneously with the contact plug 230 connected to the transistor, etc. Alternatively, the second opening OP22 connected to the transistor, etc. can be formed after the first opening OP21 has been formed, and then the connecting member 215 and the contact plug 230 can be formed.

[0054] In this case, it is desirable that the diameter of the first opening OP21 be greater than or equal to the diameter of the second opening OP22. From a circuit layout perspective, it is desirable that the diameter of the second opening OP22, which forms the contact plug 230 connected to a transistor or the like, be fine. On the other hand, it is desirable that the diameter of the first opening OP21, which forms the connecting member 215, be equal to or greater than the diameter of the second opening OP22, from the viewpoint of facilitating alignment with the through via 219 that is connected later and reducing the connection electrical resistance.

[0055] Next, as shown in Figure 8, a wiring structure including a wiring layer is formed on top of the connecting member 215 and the contact plug 230. The uppermost layer of the wiring structure is formed such that the bonding electrode E12 is exposed on the upper surface of the insulating layer IL12. This forms a part of the first circuit board 21.

[0056] Next, as shown in Figure 9, a portion of the first circuit board 21 described above and a separately prepared sensor board 11 are joined together. Note that Figure 9 is shown upside down compared to Figure 8. At this time, the joining electrode E11 formed on the sensor board 11 and the joining electrode E12 formed on the first circuit board 21 are joined together, and the sensor board 11 and the first circuit board 21 are electrically and mechanically connected.

[0057] Next, as shown in Figure 10, the second semiconductor substrate SL2SUB is thinned as needed to form the second semiconductor layer SL2. Furthermore, an insulating layer IL21 is formed on top of the second semiconductor layer SL2.

[0058] Next, as shown in Figure 11, an opening TH is formed. The opening TH is formed by etching, which penetrates the insulating layer IL21, the second semiconductor layer SL2, and the element isolation region 210, and further excavates a portion of the insulating layer 218 to the level of P1 in Figure 2. At the bottom of the opening TH, a portion of the connecting member 215 protrudes from the insulating layer 218.

[0059] Next, as shown in Figure 12, an insulating film is deposited to cover the side walls of the opening TH. For example, the insulating film can be coated to cover the inner surface of the opening, and then the insulating film at the bottom of the opening TH can be removed using an etch-back process or the like.

[0060] Next, as shown in Figure 13, a through via 219 is formed by filling the opening TH with a conductive material, as described with reference to Figure 2, for example. That is, a through via 219 is formed that penetrates the second semiconductor layer SL2 and connects to the connecting member 215. As shown in Figure 2, the tip of the through via 219 is located at the level of P1 in the insulating layer 218. The through via 219 may be formed of a barrier metal such as Ti or TiN and tungsten, but it may also be formed of other materials such as aluminum or copper.

[0061] Next, as shown in Figure 14, a junction electrode E21 is formed on the through via 219. Although not shown here, it is also possible to form a wiring structure including a wiring layer between the through via 219 and the junction electrode E21.

[0062] Next, as shown in Figure 15, a separately prepared second circuit board 31 is bonded to the joint of the first circuit board 21 and the sensor board 11 formed in Figure 14. Note that Figure 15 is shown upside down compared to Figure 14. At this time, the bonding electrode E21 of the first circuit board 21 and the bonding electrode E22 of the second circuit board 31 are bonded, and the first circuit board 21 and the second circuit board 31 are electrically and mechanically connected. As a result, the sensor board 11, the first circuit board 21, and the second circuit board 31 are integrated and electrically and mechanically connected. After that, if necessary, the first semiconductor layer SL1 is thinned, and the photoelectric conversion device 100 shown in Figure 1 is completed.

[0063] According to the manufacturing method described above, as shown in Figure 7, the connecting member 215 is formed to penetrate the insulating layer 218 and reach a predetermined depth (P3 in Figure 2) within the element isolation region 210. Then, as shown in Figure 13, a through via 219 is formed that penetrates the second semiconductor layer SL2, with its tip located within the insulating layer 218 and connecting to the connecting member 215.

[0064] As a result, one end of the through-via 219 is located on the side of the insulating layer IL12 rather than on the extension of the interface between the insulating layer IL12 and the second semiconductor layer SL2. In other words, the through-via 219 penetrates the second semiconductor layer SL2, and at least a portion of it extends into the insulating layer IL12.

[0065] Furthermore, one end of the connecting member 215 is located on the side of the second semiconductor layer SL2, rather than on the extension line of the interface between the insulating layer IL12 and the second semiconductor layer SL2. In other words, the connecting member 215 penetrates a portion of the insulating layer IL12, and at least a portion of it extends into the second semiconductor layer SL2.

[0066] In this embodiment, the inner surface of the recess of the through via 219 and the side surface of the end of the connecting member 215 are joined over a wide area, from P1 on the insulating layer IL12 side to P3 on the second semiconductor layer SL2 side. In other words, the through via 219 and the connecting member 215 are joined over a wide area on each other's sides, straddling the interface (P2) between the insulating layer IL12 and the second semiconductor layer SL2. Thus, not only the bottom surface of the recess of the through via 219 and the tip surface of the end of the connecting member 215 are joined over a wide area, but also the inner surface of the recess of the through via 219 and the side surface of the end of the connecting member 215. For this reason, in this embodiment, the electrical resistance of the connection between the connecting member 215 and the through via 219 can be reduced, and the occurrence of poor conduction and resistance variations can be significantly reduced.

[0067] [Embodiment 2] As a second embodiment, a device equipped with the semiconductor device (solid-state imaging device) according to the above-described embodiment will be described. Figure 16(a) is a schematic diagram illustrating a device 9191 equipped with the semiconductor device 930 according to the above-described embodiment. The device 9191 equipped with the semiconductor device 930 will be described in detail.

[0068] The semiconductor device 930 comprises a semiconductor device 910 that integrates a first chip as a photoelectric converter and a second chip having at least one of a memory circuit or a logic circuit. In addition to the semiconductor device 910, the semiconductor device 930 may also include a package 920 that houses the semiconductor device 910. The package 920 may include a substrate on which the semiconductor device 910 is fixed and a cover made of glass or the like that faces the semiconductor device 910. The package 920 may further include bonding members such as bonding wires or bumps that connect terminals provided on the substrate and terminals provided on the semiconductor device 910.

[0069] The device 9191 may include at least one of the following: an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 is provided in conjunction with the semiconductor device 930 and includes an optical system that guides light to the semiconductor device 930, such as a lens, shutter, and mirror. The control device 950 controls the semiconductor device 930. The control device 950 is a semiconductor device such as an ASIC.

[0070] The processing unit 960 processes the signals output from the semiconductor device 930. The processing unit 960 is a semiconductor device such as a CPU or ASIC that constitutes an AFE (analog front end) or DFE (digital front end). The display device 970 is an EL display device or liquid crystal display device that displays the information (image) obtained by the semiconductor device 930. The storage device 980 is a magnetic device or semiconductor device that stores the information (image) obtained by the semiconductor device 930. The storage device 980 is a volatile memory such as SRAM or DRAM, or a non-volatile memory such as flash memory or a hard disk drive.

[0071] The mechanical device 990 has movable parts or propulsion parts such as motors and engines. The device 9191 displays signals output from the semiconductor device 930 on the display device 970 or transmits them to the outside using a communication device (not shown) provided in the device 9191. For this purpose, it is preferable that the device 9191 further includes a storage device 980 and a processing device 960, separate from the memory circuits and arithmetic circuits of the semiconductor device 930. The mechanical device 990 may be controlled based on signals output from the semiconductor device 930.

[0072] Furthermore, the device 9191 is suitable for electronic devices such as information terminals with shooting capabilities (e.g., smartphones and wearable devices) and cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). In a camera, the mechanical device 990 can drive components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in a camera can move the semiconductor device 930 for vibration damping.

[0073] Furthermore, the device 9191 may be a transport device such as a vehicle, ship, or aircraft. The mechanical device 990 in the transport device may be used as a mobile device. The device 9191 as a transport device is suitable for transporting the semiconductor device 930 or for assisting and / or automating driving (operation) through its imaging function. The processing device 960 for assisting and / or automating driving (operation) can perform processing to operate the mechanical device 990 as a mobile device based on information obtained from the semiconductor device 930. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring instrument such as a distance sensor, an analytical instrument such as an electron microscope, office equipment such as a copier, or industrial equipment such as a robot. According to the above embodiment, since the electrical resistance of the connection between conductive members such as vias and plugs in the image sensor or circuit section is reduced, it is possible to stably acquire images with good characteristics.

[0074] Therefore, by using the semiconductor device 930 according to this embodiment in the device 9191, the value of the device can also be improved. For example, by mounting the semiconductor device 930 on a transport device, excellent performance can be obtained when taking external images of the transport device or measuring the external environment. Therefore, when manufacturing and selling transport devices, deciding to mount the semiconductor device according to this embodiment on the transport device is advantageous in improving the performance of the transport device itself. In particular, the semiconductor device 930 is suitable for transport devices that use information obtained from the semiconductor device to assist in driving and / or perform autonomous driving. Furthermore, its implementation in vehicles, ships, aircraft, etc., is not limited to equipment used for transport purposes, but can also be suitably implemented in drones that perform aerial photography for various purposes, such as inspecting buildings and agricultural facilities, and monitoring natural phenomena.

[0075] The photoelectric conversion system and mobile body of this embodiment will be described with reference to Figures 16(b) and 16(c). Figure 16(b) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 8 has a photoelectric conversion device 80. The photoelectric conversion device 80 is a photoelectric conversion device as an electronic component as described in the above embodiment. The photoelectric conversion system 8 has an image processing unit 801 that performs image processing on a plurality of image data acquired by the photoelectric conversion device 80, and a parallax acquisition unit 802 that calculates parallax (phase difference of parallax images) from a plurality of image data acquired by the photoelectric conversion system 8. The photoelectric conversion system 8 also has a distance acquisition unit 803 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax acquisition unit 802 and the distance acquisition unit 803 are examples of distance information acquisition means that acquire distance information to an object. That is, distance information is information related to parallax, defocus amount, distance to an object, etc. The collision detection unit 804 may use any of this distance information to determine the possibility of a collision. The distance information acquisition means may be implemented by specially designed hardware, a software module, or an FPGA (Field Programmable Gate Array) or ASIC (Application Specific Integrated Circuit).

[0076] The photoelectric conversion system 8 is connected to the vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 8 is also connected to the control ECU 820, which is a control device that outputs a control signal to generate braking force on the vehicle based on the judgment result of the collision judgment unit 804. The photoelectric conversion system 8 is also connected to the warning device 830, which issues a warning to the driver based on the judgment result of the collision judgment unit 804. For example, if the collision judgment result of the collision judgment unit 804 indicates a high probability of collision, the control ECU 820 performs vehicle control to avoid a collision or mitigate damage by applying the brakes, releasing the accelerator, or suppressing engine output. The warning device 830 warns the user by sounding an alarm, displaying warning information on a screen such as a car navigation system, or vibrating the seat belt or steering wheel.

[0077] In this embodiment, the photoelectric conversion system 8 images the area around the vehicle, for example, the front or rear. Figure 16(c) shows the photoelectric conversion system when imaging the area in front of the vehicle (imaging range 850). The vehicle information acquisition device 810 sends instructions to the photoelectric conversion system 8 or the photoelectric conversion device 80. This configuration can further improve the accuracy of distance measurement.

[0078] The above example describes control to prevent collisions with other vehicles, but it can also be applied to control systems that automatically follow other vehicles or control systems that automatically stay within their lanes. Furthermore, the photoelectric conversion system can be applied not only to vehicles such as the vehicle itself, but also to mobile objects (mobile devices) such as ships, aircraft, or industrial robots. In addition, it can be applied not only to mobile objects but also to a wide range of devices that utilize object recognition, such as intelligent transportation systems (ITS). According to the embodiment described above, it is possible to stably acquire images with good characteristics.

[0079] [Embodiment 3] As Embodiment 3, another example of a radiation imaging system incorporating the semiconductor device described in Embodiment 1 as a radiation detector will be described with reference to Figures 17(a) and 17(b).

[0080] Figure 17(a) shows the instrument EQP as a radiation imaging system equipped with a radiation detector 1000. The radiation detector 1000 includes an image sensor 101 (a photoelectric conversion element capable of detecting radiation), which is a semiconductor device, as well as a package PKG for mounting the image sensor 101.

[0081] The package PKG may include a base on which the image sensor 101 is fixed, a cover made of glass or the like facing the image sensor 101, and connecting members such as bonding wires or bumps that connect terminals provided on the base and terminals provided on the image sensor 101. The image sensor 101 has a pixel array 102 in which pixels 103 are arranged in a matrix and a peripheral region around it. Peripheral circuits (for example, a vertical scanning circuit 104 or a DFE 109) can be provided in the peripheral region.

[0082] The EQP device may further comprise at least one of the following: an optical system OPT, a control unit CTRL, a processing unit PRCS, a display device DSPL, a memory device MMRY, and a mechanical device MCHN. The optical system OPT images the radiation onto the radiation detector 1000 and is, for example, a lens, shutter, or mirror. Depending on the type of radiation being handled, the optical system OPT may also image particle beams such as electron beams or proton beams onto the radiation detector 1000. The control unit CTRL controls the radiation detector 1000 and is, for example, an ASIC. The processing unit PRCS processes the signals output from the radiation detector 1000 and is a device such as a CPU or ASIC for configuring an AFE (analog front end) or DFE (digital front end). The display device DSPL is an EL display device or liquid crystal display device that displays the information obtained by the radiation detector 1000 in the form of a visible image or the like. The memory device MMRY is a magnetic device or semiconductor device that stores the information obtained by the radiation detector 1000. The memory device MMRY is a volatile memory such as SRAM or DRAM, or a non-volatile memory such as flash memory or a hard disk drive. The mechanical device MCHN has moving parts such as motors and engines, or propulsion parts.

[0083] The EQP device displays the signal output from the radiation detector 1000 on the DSPL display device, or transmits it externally via a communication device (not shown) provided by the EQP device. For this purpose, it is preferable that the EQP device further includes a memory device MMRY and a processing device PRCS, separate from the memory circuit and arithmetic circuit of the radiation detector 1000. The mechanical device MCHN may be controlled based on the signal output from the radiation detector 1000.

[0084] The EQP device shown in Figure 17(a) may be a medical device such as an endoscope or radiological diagnostic equipment, a measuring instrument such as a distance sensor, or an analytical instrument such as an electron microscope.

[0085] Figure 17(b) is a schematic diagram showing the configuration of a transmission electron microscope (TEM) as an example of an EQP instrument. The EQP instrument as an electron microscope includes an electron source 1202 (electron gun), an irradiation lens 1204, a vacuum chamber 1201 (microscope tube), an objective lens 1206, a magnification lens system 1207, and a camera 1209 as a radiation detector 1000.

[0086] The electron beam 1203, an energy beam emitted from the electron source 1202 (radiation source), is focused by the irradiation lens 1204 and irradiated onto the sample S, which is the object of analysis (image target) and is held in the sample holder. The space through which the electron beam 1203 passes is formed by the vacuum chamber 1201 (lens tube), and this space is maintained in a vacuum. The radiation detector 1000 is positioned to face the vacuum space through which the electron beam 1203 passes. The electron beam 1203 that has passed through the sample S is magnified by the objective lens 1206 and the magnifying lens system 1207 and projected onto the radiation detector 1000. The electron optical system for irradiating the sample S with the electron beam is called the irradiation optical system, and the electron optical system for imaging the electron beam that has passed through the sample S onto the radiation detector 1000 is called the imaging optical system.

[0087] The electron source 1202 is controlled by the electron source control device 1211. The irradiation lens 1204 is controlled by the irradiation lens control device 1212. The objective lens 1206 is controlled by the objective lens control device 1213. The magnification lens system 1207 is controlled by the magnification lens system control device 1214. The sample holder control mechanism 1205 is controlled by the holder control device 1215, which controls the drive mechanism of the sample holder.

[0088] The electron beam 1203 that passes through the sample S is detected by the direct detector 1200 of the camera 1209. The output signal from the direct detector 1200 is processed by the signal processing device 1216 and the image processing device 1218, which function as the processing device PRCS, to generate an image signal. The generated image signal (transmitted electron image) is displayed on the image display monitor 1220 and the analysis monitor 1221, which correspond to the display device DSPL.

[0089] Camera 1209 is located at the bottom of the EQP instrument. Camera 1209 has a direct electron detector 1200, which corresponds to the image sensor 101. At least a portion of camera 1209 is located inside the camera 1209 so that it is exposed to the vacuum space formed by the vacuum chamber 1201.

[0090] The electron source control device 1211, the irradiation lens control device 1212, the objective lens control device 1213, the magnification lens system control device 1214, and the holder control device 1215 are each connected to the image processing device 1218. This allows for the exchange of data between them to set the imaging conditions of the electron microscope. For example, the electron beam irradiation rate can be set to 0.5 electrons / pix / frm or less. In this case, the electron source control device 1211 and the image processing device 1218 function as control means for controlling the radiation irradiation rate. Signals from the image processing device 1218 allow for the driving control of the sample holder and the setting of observation conditions for each lens.

[0091] The operator prepares the sample S to be photographed and sets the imaging conditions using the input device 1219 connected to the image processing device 1218. The operator inputs predetermined data to the electron source control device 1211, the irradiation lens control device 1212, the objective lens control device 1213, and the magnification lens system control device 1214, respectively, to obtain the desired acceleration voltage, magnification, and observation mode. The operator also inputs conditions such as the number of continuous field images, the starting position for imaging, and the movement speed of the sample holder to the image processing device 1218 using the input device 1219, such as a mouse, keyboard, or touch panel. The image processing device 1218 may also be configured to automatically set the conditions without operator input. The radiation imaging system described in Embodiment 7 is merely illustrative, and the semiconductor device described in Embodiment 1 may be applied to other systems.

[0092] [Other embodiments] It should be noted that the present invention is not limited to the embodiments and modifications described above, and many modifications are possible within the technical concept of the present invention. For example, all or part of the different embodiments and modifications described above may be combined and implemented.

[0093] For example, the semiconductor device described in the embodiment may be applied to a detector using a SPAD (single-photon avalanche diode) and an imaging system equipped therewith.

[0094] The semiconductor device described in the embodiment is not limited to imaging applications. For example, it can also be applied to distance measuring devices (devices for distance measurement using focus detection or TOF (Time of Flight)), photometric devices (devices for measuring the amount of incident light), and so on.

[0095] The photoelectric conversion device to which the present invention can be applied is not limited to a specific form, and may be, for example, a front-illuminated sensor or a back-illuminated sensor. Alternatively, it may be a stacked type photoelectric conversion device in which a semiconductor chip equipped with a light-receiving section and a semiconductor chip equipped with an electrical circuit such as a logic circuit are stacked.

[0096] Various devices equipped with a semiconductor device according to the embodiment are also included in the embodiments of the present invention. The device according to the embodiment may include at least one of the following six: an optical device corresponding to the semiconductor device, a control device for controlling the semiconductor device, a processing device for processing information obtained from the semiconductor device, a display device for displaying information obtained from the semiconductor device, a storage device for storing information obtained from the semiconductor device, and a mechanical device that operates based on information obtained from the semiconductor device.

[0097] This specification discloses at least the following matters. The reference numerals provided below for reference are merely examples of disclosures and do not limit the scope of disclosure. [Item 1] Semiconductor layer (SL2), An insulating layer (IL12) is laminated on the semiconductor layer (SL2), A conductive through via (219) extends through the semiconductor layer (SL2) into the interior of the insulating layer (IL12) and has a recess at its end on the insulating layer (IL12) side, The device comprises a conductive connecting member (215) disposed in the insulating layer (IL12), the latter having a portion of its side surface in contact with the inner surface of the recess of the through via (219), A portion of the side surface of the connecting member (215) that is in contact with the through via (219) extends from the insulating layer (IL12) side to the semiconductor layer (SL2) side with respect to the extension line of the interface (P2) between the insulating layer (IL12) and the semiconductor layer (SL2). A semiconductor device characterized by the following features. [Matter 2] Furthermore, the first substrate (11) comprises a first semiconductor layer (SL1) and a first insulating layer (IL11), The insulating layer (IL12) and the semiconductor layer (SL2) are formed on the second substrate (21). The first substrate (11) and the second substrate (21) are joined together such that the first insulating layer (IL11) and the insulating layer (IL12) are adjacent to each other. A semiconductor device as described in item 1, characterized by the features described above. [Matter 3] The first semiconductor layer (SL1) includes a photoelectric conversion element, and the second substrate (21) includes an electrical circuit that processes the signal output by the first substrate (11). A semiconductor device as described in item 2, characterized by the features described above. [Matter 4] Furthermore, it comprises a third substrate (31) including a third semiconductor layer (SL3) and a third insulating layer (IL22), The insulating layer (IL12) and the semiconductor layer (SL2) are formed on a second substrate (21), and the second substrate further comprises a second insulating layer (IL21) formed on the side opposite to the insulating layer (IL12) relative to the semiconductor layer (SL2). The third substrate (31) and the second substrate (21) are joined together such that the second insulating layer (IL21) and the third insulating layer (IL22) are adjacent to each other. A semiconductor device as described in any one of items 1 to 3, characterized by the features described herein. [Matter 5] The through via (219) comprises a conductive first core material (2192) and a conductive first covering material (2191) that covers the first core material. A semiconductor device according to any one of items 1 to 4, characterized by the features described herein. [Matter 6] The thickness of the first covering material (TS23, TS24) covering the side surface of the first core material is approximately equal to the thickness of the first covering material (TB23, TB24) covering the bottom surface of the recess of the first core material. A semiconductor device as described in item 5, characterized by the features described herein. [Matter 7] The thickness (TS22, TS25) of the first covering material covering the side surface of the first core material is smaller than the thickness (TB22, TB25) of the first covering material covering the bottom surface of the recess of the first core material. A semiconductor device as described in item 5, characterized by the features described herein. [Matter 8] The connecting member (215) has a conductive second core material (2152) and a conductive second covering material (2151) that covers the second core material. A semiconductor device as described in any one of items 1 to 7, characterized by the features described herein. [Matter 9] The thickness of the second covering material covering the side surface of the second core material (TS12, TS13) is approximately equal to the thickness of the second covering material covering the end face of the second core material on the through via side (TB12-TB22, TB13-TB23). A semiconductor device as described in item 8, characterized by the features described above. [Matter 10] The thickness of the second covering material covering the side surface of the second core material (TS14, TS15) is smaller than the thickness of the second covering material covering the end face of the second core material on the through via side (TB14-TB24, TB15-TB25). A semiconductor device as described in item 8, characterized by the features described above. [Matter 11] A semiconductor device (910) described in any one of items 1 to 10, The system comprises an optical device (940) corresponding to the aforementioned semiconductor device, An imaging device characterized by the following features. [Matter 12] A semiconductor device (101) described in any one of items 1 to 10, A radiation source (1202) that irradiates the imaging target (S) with radiation, A radiation imaging system characterized by having the following features. [Matter 13] A semiconductor device (101) described in any one of items 1 to 10, Optical device (OPT) corresponding to the aforementioned semiconductor device, Control device (CTRL) for controlling the semiconductor device, A processing unit (PRCS) for processing information obtained from the aforementioned semiconductor device, A display device (DSPL) that displays information obtained from the aforementioned semiconductor device, A memory device (MMRY) for storing information obtained from the semiconductor device, and A mechanical device (MCHN) that operates based on information obtained from the aforementioned semiconductor device, A device comprising at least one of the six of the following, A device characterized by the following features. [Matter 14] The process involves preparing a second substrate (21) comprising a semiconductor layer (SL2) on which semiconductor elements are formed, and an element isolation region (210) for separating the semiconductor elements, wherein an insulating layer (IL12) is provided so as to cover the semiconductor layer (SL2) and the element isolation region (210), A step of forming a first opening (OP21) in the second substrate (21) that penetrates the insulating layer (IL12) and reaches a part of the element isolation region (210), The process involves filling the first opening (OP21) with a conductive material to form a conductive connecting member (215), A step of forming a second opening (TH) in the second substrate (21) that penetrates the semiconductor layer (SL2) and the element isolation region (210) and reaches a part of the insulating layer (IL12), exposing a part of the connecting member (215), The process includes the step of filling the second opening (TH) with a conductive material to form a conductive through via (219), An electrical connection structure is formed by joining a conductive through-via (219) that penetrates the semiconductor layer (SL2) and extends into the interior of the insulating layer (IL12), and having a recess at its end on the insulating layer (IL12) side, and a conductive connecting member (215) that is disposed in the insulating layer (IL12), with a portion of its side surface abutting the inner surface of the recess of the through-via (219). A method for manufacturing a semiconductor device, characterized by the following: [Matter 15] A portion of the side surface of the connecting member (215) that is in contact with the through via (219) extends from the insulating layer (IL12) side to the semiconductor layer (SL2) side with respect to the extension line of the interface (P2) between the insulating layer (IL12) and the semiconductor layer (SL2). A method for manufacturing a semiconductor device as described in item 14. [Matter 16] A step of preparing a first substrate (11) including a first semiconductor layer (SL1) and a first insulating layer (IL11), The process further comprises the step of joining the second substrate (21) and the first substrate (11) such that the first insulating layer (IL11) and the insulating layer (IL12) are adjacent to each other. A method for manufacturing a semiconductor device as described in item 14 or 15. [Matter 17] The second substrate comprises a second insulating layer (IL21) formed on the side opposite to the insulating layer (IL12) with respect to the semiconductor layer (SL2), A step of preparing a third substrate (31) including a third semiconductor layer (SL3) and a third insulating layer (IL22), The method further comprises the step of joining the third substrate (31) and the second substrate (21) such that the second insulating layer (IL21) and the third insulating layer (IL22) are adjacent to each other. A method for manufacturing a semiconductor device as described in any one of items 14 to 16. [Matter 18] The step of forming the through via (219) is as follows: A step of forming a conductive first coating material (2191) in the second opening (TH), The process includes the step of forming a conductive first core material (2192) in the second opening (TH) in which the first covering material (2191) is formed. A method for manufacturing a semiconductor device as described in any one of items 14 to 17. [Matter 19] In the process of forming the previous coating material (2191), The first covering material (2191) is formed such that the thickness of the first covering material covering the side surface of the first core material (TS23, TS24) and the thickness of the first covering material covering the end face of the first core material on the insulating layer side (TB23, TB24) are approximately equal. A method for manufacturing a semiconductor device as described in item 18. [Matter 20] In the process of forming the previous coating material (2191), The first covering material (2191) is formed such that the thickness of the first covering material (TS22, TS25) covering the side surface of the first core material is smaller than the thickness of the first covering material (TB22, TB25) covering the end face of the first core material on the insulating layer side. A method for manufacturing a semiconductor device as described in item 18. [Matter 21] The step of forming the connecting member (215) is as follows: The process involves forming a second covering material (2151) within the first opening (OP21), The process includes the step of forming a conductive second core material (2152) within the first opening (OP21) where the second covering material is formed. A method for manufacturing a semiconductor device as described in any one of items 14 to 20. [Matter 22] In the process of forming the previous 2 coating material (2151), The thickness of the second covering material covering the side surface of the second core material (TS12, TS13) is approximately equal to the thickness of the second covering material covering the end face of the second core material on the through via side (TB12-TB22, TB13-TB23) when the second covering material is formed. A method for manufacturing a semiconductor device as described in item 21. [Matter 23] In the process of forming the previous 2 coating material (2151), The thickness of the second covering material covering the side surface of the second core material (TS14, TS15) is smaller than the thickness of the second covering material covering the end face of the second core material on the through via side (TB14-TB24, TB15-TB25) when the second covering material is formed. A method for manufacturing a semiconductor device as described in item 21. [Explanation of Symbols]

[0098] 11...Sensor board / 21...First circuit board / 31...Second circuit board / 100...Photoelectric converter / 201...Photoelectric converter element / 210...Element isolation region / 211...Silicide layer / 215...Connecting member / 216...Insulating film / 217...Wiring pattern / 218...Insulating layer / 219...Through-through via / 230...Contact plug / 2151...Covering material / 2152...Core material / 2191 ...Coating material / 2192...Core material / E11, E12, E21, E22...Bonding electrode / IL1...First insulating layer / IL11, IL12...Insulating layer / IL2...Second insulating layer / IL21, IL22...Insulating layer / OP21...First opening / OP22...Second opening / SL1...First semiconductor layer / SL2...Second semiconductor layer / SL2SUB...Second semiconductor substrate / SL3...Third semiconductor layer / TH...Opening

Claims

1. Semiconductor layer, An insulating layer laminated on the semiconductor layer, A conductive through via extends through the semiconductor layer into the interior of the insulating layer and has a recess at its end on the insulating layer side, The insulating layer comprises a conductive connecting member, the latter having a portion of its side surface in contact with the inner surface of the recess of the through via, The portion of the side surface of the connecting member that is in contact with the through via extends from the insulating layer side to the semiconductor layer side with respect to the extension line of the interface between the insulating layer and the semiconductor layer. A semiconductor device characterized by the following features.

2. Furthermore, the first substrate comprises a first semiconductor layer and a first insulating layer. The insulating layer and the semiconductor layer are formed on the second substrate. The first substrate and the second substrate are joined together such that the first insulating layer and the insulating layer are adjacent to each other. The semiconductor device according to feature 1.

3. The first semiconductor layer includes a photoelectric conversion element, and the second substrate includes an electrical circuit for processing the signal output by the first substrate. The semiconductor device according to claim 2.

4. Furthermore, the third substrate includes a third semiconductor layer and a third insulating layer, The insulating layer and the semiconductor layer are formed on a second substrate, and the second substrate further comprises a second insulating layer formed on the side opposite to the insulating layer relative to the semiconductor layer. The third substrate and the second substrate are joined together such that the second insulating layer and the third insulating layer are adjacent to each other. The semiconductor device according to feature 1.

5. The through via comprises a conductive first core material and a conductive first covering material that covers the first core material. A semiconductor device according to any one of claims 1 to 4.

6. The thickness of the first covering material covering the side surface of the first core material is approximately equal to the thickness of the first covering material covering the bottom surface of the recess of the first core material. The semiconductor device according to feature 5.

7. The thickness of the first covering material covering the side surface of the first core material is smaller than the thickness of the first covering material covering the bottom surface of the recess of the first core material. The semiconductor device according to feature 5.

8. The connecting member comprises a conductive second core material and a conductive second covering material that covers the second core material. A semiconductor device according to any one of claims 1 to 4.

9. The thickness of the second covering material covering the side surface of the second core material is approximately equal to the thickness of the second covering material covering the end face of the second core material on the through via side. The semiconductor device according to feature 8.

10. The thickness of the second covering material covering the side surface of the second core material is less than the thickness of the second covering material covering the end face of the second core material on the through via side. The semiconductor device according to feature 8.

11. A semiconductor device according to any one of claims 1 to 4, The optical device comprises the aforementioned semiconductor device, An imaging device characterized by the following features.

12. A semiconductor device according to any one of claims 1 to 4, A radiation source that irradiates the object to be imaged with radiation, A radiation imaging system characterized by having the following features.

13. A semiconductor device according to any one of claims 1 to 4, Optical device corresponding to the aforementioned semiconductor device, Control device for controlling the aforementioned semiconductor device, A processing device for processing information obtained from the aforementioned semiconductor device, A display device that displays information obtained from the aforementioned semiconductor device, A memory device for storing information obtained from the aforementioned semiconductor device, and A mechanical device that operates based on information obtained from the aforementioned semiconductor device, A device comprising at least one of the six of the following, A device characterized by the following features.

14. A step of preparing a second substrate comprising a semiconductor layer on which semiconductor elements are formed and an element isolation region for separating the semiconductor elements, wherein an insulating layer is provided so as to cover the semiconductor layer and the element isolation region, A step of forming a first opening in the second substrate that penetrates the insulating layer and reaches a part of the element isolation region, The process involves filling the first opening with a conductive material to form a conductive connecting member, A step of forming a second opening in the second substrate that penetrates the semiconductor layer and the element isolation region, reaches a part of the insulating layer, and exposes a part of the connecting member, The process includes the step of filling the second opening with a conductive material to form a conductive through via, An electrical connection structure is formed by joining a conductive through-via that penetrates the semiconductor layer and extends into the interior of the insulating layer, having a recess at its end on the insulating layer side, and a conductive connecting member disposed in the insulating layer, with a portion of its side surface in contact with the inner surface of the recess of the through-via. A method for manufacturing a semiconductor device, characterized by the following:

15. The portion of the side surface of the connecting member that is in contact with the through via extends from the insulating layer side to the semiconductor layer side with respect to the extension line of the interface between the insulating layer and the semiconductor layer. The method for manufacturing a semiconductor device according to claim 14.

16. A step of preparing a first substrate including a first semiconductor layer and a first insulating layer, The process further comprises the step of joining the second substrate and the first substrate such that the first insulating layer and the insulating layer are adjacent to each other. The method for manufacturing a semiconductor device according to claim 14.

17. The second substrate comprises a second insulating layer formed on the side opposite to the insulating layer relative to the semiconductor layer, A step of preparing a third substrate including a third semiconductor layer and a third insulating layer, The method further comprises the step of joining the third substrate and the second substrate such that the second insulating layer and the third insulating layer are adjacent to each other. The method for manufacturing a semiconductor device according to claim 14.

18. The step of forming the through via is, The process involves forming a conductive first coating material within the second opening, The process includes the step of forming a conductive first core material in the second opening where the first covering material is formed, A method for manufacturing a semiconductor device according to any one of claims 14 to 17.

19. In the process of forming the aforementioned first coating material, The first covering material is formed such that the thickness of the first covering material covering the side surface of the first core material is approximately equal to the thickness of the first covering material covering the end surface of the first core material on the insulating layer side. The method for manufacturing a semiconductor device according to claim 18, characterized in that it is a semiconductor device.

20. In the process of forming the aforementioned first coating material, The first covering material is formed such that the thickness of the first covering material covering the side surface of the first core material is smaller than the thickness of the first covering material covering the end surface of the first core material on the insulating layer side. The method for manufacturing a semiconductor device according to claim 18, characterized in that it is a semiconductor device.

21. The step of forming the connecting member is: The process involves forming a second covering material within the first opening, The process includes the step of forming a conductive second core material within the first opening where the second covering material is formed, A method for manufacturing a semiconductor device according to any one of claims 14 to 17.

22. In the process of forming the two coating materials described above, The thickness of the second covering material covering the side surface of the second core material is approximately equal to the thickness of the second covering material covering the end face of the second core material on the through via side, as the second covering material is formed. A method for manufacturing a semiconductor device according to claim 21, characterized in that it is a semiconductor device.

23. In the process of forming the two coating materials described above, The thickness of the second covering material covering the side surface of the second core material is smaller than the thickness of the second covering material covering the end face of the second core material on the through via side. A method for manufacturing a semiconductor device according to claim 21, characterized in that it is a semiconductor device.

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