Semiconductor device and method for manufacturing a semiconductor device

Abstract

This disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device, and aims to provide a semiconductor device and a method for manufacturing a semiconductor device that can uniformly bond a conductor plate covered with a sealing material and a metal plate by applying pressure to a portion of the conductor plate exposed from the sealing material. [Solution] The semiconductor device of this disclosure comprises a conductor plate having a first main surface and a second main surface on opposite sides of the conductor plate, a semiconductor element bonded to the first main surface of the conductor plate, a sealing material covering a part of the first main surface of the conductor plate and the semiconductor element, and a metal plate bonded to the second main surface of the conductor plate, wherein the first main surface of the conductor plate has a pressing portion which is an area exposed from the sealing material.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device.

Background Art

[0002] Patent Document 1 discloses a technique of soldering a conductor plate on which a semiconductor element is mounted to an insulating substrate with a circuit pattern. However, when the conductor plate and the insulating substrate are soldered, there is a problem that cracks occur in the solder joint due to stress such as a cycle test.

[0003] To solve this problem, there is a method of adopting a sintering joint or a solid-phase joint that is superior in joint life to soldering. This sintering joint and solid-phase joint require a pressure bonding process in a high-temperature environment of about 300 degrees.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, when applying the above method to the joining of a conductor plate covered with a sealing material and a metal plate, the sealing material softens in the high-temperature environment of the pressure bonding process. As a result, cracking or deformation of the sealing material occurs around the pressure-applied portion, making it difficult to obtain a uniform joint.

[0006] In order to solve the above problems, an object of the present disclosure is to provide a semiconductor device and a method for manufacturing a semiconductor device capable of uniformly joining a conductor plate covered with a sealing material and a metal plate by pressing a part of the conductor plate exposed from the sealing material.

Means for Solving the Problems

[0007] Aspects of the present disclosure preferably include a semiconductor device comprising a conductor plate having a first main surface and a second main surface on opposite sides, a semiconductor element bonded to the first main surface of the conductor plate, a sealing material covering a part of the first main surface of the conductor plate and the semiconductor element, and a metal plate bonded to the second main surface of the conductor plate, wherein the first main surface of the conductor plate has a pressing portion which is an area exposed from the sealing material. [Effects of the Invention]

[0008] According to an aspect of this disclosure, the conductor plate covered with the sealing material and the metal plate can be uniformly joined by applying pressure to a portion of the conductor plate exposed from the sealing material. [Brief explanation of the drawing]

[0009] [Figure 1] This is a plan view showing a semiconductor device according to Embodiment 1 of the present disclosure. [Figure 2] This is a first figure showing the sealing process of a semiconductor device according to Embodiment 1 of the present disclosure. [Figure 3] This is a second figure showing the sealing process of a semiconductor device according to Embodiment 1 of the present disclosure. [Figure 4] This is a third figure showing the sealing process of a semiconductor device according to Embodiment 1 of the present disclosure. [Figure 5] This is the fourth figure showing the sealing process of a semiconductor device according to Embodiment 1 of the present disclosure. [Figure 6] This is a plan view showing a semiconductor device according to Embodiment 2 of the present disclosure. [Figure 7] This figure shows the thermal interference of a semiconductor device relating to a comparative example. [Figure 8] This figure shows the thermal interference of a semiconductor device according to Embodiment 2 of the present disclosure. [Figure 9] This is the first figure showing the sealing process of a semiconductor device according to Embodiment 2 of the present disclosure. [Figure 10] This is a second figure showing the sealing process of a semiconductor device according to Embodiment 2 of the present disclosure. [Figure 11] This is a third figure showing the sealing process of a semiconductor device according to Embodiment 2 of the present disclosure. [Figure 12] The fourth figure showing the sealing process of the semiconductor device according to Embodiment 2 of the present disclosure. [Figure 13] A plan view showing a semiconductor device according to Embodiment 3 of the present disclosure. [Figure 14] A cross-sectional view taken along A-A' of FIG. 13. [Figure 15] A cross-sectional view taken along B-B' of FIG. 13.

Embodiments for Carrying Out the Invention

[0010] The semiconductor device according to the present disclosure will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and the repeated description may be omitted. In the present disclosure, the surface facing the first main surface is defined as the second main surface.

[0011] Embodiment 1 FIG. 1 is a plan view showing a semiconductor device according to Embodiment 1 of the present disclosure. The semiconductor device 100 includes a conductor plate 10. The conductor plate 10 is made of a material mainly composed of, for example, copper.

[0012] A plurality of semiconductor elements 20 are joined to the first main surface of the conductor plate 10 by a connecting material. This connecting material is, for example, a sintered joining material and is made of a material mainly composed of, for example, silver or copper.

[0013] The semiconductor element 20 is a switching element such as, for example, a MOSFET. When the semiconductor element 20 is a MOSFET, the conductor plate 10 can be used as a drain electrode. When the semiconductor element 20 is a MOSFET, a control pad 22 is provided on the semiconductor element 20. The control pad 22 is, for example, a gate pad or a Kelvin source pad. The control pad 22 is electrically connected to the signal terminal 26 by using a wire 24 made of, for example, aluminum, copper or silver.

[0014] The semiconductor element 20 is made of a heat-resistant material. The heat-resistant material is, for example, silicon carbide. When the semiconductor element 20 is made of silicon carbide, the current capacity per semiconductor element 20 becomes small. Therefore, in order to secure the output capacity in the semiconductor device 100, the semiconductor elements 20 are often mounted on the conductor plate 10 in plurality.

[0015] Furthermore, an electrode material 50 is connected to the first main surface of the semiconductor element 20 by a bonding material. The electrode material 50 is made of, for example, copper. This bonding material is, for example, a sintered bonding material and is made of a material mainly composed of silver or copper.

[0016] When a plurality of semiconductor elements 20 are mounted on the conductor plate 10, the electrode material is configured to electrically connect the first main surfaces of the plurality of semiconductor elements 20. Therefore, when the semiconductor element 20 is a MOSFET, the electrode material can be used as a source electrode.

[0017] The semiconductor element 20 and the electrode material 50 are joined by, for example, sintered joining. For the sintered joining of the semiconductor element 20 and the electrode material 50, there is no need to adopt a process involving pressure in a high-temperature environment for two reasons. The first reason is that the connection area between the electrode material 50 and the first main surface of the semiconductor element 20 is smaller than the connection area between the semiconductor element 20 and the conductor plate 10 on the second main surface. The second reason is that the heat dissipation property of the semiconductor element 20 is determined depending on the state on the second main surface side of the semiconductor element 20. Due to the above two reasons, there is little need to consider the thickness uniformity and density in the joining of the semiconductor element 20 and the electrode material 50. Therefore, it is preferable to adopt a process not involving pressure in a high-temperature environment for the sintered joining of the semiconductor element 20 and the electrode material 50.

[0018] The conductor plate 10 and the semiconductor element 20 are joined, for example, by sintering. A process that does not involve pressurization under high temperature conditions may be used for the sintering of the conductor plate 10 and the semiconductor element 20. For example, if the semiconductor element 20 is a MOSFET made of silicon carbide, its thickness is generally 10 mm or less. Such a semiconductor element 20 exhibits little warping change with temperature fluctuations. Therefore, even when a process that does not involve pressurization is used for the sintering of such a semiconductor element 20 and the conductor plate 10, a uniform bond can be easily obtained.

[0019] On the other hand, a pressurized process may be used for the sintering bond between the conductive plate 10 and the semiconductor element 20. The semiconductor element 20 is made of a heat-resistant material and is thin, with a thickness of several hundred μm or less. Therefore, by using a buffer material during pressurization, the conductive plate 10 and the semiconductor element 20 can be joined well. In other words, even when a pressurized process is used in the sintering bond between such a semiconductor element 20 and conductive plate 10, a uniform bond can be easily obtained.

[0020] A portion of the first main surface of the conductor plate 10 and the first main surface of the semiconductor element 20 are covered with a sealing material 30. The sealing material 30 is made of, for example, an epoxy resin-based material. The areas exposed from the sealing material 30 at both ends of the first main surface of the conductor plate 10 are referred to as pressing portions 12. In other words, the pressing portions 12 according to this embodiment are areas that include two opposing sides of the first main surface of the conductor plate 10.

[0021] In this embodiment, the multiple pressing portions 12 are arranged on multiple straight lines 16 that pass through the center of gravity 14 of the conductor plate 10. For example, the multiple pressing portions 12 are configured such that a straight line connecting a particular pressing portion 12 and other pressing portions 12 includes a pair of pressing portions that pass through the center of gravity 14 of the conductor plate 10. The sealing process of the semiconductor device 100 with the sealing material 30 will be described later.

[0022] A metal plate 40 is bonded to the second main surface side of the conductor plate 10. The sealing material 30 is provided so as to cover a portion of the first main surface of the conductor plate 10, the first main surface of the semiconductor element 20, the first main surface of the control pad 22, and a portion of the first main surface of the wire 24 and the signal terminal 26. In other words, the sealing material 30 is connected to the metal plate 40.

[0023] The metal plate 40 is, for example, part of a circuit pattern formed on an insulating substrate. The insulating substrate is, for example, a ceramic substrate such as silicon nitride. Multiple insulating substrates are used to form a higher-level semiconductor device. The circuit pattern is made of, for example, a material mainly composed of copper.

[0024] The conductor plate 10 has a connecting pattern on the surface facing the circuit pattern, with the insulating substrate in between. The connecting pattern is made of a material mainly composed of copper, for example.

[0025] The connection pattern is a pattern for connecting to a cooler. The cooler is installed to cool the higher-level semiconductor device and is made of a material mainly composed of copper or aluminum, for example. The cooler may have multiple protrusions on pin fins and be cooled by cooling water. Alternatively, the cooler may have multiple protrusions on blades and be air-cooled by blowing air between the blades.

[0026] The cooler and the insulating substrate are connected, for example, via a case. The case is installed, for example, on top of the cooler, surrounding the insulating substrate. The inside of the case is filled with a sealing material, for example, gel. The case is also provided with case electrodes. The case electrodes are electrically connected to the corresponding circuit patterns on the insulating substrate. An inverter unit is formed by connecting, for example, output terminals and capacitor terminals to the case electrodes.

[0027] The connection between the connection pattern and the cooler is made, for example, by soldering. The connection pattern is larger than the circuit pattern. Also, the connection pattern is far from the semiconductor element 20, which is the heat source of the semiconductor device 100, and close to the cooler. Furthermore, since the connection pattern is connected to the circuit pattern via a conductive plate 10 beneath the semiconductor element 20, the temperature does not rise easily due to heat diffusion, and the temperature gradient is gentle. For these reasons, there is little need to use sintering bonding to connect the connection pattern and the cooler.

[0028] Furthermore, when the connection pattern and the cooler are joined by sintering, the warping of both the cooler and the insulating substrate changes due to temperature changes during the joining process. As a result, applying sintering becomes difficult. For these reasons, sufficient power cycle life is ensured by joining the connection pattern and the cooler by soldering.

[0029] The conductor plate 10 and the metal plate 40 are joined by a bonding method involving pressure. This bonding method may be, for example, sintering bonding or solid-state bonding. If the bonding method involves sintering bonding, the conductor plate 10 and the metal plate 40 are joined with a sintering bonding material. The sintering bonding material may be, for example, a material mainly composed of silver or copper. The sintering bonding process may include, for example, a step of printing silver paste, a step of drying the printed silver paste, and a sintering bonding step.

[0030] On the other hand, when the joining method involving pressure is solid-phase joining, the conductor plate 10 and the metal plate 40 are joined with a solid-phase joining material. The solid-phase joining material is, for example, a material mainly composed of silver or copper.

[0031] The bonding of the conductor plate 10 and the metal plate 40 is performed under a specific high-temperature environment that exceeds the glass transition temperature of the sealing material 30. The glass transition temperature of the sealing material 30 is, for example, 200 degrees. The specific high temperature is, for example, 300 degrees.

[0032] The pressure used in joining the conductive plate 10 and the metal plate 40 is applied by pressing the pressing part 12. The pressure applied during pressing needs to be optimized according to the type or process of the sintered bonding material or solid-state bonding material used. The pressure is, for example, several MPa to tens of MPa.

[0033] Before explaining the advantages obtained by joining the conductive plate 10 and the metal plate 40 according to this embodiment, we will first describe in detail the problems that arise in joining a conductive plate and a metal plate according to a comparative example. Patent Document 1 discloses a technique for soldering a conductive plate on which a semiconductor element is mounted to an insulating substrate with a circuit pattern.

[0034] However, when a conductive plate and an insulating substrate are soldered together, there is a problem in that cracks can form in the solder joint due to stress from cycle testing, etc. When cracks form in the solder joint, the thermal conductivity of the solder joint decreases, which increases the thermal resistance between the semiconductor element and the cooler. As a result, the maximum temperature of the semiconductor element during power cycle testing increases, leading to a problem of reduced power cycle life.

[0035] To address the aforementioned challenges, one approach is to employ sintering or solid-state bonding, which offers superior bonding life compared to soldering. However, when joining conductive plates large enough to accommodate multiple semiconductor elements using sintering or solid-state bonding, a high-temperature, pressurized bonding process at around 300 degrees Celsius is required.

[0036] On the other hand, in sintering bonding processes that directly connect simple semiconductor elements to circuit patterns, the warping of the semiconductor elements in high-temperature environments is small, so processes that do not involve pressurization can be used. In contrast, consider the case where a circuit pattern is sintered bonded to a conductor plate with a complex structure, such as one on which multiple semiconductor elements are mounted, with wiring routed inside and the top surface covered with a sealing material. In this case, warping occurs in the conductor plate, and the shape of this warping changes as the temperature rises during sintering bonding. Therefore, it becomes necessary to control the shape change by applying pressure to the conductor plate while bonding.

[0037] However, in the case of a conductive plate whose top surface is covered with a sealing material, it is necessary to apply pressure to the conductive plate through the sealing material. Here, sealing materials commonly used in semiconductor devices have a glass transition temperature of around 200 degrees Celsius. Therefore, in the aforementioned bonding process, the sealed material that is pressed changes its physical properties in a temperature environment above the glass transition temperature, making it prone to softening. As a result, the resin strength or peel resistance of the sealing material changes. This has led to problems such as cracking or deformation of the sealing material around the pressurized area, delamination at the bonding interface between the conductive plate and the sealing material, and difficulty in obtaining a uniform bond because the pressurizing force is not evenly transmitted to the conductive substrate.

[0038] The advantages obtained by joining the conductive plate 10 and the metal plate 40 according to this embodiment will be explained. As a comparative example, consider the case in which a conductive plate, which is entirely covered with a sealing material, and a metal plate are joined by a joining method involving pressure.

[0039] In this case, the pressure required to join the conductor plate and the metal plate is applied by pressing the sealing material covering the conductor plate. This pressing is performed in a high-temperature environment exceeding the glass transition temperature of the sealing material covering the conductor plate. As a result, the sealing material covering the conductor plate deforms, peels off from the conductor plate or semiconductor element, or cracks. In other words, the sealing material deteriorates. Therefore, the joining method in the comparative example had the problem of reduced manufacturability or reliability of the resulting semiconductor device.

[0040] On the other hand, in this embodiment, the pressure required to join the conductor plate 10 and the metal plate 40 is applied by pressing the pressing part 12. That is, the conductor plate 10 and the metal plate 40 are pressurized and joined by applying a load to the pressing part 12, thus avoiding pressure being applied to the sealing material 30. As a result, deterioration of the sealing material 30 can be avoided, and the conductor plate 10 and the metal plate 40 covered with the sealing material 30 can be joined uniformly.

[0041] Furthermore, the multiple pressing portions 12 according to this embodiment are arranged on multiple straight lines 16 that pass through the center of gravity 14 of the conductor plate 10. That is, when the multiple pressing portions 12 are pressed, the load is applied uniformly to the entire conductor plate 10. As a result, the conductor plate 10 covered with the sealing material 30 and the metal plate 40 can be joined more uniformly.

[0042] Although this description shows a method of joining the conductor plate 10 and the metal plate 40 using sintering or solid-state bonding, it is not limited to these methods. In other words, the joining of the conductor plate 10 and the metal plate 40 can be selected from among joining methods involving heating and pressurization, provided that the method is highly reliable.

[0043] Furthermore, in the joining method according to this embodiment, the conductor plate 10 and the metal plate 40 can be joined uniformly, thus offering the advantage of improved yield and productivity.

[0044] A specific example of the encapsulation process for the semiconductor device 100 will be described. Figure 2 is a first diagram showing the encapsulation process for a semiconductor device according to Embodiment 1 of this disclosure. Figure 2 shows an example of the configuration of the bonded body 200, which is the state before the semiconductor device 100 is encapsulated. The bonded body 200 comprises a conductive plate 10. A semiconductor element 20 is bonded to the conductive plate 10, and an electrode material 50 is bonded to the semiconductor element 20.

[0045] Figure 3 is a second diagram showing the sealing process of a semiconductor device according to Embodiment 1 of the present disclosure. Figure 3 shows the state in which the bonded body 200 is assembled into a mold for sealing.

[0046] The molding die consists of a lower die 60 that supports the conductor plate 10 from the second main surface side and an upper die 62 that contacts the first main surface side of the conductor plate 10 with a projection. The area where this projection contacts the conductor plate 10 becomes the pressing portion 12.

[0047] Figure 4 is a third diagram showing the sealing process of a semiconductor device according to Embodiment 1 of the present disclosure. Figure 4 shows the state in which the bonded body 200 is sealed by sealing a sealing material 30 in a mold. The sealing material 30 is made of, for example, epoxy resin. This sealing is performed, for example, by a transfer mold sealing method.

[0048] Furthermore, the encapsulation shown in Figure 4 may also be performed with a buffer film sandwiched between the lower mold 60 and the conductor plate 10, and between the upper mold 62 and the conductor plate 10. This configuration prevents epoxy resin from adhering to areas other than those in contact with the sealing material 30 on the surface of the conductor plate 10.

[0049] Alternatively, after the sealing process shown in Figure 4 is complete, the epoxy resin adhering to areas other than those in contact with the sealing material 30 on the surface of the conductor plate 10 may be removed to expose the surface of the conductor plate 10. In this embodiment, the area on the surface of the conductor plate 10 to which the epoxy resin adheres can be limited to only the area in contact with the sealing material 30.

[0050] Figure 5 is a fourth figure showing the sealing process of a semiconductor device according to Embodiment 1 of the present disclosure. The process shown in Figures 2 to 4 creates pressed portions 12 at both ends of the first main surface of the conductor plate 10, which are areas exposed from the sealing material 30.

[0051] Multiple pressing portions 12 may be provided. In this embodiment, the pressing portions 12 are two regions exposed from the sealing material 30 at both ends of the first main surface of the conductor plate 10. The two pressing portions 12 are configured to be arranged on multiple straight lines passing through the center of gravity 14 of the conductor plate 10.

[0052] Just as the pressing portion 12 is exposed from the sealing material 30, the signal terminal 26 and electrode material 50 are also exposed in the necessary places depending on the application. The signal terminal 26 can be used as a terminal by being exposed and extended from one side of the sealing material 30. The electrode material 50 can be used as an electrode by being exposed from the top surface of the sealing material.

[0053] Embodiment 2 Figure 6 is a plan view showing a semiconductor device according to Embodiment 2 of the present disclosure. The semiconductor device 100a according to this embodiment differs from the semiconductor device 100 in that the pressing portion 12a is an area exposed from a notch in the sealing material 30a, and that a plurality of semiconductor elements are arranged in a zigzag pattern.

[0054] The semiconductor device 100a includes a sealing material 30a. The sealing material 30a has four notches in a plan view. The pressing portion 12a in this embodiment is a region that is exposed from these notches and includes the four corners of the first main surface of the conductor plate 10. In this embodiment, the multiple pressing portions 12a are exposed such that they are connected by multiple straight lines passing through the centroid of the conductor plate 10.

[0055] The semiconductor device 100a also includes semiconductor elements 20a to 20f. The semiconductor elements 20a to 20f are arranged in a zigzag pattern along the longitudinal direction of the first main surface of the conductor plate 10 so that their respective heat-generating centers are not aligned in a straight line. Furthermore, the semiconductor elements 20a and 20f, which are located at both ends, are positioned closer to the center of the first main surface in the short direction of the first main surface compared to one or more of the other semiconductor elements 20b to 20e. As a result, the notches in the sealing material 30a are provided in the vicinity of the semiconductor elements 20a and 20f.

[0056] The advantages obtained by joining the conductive plate 10 and the metal plate 40 according to this embodiment will be explained. The pressing portion 12a according to this embodiment is a region that includes the four corners of the first main surface of the conductive plate 10. Therefore, the semiconductor device 100a can reduce the longitudinal dimensions compared to the semiconductor device 100 in which the pressing portion 12 includes a region that includes two opposing sides of the first main surface of the conductive plate 10. In other words, the overall size of the semiconductor device 100a can be reduced compared to the semiconductor device 100.

[0057] Furthermore, the semiconductor elements 20a to 20f according to this embodiment are arranged in a zigzag pattern so that their respective heat-generating centers are not aligned in a straight line. This arrangement suppresses thermal interference caused by the semiconductor elements.

[0058] We will now explain in more detail the thermal interference caused by semiconductor devices. Figure 7 shows the thermal interference of a semiconductor device related to a comparative example.

[0059] In Figure 7, semiconductor elements 20a and 20f are not positioned as close to the center of the first main surface in the short-side direction compared to the other semiconductor elements 20b to 20e. That is, semiconductor elements 20a and 20f are positioned around one of the four corners of the first main surface of the conductor plate 10. As a result, semiconductor elements 20a and 20f can more easily dissipate heat to the outside of the conductor plate 10. Therefore, the thermal interference of semiconductor elements 20b to 20e is relatively larger than that of semiconductor elements 20a and 20f. In other words, semiconductor elements 20b to 20e, which are not positioned at both ends, tend to become hotter than semiconductor elements 20a and 20f, which are positioned at both ends.

[0060] Figure 8 shows the thermal interference of a semiconductor device according to Embodiment 2 of this disclosure. In Figure 8, semiconductor elements 20a and 20f are positioned closer to the center of the first main surface in the short-side direction compared to the other semiconductor elements 20b to 20e. As a result, semiconductor elements 20a and 20f have difficulty dissipating heat to the outside of the conductor plate 10. Therefore, the thermal interference of semiconductor elements 20a and 20f in Figure 8 is relatively larger than the thermal interference of semiconductor elements 20a and 20f in Figure 7. In other words, semiconductor elements 20a and 20f positioned at both ends become as hot as semiconductor elements 20b to 20e which are not positioned at both ends.

[0061] As described above, in the plurality of semiconductor elements according to this embodiment, the semiconductor elements located at both ends are positioned closer to the center of the first main surface in the short direction of the first main surface compared to one or more of the other semiconductor elements. This arrangement makes it possible to equalize the temperature of the plurality of semiconductor elements.

[0062] Furthermore, the pressing portion 12a according to this embodiment is positioned in a region created by arranging the semiconductor elements located at both ends closer to the center of the first main surface in the short-side direction of the first main surface. In other words, there is no need to create a new region to provide the pressing portion 12a. Therefore, the semiconductor device according to this embodiment can be made smaller in overall size compared to the semiconductor device according to Embodiment 1.

[0063] A specific example of the sealing process for the semiconductor device 100a will be described. Figure 9 is a first diagram showing the sealing process for a semiconductor device according to Embodiment 2 of this disclosure. Figure 9 shows an example of the configuration of the bonded body 200a, which is the state before sealing the semiconductor device 100a. The bonded body 200a comprises a conductive plate 10. Semiconductor elements 20a to 20f are bonded to the conductive plate 10, and electrode material 50 is bonded to the semiconductor elements 20a to 20f.

[0064] Figure 10 is a second diagram showing the sealing process of a semiconductor device according to Embodiment 2 of the present disclosure. Figure 10 shows the state in which the bonded body 200a is assembled into a mold for sealing.

[0065] The molding die consists of a lower die 60a that supports the conductor plate 10 from the second main surface side and an upper die 62a that contacts the first main surface side of the conductor plate 10 via a projection. This projection is configured to manufacture the notch portion of the sealing material 30a shown in Figure 6. In other words, the area in contact with the conductor plate 10 by this projection becomes the pressing portion 12a.

[0066] In this embodiment, a lower frame 64 is provided for the upper mold 62a. The lower frame 64 is made of a material mainly composed of resin, for example.

[0067] Figure 11 is a third diagram showing the sealing process of a semiconductor device according to Embodiment 2 of the present disclosure. Figure 11 shows the state in which the bonded body 200a is sealed by sealing a sealing material 30a in a mold molding die. The sealing material 30a is made of, for example, epoxy resin. This sealing is performed, for example, by a transfer mold sealing method.

[0068] Furthermore, the encapsulation shown in Figure 11 may also be performed with a buffer film sandwiched between the lower mold 60a and the conductor plate 10, and between the upper mold 62a and the conductor plate 10. This configuration prevents epoxy resin from adhering to areas other than those in contact with the sealing material 30a on the surface of the conductor plate 10.

[0069] Alternatively, after the sealing process shown in Figure 11 is complete, the epoxy resin adhering to areas other than those in contact with the sealing material 30a on the surface of the conductor plate 10 may be removed to expose the surface of the conductor plate 10. In this embodiment, the area on the surface of the conductor plate 10 to which the epoxy resin adheres can be limited to only the area in contact with the sealing material 30a.

[0070] Figure 12 is a fourth figure showing the sealing process of a semiconductor device according to Embodiment 2 of the present disclosure. The process shown in Figures 9 to 11 creates pressed portions 12a at both ends of the first main surface of the conductor plate 10, which are regions exposed from the sealing material 30a.

[0071] Multiple pressing portions 12a may be provided. In this embodiment, the pressing portion 12a is a region that includes the four corners of the first main surface of the conductor plate 10, which is exposed by the notch in the sealing material 30. In this embodiment, multiple pressing portions 12a are exposed so as to be connected by multiple straight lines passing through the center of gravity of the conductor plate 10.

[0072] Just as the pressing portion 12a is exposed from the sealing material 30a, the signal terminal 26 and electrode material 50 are also exposed in the necessary places depending on the application. The signal terminal 26 can be used as a terminal by being exposed and extended from one side of the sealing material 30. The electrode material 50 can be used as an electrode by being exposed from the top surface of the sealing material.

[0073] Embodiment 3 Figure 13 is a plan view showing a semiconductor device according to Embodiment 3 of the present disclosure. Figure 14 is a cross-sectional view along AA' of Figure 13. Figure 15 is a cross-sectional view along BB' of Figure 13. The semiconductor device 100b according to this embodiment differs from the semiconductor device 100a in that a crosslinking material 70 is provided inside the conductive plate 10a.

[0074] The semiconductor device 100b includes a conductive plate 10a. The conductive plate 10a has a crosslinking material 70 inside. The crosslinking material 70 is made of a material that is harder and has a lower thermal diffusivity than the conductive plate 10a. The crosslinking material 70 may be a single or alloyed metal material, or an insulating material such as ceramic.

[0075] The crosslinking material 70 extends in the longitudinal direction of the conductor plate 10a. The crosslinking material 70 is positioned directly below the pressing portion 12a. The crosslinking material 70 is positioned not directly below the semiconductor elements 20a to 20f.

[0076] By placing the crosslinking material 70 directly beneath the pressing portion 12a, the load applied to the pressing portion 12a can be transmitted more uniformly across the entire conductive plate 10a. Note that when a high-hardness material is used for the crosslinking material 70, the thermal diffusivity coefficient is often low. However, in this embodiment, since the crosslinking material 70 is placed at a position not directly beneath the semiconductor elements 20a to 20f, a decrease in the heat dissipation performance of the semiconductor elements can be avoided.

[0077] As described above, the semiconductor device 100b according to this embodiment has a crosslinking material 70 inside the conductive plate 10a. As a result, the semiconductor device 100b can more uniformly transmit the load applied to the pressing portion 12a across the entire conductive plate 10a.

[0078] The aspects of this disclosure are summarized below as an appendix.

[0079] (Note 1) A conductive plate having a first main surface and a second main surface facing each other, A semiconductor element bonded to the first main surface of the conductor plate, A sealing material covering a part of the first main surface of the conductor plate and the semiconductor element, The metal plate bonded to the second main surface of the conductor plate and Equipped with, The first main surface of the conductor plate has a pressing portion which is an area exposed from the sealing material. Semiconductor equipment. (Note 2) The conductor plate and the metal plate are joined together with a sintered bonding material or a solid-state bonding material. The semiconductor device described in Appendix 1. (Note 3) The pressing portion is a plurality of pressing portions arranged on a plurality of straight lines passing through the center of gravity of the conductor plate. Semiconductor device as described in Appendix 1 or 2. (Note 4) The aforementioned sealing material has a notch, The pressing portion is exposed from the notch. A semiconductor device described in any one of the appendices 1 to 3. (Note 5) The aforementioned semiconductor element has a plurality of semiconductor elements, The plurality of semiconductor elements are arranged in a zigzag pattern along the longitudinal direction of the first main surface of the conductor plate such that their respective heat-generating centers are not aligned in a straight line. The semiconductor elements located at both ends of the plurality of semiconductor elements are positioned closer to the center of the first main surface in the short direction of the first main surface compared to one or more of the other semiconductor elements. The aforementioned notches are provided near the semiconductor elements located at both ends of the plurality of semiconductor elements. Semiconductor device as described in Appendix 4. (Note 6) The conductor plate is further provided with a crosslinking material made of a material with higher hardness than the conductor plate, The bridging material extends in the longitudinal direction of the conductor plate and is positioned directly below the pressing portion. A semiconductor device described in any one of the appendices 1 to 5. (Note 7) The aforementioned crosslinking material is made of a material having a lower thermal diffusion coefficient than the conductive plate and is positioned not directly beneath the semiconductor element. Semiconductor device as described in Appendix 6. (Note 8) A method for manufacturing a semiconductor device as described in any one of the appendices 1 to 7, It has a sealing process using a mold, The mold includes an upper mold that contacts the upper surface of the conductor plate, The upper mold has a projection that contacts the pressing portion. A method for manufacturing a semiconductor device. [Explanation of symbols]

[0080] 10: Conductor board 10a: Conductor board 12: Pressing part 12a: Pressing part 14: Center of gravity 16: Straight line 20: Semiconductor elements 20a: Semiconductor device 20b: Semiconductor element 20c: Semiconductor device 20d: Semiconductor element 20e: Semiconductor element 20f: Semiconductor element 30: Sealing material 30a: Sealing material 40: Metal plate 62: Upper mold 62a: Upper mold 70: Crosslinking material 100: Semiconductor Device 100a: Semiconductor equipment 100b: Semiconductor equipment

Claims

1. A conductive plate having a first main surface and a second main surface facing each other, A semiconductor element bonded to the first main surface of the conductor plate, A sealing material covering a part of the first main surface of the conductor plate and the semiconductor element, The metal plate bonded to the second main surface of the conductor plate and Equipped with, The first main surface of the conductor plate has a pressing portion which is an area exposed from the sealing material. Semiconductor equipment.

2. The conductor plate and the metal plate are joined together with a sintered bonding material or a solid-state bonding material. The semiconductor device according to claim 1.

3. The pressing portion is a plurality of pressing portions arranged on a plurality of straight lines passing through the center of gravity of the conductor plate. The semiconductor device according to claim 1.

4. The aforementioned sealing material has a notch, The pressing portion is exposed from the notch. The semiconductor device according to claim 1.

5. The aforementioned semiconductor element has a plurality of semiconductor elements, The plurality of semiconductor elements are arranged in a zigzag pattern along the longitudinal direction of the first main surface of the conductor plate such that their respective heat-generating centers are not aligned in a straight line. The semiconductor elements located at both ends of the plurality of semiconductor elements are positioned closer to the center of the first main surface in the short direction of the first main surface compared to one or more of the other semiconductor elements. The aforementioned notches are provided near the semiconductor elements located at both ends of the plurality of semiconductor elements. The semiconductor device according to claim 4.

6. The conductor plate is further provided with a crosslinking material made of a material with higher hardness than the conductor plate, The bridging material extends in the longitudinal direction of the conductor plate and is positioned directly below the pressing portion. The semiconductor device according to claim 1.

7. The aforementioned crosslinking material is made of a material having a lower thermal diffusion coefficient than the conductive plate and is positioned not directly beneath the semiconductor element. The semiconductor device according to claim 6.

8. A method for manufacturing a semiconductor device according to claim 1, It has a sealing process using a mold, The mold includes an upper mold that contacts the upper surface of the conductor plate, The upper mold has a projection that contacts the pressing portion. A method for manufacturing a semiconductor device.

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