Circuit boards and power devices

Abstract

To provide circuit boards and power devices that can enhance resistance to thermal cycling and improve reliability. [Solution] A circuit board 50 comprising a ceramic substrate 10, a bonding layer 20 formed on one main surface 12 of the ceramic substrate 10, and a conductive layer 30 made of metal bonded to the ceramic substrate 10 via the bonding layer 20, wherein the ceramic substrate 10 has microcracks 14 consisting of voids that open on the interface side with the bonding layer 20.

Description

Technical Field

[0001] The present invention relates to a circuit board and a power device.

Background Art

[0002] Silicon nitride has high thermal conductivity and strength, and has attracted attention as an insulating heat dissipation substrate for power modules used in electric vehicles (EVs) and hybrid vehicles (HVs). Conventionally, aluminum nitride has been widely used as an insulating heat dissipation substrate material. However, in the case of power modules for large currents such as EVs, the temperature rises to about 250°C, and a large thermal stress is generated in the substrate due to the difference in thermal expansion from metals such as copper to which it is joined. As a result, aluminum nitride with low strength develops cracks and fractures. Therefore, although silicon nitride has inferior thermal conductivity compared to aluminum nitride, among general insulating ceramics, it has high thermal conductivity and its adoption is increasing due to its higher strength. The joining of a silicon nitride heat dissipation substrate and a conductor layer is generally performed by brazing using a brazing material containing a metal.

[0003] Patent Document 1 discloses a copper / ceramics joined body comprising a copper member made of copper or a copper alloy and a ceramics member, the copper member and the ceramics member being joined, and at the joining interface between the ceramics member and the copper member, an active metal compound layer made of an active metal compound is formed on the ceramics member side, and microcracks that progress from the joining interface to the inner side of the ceramics member exist in the ceramics member, and at least a part of the microcracks is filled with the active metal compound.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

[0005] Patent Document 1 states that by filling at least a portion of the microcracks with an activated metal compound, the occurrence of ceramic cracks originating from the microcracks can be suppressed, the occurrence of cracks in the ceramic member under cold and hot cycling loads can be suppressed, and the bonding strength between the ceramic member and the copper member can be improved by the anchoring effect of the activated metal compound filling the microcracks. However, the copper / ceramic bond described in Patent Document 1 had a thick Ag-Cu alloy layer derived from the bonding material, which was likely to act as a thermal barrier between the ceramic substrate and the circuit layer. Furthermore, under more severe cold and hot cycling conditions, the difference in thermal expansion coefficients between the ceramic member and the activated metal compound filling the microcracks could cause the microcracks themselves to expand, resulting in insufficient resistance to cold and hot cycling.

[0006] For these reasons, when using circuit boards for power devices that bond a ceramic heat dissipation substrate and a conductive layer, there has been a demand for circuit boards with enhanced resistance to thermal cycling.

[0007] This invention has been made in view of these circumstances, and aims to provide a circuit board and a power device that can increase resistance to thermal cycling and improve reliability. [Means for solving the problem]

[0008] (1) In order to achieve the above objective, the circuit board of the present invention employs the following means. Specifically, the circuit board of the application example of the present invention comprises a ceramic substrate, a bonding layer formed on one main surface of the ceramic substrate, and a conductive layer made of metal bonded to the ceramic substrate via the bonding layer, wherein the ceramic substrate has microcracks consisting of voids that open on the interface side with the bonding layer, and even when a thermal cycle test is performed in which one cycle consists of maintaining the temperature at -40°C for 5 minutes and maintaining the temperature at 250°C for 5 minutes, no cracks of 1 mm or more occur for more than 500 cycles.

[0009] (2) In addition, in the circuit board of the application example of (1) above, the microcracks include those with a length of 1 μm or more and 3 μm or less, and the average value of the angle of the microcracks with a length of 1 μm or more and 3 μm or less with respect to the direction perpendicular to the interface is 0° or more and 80° or less.

[0010] (3) In addition, in the circuit board of the application example of (1) or (2) above, the bonding layer is mainly composed of titanium.

[0011] (4) Furthermore, in the circuit board of any of the application examples (1) to (3) above, a second bonding layer containing titanium is formed on the other main surface of the ceramic substrate opposite to the one main surface, and a second conductive layer containing copper is bonded to the ceramic substrate via the second bonding layer, wherein the bonding layer contains titanium, the conductive layer contains copper, and the thermal conductivity in the direction perpendicular to the one main surface of the circuit board is 150 W / mK or more.

[0012] (5) Furthermore, a power device of an application example of the present invention comprises a circuit board described in any of (1) to (4) above, and a power semiconductor mounted on the conductor layer. [Effects of the Invention]

[0013] According to the present invention, the circuit board or power device can be made more resistant to thermal cycling and have improved reliability. [Brief explanation of the drawing]

[0014] [Figure 1] This is a schematic cross-sectional view showing an example of a circuit board according to the embodiment. [Figure 2] This is a schematic plan view showing an example of a circuit board according to the embodiment. [Figure 3] This is a schematic partially enlarged cross-sectional view showing an example of a circuit board according to the embodiment. [Figure 4] (a) to (c) are schematic diagrams showing examples of microcracks in a circuit board according to the respective embodiments. [Figure 5] This is a schematic cross-sectional view showing a modified example of the circuit board according to the embodiment. [Figure 6] This is a schematic bottom view showing a modified example of the circuit board according to the embodiment. [Figure 7] This is a schematic cross-sectional view showing an example of a power device according to the embodiment. [Figure 8] This table shows the polishing conditions, metal layer formation methods, and test results for the circuit boards of the examples and comparative examples. [Modes for carrying out the invention]

[0015] Next, embodiments of the present invention will be described with reference to the drawings. To facilitate understanding of the explanation, the same reference numeral is used for identical components in each drawing, and redundant explanations are omitted. Note that the sizes of each component in the configuration diagrams are conceptual representations and do not necessarily represent actual dimensional ratios.

[0016] [Circuit board configuration] (Embodiment) First, a circuit board according to an embodiment of the present invention will be described. FIG. 1 is a schematic cross-sectional view showing an example of a circuit board 50 according to an embodiment of the present invention. FIG. 2 is a schematic plan view showing an example of the circuit board 50 according to an embodiment of the present invention. FIG. 3 is a schematic partial enlarged cross-sectional view showing an example of the circuit board according to an embodiment of the present invention. The circuit board 50 according to an embodiment of the present invention includes a ceramic substrate 10, a bonding layer 20, and a conductor layer 30.

[0017] The ceramic substrate 10 is made of ceramics. The ceramic substrate 10 can be formed of, for example, ceramics containing silicon nitride, aluminum nitride, aluminum oxide, etc. The ceramic substrate 10 is preferably made of a material having silicon nitride as a main component. Having silicon nitride as a main component means containing 86 wt% or more of silicon nitride. When the ceramic substrate 10 is made of a material having silicon nitride as a main component, the ceramic substrate 10 may contain sialon. The ceramic substrate 10 is formed, for example, in a flat plate shape.

[0018] The thickness in the direction perpendicular to one main surface 12 of the ceramic substrate 10 is preferably 220 μm or more and 690 μm or less. Thereby, the balance between the strength and heat dissipation of the ceramic substrate 10 can be improved. If the thickness is smaller than this range, the strength of the ceramic substrate 10 may be low. Also, if the thickness is larger than this range, the heat dissipation may decrease.

[0019] The ceramic substrate 10 has microcracks 14 formed by voids, which open on the interface (one main surface 12) side with the bonding layer 20 described later. Cracks generated in the ceramic substrate 10 due to the difference in the coefficient of thermal expansion between the conductor layer 30 and the ceramic substrate 10 extend in a direction generally parallel to the bonding interface. The circuit board 50 of the present invention has microcracks 14 in the thickness direction of the ceramic substrate 10, so that the extension of cracks in the ceramic substrate 10 can be suppressed by the microcracks 14. Also, even when the cracks extend beyond the microcracks 14, their direction can be changed, so that the cracks cannot extend linearly. As a result, the resistance to thermal cycles can be enhanced, and the reliability of the circuit board 50 can be improved.

[0020] The fact that the microcracks 14 are formed by voids means that 90% or more of the line segment defining the length of the microcracks 14 described later is a void. It may be said that the material for forming the bonding layer 20 is not substantially filled in the microcracks 14. This is because if the material for forming the bonding layer 20 enters the microcracks 14, the microcracks 14 themselves may extend during severe thermal cycles. For the polished surface of a cross-section perpendicular to one main surface 12 of the ceramic substrate 10, when 10 locations are randomly selected and observed at a magnification of 5000 times in a field of view of 16 μm × 20 μm, it is preferable that the average number of microcracks is 1 or more and 5 or less. However, microcracks with a length less than 0.1 μm measured by the method described later are not included in the microcracks 14 of the present invention.

[0021] The microcracks 14 are preferably 1 μm or longer and 3 μm or shorter. Microcracks less than 1 μm in length have a reduced effect in suppressing crack propagation. Microcracks longer than 3 μm may propagate themselves. Therefore, it is preferable that the microcracks 14 do not contain any that exceed 3 μm in length. Not containing microcracks 14 longer than 3 μm means that no microcracks 14 longer than 3 μm are observed in the 10 SEM images described later. The average angle of the microcracks 14 relative to the direction perpendicular to the interface is preferably 0° or longer and 80° or shorter. The average angle of the microcracks 14 is the average of the angles measured for microcracks 14 with a length of 1 μm or longer and 3 μm or shorter. If the average angle exceeds 80°, it will roughly coincide with the direction of crack propagation, which may prevent the suppression of delamination. If the average angle is 80° or less, the direction of crack propagation can be changed, and delamination can be suppressed. This can further enhance resistance to thermal cycling and improve the reliability of the circuit board 50. The average angle of the microcracks 14 is more preferably between 0° and 70°, and even more preferably between 0° and 60°. In addition, the aspect ratio of the microcracks is preferably 3 or more, more preferably 4 or more, and even more preferably 5 or more.

[0022] Figures 4(a) to 4(c) are schematic diagrams showing examples of microcracks 14 in a circuit board 50 according to an embodiment of the present invention. The length and angle of the microcracks 14 can be determined by SEM (Scanning Electron Microscope) observation. Specifically, 10 locations are randomly selected from the polished surface of a cross section perpendicular to one of the main surfaces 12 of the ceramic substrate 10, and a field of view of 16 μm × 20 μm is observed at a magnification of 5000x. For microcracks 14 that are entirely included in the observed field of view, the length or angle is determined according to the following criteria. Note that the fact that the microcracks 14 consist of voids can be confirmed from the EPMA results described later for the same screen as the SEM image.

[0023] As shown in Figure 4(a), when the microcrack 14 is linear, the length of the microcrack 14 is the distance between P and Q, where P is the midpoint of the opening P1P2 at the interface between the ceramic substrate 10 and the bonding layer 20, and Q is the point of the deepest microcrack 14 in the direction perpendicular to the reference interface. Furthermore, when the intersection points of the perpendicular bisector M of PQ with P1Q and P2Q are P3 and P4, respectively, the aspect ratio is PQ / P3P4. Note that if the actual interface in the SEM image is not linear, the reference interface is the same as the reference straight line described later.

[0024] As shown in Figure 4(b), when the microcrack 14 is bent, the length of the microcrack 14 is given by PR+RQ, where P is the midpoint of the opening P1P2 at the interface between the ceramic substrate 10 and the bonding layer 20, R is the midpoint of the line segment connecting the angles R1 and R2 of the bent line, and Q is the point of the deepest microcrack 14 in the direction perpendicular to the reference interface. Also, let T be the midpoint of PR+RQ, and let M be the perpendicular line from PR or RQ passing through T (in Figure 4(b), PR⊥M). Then, when P3 is the intersection of M and P1R1 or R1Q, and P4 is the intersection of M and P2R2 or R2Q, the aspect ratio is (PR+RQ) / P3P4. The same applies when a single microcrack 14 is bent two or more times. Furthermore, if the microcrack 14 is curved, the sum of the line segments drawn for each short portion that can be considered straight in SEM images at low magnifications of less than 5000x is used.

[0025] As shown in Figure 4(c), when a microcrack 14 is bifurcated, the length of the microcrack 14 is determined by separating the length of the first microcrack 14 that occurred and the length of the second microcrack 14 that occurred. In the case of Figure 4(c), the length of the right microcrack 14, which is thought to have occurred first, is PR+RQ. The length of the left microcrack 14, which is thought to have occurred later, is P'R'. R' is the midpoint of the line segment of the boundary dividing the microcrack 14 into two. The aspect ratio is determined as described above for each separated microcrack. The same applies when it is bifurcated into three or more parts. Note that if the actual interface on the SEM image is not parallel to the reference interface, there may be microcracks with an angle of 90°. The length of such microcracks is the distance from end to end of only the 90° portion.

[0026] The distance P1P2 between the openings of the microcracks 14 is preferably 0.5 μm or less. This is because if the openings are larger than this, the material forming the bonding layer 20 can easily penetrate into the microcracks 14.

[0027] The angle of the microcrack 14 with respect to the direction perpendicular to the interface is defined as the angle θ between the line L passing through the midpoint P of the opening and perpendicular to the interface, and the line segment on the side closer to the interface, as shown in Figures 4(a) to (c).

[0028] The bonding layer 20 is formed on one main surface 12 of the ceramic substrate 10. The bonding layer 20 preferably contains titanium, and more preferably has titanium as its main component. This makes it possible to increase the bonding strength between the ceramic substrate 10 and the conductive layer 30 while maintaining the heat transfer between the ceramic substrate 10 and the conductive layer 30. The bonding layer 20 may also contain layers other than the layer with titanium as its main component (layers that can be distinguished from the layer with titanium as its main component by SEM imaging or EPMA).

[0029] The thickness of the bonding layer 20 is preferably 0.1 μm or more and 5 μm or less. The thickness of the bonding layer 20 can be determined by SEM observation. Specifically, 10 locations are randomly selected on the polished surface of a cross section perpendicular to one of the main surfaces 12 of the ceramic substrate 10, and a field of view of 16 μm × 20 μm is observed at a magnification of 5000x. Next, the length between the interfaces of each layer is determined by drawing 10 line segments perpendicular to a 10 μm line segment drawn at the interface between the ceramic substrate 10 and the bonding layer 20 at equal intervals. The average value of these values ​​is then taken as the thickness of the bonding layer 20. If the interface between the ceramic substrate 10 and the bonding layer 20 is not a straight line in the SEM image, the straight line drawn at the interface in a lower magnification SEM image where the interface between the ceramic substrate 10 and the bonding layer 20 can be considered a straight line is used as the reference straight line. In addition, since each layer has a different color tone in the SEM image, the interfaces of each layer can be distinguished.

[0030] The types and proportions of elements contained in the ceramic substrate 10, the bonding layer 20, and the conductive layer 30 can be measured by performing qualitative and quantitative analysis using an EPMA (Electron Probe Micro Analyzer) on the polished surface of a cross-section perpendicular to one of the main surfaces 12 of the ceramic substrate 10 of the circuit board 50.

[0031] The conductive layer 30 is made of metal and is bonded to the ceramic substrate 10 via the bonding layer 20. The conductive layer 30 is preferably made of a metal containing copper, more preferably a metal mainly composed of copper, and even more preferably oxygen-free copper. A metal mainly composed of copper refers to a metal containing 99 wt% or more of copper. The thickness of the conductive layer 30 is preferably 0.2 mm or more and 1.5 mm or less.

[0032] (modified version) Figure 5 is a schematic cross-sectional view showing a modified example of the circuit board 50 according to an embodiment of the present invention. Figure 6 is a schematic bottom view showing a modified example of the circuit board 50 according to an embodiment of the present invention. The circuit board 50 according to an embodiment of the present invention comprises a ceramic substrate 10, a bonding layer 20, a conductor layer 30, a second bonding layer 26, and a second conductor layer 32. The configuration of the ceramic substrate 10, the bonding layer 20, and the conductor layer 30 is the same as that of the circuit board 50 described above.

[0033] The ceramic substrate 10 may have microcracks 14 that open on the side of the interface with the second bonding layer 26 (the other main surface 16 facing one main surface 12) and are not filled with the material forming the second bonding layer 26. This can increase resistance to thermal cycling on the second bonding layer 26 side as well, thereby improving reliability. It is preferable that the microcracks 14 that open on the other main surface 16 side also have the above characteristics.

[0034] The second bonding layer 26 is formed on the other main surface 16 of the ceramic substrate 10. The second bonding layer 26 preferably contains titanium, and more preferably has titanium as its main component. This makes it possible to increase the bonding strength between the ceramic substrate 10 and the second conductive layer 32 while maintaining the heat transfer between the ceramic substrate 10 and the second conductive layer 32. If the second bonding layer 26 contains a layer with titanium as its main component, the second bonding layer 26 may also contain layers other than the layer with titanium as its main component (layers that can be distinguished from the layer with titanium as its main component by SEM image or EPMA).

[0035] The thickness of the second bonding layer 26 is preferably 0.1 μm or more and 5 μm or less. The thickness of the second bonding layer 26 may be the same as or different from the thickness of the bonding layer 20.

[0036] The second conductor layer 32 is made of metal and is bonded to the ceramic substrate 10 via the second bonding layer 26. The second conductor layer 32 is preferably made of a metal containing copper, more preferably a metal mainly composed of copper, and even more preferably oxygen-free copper. The material of the second conductor layer 32 may be different from the material of the conductor layer 30, but it is preferable that they be the same. The thickness of the second conductor layer 32 is preferably 0.2 mm or more and 1.5 mm or less. The thickness of the second conductor layer 32 may be the same as or different from the thickness of the conductor layer 30.

[0037] As shown in Figure 5, it is preferable that the second conductive layer 32 is bonded to an area of ​​75% or more of the area of ​​the other main surface 16 of the ceramic substrate 10. This allows for efficient heat dissipation from the second conductive layer 32, improving the heat dissipation performance of the circuit board 50.

[0038] The thermal conductivity of the circuit board 50 in the direction perpendicular to one of the main surfaces 12 is preferably 150 W / mK or higher. This ensures that the heat dissipation of the circuit board 50 is sufficiently high. The thermal conductivity of the circuit board 50 in the direction perpendicular to one of the main surfaces 12 is measured for a circuit board 50 that includes a conductor layer 30 and a second conductor layer 32, as in the modified circuit board 50.

[0039] The thermal conductivity of the circuit board 50 in a direction perpendicular to one of its main surfaces 12 can be measured and calculated using the laser flash method.

[0040] These features enhance resistance to thermal cycling and improve the reliability of the circuit board 50. Furthermore, it is possible to increase the bonding strength between the ceramic substrate 10 and the conductor layer 30 while maintaining heat transfer between them.

[0041] [Power device configuration] Figure 7 is a schematic cross-sectional view showing an example of a power device according to an embodiment of the present invention. The power device 100 comprises a circuit board 50 and a power semiconductor 60. In Figure 7, the bonding layer 20, the second bonding layer 26, etc. of the circuit board 50 are omitted.

[0042] The circuit board 50 is the circuit board 50 described above. The circuit board 50 has a conductive layer 30 formed on at least one main surface 12 of the ceramic substrate 10. The circuit board 50 may also have a second conductive layer 32 formed on the other main surface 16 facing the first main surface 12.

[0043] A power semiconductor 60 is mounted on the upper side of the conductor layer 30 of the circuit board 50. The power semiconductor 60 and the conductor layer 30 may be joined using solder 52 or the like. The power semiconductor 60 may be, for example, a semiconductor that can handle large currents for EVs and is prone to high temperatures. The circuit board 50 of the present invention has improved bonding strength while maintaining heat dissipation, and therefore has high resistance to thermal cycling. As a result, even if high temperatures cause large thermal stress in the ceramic substrate 10 due to the difference in thermal expansion between the ceramic substrate 10 and the metal to which it is joined, cracks and fractures are less likely to occur.

[0044] If the circuit board 50 includes a second conductor layer 32, a heat sink 70 may be bonded to the underside of the second conductor layer 32. The heat sink 70 and the second conductor layer 32 may be joined using solder 52 or the like.

[0045] The surface of the heat sink 70 that is joined to the second conductive layer 32 may be in contact with the heat dissipation member 80 via grease 72 or the like. The heat sink 70 is preferably made of metal, more preferably of a metal mainly composed of copper, and even more preferably of oxygen-free copper. The heat dissipation member 80 is preferably formed with heat dissipation fins. The heat dissipation member 80 is preferably made of metal, more preferably of a metal mainly composed of copper or aluminum.

[0046] [Manufacturing method for circuit boards] An example of a manufacturing method for the above-mentioned circuit board is shown below. A general silicon nitride sintered body can be used as the ceramic substrate. The silicon nitride sintered body can be manufactured, for example, by the following method. First, the raw material powder for the silicon nitride sintered body is weighed. The raw material powder for the silicon nitride sintered body may be oxides, carbonates, hydroxides, nitrides, etc. of each element contained in the silicon nitride sintered body. In addition to silicon nitride, the raw material powder for the silicon nitride sintered body may include, for example, magnesium carbonate, calcium carbonate, yttrium oxide, etc.

[0047] Ethanol is added to these raw material powders, and the mixture is wet-mixed and ground in a ball mill at, for example, 60 rpm for 6 to 60 hours to obtain a slurry. The slurry is then dried using a water bath or spray dryer to obtain a mixed powder.

[0048] Next, the mixed powder is filled into a mold and molded into the desired shape by uniaxial pressing at a pressure of, for example, 30 MPa. Then, a molded body is obtained by performing CIP treatment (cold isohydrostatic pressing) at a pressure of, for example, 150 MPa. The obtained molded body (CIP pressed body) is placed in a silicon carbide mold, for example, with the inside coated with BN, and fired at a maximum temperature of 1800°C to 1900°C for 5 to 30 hours in a nitrogen atmosphere at 9 atmospheres to obtain a silicon nitride sintered body.

[0049] A ceramic substrate is manufactured by processing the obtained silicon nitride sintered body to achieve a predetermined shape and thickness. Processing can be carried out by cutting, grinding, polishing, etc. It is preferable to polish the main surface of the ceramic substrate on the side to which the conductive layer or the second conductive layer is joined to a surface roughness Ra of 0.5 μm or less. At this time, grinding and polishing are performed so that microcracks with a length of 1 μm to 3 μm are formed on at least one of the main surfaces. The length, number, and angle of the formed microcracks can be adjusted by adjusting the amount and speed of grinding and polishing.

[0050] Apart from the manufacturing of the ceramic substrate, a metal plate of a predetermined thickness is prepared to serve as the conductive layer or a second conductive layer. The plate is preferably made of a metal containing copper, more preferably a metal mainly composed of copper, and even more preferably oxygen-free copper. Next, a metal film mainly composed of Ti is formed on one main surface of the plate or ceramic substrate to serve as a bonding layer. The metal film can be formed by sputtering, vapor deposition, or the like. The thickness of the metal film is preferably 0.1 μm or more and 5 μm or less. A metal film to serve as the second bonding layer may be formed on the other main surface.

[0051] Next, the ceramic substrate and the plate material are laminated with a metal film sandwiched in between. Then, the plate material and the ceramic substrate can be joined by HP treatment (hot pressing treatment) or HIP treatment (hot isostatic pressing treatment). For example, the conditions for HP treatment can be a pressure of 5 MPa to 30 MPa, a maximum temperature of 700°C to 980°C, and a maximum temperature holding time of 10 minutes to 2 hours. By joining the ceramic substrate and the plate material, which have microcracks formed on them, via a thin metal film formed by sputtering or the like, it is possible to prevent the metal film material from entering into the microcracks.

[0052] This manufacturing method makes it possible to produce circuit boards that have increased resistance to thermal cycling and improved reliability.

[0053] [Examples, Comparative Examples] (Example 1) The raw materials were weighed to obtain a mixture of 94 wt% silicon nitride powder (average particle size 1.4 μm), 3 wt% magnesium carbonate powder (average particle size 2.5 μm), and 3 wt% yttrium oxide powder (average particle size 1.0 μm). Next, the weighed raw material powders were ball-milled to obtain a mixed slurry. In ball milling, the raw material powders and ethanol were placed in a resin pot, and the mixture was ground and mixed at 60 rpm for 24 hours using silicon nitride balls. The resulting mixed slurry was dried by water bath to obtain a mixed powder.

[0054] The obtained mixed powder was powder-pressed using a uniaxial press and CIP to produce molded bodies. First, the mixed powder was filled into a dedicated mold and pre-molded using a uniaxial press at a pressure of 30 MPa. Next, the pre-molded body was placed in a dedicated bag under vacuum and CIP molding was performed at a pressure of 150 MPa. The obtained molded bodies were fired. The sintering method was atmospheric firing with a gas pressure of 9 atmospheres of nitrogen, and the maximum temperature was maintained at 1900°C for 10 hours. A silicon carbide mold with a BN coating on the inside was used. The fired silicon nitride sintered body was cut to a size of 100 mm × 100 mm × 0.32 mm, and the surface roughness Ra of one main surface and the other main surface of the ceramic substrate, which will be the bonding surface between the conductive layer and the second conductive layer, was polished to 0.5 μm or less. At this time, the polishing amount was 5 μm and the polishing speed was 10 mm / sec. In this way, the ceramic substrate was prepared.

[0055] Separately, two oxygen-free copper plates measuring 100 mm x 100 mm x 0.5 mm (conductor layer, second conductor layer) were prepared. Next, a metal film containing Ti was sputtered to one main surface and the other main surface (bonding surface with the plate) of a ceramic substrate with a thermal conductivity of 70 W / mK or higher and a thickness of 0.32 mm, to a thickness of 0.1 μm to 5 μm. Then, the conductor layer, ceramic substrate, and conductor layer (second conductor layer) were laminated in that order and bonded by HP treatment (hot pressurization treatment). The pressure was 10 MPa, the maximum temperature was 900 °C, and the maximum temperature holding time was 30 minutes. In this way, the circuit board of Example 1 was fabricated.

[0056] (Example 2) The circuit board of Example 2 was manufactured under the same conditions as the circuit board of Example 1, except that the polishing conditions for one main surface and the other main surface of the ceramic substrate were changed to a polishing amount of 5 μm and a polishing speed of 14 mm / sec.

[0057] (Example 3) The circuit board of Example 3 was manufactured under the same conditions as the circuit board of Example 1, except that the polishing conditions for one main surface and the other main surface of the ceramic substrate were changed to a polishing amount of 5 μm and a polishing speed of 18 mm / sec.

[0058] (Example 4) The circuit board of Example 4 was manufactured under the same conditions as the circuit board of Example 1, except that the polishing conditions for one main surface and the other main surface of the ceramic substrate were changed to a polishing amount of 5 μm and a polishing speed of 20 mm / sec.

[0059] (Example 5) The circuit board of Example 5 was manufactured under the same conditions as the circuit board of Example 1, except that the polishing conditions for one main surface and the other main surface of the ceramic substrate were changed to a polishing amount of 10 μm and a polishing speed of 10 mm / sec.

[0060] (Comparative Example 1) The circuit board of Comparative Example 1 was manufactured under the same conditions as the circuit board of Example 1, except that the Ti was not sputtered onto the plate material, and a brazing material containing Ti, Cu, and Ag was applied to a thickness of 15 μm and then heated to 800°C for bonding.

[0061] (Comparative Example 2) The circuit board of Comparative Example 2 was manufactured under the same conditions as the circuit board of Example 1, except that the polishing conditions for one main surface and the other main surface of the ceramic substrate were changed to a polishing amount of 10 μm and a polishing speed of 20 mm / sec.

[0062] [Various measurements] The circuit boards of the obtained examples and comparative examples were evaluated by the following measurements.

[0063] (Calculation of thermal conductivity) The thermal conductivity of the circuit boards in the examples and comparative examples was determined by the laser flash method at room temperature.

[0064] (Measurement of porosity, length, and angle of microcracks) The circuit boards of the examples and comparative examples were cut perpendicular to one main surface of the ceramic substrate and polished. Next, SEM images at 5000x magnification were taken of 10 randomly selected locations. Elemental mapping was also performed by measuring the elements contained in the same images using EPMA. The porosity within the microcracks was measured from the results of the elemental mapping. The length and angle of the microcracks in each SEM image were also measured. Microcracks that opened at the interface and were entirely contained within the SEM image were targeted for measurement. If the porosity of all microcracks was 90% or more, the porosity criterion was met (○). If even one microcrack had a porosity below 90%, the porosity criterion was not met (×). Similarly, if there were microcracks longer than 1 μm and the length of all microcracks was 3 μm or less, the length criterion was met (○). If even one microcrack had a length exceeding 3 μm, the length criterion was not met (×). Furthermore, if the average angle of microcracks between 1 μm and 3 μm was between 0° and 80°, the angle criterion was met (○), and if the average angle exceeded 80°, the angle criterion was not met (×).

[0065] (Cold cycle test) The circuit boards of the examples and comparative examples were placed on a thermal cycling test machine, and a thermal cycling test was performed for a maximum of 2000 cycles, with one cycle consisting of -40°C for 5 minutes, 250°C for 5 minutes, and then cooling back to -40°C. Then, SAT inspection (ultrasonic testing) was performed every 100 cycles to check for the presence of cracks at the edges of the bonding layer. If a crack was found, its length was measured, and it was determined that a crack of 1 mm or more had occurred that prevented continued use. Circuit boards that developed a crack that prevented continued use before 500 cycles were deemed unacceptable (×), while those that developed a crack that prevented continued use before 500 cycles were deemed acceptable. Among those that passed, those with less than 1000 cycles were judged as good (〇), and those with 1000 cycles or more were judged as excellent (◎).

[0066] (result) Figure 8 is a table showing the polishing conditions, metal layer formation method, and results of various tests for the circuit boards of the examples and comparative examples. Examples 1 to 5, which passed the thermal cycling test, met the void ratio standard. In contrast, comparative examples 1 and 2, which failed the thermal cycling test, did not meet the void ratio standard. In comparative example 1, it is thought that a large amount of brazing material penetrated into the microcracks during bonding, and the microcracks expanded due to the thermal cycling. In comparative example 2, it is thought that the large amount of polishing and fast polishing speed resulted in larger microcrack openings, allowing Ti to penetrate into the microcracks even with sputtering, and that the long length and poor angle of the microcracks further expanded due to the thermal cycling. This shows that the presence of microcracks that meet the void ratio standard can increase resistance to thermal cycling.

[0067] Examples 1-3, which met the criteria for microcrack length and angle, showed better results in the thermal cycling test compared to Examples 4 or 5, which did not meet either criterion. Furthermore, it was found that an average angle of 70° or less was more preferable, and 60° or less was even more preferable. These findings indicate that microcracks meeting the porosity criteria can be made even more resistant to thermal cycling and more reliable by also meeting the length and angle criteria.

[0068] As described above, it has been confirmed that the circuit board or power device of the present invention can improve heat transfer between the ceramic substrate and the conductor layer, while also increasing resistance to thermal cycling and thus achieving high reliability.

[0069] The present invention is not limited to the embodiments described above, and it goes without saying that it extends to various modifications and equivalents that fall within the spirit and scope of the present invention. Furthermore, the structure, shape, number, position, size, etc., of the components shown in each drawing are for illustrative purposes only and may be modified as appropriate. [Explanation of Symbols]

[0070] 10 Ceramic substrates 12 One main surface 14 Microcracks 16 The other main surface 20 Bonding layer 26 Second bonding layer 30 Conductor Layers 32 Second Conductor Layer 50 Circuit boards 52 Solder 60 Power Semiconductors 70 Heat sink 72 Grease 80 Heat dissipation components 100 Power Devices

Claims

1. Ceramic substrate and A bonding layer formed on one main surface of the ceramic substrate, The system comprises a conductive layer made of metal bonded to the ceramic substrate via the bonding layer, The ceramic substrate has microcracks that open on the interface side with the bonding layer and consist of voids, A circuit board characterized by the fact that, even after performing a thermal cycle test consisting of maintaining the board at -40°C for 5 minutes and then at 250°C for 5 minutes, no cracks of 1 mm or more occur even after more than 500 cycles.

2. The circuit board according to claim 1, characterized in that the microcracks include those having a length of 1 μm or more and 3 μm or less, and the average value of the angle of the microcracks having a length of 1 μm or more and 3 μm or less with respect to the direction perpendicular to the interface is 0° or more and 80° or less.

3. The circuit board according to claim 1 or claim 2, characterized in that the bonding layer has titanium as its main component.

4. A second bonding layer containing titanium is formed on the other main surface of the ceramic substrate opposite to the one main surface, The present invention further comprises a second conductive layer containing copper, which is bonded to the ceramic substrate via the second bonding layer, The bonding layer contains titanium, The aforementioned conductor layer contains copper, The circuit board according to claim 1 or 2, characterized in that the thermal conductivity in the direction perpendicular to one of the main surfaces of the circuit board is 150 W / mK or more.

5. A circuit board according to claim 1 or claim 2, A power device characterized by comprising a power semiconductor mounted on the aforementioned conductive layer.

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