Semiconductor equipment

Abstract

Provide a semiconductor device with good electrical characteristics. Provide a highly reliable semiconductor device. Provide a semiconductor device with stable electrical characteristics. 【Solution means】The semiconductor device includes a semiconductor layer, a first insulating layer, a second insulating layer, and a conductive layer. The semiconductor layer, the second insulating layer, and the conductive layer are laminated in this order on the first insulating layer. The semiconductor layer contains indium and oxygen, and in a triangular diagram showing the atomic ratio of indium, element M, and zinc, it has a composition within the range that connects the first coordinate (1:0:0), the second coordinate (2:1:0), the third coordinate (14:7:1), the fourth coordinate (7:2:2), the fifth coordinate (14:4:21), the sixth coordinate (2:0:3), and the first coordinate in a straight line in this order. Also, element M is one or more of gallium, aluminum, yttrium, or tin. ​

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device and a method for manufacturing the same. One aspect of the present invention relates to a display device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. As the technical field of one aspect of the present invention disclosed in this specification and the like, semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, their driving methods, or their manufacturing methods can be cited as an example. A semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics.

Background Art

[0003] As a semiconductor material applicable to a transistor, an oxide semiconductor using a metal oxide has attracted attention. For example, in Patent Document 1, a plurality of oxide semiconductor layers are laminated, and among the plurality of oxide semiconductor layers, the oxide semiconductor layer serving as a channel contains indium and gallium, and by making the ratio of indium larger than the ratio of gallium, a semiconductor device with increased field-effect mobility (sometimes simply referred to as mobility or μFE) is disclosed.

[0004] In Non-Patent Document 1 and Non-Patent Document 2, an oxide semiconductor material of InGaO3(ZnO)m (m: natural number) is disclosed.

[0005] Since the metal oxide that can be used for the semiconductor layer can be formed by using a sputtering method or the like, it can be used for the semiconductor layer of a transistor that constitutes a large display device. Also, by improving a part of the production equipment of a transistor using polycrystalline silicon or amorphous silicon, it can be used. Because it can be used, capital investment can be reduced. Also, a transient using metal oxides Because it has a higher field-effect mobility compared to when amorphous silicon is used, the drive circuit This enables the creation of high-performance display devices. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2014-7399 [Non-patent literature]

[0007] [Non-Patent Document 1] M. Nakamura, N. Kimizuka, and T. Mohri, "The Phase Relations in the In2O3-Ga2ZnO4-ZnO System at 1350℃", J. Solid State Chem., 1991, Vol.93, p.298-315 [Non-Patent Document 2] N. Kimizuka, M. Isobe, and M. Nakamura, “Syntheses and Single-Crystal Data of Homologous Compounds, In2O3(ZnO)m(m=3,4, and 5), InGaO3(ZnO)3, and Ga2O3(ZnO)m(m=7,8,9, and 16) in the In2O3-ZnGa2O4-ZnO System”, J. Solid State Chem., 1995, Vol.116, p.170-178 [Overview of the Initiative] [Problems that the invention aims to solve]

[0008] One aspect of the present invention aims to provide a semiconductor device with good electrical characteristics. One aspect of the invention aims to provide a highly reliable semiconductor device. One aspect of this invention aims to provide a semiconductor device with stable electrical characteristics. One of the objectives is to provide a highly reliable display device.

[0009] Furthermore, the description of these problems does not preclude the existence of other problems. One approach does not require that all of these issues be resolved. The title can be extracted from descriptions such as the specification, drawings, and claims. [Means for solving the problem]

[0010] One aspect of the present invention comprises a semiconductor layer, a first insulating layer, a second insulating layer, and a conductive layer. This is a semiconductor device. The semiconductor layer, the second insulating layer, and the conductive layer are arranged in this order on the first insulating layer. The layers are stacked. The semiconductor layer contains indium and oxygen, and indium, element M and zinc. In the triangular diagram showing the atomic ratio, the first coordinate (1:0:0) and the second coordinate (2:1: 0), the third coordinate (14:7:1), the fourth coordinate (7:2:2), and the fifth coordinate (1 Connect the coordinates 4:4:21, the sixth coordinate (2:0:3), and the first coordinate with a straight line in this order. It is preferable that the composition is within the specified range. Also, element M is gallium, aluminum, and It is one or more of either thorium or tin.

[0011] One aspect of the present invention comprises a semiconductor layer, a first insulating layer, a second insulating layer, and a conductive layer. This is a semiconductor device. The semiconductor layer, the second insulating layer, and the conductive layer are arranged in this order on the first insulating layer. They are stacked. The semiconductor layer has indium and oxygen, and the semiconductor layer has indium and oxygen. In the triangular diagram showing the atomic ratio of element M and zinc, the first coordinate (7:1:0) and the second coordinate The target (2:1:0), the third coordinate (14:7:1), the fourth coordinate (7:2:2), and the The coordinates of 5 (14:4:21), the 6th coordinates (2:0:3), and the 7th coordinates (7:0:1 It is preferable that the composition has a range within which the first coordinate and are connected by a straight line in this order. Element M is one or more of gallium, aluminum, yttrium, or tin. .

[0012] One aspect of the present invention comprises a semiconductor layer, a first insulating layer, a second insulating layer, and a conductive layer. This is a semiconductor device. The semiconductor layer, the second insulating layer, and the conductive layer are arranged in this order on the first insulating layer. They are stacked. The semiconductor layer has indium, zinc, and oxygen, and indium is element M And in the triangular diagram showing the atomic ratio of zinc, the first coordinate (44:11:10) and the second The coordinates (4:1:6), the third coordinates (2:0:3), and the fourth coordinates (11:0:2), It is preferable that the composition has a range within which the first coordinate and are connected by a straight line in this order. M is one or more of gallium, aluminum, yttrium, or tin.

[0013] One aspect of the present invention comprises a semiconductor layer, a first insulating layer, a second insulating layer, and a conductive layer. This is a semiconductor device. The semiconductor layer, the second insulating layer, and the conductive layer are arranged in this order on the first insulating layer. They are stacked. The semiconductor layer has indium, zinc, and oxygen, and indium is element M And in the triangular diagram showing the atomic ratio of zinc, the first coordinate (44:11:10) and the second The coordinates (4:1:4), the third coordinates (1:0:1), and the fourth coordinates (11:0:2), It is preferable that the composition has a range within which the first coordinate and are connected by a straight line in this order. M is one or more of gallium, aluminum, yttrium, or tin.

[0014] In the aforementioned semiconductor device, the semiconductor layer has a region that does not overlap with the conductive layer, and the region is It has one or more of the following: ions, boron, magnesium, aluminum, or silicon. This is preferable.

[0015] In the semiconductor device described above, the second insulating layer is preferably in contact with the region.

[0016] The semiconductor device described above further has a third insulating layer, the third insulating layer is on top of the conductive layer. It is preferable that the surface and sides, the sides of the second insulating layer, and the top and sides of the semiconductor layer be in contact with each other. Furthermore, it is preferable that the second insulating layer contains oxygen and the third insulating layer contains nitrogen.

[0017] In the aforementioned semiconductor device, the second insulating layer contains silicon oxide, and the third insulating layer contains, It is preferable that the material contains silicon nitride. [Effects of the Invention]

[0018] According to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. Or, reliability We can provide semiconductor devices with high performance, or semiconductor devices with stable electrical characteristics. Alternatively, a highly reliable display device can be provided.

[0019] Furthermore, the description of these effects does not preclude the existence of other effects. One embodiment does not necessarily have to possess all of these effects. Furthermore, other effects may be considered. This information can be extracted from descriptions such as specifications, drawings, and claims. [Brief explanation of the drawing]

[0020] [Figure 1] Figures 1A and 1B illustrate the composition of metal oxides. [Figure 2] Figures 2A and 2B illustrate the composition of metal oxides. [Figure 3] Figures 3A and 3B illustrate the composition of metal oxides. [Figure 4] Figure 4 is a diagram illustrating the composition of metal oxides. [Figure 5] Figure 5A illustrates the classification of IGZO crystal structures. Figure 5B illustrates the XRD spectrum of quartz glass. Figure 5C illustrates the XRD spectrum of crystalline IGZO. [Figure 6] Figures 6A and 6B show examples of transistor configurations. [Figure 7] Figures 7A and 7B show examples of transistor configurations. [Figure 8] Figure 8A is a top view of the transistor. Figures 8B and 8C are cross-sectional views of the transistor. [Figure 9] Figure 9A is a top view of the transistor. Figures 9B and 9C are cross-sectional views of the transistor. [Figure 10] Figure 10A is a top view of the transistor. Figures 10B and 10C are cross-sectional views of the transistor. [Figure 11] Figure 11A is a top view of the transistor. Figures 11B and 11C are cross-sectional views of the transistor. [Figure 12] Figures 12A, 12B, 12C, and 12D are cross-sectional views of a transistor. [Figure 13] Figures 13A, 13B, 13C, and 13D are cross-sectional views of a transistor. [Figure 14] Figures 14A, 14B, 14C, 14D, and 14E illustrate the method for fabricating a transistor. [Figure 15]Figures 15A, 15B, 15C, and 15D illustrate the method for fabricating a transistor. [Figure 16] Figures 16A and 16B illustrate the method for fabricating a transistor. [Figure 17] Figures 17A, 17B, 17C, and 17D illustrate the method for fabricating a transistor. [Figure 18] Figures 18A, 18B, and 18C are top views of the display device. [Figure 19] Figure 19 is a cross-sectional view of the display device. [Figure 20] Figure 20 is a cross-sectional view of the display device. [Figure 21] Figure 21 is a cross-sectional view of the display device. [Figure 22] Figure 22 is a cross-sectional view of the display device. [Figure 23] Figure 23A is a block diagram of the display device. Figures 23B and 23C are circuit diagrams of the display device. [Figure 24] Figures 24A, 24C, and 24D are circuit diagrams of the display device. Figure 24B is a timing chart of the display device. [Figure 25] Figures 25A and 25B show examples of the display module configuration. [Figure 26] Figures 26A and 26B show examples of electronic device configurations. [Figure 27] Figures 27A, 27B, 27C, 27D, and 27E show examples of electronic device configurations. [Figure 28] Figures 28A, 28B, 28C, 28D, 28E, 28F, and 28G show examples of electronic device configurations. [Figure 29] Figures 29A, 29B, 29C, and 29D show examples of electronic device configurations. [Figure 30] Figure 30 shows the results of the XRD analysis. [Figure 31] Figure 31 shows the ID-VG characteristics of a transistor. [Figure 32] Figure 32 shows the mobility of a transistor. [Figure 33] Figure 33 shows the TDS analysis results. [Figure 34] Figure 34 shows the ID-VG characteristics of a transistor. [Figure 35] Figure 35 shows the ID-VG characteristics of a transistor. [Figure 36] Figure 36 shows the reliability of a transistor. [Figure 37] Figure 37 shows the ID-VG characteristics of a transistor. [Figure 38] Figure 38 shows the ID-VG characteristics of a transistor. [Figure 39] Figure 39 shows the ID-VG characteristics of a transistor. [Figure 40] Figure 40 shows the ID-VG characteristics of a transistor. [Figure 41] Figure 41 shows the ID-VG characteristics of a transistor. [Figure 42] Figure 42 shows the ID-VG characteristics of a transistor. [Figure 43] Figure 43 shows the ID-VG characteristics of a transistor. [Figure 44] Figure 44 shows the ID-VG characteristics of a transistor. [Figure 45] Figure 45 shows the ID-VG characteristics of a transistor. [Figure 46] Figure 46 shows the ID-VG characteristics of a transistor. [Figure 47] Figure 47 shows the ID-VG characteristics of a transistor. [Figure 48] Figure 48 shows the ID-VG characteristics of a transistor. [Figure 49] Figure 49 shows the ID-VG characteristics of a transistor. [Figure 50] Figure 50 shows the ID-VG characteristics of a transistor. [Figure 51] Figure 51 shows the ID-VG characteristics of a transistor. [Figure 52] Figure 52 shows the reliability of a transistor. [Figure 53] Figure 53 shows the results of XRD analysis of metal oxides. [Figure 54] Figure 54 shows the results of XRD analysis of metal oxides. [Figure 55] Figure 55 shows the band gap of a metal oxide. [Figure 56] Figure 56A shows the carrier concentration of a metal oxide. Figure 56B shows the Hall mobility of a metal oxide. [Figure 57] Figure 57A shows the carrier concentration of a metal oxide. Figure 57B shows the Hall mobility of a metal oxide. [Modes for carrying out the invention]

[0021] The embodiments will be described below with reference to the drawings. However, many embodiments are described. It can be implemented in different ways, without deviating from its purpose and scope. Those skilled in the art will readily understand that the form and details can be modified in various ways. Therefore, the present invention This shall not be interpreted as being limited to the contents described in the following embodiments.

[0022] In each figure described herein, the size, layer thickness, or area of ​​each component is clearly defined. It may be exaggerated for that reason.

[0023] The ordinal numbers "1st," "2nd," and "3rd" used in this specification, etc., are intended to avoid confusion of constituent elements. This was added to avoid the issue of a numerical limitation.

[0024] In this specification, phrases indicating placement such as "above" and "below" refer to the relative positions of the constituent elements. The positional relationships are used for convenience in explaining them with reference to the drawings. Also, the positions of the components are shown. The arrangement changes as appropriate depending on the direction in which each component is described. Therefore, the description in the specification is not provided. The vocabulary is not limited to the explicitly stated terms; it can be appropriately rephrased depending on the situation.

[0025] In this specification, the source and drain functions of a transistor are defined as having different polarities. When using transistors, or when the direction of current changes during circuit operation, They can be swapped. Therefore, the terms source and drain can be used interchangeably. It shall be done.

[0026] In this specification and elsewhere, the channel length direction of a transistor refers to the source region and the drain region. It refers to one of the directions parallel to the straight line connecting the two points by the shortest distance. In other words, the channel length direction is This corresponds to one of the directions of current flowing through the semiconductor layer when the transistor is in the ON state. Furthermore, the channel width direction refers to the direction perpendicular to the channel length direction. Depending on the structure and shape of the zista, the channel length and channel width directions may not be uniquely determined. There are cases where this is the case.

[0027] In this specification, etc., "electrically connected" means "having some kind of electrical effect." This includes cases where they are connected via. Here, "something that has some kind of electrical effect" is There are no particular restrictions as long as it enables the exchange of electrical signals between connected objects. For example, "things that have some kind of electrical effect" include electrodes, wiring, transistors, etc. Switching elements, resistive elements, inductors, capacitors, and other elements with various functions This includes children, etc.

[0028] In this specification, the terms "membrane" and "layer" are interchangeable. It is possible. For example, the terms "conductive layer" and "insulating layer" are similar to "conductive film" and "insulating layer". In some cases, the term "membrane" can be used interchangeably.

[0029] In this specification, unless otherwise specified, off-current refers to the state in which the transistor is in the off state. This refers to the drain current when the device is in a non-conductive state or interrupted state. The off state is a special state. Unless otherwise specified, in an n-channel transistor, the voltage between the gate and source V gs but Threshold voltage V th Lower than (in p-channel transistors, V th (Higher than) To describe a state or attitude.

[0030] In this specification, a display panel, which is one form of a display device, displays an image or the like on its display surface. It has the function of (powering). Therefore, the display panel is one form of an output device.

[0031] In this specification, the substrate of the display panel is, for example, FPC (Flexible Printed Circuit). ed Circuit) or TCP (Tape Carrier Package) Connectors such as those mentioned above are attached, or COG (Chip On Glare) is attached to the circuit board. A display panel module, display module, etc., is a device on which an IC is mounted using the ss) method, etc. Alternatively, it may simply be called a display panel.

[0032] In this specification, a touch panel, which is one form of a display device, displays images, etc. on its display surface. The display function detects when a finger, stylus, or other object touches, presses, or comes near the display surface. It has the function of a touch sensor that detects things like touching. Therefore, touch panel This is one form of an input / output device.

[0033] A touch panel is, for example, a display panel (or display device) with a touch sensor. It can also be called a display panel (or display device) with a touch function. It can also be configured to have a panel and a touch sensor panel. Alternatively, the display panel The configuration can also include a touch sensor functioning either internally or on its surface.

[0034] In this specification, a touch panel circuit board with connectors and ICs mounted on it is referred to as a touch panel. It may be called a touch panel module, display module, or simply a touch panel.

[0035] (Embodiment 1) In this embodiment, a metal that can be suitably used in a semiconductor device according to one aspect of the present invention. Let me explain oxides.

[0036] One aspect of the present invention is a semiconductor device in which a metal acid functioning as a semiconductor is formed in a channel-forming region. It contains oxides (hereinafter also called oxide semiconductors). When metal oxides are used, silicon and others Compared to other semiconductors, transistors have good switching characteristics and extremely low off-current. It is preferable because it is low.

[0037] Here, the composition of the metal oxide significantly affects the electrical characteristics and reliability of the transistor. The metal oxide preferably contains indium. Furthermore, the metal oxide contains indium. A high content is preferable. By increasing the indium content of the metal oxide, the metal acid The carrier mobility (electron mobility) of the ion can be increased. Therefore, indium Transistors using metal oxides with a high content in the channel formation region have a high field-effect mobility. It can conduct high and large currents. Furthermore, semiconductor devices using this transistor... High-speed driving becomes possible. Therefore, a display device having such a semiconductor device has a pixel section The transistors used in the drive circuit and the transistors used in the drive circuit can be formed on the same substrate. It is possible. Furthermore, by using such transistors in the pixel section, high-quality images can be provided. It is possible.

[0038] The metal oxide preferably contains element M in addition to indium. Element M is oxygen and It is preferable that the bond energy is high. In particular, the bond energy of element M with oxygen is It is preferable that the concentration is higher than that of indium. Metal oxides have a higher bonding energy with oxygen than indium. Having element M with high ghee content makes it less likely for oxygen vacancies to form in the metal oxide. Element M includes gallium, aluminum, silicon, boron, yttrium, tin, and copper. Vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum Butene, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or One or more elements of magnesium can be used. In particular, as element M, gallium, aluminum, etc. One or more of um, yttrium, or tin can be used. Also, element M is a metal. It has the function of increasing the energy gap of oxides.

[0039] Gallium can be particularly preferred as element M. The metal oxide is indium. By having gallium with a higher bonding energy with oxygen than the metal oxide, acid Elementary defect formation becomes less likely. Oxygen vacancies are present in the metal oxide used in the channel formation region. If there are too many, it can lead to a decrease in the electrical characteristics and reliability of the transistor. Therefore, indicators By using metal oxides containing um and gallium, high field-effect mobility and reliable This enables the creation of high-performance transistors.

[0040] The metal oxide preferably contains zinc in addition to indium. Alternatively, the metal oxide It is preferable that it contains indium, element M, and zinc. Zinc is a crystalline metal oxide. It has the function of enhancing [something]. Crystalline metal oxides are suitably used in the channel formation region. This is possible. For example, CAAC (c-axis aligned crystal) as described later. Metals having structures such as al(a) structure, polycrystalline structure, and microcrystalline (nc: nanocrystal) structure. Oxides can be used in the channel-forming region. Crystalline metal oxides can be used as channels. By using it in the channel formation region, the defect level density in the channel formation region can be reduced, and reliability This enables the creation of high-performance transistors.

[0041] The higher the crystallinity of the metal oxide, the lower the defect level density in the film. On the other hand, the lower the crystallinity... By using a metal oxide in the channel-forming region, a channel capable of carrying a large current can be created. It is possible to realize ZISTA.

[0042] <Composition of metal oxides> The composition of metal oxides will be explained in detail below. This shows the atomic ratios of indium, element M, and zinc.

[0043] The preferred range of the atomic ratios of indium, element M, and zinc in the metal oxide is shown in Figure 1A. This is shown in Figures 1B, 2A, and 2B. Figures 1A, 1B, 2A, and 2B are indium. Using an equilateral triangle with elements M and zinc as vertices, the atomic ratios of indium, element M, and zinc are determined. This is shown and is also called a triangular diagram, triangular coordinate diagram, or triangular figure. (See Figure 1A, Figure 1) B. Figures 2A and 2B do not show the atomic ratio of oxygen.

[0044] First, the atomic ratios of each element will be explained using Figures 3A, 3B, and 4. Figure 3A Figures 3B and 4 show examples of metal oxides containing elements X, Y, and Z, respectively. The triangular diagrams shown in Figures 3A, 3B, and 4 have points X, Y, and Z as vertices. A triangle and the coordinate point W(α:β:γ) are shown as an example of the composition of a metal oxide.

[0045] The coordinate point W(α:β:γ) is such that the atomic ratio of elements X, Y, and Z is X:Y:Z=α: This indicates that the ratio is β:γ. The atomic ratio of each element is higher closer to each vertex. The further away it is, the lower the value. Here, point X has coordinates (1:0:0) and elements X and Y. And the atomic ratio of element Z is X:Y:Z=1:0:0, that is, the metal oxide contains element X. This also indicates that it does not contain either element Y or element Z. Point Y has coordinates (0:1:0 ) and the atomic ratio of elements X, Y, and Z is X:Y:Z=0:1:0, that is, gold This indicates that the group oxide contains element Y, but does not contain either element X or element Z. Point Z has coordinates (0:0:1) and the atomic ratio of elements X, Y, and Z is X:Y:Z =0:0:1, meaning the metal oxide contains element Z, and also contains both element X and element Y. It indicates that they will not.

[0046] In this specification, the atomic ratio of elements X, Y, and Z is denoted as X:Y:Z. In some cases, the ratio of the total number of atoms of elements X and Y to the number of atoms of element Z is (X + Y ): This is sometimes written as Z. Other combinations of each element may be written similarly.

[0047] Figure 3A shows lines LNx, LNy, and LNz. Line LNx is the length of side YZ. The line LNx is the line connecting point Dx (0:β:γ), which divides the element in the ratio γ:β, and point X. It can also be described as the set of points where the atomic ratio of element Y to element Z is Y:Z=β:γ. The line LNy is the same as the edge X. The line LNy is the line connecting point Dy (α:0:γ), which divides the length of Z in the ratio γ:α, and point Y. It can also be described as the set of points where the atomic ratio of element X to element Z is X:Z=α:γ. The line LNz is Line L is the straight line connecting point Dz (α:β:0), which divides the length of side XY in the ratio β:α, and point Z. Nz can also be described as the set of points where the atomic ratio of elements X and Y satisfies X:Y=α:β. Lines LNx, LNy, and LNz all intersect the coordinate point W(α:β:γ).

[0048] In this specification, etc., "the straight line connecting point A and point B" is referred to as "the line segment connecting point A and point B". It can be replaced.

[0049] Here, the coordinate point W(α:β:γ) can also be said to be the intersection of the line LNx and the line LNy. Furthermore, the coordinate point W(α:β:γ) can also be said to be the intersection of line LNy and line LNz. The reference point W(α:β:γ) can also be described as the intersection of line LNx and line LNz.

[0050] Note that the ratio of the total number of atoms of element X and element Y to the number of atoms of element Z is (X + Y ): This is the set of points satisfying Z=1:0. In other words, the edge XY is such that the metal oxide is element X or This indicates that it has one or more elements of Y, and does not have element Z. The edge YZ is element The set of points where the atomic ratio of element X to the sum of elements Y and Z is X:(Y+Z)=0:1. Therefore, the side YZ contains one or more elements Y or Z in the metal oxide. This also indicates that element X is not present. The edge XZ is the sum of elements X and Z, and element Y This is the set of points where the atomic ratio of (X+Z):Y=1:0. In other words, edge XZ is a metal. This indicates that the oxide contains one or more elements X or Z, and does not contain element Y. It is.

[0051] As a concrete example, let's explain the case where the coordinate point W is (5:1:3). Coordinate point W(5:1: In case 3), the ratio of the length of line segment XDz to the length of line segment DzY is 1:5. The ratio of the lengths of line segments Dx and Z is 3:1. The ratio of the length of line segment XDy to the length of line segment DyZ is The ratio becomes 3:5. Also, the line LNx satisfies the atomic ratio of element Y to element Z: Y:Z=1:3. It is a point. The line LNy is the set of points where the atomic ratio of element X to element Z is X:Z=5:3. Yes, the line LNz is the set of points where the atomic ratio of element X to element Y is X:Y=5:1. .

[0052] Figure 3B shows lines PEx, PEy, and PEz. Line PEx is the coordinate point W( It is the perpendicular line drawn from α:β:γ) to side YZ. Line PEy is the coordinate point W(α:β:γ) This is a perpendicular line dropped to edge XZ. Line PEz is a perpendicular line dropped from coordinate point W(α:β:γ) to edge XY. This is the perpendicular line. Here, the ratio of the lengths of line PEx, line Pey, and line Pez is α :β:γ.

[0053] As a concrete example, let's explain the case where the coordinate point W is (5:1:3). Coordinate point W(5:1: In case 3), the ratio of the lengths of lines PEx, PEY, and Pez is 5:1:3. ru.

[0054] Figure 4A shows lines PAx, PAy, and PAz. Line PAx is parallel to side YZ. It is a straight line and intersects the coordinate point W(α:β:γ). Line PAy is a straight line parallel to side XZ. It is a line and intersects the coordinate point W(α:β:γ). Line PAz is a straight line parallel to side XY. Furthermore, the line PAx intersects with element X, element Y, and element It can also be described as the set of points where the ratio of the total number of atoms of prime Z satisfies X:(Y+Z)=α:(β+γ). Line PAy is the ratio of the total number of atoms of element X and element Z to the number of atoms of element Y (X+Z): It can also be described as the set of points satisfying Y=(α+γ):β. The line PAz represents the sum of elements X and Y. The set of points where the ratio of the number of atoms of element X to the number of atoms of element Z is (X+Y):Z=(α+β):γ That's also true.

[0055] As a concrete example, let's explain the case where the coordinate point W is (5:1:3). Coordinate point W(5:1: In case 3), the line PAx is the ratio of the number of atoms of element X to the total number of atoms of elements Y and Z. This is the set of points satisfying (Y+Z)=5:4. The line PAy is the sum of the elements X and Z. This is the set of points where the ratio of the number of atoms to the number of atoms of element Y is (X+Z):Y=8:1. (Line P) Az is the ratio of the total number of atoms of elements X and Y to the number of atoms of element Z, where (X+Y):Z=2 This is the set of points that satisfy :1.

[0056] The following describes metal oxides that can be suitably used in the channel formation region of a transistor. I will now explain the composition in detail.

[0057] [Composition of metal oxides 1] The metal oxide preferably contains indium and oxygen. It may contain one or more of element M or zinc. The composition of metal oxides that can be suitably used is shown in Figure 1A. Indium metal oxide The atomic ratio of element M and zinc falls within range 11 in the triangular diagram shown in Figure 1A. This is preferable. Range 11 is coordinate point A(1:0:0), coordinate point B(2:1:0), and coordinate Point C (14:7:1), coordinate point D (7:2:2), coordinate point E (14:4:21), The interior of the polygon formed by connecting coordinate point F(2:0:3) and the aforementioned coordinate point A with straight lines in that order. Note that range 11 also includes each coordinate point and each edge. Metals having compositions included in range 11. By using oxides in the channel formation region, high reliability and high field effect mobility are achieved. It can be made into a transistor.

[0058] Furthermore, if element M has multiple elements, the ratio of the total number of atoms of those elements is used. It is used as the atomic ratio of element M. For example, when element M is gallium and tin. The ratio of the total number of atoms of gallium and tin is used as the atomic ratio of element M.

[0059] Here, the coordinate point B(2:1:0) is the set of points satisfying (In+M):Zn=1:0. The intersection point C is the point where line L1 intersects with line L2, which is the set of points satisfying In:M=2:1. (14:7:1) is the set of points that satisfy the aforementioned line L2 and In:(M+Zn)=7:4. It is the intersection point of a certain line L3. Also, the coordinate point C is the same as the aforementioned line L2, with In:Zn=14:1. It is also an intersection point of line L4, which is the set of points that satisfy the condition. Coordinate point D(7:2:2) is the same as the aforementioned line L3 And it is the intersection point of line L5, which is the set of points satisfying In:Zn=7:2. Also, coordinate point D is It is also the intersection point of the aforementioned line L3 and line L6, which is the set of points satisfying In:M=7:2. The reference point E(14:4:21) is the set of points that satisfy the aforementioned line L6 and In:Zn=2:3. It is the intersection point of a certain line L7. The coordinate point F(2:0:3) is the intersection point of the aforementioned line L7 and (In+Zn) These are the intersection points of line L8, which is the set of points satisfying :M=1:0.

[0060] In this specification, the ratio of the number of atoms of indium, element M, and zinc is referred to as In:M:Z. It is sometimes denoted as n. Also, the ratio of the total number of atoms of indium and element M to the number of atoms of zinc. This is sometimes written as (In+M):Zn. The same applies to other combinations of each element. .

[0061] Side AB lies on the aforementioned line L1, side BC lies on the aforementioned line L2, and side CD lies on the aforementioned line L 3 is on the line L6, edge DE is on the aforementioned line L6, edge EF is on the aforementioned line L7, and edge FA is It lies on line L8 as mentioned above. In other words, range 11 is on lines L1, L2, L3, L6, and L7. It can also be said that it is the interior of a polygon enclosed by line L8.

[0062] The composition of the metal oxide satisfies line L2, In:M=2:1, as shown in range 11. It is preferable that the indium content is higher than In:M = 2:1. In other words, element M It is preferable that the ratio of the number of indium atoms to the number of other atoms, In / M, is 2 or greater. Metal oxides with a high zinc content have high carrier mobility (electron mobility), and indium content Transistors using metal oxides with a high efficiency in the channel formation region have high field-effect mobility. It can conduct a large current.

[0063] However, a high content of element M increases the number of defect levels, which alters the threshold voltage in reliability tests. The dynamic range can sometimes become large. This is one of the indicators used to evaluate the reliability of transistors. And, the gate is held in a state where an electric field is applied to it, GBT (Gate Bias Tempo There is a stress test (ratio). In particular, the source potential and drain potential A test in which a positive potential is applied to the gate and held at a high temperature is called PBTS (Positive Potential Test). (e Bias Temperature Stress) test, applying a negative potential to the gate. In this state, a test is conducted in which the condition is maintained at a high temperature (NBTS - Negative Bias Tempe This is called a stress test. It also involves irradiating the body with light such as white LED light. The PBTS and NBTS tests conducted at the following locations are referred to as PBTIS (Positive Biological Inspection System). (as a test of NB) TIS(Negative Bias Temperature Illuminati) This is called an "on-stress" test.

[0064] In particular, in n-type transistors using metal oxides, when the transistor is in the ON state ( When current is flowing, a positive potential is applied to the gate. Therefore, PBTS test The amount of variation in the threshold voltage is an important factor to consider as an indicator of transistor reliability. It will be one of them.

[0065] Here, by using a metal oxide that does not contain element M, or has a low content of element M, The variation in threshold voltage in PBTS testing can be reduced. Furthermore, it contains element M. In some cases, the composition of the metal oxide is such that the content of element M is smaller than the indium content. It is preferable to do so. Furthermore, the ratio of the number of indium atoms to the number of atoms of element M, In / M, is Preferably, it is 2 or more. This makes it possible to realize a highly reliable transistor. It is possible.

[0066] One factor causing the threshold voltage fluctuation in PBTS testing is the relationship between the semiconductor layer and the gate insulating layer. Examples include defect levels at or near the interface. The higher the defect level density, the higher the PB Degradation becomes significant in TS tests. However, in the part of the semiconductor layer that is in contact with the gate insulating layer. By reducing the content of element M, the formation of the defect level can be suppressed. .

[0067] By not including element M, or by reducing the content of element M, PBTS degradation can be suppressed. Possible reasons for this include the following: The element M contained in the semiconductor layer is also Compared to other metallic elements (such as indium and zinc), it has a property that makes it more likely to attract oxygen. Therefore, at the interface between the metal oxide film containing a large amount of element M and the insulating layer containing oxide, Element M combines with excess oxygen in the insulating layer, creating a carrier (electron) trap site. It is presumed that this makes it easier to cause this. Therefore, when a positive potential is applied to the gate... In this case, carriers are trapped at the interface between the semiconductor layer and the gate insulating layer, thus creating a threshold. The voltage value may fluctuate.

[0068] Therefore, metal acids in which the ratio of the number of indium atoms to the number of atoms of element M (In / M) is 2 or greater By using the ion in the channel formation region, the generation of defect levels can be suppressed, resulting in high reliability. Furthermore, it is possible to create a transistor with high field-effect mobility.

[0069] The composition of the metal oxide is as shown in range 11, line L3: In:(M+Zn)=7: It is preferable that the condition satisfies 4, or that the indium content is higher than In:(M+Zn)=7:4. In other words, the ratio of the number of indium atoms to the total number of atoms of element M and zinc is In / (M+ It is preferable that the indium content is 7 / 4 or more. Metal oxides with a high indium content are... Metal oxides with high rear mobility (electron mobility) and high indium content form channel-forming regions. The transistor used in this region has high field-effect mobility and can conduct large currents. Therefore, metal oxides having the atomic ratio within the aforementioned range are used in the channel-forming region. This allows for the creation of transistors with higher field-effect mobility.

[0070] The composition of the metal oxide satisfies line L6, In:M=7:2, as shown in range 11. Alternatively, it is preferable that the indium content is higher than In:M = 7:2. In other words, element M It is preferable that the ratio of the number of indium atoms to the number of atoms of , In / M, is 7 / 2 or greater. By using a metal oxide having an atomic ratio within the aforementioned range in the channel formation region, defects can be eliminated. To create a transistor that can suppress the generation of energy levels, is highly reliable, and has high field-effect mobility. It is possible.

[0071] The composition of the metal oxide satisfies line L7, In:Zn=2:3, as shown in range 11. It is preferable that the indium content is higher than In:Zn = 2:3. It is preferable that the ratio of indium atoms to lead atoms (In / Zn) is 2 / 3 or greater. High zinc content can result in polycrystalline metal oxides. These become defect levels and act as carrier traps and carrier sources, thus polycrystalline metallic acids Transistors using synthetic materials often exhibit large fluctuations in electrical characteristics, resulting in low reliability. Therefore, by setting the atomic ratio to the aforementioned range, the metal oxide becomes polycrystalline. It can be suppressed. Furthermore, by using the metal oxide in the channel formation region, reliability can be increased. It can be made into a transistor.

[0072] As the metal oxide, an In-M-Zn oxide having a composition within range 11 is used. This can be done. As an In-M-Zn oxide, for example, In:M:Zn = 5:1:1, In :M:Zn=5:1:2, In:M:Zn=5:1:3, In:M:Zn=5:1:4, In:M:Zn=5:1:5, In:M:Zn=5:1:6, In:M:Zn=10:1 :1, In:M:Zn=10:1:2, In:M:Zn=10:1:3, In:M:Zn =10:1:4, In:M:Zn=10:1:5, In:M:Zn=10:1:6, In :M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=10:1 :10, In:M:Zn=10:1:12, In:M:Zn=10:1:15, or this These vicinity can be suitably used. In addition, indium oxide can be used as the metal oxide. It is possible to use it. Furthermore, In-M oxide can be used as the metal oxide. For nM oxides, for example, In:M=2:1, In:M=7:2, In:M=5:1 In:M=7:1, In:M=10:1, or a range near these values ​​can be preferably used. In addition, In-Zn oxide can be used as the metal oxide. As examples of chromosomes, for instance, In:Zn=2:3, In:Zn=3:2, In:Zn=7:2, In:Zn=4:1, In:Zn=11:2, In:Zn=7:1, In:Zn=14: 1, or a vicinity thereof, can be preferably used.

[0073] For example, energy-dispersive X-ray spectroscopy (EDX) is used as an analytical technique for the composition of metal oxides. Energy Dispersive X-ray spectroscopy), X-ray Photoelectron spectroscopy (XPS:X-ray Photoelectron Spectrosc) Opy), Inductively Coupled Plasma Mass Spectrometry (ICP-MS) (inductively coupled plasma-mass spectrometry), Emission spectroscopy (ICP-AES: Inductively Coupled Plasma Emission Spectroscopy) - Atomic Emission Spectroscopy (ATOM) and other methods can be used. It is possible. However, for elements with low content, the actual content may differ from the analysis result due to the influence of analytical accuracy. The obtained content may differ. For example, if the content of element M is low, the analysis may show The resulting element M content may be lower than the actual content.

[0074] Furthermore, when forming metal oxides by sputtering, the atomic ratio of the target and the The atomic ratio of metal oxides can vary. In particular, zinc may have a different atomic ratio than the target. The atomic ratio of metal oxides may decrease. Specifically, the zinc contained in the target The atomic ratio may be between 40% and 90%. The target used here is Polycrystalline is preferable.

[0075] [Composition of metal oxides 2] Metal oxides contain one or more of the elements M or zinc, indium, and oxygen. Preferably, a metal oxide suitable for use in the channel formation region of a transistor. The composition of the substance is shown in Figure 1B. The atomic ratios of indium, element M, and zinc in the metal oxide are shown in Figure In the triangular diagram shown in 1B, it is preferable that it is included in range 13. Range 13 is coordinate point G (7:1:0), coordinate point B(2:1:0), coordinate point C(14:7:1), and coordinate point D (7:2:2), coordinate point E(14:4:21), coordinate point F(2:0:3), and coordinate point This is the interior of the polygon formed by connecting H(7:0:1) and the aforementioned coordinate point G with straight lines in that order. Range 13 also includes each coordinate point and each edge. Metal oxides having compositions included in Range 13. By using this in the channel formation region, a highly reliable and high field-effect mobility transistor is produced. It can be used as a generator.

[0076] Here, the coordinate point G(7:1:0) is the set of points satisfying (In+M):Zn=1:0. It is the intersection of a line L1 and a line L9 which is the set of points satisfying In:(M+Zn)=7:1. The coordinate point H(7:0:1) is the point that satisfies (In+Zn):M=1:0 with the aforementioned line L9. These are the intersection points of line L8, which is the set of points. For coordinate points B through F, please refer to the description above. Since it is possible, a detailed explanation will be omitted.

[0077] Edge GB lies on the aforementioned line L1, edge BC lies on the aforementioned line L2, and edge CD lies on the aforementioned line L 3 is on the line L6 mentioned above, edge DE is on the line L7 mentioned above, edge EF is on the line L7 mentioned above, edge FH is It lies on the aforementioned line L8, and edge HG lies on the aforementioned line L9. In other words, range 13 is on line L1, It is also the interior of the polygon enclosed by lines L2, L3, L6, L7, L8, and L9. Yes, I can.

[0078] The composition of the metal oxide is as shown in range 13, line L9, In:(M+Zn)=7: It is preferable that the formula satisfies 1, or that the In content is lower than In:(M+Zn)=7:1. In other words, the ratio of the number of indium atoms to the total number of atoms of element M and zinc is In / (M+Zn). However, it is preferable that it be 7 or less. If the indium content is high, the metal oxide will be bixba In some cases, a lithotype crystal structure may be formed. Alternatively, the metal oxide may have a bixbite-type crystal structure. In some cases, a crystalline structure may exist in which layered crystalline structures coexist. Grain boundaries can form between different crystal structures. Grain boundaries are defect levels and As such, metal oxides with grain boundaries become carrier traps and carrier sources. Transistors using this technology can exhibit large fluctuations in electrical characteristics, resulting in low reliability. Therefore, by setting the atomic ratio within the aforementioned range, the metal oxide becomes a bixbite type crystal. The formation of a structure is suppressed, and it becomes easier to have a layered crystalline structure. By using this in the channel formation region, a highly reliable transistor can be created. .

[0079] The composition of the metal oxide satisfies line L2, In:M=2:1, as shown in range 13. It is preferable that the indium content is higher than In:M = 2:1. In other words, element M It is preferable that the ratio of the number of indium atoms to the number of atoms of the other substance (In / M) is 2 or greater. By using a metal oxide with an atomic ratio within this range in the channel formation region, defect levels can be formed. This allows for the suppression of generation, resulting in a highly reliable transistor with high field-effect mobility. Cut.

[0080] The composition of the metal oxide is as shown in range 13, line L3: In:(M+Zn)=7: It is preferable that the condition satisfies 4, or that the indium content is higher than In:(M+Zn)=7:4. In other words, the ratio of the number of indium atoms to the total number of atoms of element M and zinc is In / (M+ Preferably, Zn is 7 / 4 or more. By using this in the channel formation region, a transistor with high field-effect mobility can be created. can.

[0081] The composition of the metal oxide satisfies line L6, In:M=7:2, as shown in range 13. Alternatively, it is preferable that the indium content is higher than In:M = 7:2. In other words, element M It is preferable that the ratio of the number of indium atoms to the number of atoms of , In / M, is 7 / 2 or greater. By using a metal oxide having an atomic ratio within the aforementioned range in the channel formation region, defects can be eliminated. To create a transistor that can suppress the generation of energy levels, is highly reliable, and has high field-effect mobility. It is possible.

[0082] The composition of the metal oxide satisfies line L7, In:Zn=2:3, as shown in range 13. It is preferable that the indium content is higher than In:Zn = 2:3. It is preferable that the ratio of indium atoms to lead atoms (In / Zn) is 2 / 3 or greater. By setting the atomic ratio within the aforementioned range, the formation of polycrystalline metal oxides can be suppressed. By using the metal oxide in the channel formation region, a highly reliable transistor can be produced. It is possible.

[0083] As the metal oxide, an In-M-Zn oxide having a composition included in range 13 is used. This can be done. As an In-M-Zn oxide, for example, In:M:Zn = 5:1:1, In :M:Zn=5:1:2, In:M:Zn=5:1:3, In:M:Zn=5:1:4, In:M:Zn=5:1:5, In:M:Zn=5:1:6, In:M:Zn=10:1 :1, In:M:Zn=10:1:2, In:M:Zn=10:1:3, In:M:Zn =10:1:4, In:M:Zn=10:1:5, In:M:Zn=10:1:6, In :M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=10:1 :10, In:M:Zn=10:1:12, In:M:Zn=10:1:15, or this These vicinity can be suitably used. In addition, In-M oxide can be used as the metal oxide. It can exist. As an In-M oxide, for example, In:M=2:1, In:M=7: 2. In:M=5:1, In:M=7:1, or a range close to these can be preferably used. In addition, In-Zn oxide can be used as the metal oxide. As examples of chromosomes, for instance, In:Zn=2:3, In:Zn=3:2, In:Zn=7:2, In:Zn=4:1, In:Zn=11:2, In:Zn=7:1, or neighborhoods of these. This can be used suitably.

[0084] [Composition of metal oxides 3] The metal oxide preferably contains indium, zinc, and oxygen. It may also contain element M. It is suitable for use in the channel formation region of a transistor. The composition of the resulting metal oxide is shown in Figure 2A. The metal oxides are indium, element M, and zinc. The atomic ratio is preferably included within range 15 in the triangular diagram shown in Figure 2A. 5 is coordinate point I (44:11:10), coordinate point J (4:1:6), and coordinate point F (2:0 A polygon formed by connecting point 3), coordinate point K(11:0:2), and the aforementioned coordinate point I with straight lines in this order. This is the interior of [the region]. Note that range 15 also includes each coordinate point and each edge. Composition included in range 15 By using a metal oxide having the properties of the field effect in the channel formation region, a highly reliable and field-effect-resistant material is obtained. This allows for the creation of transistors with high reproductive mobility.

[0085] Here, the coordinate point I(44:11:10) is the set of points satisfying In:M=4:1. The intersection of line L10 and line L11, which is the set of points satisfying (In+M):Zn=11:2 The coordinate point J(4:1:6) is the intersection of the aforementioned line L7 and the aforementioned line L10. K(11:0:2) is the intersection of the aforementioned line L11 and the aforementioned line L8. Regarding coordinate point F... Therefore, since the above information can be found, a detailed explanation will be omitted.

[0086] Edge IJ lies on the aforementioned line L10, edge JF lies on the aforementioned line L7, and edge FK lies on the aforementioned line It lies on line L8, and edge KI lies on the aforementioned line L11. In other words, range 15 is on line L10, line L 7. It can also be said that it is the interior of the polygon enclosed by lines L8 and L11.

[0087] The composition of the metal oxide satisfies line L10, In:M=4:1, as shown in range 15. It is preferable that the In content is higher than In:M = 4:1. In other words, the original content of element M It is preferable that the ratio In / M of the number of indium atoms to the number of sub atoms is 4 or more. By using the metal oxide having the atomic ratio within the above range in the channel formation region, generation of defect levels can be suppressed, and a transistor with high reliability and high field-effect mobility can be obtained. It is preferable that the composition of the metal oxide satisfies In:Zn = 2:3 which is the line L7 as shown in Range 15, or that the indium content rate is higher than In:Zn = 2:3. That is, it is preferable that the ratio In / Zn of the number of indium atoms to the number of zinc atoms is 2 / 3 or more. By setting the atomic ratio within the above range, it is possible to suppress the metal oxide from becoming polycrystalline. Also, by using the metal oxide in the channel formation region, a transistor with high reliability can be obtained. .

[0088] It is preferable that the composition of the metal oxide satisfies (In + M):Zn = 11:2 which is the line L11 as shown in Range 15, or that the zinc content rate is higher than (In + M):Zn = 11:2. That is, it is preferable that the ratio (In + M) / Zn of the total number of indium and element M atoms to the number of zinc atoms is 11 / 2 or less. Since the metal oxide has zinc, it tends to have a layered crystal structure. Also, the higher the zinc content rate, the higher the crystallinity of the metal oxide. As the metal oxide, an In-M-Zn oxide having a composition included in Range 15 can be used. As the In-M-Zn oxide, for example, In:M:Zn = 5:1:2, In:M:Zn = 5:1:3, In:M:Zn = 5:1:4, In:M:Zn = 5:1:5,

[0089]

[0090] ​​​​​​​​​​​​​​In:M:Zn = 5:1:6, In:M:Zn = 10:1:2, In:M:Zn = 10: 1:3, In:M:Zn = 10:1:4, In:M:Zn = 10:1:5, In:M:Z n = 10:1:6, In:M:Zn = 10:1:7, In:M:Zn = 10:1:8, I n:M:Zn = 10:1:10, In:M:Zn = 10:1:12, In:M:Zn = 1 0:1:15, or those in the vicinity thereof can be preferably used. Also, as the metal oxide te, In-Zn oxide can be used. As the In-Zn oxide, for example, In: Zn = 2:3, In:Zn = 3:2, In:Zn = 7:2, In:Zn = 4:1, In: Zn = 11:2, In:Zn = 7:1, or those in the vicinity thereof can be preferably used .

[0091] The metal oxide has a composition within the aforementioned range and is CAAC-OS (c-axis Alig ned Crystalline Oxide Semiconductor), nc- OS (nanocrystalline oxide semiconductor), or CAC-OS (Cloud-Aligned Composite Oxide Semiconductor), which is preferable.

[0092] Here, CAC-OS, which is a metal oxide that can be used in a transistor, and CA AC-OS will be described.

[0093] 〔Structure of Metal Oxide〕 CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and has a function as a semiconductor in the whole material. Note that CAC-OS or CAC-m When ethanol oxide is used in the active layer of a transistor, its conductive function is due to the carrier The function of A is to allow electrons (or holes) to flow, and the insulating function is to allow carrier electrons to flow. It has a function to prevent flow. It utilizes the complementary functions of conductivity and insulation. This allows the switching function (the function to turn on / off) to be controlled by CAC-OS or CAC -Can be applied to metal oxide. CAC-OS or CAC-meta In 1-oxide, by separating the functions of each component, the functions of both components can be maximized. It is possible to do so.

[0094] CAC-OS or CAC-metal oxide has conductive regions and insulating regions. The conductive region has the conductive function described above, and the insulating region has the insulating function described above. It has the following properties. Furthermore, within the material, the conductive region and the insulating region are separated at the nanoparticle level. They may be separated. Also, conductive regions and insulating regions are unevenly distributed within the material. In some cases, the conductive region may appear as a cloud-like, connected area with a blurred periphery. There is.

[0095] In CAC-OS or CAC-metal oxide, there is a conductive region and an insulating region. The range refers to a range of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. The particles may be dispersed within the material depending on their size.

[0096] CAC-OS or CAC-metal oxides have different band gaps. It is composed of the following components. For example, CAC-OS or CAC-metal oxide is Components with a wide gap due to the insulating region and components with a narrow gap due to the conductive region It is composed of a component having a narrow gap. In the component having a narrow gap, carriers mainly flow. Also, the component having a narrow gap acts complementarily to the component having a wide gap, and carriers also flow through the component having a wide gap in conjunction with the component having a narrow gap. Therefore, when the above CAC-OS or CAC-metal oxide is used for the channel formation region of a transistor , a high current driving force, that is, a large on-current, and a high field-effect mobility can be obtained in the on-state of the transistor. That is, CAC-OS or CAC-metal oxide can also be referred to as a matrix composite (matrix composite), or a metal matrix composite (metal matrix composite).

[0097] (matrix composite), or a metal matrix composite (metal matrix composite). That is, CAC-OS or CAC-metal oxide can also be referred to as a matrix composite

[0098] (matrix composite), or a metal matrix composite (metal matrix composite). 〔Structure of Metal Oxide〕 Oxide semiconductors can be divided into single-crystalline oxide semiconductors and other non-single-crystalline oxide semiconductors. Examples of non-single-crystalline oxide semiconductors include CAAC-OS, polycrystalline oxide semiconductors, nc-OS, pseudo-amorphous oxide semiconductors (a-like OS: amorphous-like oxide semiconductor), and amorphous oxide semiconductors.

[0099] Oxide semiconductors may be classified differently when focusing on the crystal structure. Here, the classification of the crystal structure in oxide semiconductors will be described using Fig. 5A. Fig. 5A is a diagram for explaining the classification of the crystal structure of an oxide semiconductor, typically IGZO (metal oxide containing In, Ga, and Zn). 5A is a diagram for explaining the classification of the crystal structure of an oxide semiconductor, typically IGZO (metal oxide containing In, Ga, and Zn).

[0100] 5A is a diagram for explaining the classification of the crystal structure of an oxide semiconductor, typically IGZO (metal oxide containing In, Ga, and Zn).

[0100] As shown in Figure 5A, IGZO can be broadly divided into Amorphous and Crystal They are classified into line and crystal. Furthermore, within Amorphous, It includes completely amorphous components. Also, Crystalline Among them are CAAC (c-axis aligned crystalline), nc (nanocrystalline), and CAC (Cloud-Aligned Co This includes mposite. Note that the classification of Crystalline includes the si (described later). ngle crystals and polycrystals are excluded. Also, Crys The term "tal" includes single crystals and polycrystals. It can be done.

[0101] Note that the structure within the thick frame shown in Figure 5A is in the New crystalline phase. It is a structure to which it belongs. This structure is the boundary area between Amorphous and Crystal. It is in the region. That is, the energetically unstable Amorphous and Crystal This can be rephrased as having a completely different structure from ine.

[0102] The crystal structure of the film or substrate can be determined by X-ray diffraction (XRD). It can be evaluated using an ion pattern. Here, quartz glass and Cryst X of IGZO (also called crystalline IGZO) which has a crystalline structure classified as alline The RD spectra are shown in Figures 5B and 5C. Figure 5B shows the quartz glass, and Figure 5C shows the crystal. This is the XRD spectrum of crystalline IGZO. Note that the composition of crystalline IGZO shown in Figure 5C is I n:Ga:Zn = 4:2:3 [atomic ratio]. Also, the crystalline IGZO shown in Figure 5C The thickness is 500 nm.

[0103] As shown by the arrow in Figure 5B, the peaks in the XRD spectrum of quartz glass are nearly symmetrical. On the other hand, as shown by the arrow in Figure 5C, crystalline IGZO has a pinpoint XRD spectrum. The peaks are asymmetrical. The asymmetrical peaks in the XRD spectrum indicate that the crystal is Its presence is clearly indicated. In other words, if the peaks in the XRD spectrum are not symmetrical, Am It cannot be said that it is orphosal. Note that Figure 5C shows 2θ = 31° or its vicinity. It is clearly stated that it is a nanocrystal. The peaks in the XRD spectrum are Therefore, it is presumed that the asymmetry is due to the microcrystals in question.

[0104] Specifically, as shown in Figure 5C, crystalline IGZO has a 2θ spectrum in its XRD spectrum. It has a peak at 2θ=34° or near it. Also, the microcrystals have a peak at 2θ=31° or near it. It has a peak nearby. When evaluating oxide semiconductor films using X-ray diffraction patterns, see Figure 5C. As shown, the spectral width at angles lower than the peak at 2θ=34° or nearby is It widens. This is because the oxide semiconductor film has a peak at or near 2θ = 31°. This suggests the presence of microcrystals.

[0105] CAAC-OS has c-axis orientation and multiple nanocrystals are linked in the ab-plane direction. It has a crystalline structure that is linked and distorted. Note that distortion refers to the linkage between multiple nanocrystals. Within a region, between a region with a aligned grid arrangement and another region with a aligned grid arrangement, the grid arrangement This refers to the point where the orientation has changed.

[0106] Nanocrystals are based on a hexagonal shape, but they are not necessarily regular hexagons; they can also be non-regular hexagonal. Furthermore, the distortion may have a grid arrangement such as pentagons and heptagons. Furthermore, in CAAC-OS, even near strain, clear grain boundaries (grain bounds) are present. It is not possible to confirm the grain boundaries (also known as dally). In other words, due to the distortion of the lattice arrangement, the grain boundaries It can be seen that the formation is suppressed. This is because CAAC-OS is in the ab plane direction The arrangement of oxygen atoms is not dense, and the bond distance between atoms changes due to the substitution of metal elements. This is thought to be because distortion can be tolerated by processes such as transformation.

[0107] Furthermore, crystal structures in which clear grain boundaries can be observed are known as multi-grain structures. It is called a polycrystal. The grain boundaries become recombination centers, and carriers A is trapped, causing a decrease in the transistor's on-current or a decrease in its field-effect mobility. It is highly likely. Therefore, CAAC-OS, in which no clear grain boundaries can be identified, is a transistor It is one of the crystalline oxides having a crystal structure suitable for semiconductor layers. A configuration containing Zn is preferred for S. For example, In-Zn oxide and In -Ga-Zn oxide is preferred because it can suppress the generation of grain boundaries more effectively than In oxide.

[0108] CAAC-OS consists of a layer containing indium and oxygen (hereinafter referred to as the In layer), and the element M, sub A layered crystalline structure in which layers containing lead and oxygen (hereinafter referred to as (M,Zn) layers) are stacked (layered It tends to have a structure (also called a structure). Furthermore, indium and element M are mutually substitutable. Furthermore, when the element M in the (M,Zn) layer is replaced with indium, it is represented as the (In,M,Zn) layer. It is also possible that if the indium in the In layer is replaced by element M, the (In,M) layer and the surface It is possible.

[0109] CAAC-OS is a highly crystalline oxide semiconductor. On the other hand, CAAC-OS has a clear Since grain boundaries cannot be identified, a decrease in electron mobility caused by grain boundaries occurs. It can be said that it is difficult. Also, the crystallinity of oxide semiconductors is affected by the inclusion of impurities and the formation of defects. Because it may decrease, CAAC-OS is an oxidation product with fewer impurities and defects (such as oxygen deficiencies). It can also be called a material semiconductor. Therefore, oxide semiconductors containing CAAC-OS have stable physical properties. Therefore, oxide semiconductors containing CAAC-OS are heat-resistant and highly reliable. Furthermore, CAAC-OS is designed to withstand high temperatures (so-called thermal budgets) in the manufacturing process. It is also stable. Therefore, when using CAAC-OS in OS transistors, the manufacturing process This will allow for greater flexibility.

[0110] nc-OS is used in minute regions (for example, regions between 1 nm and 10 nm, especially regions larger than 1 nm). It has periodicity in the atomic arrangement in the region of 3 nm or less. Also, nc-OS has different na No regularity is observed in the crystal orientation between the crystals. Therefore, no orientation is observed throughout the entire film. Therefore, depending on the analytical method, nc-OS may be a-like OS or amorphous oxide semiconductor. It can sometimes be indistinguishable from the body.

[0111] a-like OS is an oxide having a structure between nc-OS and amorphous oxide semiconductors. It is a semiconductor. an a-like OS has porous or low-density regions. That is, a-like OS has lower crystallinity compared to nc-OS and CAAC-OS.

[0112] Oxide semiconductors can take on diverse structures, each possessing different properties. One embodiment of the present invention Oxide semiconductors include amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, and n It may have two or more types of c-OS and CAAC-OS.

[0113] [Transistors containing oxide semiconductors] Next, we will explain the case where the above oxide semiconductor is used in a transistor.

[0114] By using the above oxide semiconductor in a transistor, a transistor with high field-effect mobility is obtained. This can be achieved. Furthermore, highly reliable transistors can be realized.

[0115] It is preferable to use an oxide semiconductor with a low carrier concentration for the transistor. When lowering the carrier concentration of a semiconductor film, the impurity concentration in the oxide semiconductor film is reduced. Therefore, it is sufficient to lower the defect level density. In this specification, the impurity concentration is low and the defect level A low particle density is referred to as high-purity intrinsic or substantially high-purity intrinsic.

[0116] High-purity intrinsic or substantially high-purity intrinsic oxide semiconductor films have a low defect level density. In some cases, the trap level density may also be low.

[0117] Charges trapped in the trap levels of oxide semiconductors take a long time to disappear. It can sometimes behave as if it were a fixed charge. Therefore, oxidation with a high trap level density In transistors where a channel formation region is formed in a semiconductor material, the electrical characteristics become unstable. There is.

[0118] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0119] [Impurities] Here, the effects of various impurities in the oxide semiconductor will be described.

[0120] When silicon or carbon, which is one of the Group 14 elements, is contained in the oxide semiconductor, defect levels are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon near the interface with the oxide semiconductor (the concentration obtained by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry)) are set to 2 × 10 atoms / cm or less, preferably 2 × 10 atoms / cm 18 or less. 3 17 a toms / cm 3 or less.

[0121] When an alkali metal or an alkaline earth metal is contained in the oxide semiconductor, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have normally-on characteristics. For this reason, it is preferable to reduce the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor. Specifically, the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor obtained by SIMS is 1 × 10 atoms / cm or less. 18 atoms / cm 3 ​​​The following is preferably 2 × 10 16 atoms / cm 3 Do the following:

[0122] In oxide semiconductors, when nitrogen is present, electrons, which act as carriers, are generated, and the carrier concentration... The nitrogen content increases, making it easier to create an n-type semiconductor. As a result, oxide semiconductors containing nitrogen are used as semiconductors. Transistors tend to exhibit normally-on characteristics. Therefore, in the oxide semiconductor, It is preferable that nitrogen is reduced as much as possible; for example, the nitrogen concentration in an oxide semiconductor is In SIMS, 5 × 10 19 atoms / cm 3 Less than 5 × 10 18 a toms / cm 3 More preferably 1 × 10 18 atoms / cm 3 Below, further better Mashikuha 5 x 10 17 atoms / cm 3 The following applies:

[0123] Hydrogen contained in oxide semiconductors reacts with oxygen bonded to metal atoms to form water, so acid In some cases, an elementary defect may form. When hydrogen enters this oxygen defect, an electron, which acts as a carrier, is produced. This can occur. Also, some of the hydrogen combines with oxygen that is bonded to a metal atom, forming a carrier. It can generate electrons. Therefore, using an oxide semiconductor containing hydrogen... Lampistors tend to exhibit normally-on characteristics. Therefore, hydrogen in oxide semiconductors is formed. It is preferable that it be reduced as much as possible. Specifically, in oxide semiconductors, SIMS The hydrogen concentration obtained is 1 × 10 20 atoms / cm 3 Less than 1 × 10 1 9atoms / cm 3 Less than 5x10 18 atoms / cm 3 less than, further Preferably 1 × 10 18 atoms / cm 3 Less than.

[0124] Using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor. This allows for the provision of stable electrical characteristics.

[0125] [Composition of metal oxides 4] The metal oxide preferably contains indium, zinc, and oxygen. It may also contain element M. It is suitable for use in the channel formation region of a transistor. The composition of the resulting metal oxide is shown in Figure 2B. The metal oxides are indium, element M, and zinc. The atomic ratio is preferably included in range 17 in the triangular diagram shown in Figure 2B. 7 is coordinate point I (44:11:10), coordinate point L (4:1:4), and coordinate point M (1:0 A polygon formed by connecting point 1), coordinate point K(11:0:2), and the aforementioned coordinate point I with straight lines in this order. This is the interior of [the region]. Note that range 17 also includes each coordinate point and each edge. Composition included in range 17 By using a metal oxide having the properties of the field effect in the channel formation region, a highly reliable and field-effect-resistant material is obtained. This allows for the creation of transistors with high reproductive mobility.

[0126] Here, the coordinate point L(4:1:4) satisfies the ratio In:Zn=1:1 with the aforementioned line L10. It is the intersection point of line L12, which is a set of points. The coordinate point M(1:0:1) is the same as the aforementioned line L12, This is the intersection point of the aforementioned line L8. For coordinate points I and K, please refer to the previously mentioned description. Therefore, a detailed explanation will be omitted.

[0127] Edge IL lies on the aforementioned line L10, edge LM lies on the aforementioned line L12, and edge MK lies on the aforementioned line It lies on line L8, and edge KI lies on the aforementioned line L11. In other words, range 17 is on line L10, line It can also be said that it is the interior of a polygon enclosed by lines L12, L8, and L11.

[0128] The composition of the metal oxide satisfies line L10, In:M=4:1, as shown in range 17. It is preferable that the In content is higher than In:M = 4:1. In other words, the original content of element M The ratio of the number of indium atoms to the number of electrons, In / M, is preferably 4 or greater. Defect levels are generated by using a metal oxide with a specific atomic ratio in the channel formation region. This allows for the suppression of certain behaviors, resulting in a highly reliable transistor with high field-effect mobility. .

[0129] The composition of the metal oxide satisfies line L12, In:Zn=1:1, as shown in range 17. It is preferable that the indium content is higher than In:Zn = 1:1. It is preferable that the ratio of indium atoms to zinc atoms (In / Zn) is 1 or greater. By setting the atomic ratio within the aforementioned range, the formation of polycrystalline metal oxides can be suppressed. Since the oxides are less likely to form polycrystalline structures, the margin for the conditions required for metal oxide formation can be widened. Furthermore, by using the metal oxide in the channel formation region, a highly reliable tunnel can be formed. It can be used as a generator.

[0130] The composition of the metal oxide is as shown in range 17, line L11 (In+M):Zn=1 It is preferable that the ratio satisfies 1:2, or that the zinc content is higher than (In+M):Zn=11:2. In other words, the ratio of the total number of atoms of indium and element M to the number of zinc atoms (In+M) It is preferable that the Zn content is 1 1 / 2 or less. It has high crystallinity. Furthermore, by using this metal oxide in the channel-forming region, This allows for the creation of highly reliable transistors.

[0131] As the metal oxide, an In-M-Zn oxide having a composition within range 17 is used. This can be done. As an In-M-Zn oxide, for example, In:M:Zn=5:1:2, In :M:Zn=5:1:3, In:M:Zn=5:1:4, In:M:Zn=5:1:5, In:M:Zn=10:1:2, In:M:Zn=10:1:3, In:M:Zn=10 :1:4, In:M:Zn=10:1:5, In:M:Zn=10:1:6, In:M: Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=10:1:10 , or their vicinity can be suitably used as metal oxides. n oxides can be used. For example, as an in-Zn oxide, In:Zn = 2:3 , In:Zn=3:2, In:Zn=7:2, In:Zn=4:1, In:Zn=11: 2. In:Zn = 7:1, or a ratio close to these, can be preferably used.

[0132] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., are at least a part of them. This can be implemented by combining it with other configuration examples or drawings as appropriate.

[0133] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0134] (Embodiment 2) In this embodiment, the configuration example of a semiconductor device to which the metal oxide shown in Embodiment 1 is applied is as follows: I will now explain this. In this embodiment, as an example of a semiconductor device, a semiconductor in which a channel is formed is This section describes transistors that use metal oxides in their conductive layers. I will explain using an example.

[0135] <Configuration Example 1> [Configuration Example 1-1] Figure 6A shows a schematic cross-sectional view of transistor 10 in the channel length direction.

[0136] The transistor 10 consists of an insulating layer 103, a semiconductor layer 108, an insulating layer 110, and a metal oxide It has a physical layer 114 and a conductive layer 112. The insulating layer 110 functions as a gate insulating layer. The conductive layer 112 functions as a gate electrode.

[0137] Using a conductive film containing a metal or alloy as the conductive layer 112 lowers the electrical resistance. This is preferable because it allows for this. Furthermore, a conductive film containing an oxide may be used for the conductive layer 112.

[0138] The metal oxide layer 114 has the function of supplying oxygen to the insulating layer 110. Also, the conductive layer When a conductive film containing a metal or alloy that is easily oxidized as 112 is used, metal oxide Layer 114 is a barrier layer that prevents the conductive layer 112 from being oxidized by oxygen in the insulating layer 110. It can also function as such. Note that the metal oxide layer 114 is removed before the formation of the conductive layer 112. By removing this layer, the conductive layer 112 and the insulating layer 110 may be in contact.

[0139] The insulating layer 103 is preferably formed of an insulating film containing an oxide. In particular, semiconductor It is preferable to use an oxide film in the portion that is in contact with the body layer 108.

[0140] The semiconductor layer 108 contains a metal oxide (hereinafter also referred to as an oxide semiconductor) that exhibits semiconductor properties. The semiconductor layer 108 is preferably made of a metal oxide having the composition shown in Embodiment 1. It is possible to use the metal oxide in the channel formation region, which provides high reliability and electric field This allows for the creation of transistors with high effective mobility.

[0141] The region of the semiconductor layer 108 that overlaps with the conductive layer 112 functions as a channel formation region. Furthermore, the semiconductor layer 108 has a pair of low-resistance regions 108n flanking the channel formation region. This is preferable. The low-resistance region 108n is a region with a higher carrier concentration than the channel-forming region. It is a region that functions as both a source region and a drain region.

[0142] The low-resistance region 108n is a region with lower resistance and higher carrier concentration than the channel-forming region. This can also be referred to as a region with high oxygen deficiency, a region with high hydrogen concentration, or a region with high impurity concentration. I can say that.

[0143] The insulating layer 110 consists of insulating film 110a, insulating film 110b, and insulating film 1 10c has a stacked structure in this order. The insulating film 110a is a layer of semiconductor layer 108. It has a region in contact with the channel formation region. The insulating film 110c is in contact with the metal oxide layer 114. It has a region. The insulating film 110b is located between the insulating film 110a and the insulating film 110c.

[0144] Insulating film 110a, insulating film 110b, and insulating film 110c are insulating films containing oxides, respectively. It is preferable that it be a film. In this case, insulating film 110a, insulating film 110b and insulating film 110 It is preferable that each of c is deposited continuously using the same deposition apparatus.

[0145] For example, silicon oxide can be used as insulating film 110a, insulating film 110b, and insulating film 110c. Films, silicon oxide film, silicon nitride film, aluminum oxide film, hafnium oxide film yttrium oxide film, zirconium oxide film, gallium oxide film, tantalum oxide film, ma An insulating film containing one or more of the following: magnesium film, lanthanum oxide film, cerium oxide film, and neodymium oxide film. A marginal layer can be used.

[0146] The insulating layer 110 in contact with the semiconductor layer 108 preferably has a laminated structure of oxide insulating films. Furthermore, it is more preferable to have a region containing an excess of oxygen compared to the stoichiometric composition. In other words, the insulating layer 110 has an insulating film that is capable of releasing oxygen. For example, oxygen Forming the insulating layer 110 in an atmosphere, and then applying an oxygen atmosphere to the insulating layer 110 after film formation. Performing heat treatment, plasma treatment, etc., or applying an oxide film to the insulating layer 110 in an oxygen atmosphere Oxygen can also be supplied into the insulating layer 110 by forming a film.

[0147] For example, insulating film 110a, insulating film 110b and insulating film 110c are manufactured by sputtering. Chemical vapor deposition (CVD) method, true Air deposition, pulsed laser deposition (PLD) on) method, Atomic Layer Deposition (ALD) method It can be formed using methods such as plasma chemical vapor deposition (PE). These methods include CVD (Plasma-Enhanced CVD) and thermal CVD.

[0148] In particular, insulating film 110a, insulating film 110b and insulating film 110c are produced by plasma CVD. It is preferable to form it in this way.

[0149] Since the insulating film 110a is deposited on the semiconductor layer 108, it is important to keep it as close to the semiconductor layer 108 as possible. It is preferable that the film is deposited under conditions that do not cause damage. For example, the deposition rate (film deposition The film can be deposited under conditions where the rate (also called the film rate) is sufficiently low.

[0150] For example, as the insulating film 110a, a silicon oxide nitride film is formed by plasma CVD. In this case, forming it under low power conditions minimizes damage to the semiconductor layer 108. It can be made smaller.

[0151] The deposition gas used for forming silicon oxide nitride films includes, for example, silanes and disilanes. Depositing gases containing condensate, and oxidizing gases such as oxygen, ozone, nitrous oxide, and nitrogen dioxide. , can be used as a raw material gas. In addition to the raw material gas, argon and helium, It may contain diluent gases such as nitrogen.

[0152] For example, the ratio of the flow rate of the deposition gas to the total flow rate of the film-forming gas (hereinafter also simply referred to as the flow rate ratio) By reducing (u), the deposition rate can be lowered, resulting in the deposition of a dense film with fewer defects. can.

[0153] The insulating film 110b is a film deposited under conditions with a higher deposition rate than the insulating film 110a. This is preferable. This can improve productivity.

[0154] For example, insulating film 110b is subjected to conditions where the flow rate ratio of the depositing gas is increased compared to insulating film 110a. This allows for film deposition under conditions that increase the deposition rate.

[0155] The insulating film 110c has reduced surface defects and absorbs impurities contained in the atmosphere, such as water. It is preferable that the film is extremely dense and difficult to adhere to. For example, similar to insulating film 110a, The film can be deposited under conditions where the deposition rate is sufficiently low.

[0156] Since insulating film 110c is deposited on insulating film 110b, compared to insulating film 110a, the insulating film is less insulating than insulating film 110c. The effect on the semiconductor layer 108 during the deposition of 110c is small. Therefore, insulating film 110c The film can be deposited under higher power conditions than insulator 110a. The flow rate ratio of the depositing gas is By reducing the power and depositing the film at a relatively high power level, a dense film with reduced surface defects can be created. It is possible.

[0157] In other words, from the film deposition rate of highest to lowest, the films are insulating film 110b, insulating film 110a, and insulating film 110c. A laminated film formed under conditions such that the order is as described above can be used as the insulating layer 110. The insulating layer 110 consists of insulating film 110b, insulating film 110a, and insulating film 110c in that order, wet It offers a higher etching rate under the same conditions as etching or dry etching.

[0158] The insulating film 110b is preferably formed to be thicker than insulating films 110a and 110c. It is possible to form a thick insulating film 110b, which has the fastest film formation rate, thus improving the film formation process of the insulating layer 110. The time required for the process can be reduced.

[0159] Here, the boundary between insulating film 110a and insulating film 110b, and the boundary between insulating film 110b and insulating film 110 Since the boundaries of c may be unclear, these boundaries are indicated with dashed lines in Figure 6A, etc. It is present. Furthermore, since insulating film 110a and insulating film 110b have different film densities, the insulating layer 110 Transmission electron microscope (TEM) in cross-section In microscopy images, these boundaries can be observed as differences in contrast. It can sometimes be inferred. Similarly, the boundary between insulating film 110b and insulating film 110c is also con This can sometimes be observed as a difference in trust.

[0160] It is preferable to use a crystalline metal oxide film for the semiconductor layer 108. For example, CAAC (c-axis aligned crystal) structure, polycrystalline structure, which will be described later. Metal oxide films having a microcrystalline (nc) structure, etc., can be used. By using a gen oxide film in the semiconductor layer 108, the defect level density in the semiconductor layer 108 is reduced. This reduces the amount of material used, enabling the creation of highly reliable semiconductor devices.

[0161] The higher the crystallinity of the semiconductor layer 108, the lower the defect level density in the film. On the other hand, By using a metal oxide film with low crystallinity, transistors can conduct large currents. This can be achieved.

[0162] The crystallinity of semiconductor layer 108 can be determined, for example, by X-ray diffraction (XRD) or transmission electron microscopy (TEM). ), and can be analyzed by electron diffraction (ED), etc. ru.

[0163] When depositing a metal oxide film by sputtering, the substrate temperature (stage temperature) during film deposition is important. The higher the degree, the more crystalline the metal oxide film can be formed. Also, the more... The higher the ratio of the oxygen gas flow rate to the total film-forming gas (also called the oxygen flow rate ratio), the better the film formation. It is possible to form highly crystalline metal oxide films.

[0164] [Configuration Example 1-2] Figure 6B is a schematic cross-sectional view of transistor 10A. Transistor 10A is the above-mentioned transistor The main difference between this semiconductor layer 108 and the transistor 10 is the different configuration of the semiconductor layer 108.

[0165] The semiconductor layer 108 of transistor 10A is, from the insulating layer 103 side, semiconductor layer 108 It has a laminated structure in which a and semiconductor layer 108b are stacked. It is preferable that layer 108b uses the metal oxide film shown in Embodiment 1. In this embodiment, one or more of the semiconductor layer 108a and semiconductor layer 108b are made of gold as shown in Embodiment 1. It is preferable to use an oxide film.

[0166] For simplicity, here we will refer to the low-resistance region of semiconductor layer 108a and semiconductor layer 10 The low-resistance region of 8b is combined with the low-resistance region 108n, and the same hatching pattern is used. It is indicated by adding an "n". In reality, the composition of semiconductor layer 108a and semiconductor layer 108b is different. Therefore, the electrical resistivity in the low-resistance region of 10⁸n, carrier concentration, oxygen deficiency, hydrogen concentration, and The concentration of impurities may differ.

[0167] The semiconductor layer 108b is located on the upper surface of the semiconductor layer 108a and on the lower surface of the insulating film 110a, respectively. Contact. The semiconductor layer 108b can be used in the semiconductor layer 108 shown in Embodiment 1. A metal oxide film can be applied.

[0168] On the other hand, semiconductor layer 108a has a higher atomic ratio of element M than semiconductor layer 108b, and is a metal oxide A film can be used.

[0169] Because element M has a stronger bonding force with oxygen compared to indium, gold, which has a high atomic ratio of element M, By using an oxide film in the semiconductor layer 108a, oxygen vacancies are less likely to form. If there are many oxygen vacancies in layer 108a, it can lead to a decrease in the electrical characteristics and reliability of the transistor. Therefore, the atomic ratio of element M is greater in semiconductor layer 108a than in semiconductor layer 108b. By using a metal oxide film with high performance, transistors with good electrical characteristics and high reliability are produced. It can achieve 10A.

[0170] As semiconductor layer 108a, there is a region where the atomic ratio of zinc is equal to that of semiconductor layer 108b, or sub A metal oxide film is used that has a region where the atomic ratio of lead is lower than that of semiconductor layer 10⁸b. Preferably, by applying a metal oxide film that is less prone to oxygen vacancies to the semiconductor layer 108a, This can reduce degradation in NBTIS testing.

[0171] The transistor 10A shown in Figure 6B is located on the semiconductor layer 108a on the insulating layer 103 side. By using a metal oxide film with a relatively high content of element M, the oxygen in the semiconductor layer 108 can be reduced. Defects are reduced. Furthermore, the semiconductor layer 108b located on the insulating layer 110 side contains element M. By using a metal oxide film with a low percentage or one that does not contain element M, the semiconductor layer 108 is insulated. The interface defect density with layer 110 is reduced, resulting in both extremely high electrical properties and extremely high reliability. It can be made into a transistor.

[0172] In this case, it is preferable to form the semiconductor layer 108b thinner than the semiconductor layer 108a. Even if the semiconductor layer 108b is an extremely thin film, for example, between 0.5 nm and 10 nm, The density of interface defects with the marginal layer 110 can be reduced. On the other hand, semiconductors that are less prone to oxygen deficiency By making the body layer 108a relatively thicker, a more reliable transistor can be achieved. It is possible.

[0173] For example, the thickness of semiconductor layer 108a is 1.5 times or more than the thickness of semiconductor layer 108b. Preferably 0 times or less, more preferably 2 times or more and 15 times or less, and more preferably 3 times or more and 10 times The following is preferable. Furthermore, the thickness of the semiconductor layer 108b is preferably 0.5 nm or more and 30 nm or less. Furthermore, a range of 1 nm to 20 nm is preferred, and even more preferably 2 nm to 10 nm. preferable.

[0174] The semiconductor layer 108a and semiconductor layer 108b have the above-described crystalline metal oxide film It is preferable to use highly crystalline gold in both semiconductor layer 108a and semiconductor layer 108b. A metal oxide film may be used, or a metal oxide film with low crystallinity may be used. Alternatively, a semiconductor film may be used. The body layer 108a and the semiconductor layer 108b may have different crystallinity. For example, semiconductor The body layer 108a may be a film with higher crystallinity than the semiconductor layer 108b, or the semiconductor layer 108 b may be a film with higher crystallinity than semiconductor layer 108a. The crystallinity of the metal oxide film used in 108b depends on the required electrical characteristics and reliability of the transistor. It can be determined based on properties and specifications of the film deposition equipment, etc.

[0175] [Configuration Examples 1-3] Figure 7A is a schematic cross-sectional view of transistor 10B. Transistor 10B is the above-mentioned transistor Compared to the inverter 10, the configuration of the insulating layer 103 is different, and it has a conductive layer 106. And that's the main difference.

[0176] The conductive layer 106 is connected to the semiconductor layer 108, insulating layer 110, and metal oxide layer via the insulating layer 103. 114 has a region that overlaps with the conductive layer 112. The conductive layer 106 is the first gate electrode It functions as a (also called a back gate electrode). The insulating layer 103 is the first gate insulating layer. It functions as a layer. In this case, the conductive layer 112 is the second gate electrode, and the insulating layer 110 is the second It functions as a gate insulating layer.

[0177] For example, transistor 10B applies the same potential to conductive layer 112 and conductive layer 106. This allows for a larger current to flow when the device is in the ON state. The transistor 10B controls the threshold voltage on one of the conductive layers 112 and 106. One potential is applied to control the on and off states of transistor 10B. You can also give.

[0178] The insulating layer 103 consists of insulating film 103a, insulating film 103b, and insulating film 10 It has a laminated structure in which 3c and insulating film 103d are stacked. The insulating film 103a is a conductive layer 10 It is in contact with 6. Also, the insulating film 103d is in contact with the semiconductor layer 108.

[0179] The insulating layer 103, which functions as a second gate insulating layer, has high breakdown voltage and low film stress. It is not easy to release hydrogen or water, has few defects in the film, and is contained in the conductive layer 106. It is preferable to satisfy one or more of the following: suppressing the diffusion of metal elements, and all of these It is most preferable to satisfy the condition.

[0180] Of the four insulating films of the insulating layer 103, the insulating film 103a located on the conductive layer 106 side. It is preferable to use insulating films containing nitrogen for insulating film 103b and insulating film 103c. On the other hand, an insulating film containing oxygen can be used for the insulating film 103d that is in contact with the semiconductor layer 108. Preferred. In addition, the four insulating films of the insulating layer 103 each serve the plasma CVD apparatus. It is preferable to use this method to continuously form a film without exposure to the atmosphere.

[0181] For example, silicon nitride films can be used as insulating film 103a, insulating film 103b, and insulating film 103c. Nitrogen-containing insulating films such as silicon nitride film, aluminum nitride film, and hafnium nitride film. It can be used as the insulating film 103c, which can be used in the insulating layer 110. An insulating film can be used as a substitute.

[0182] The insulating film 103a and insulating film 103c can prevent the diffusion of impurities from below. Preferably, the insulating film is dense. The insulating film 103a contains the metal elements contained in the conductive layer 106. The insulating film 103c can block the hydrogen and water contained in the insulating film 103b, respectively. It is preferable that it be a film. Therefore, insulating film 103a and insulating film 103c are made of insulating film 1 An insulating film deposited under conditions with a lower deposition rate than 03b can be applied.

[0183] On the other hand, insulating film 103b is an insulating film deposited under conditions of low stress and high deposition rate. It is preferable that the insulating film 103b is more insulating than insulating film 103a and insulating film 103c. It is preferable that it is formed to be thick.

[0184] For example, plasma Even when using a silicon nitride film deposited by CVD, the insulating film 103b is different from the other two The film density is lower than that of the insulating film. Therefore, the permeability in the cross-section of the insulating layer 103 is lower. In hypermorphic electron microscope images, this can sometimes be observed as a difference in contrast. Yes. Note that the boundary between insulating film 103a and insulating film 103b, and the boundary between insulating film 103b and insulating film 10 Because the boundary of 3c may be unclear, these boundaries are indicated with dashed lines in Figure 7A, etc. It is.

[0185] As an insulating film 103d in contact with the semiconductor layer 108, impurities such as water are adsorbed on its surface. It is preferable to have a dense insulating film. Furthermore, it should have as few defects as possible, and should contain water and hydrogen. It is preferable to use an insulating film with reduced impurities. For example, as insulating film 103d An insulating film similar to the insulating film 110c of the insulating layer 110 can be used.

[0186] Furthermore, the conductive layer 106 may be a metal film or alloy in which the constituent elements do not easily diffuse into the insulating layer 103. When using a film, for example, insulating film 103a is omitted, and insulating film 103b and insulating film 103c The three insulating films, including the insulating film 103d, may be stacked in a configuration.

[0187] The insulating layer 103 having such a layered structure provides an extremely reliable transistor. It can be achieved.

[0188] [Configuration Examples 1-4] Figure 7B is a schematic cross-sectional view of transistor 10C. Transistor 10C has the above configuration The transistor 10A exemplified in Example 1-2 is connected to the transistor 1 exemplified in Configuration Example 1-3 above. This is an example of applying the conductive layer 106 and insulating layer 103 as exemplified in 0B.

[0189] This configuration provides a transistor with excellent electrical characteristics and extremely high reliability. It is possible to achieve this.

[0190] <Configuration Example 2> The following section will describe more specific examples of transistor configurations.

[0191] [Configuration Example 2-1] Figure 8A is a top view of transistor 100, and Figure 8B shows the dashed line A1 shown in Figure 8A. -This corresponds to a cross-sectional view of the cross-section in A2, and Figure 8C corresponds to the dashed line B1-B2 shown in Figure 8A. This corresponds to a cross-sectional view of the cut surface. Note that in Figure 8A, the configuration of transistor 100 Some of the elements (such as the gate insulating layer) are omitted in the diagram. Also, the dashed line A1-A2 direction The channel length direction corresponds to the channel width direction, and the dashed line B1-B2 direction corresponds to the channel width direction. Also, transition Regarding the top view of the sta, some of the components will be omitted in subsequent drawings, similar to Figure 8A. This shall be illustrated in the diagram.

[0192] The transistor 100 is provided on the substrate 102 and has an insulating layer 103, a semiconductor layer 108, and an insulating layer 103. It has an edge layer 110, a metal oxide layer 114, a conductive layer 112, an insulating layer 118, etc. Island-shaped semiconductor The body layer 108 is provided on the insulating layer 103. The insulating layer 110 is on the upper surface, half of the insulating layer 103. The metal oxide layer 114 and conductive layer 112 are provided in contact with the upper and side surfaces of the conductive layer 108. These are arranged in this order on the insulating layer 110 and have a portion that overlaps with the semiconductor layer 108. The insulating layer 118 is located on the upper surface of the insulating layer 110, the side surface of the metal oxide layer 114, and the conductive layer 11 It is provided covering the upper surface of 2.

[0193] The insulating layer 103 consists of insulating film 103a, insulating film 103b, and insulating film 103c from the substrate 102 side. It has a laminated structure in which a semiconductor and an insulating film 103d are stacked. Furthermore, the insulating layer 110 is a semiconductor Insulating film 110a, insulating film 110b, and insulating film 110c are stacked from the layer 108 side. It has a layered structure.

[0194] As shown in Figures 8A and 8B, the transistor 100 has a conductive layer 12 on an insulating layer 118. It may have conductive layer 0a and conductive layer 120b. Conductive layer 120a and conductive layer 120b are It functions as a drain electrode or a drain electrode. Conductive layers 120a and 120b are The openings 141a or 141 provided in the insulating layer 118 and the insulating layer 110 respectively It is electrically connected to the low-resistance region 108n via b.

[0195] A portion of the conductive layer 112 functions as a gate electrode. A portion of the insulating layer 110 functions as a gate insulating layer. It functions as a marginal layer. Transistor 100 has a gate electrode provided on the semiconductor layer 108. It is a so-called top-gate type transistor.

[0196] The conductive layer 112 and the metal oxide layer 114 are processed so that their upper surface shapes are roughly identical to each other. It is being done.

[0197] In this specification, "approximately matching top surface shape" means that there is a small difference between the stacked layers. This refers to the overlapping of parts of the outlines. For example, the upper layer and the lower layer may have the same mask pattern. , or including cases where part of it is processed with the same mask pattern. However, strictly speaking, ring The walls do not overlap, and the upper layer is located inside the lower layer, or the upper layer is located outside the lower layer. In this case as well, it is said that "the top surface shape is roughly the same."

[0198] The metal oxide layer 114 located between the insulating layer 110 and the conductive layer 112 is in the insulating layer 110. It functions as a barrier film that prevents the contained oxygen from diffusing to the conductive layer 112. The oxide layer 114 allows hydrogen and water contained in the conductive layer 112 to diffuse towards the insulating layer 110. It also functions as a barrier film to prevent this. The metal oxide layer 114 is, for example, at least the insulating layer 11 It is preferable to use a material that is less permeable to oxygen and hydrogen than 0.

[0199] The metal oxide layer 114 makes it easier for the conductive layer 112 to attract oxygen such as aluminum and copper. Even when using a metallic material, oxygen will diffuse from the insulating layer 110 to the conductive layer 112. This can prevent the conductive layer 112 from containing hydrogen. This prevents hydrogen from diffusing from the insulating layer 110 to the semiconductor layer 108. As a result, the carrier density in the channel formation region of the semiconductor layer 108 is made extremely low. It is possible.

[0200] As the metal oxide layer 114, an insulating material or a conductive material can be used. If the oxide layer 114 has insulating properties, it functions as part of the gate insulating layer. On the other hand, If the metal oxide layer 114 is conductive, it functions as part of the gate electrode.

[0201] As the metal oxide layer 114, an insulating material with a higher dielectric constant than silicon oxide is used. This is preferred. In particular, an aluminum oxide film, a hafnium oxide film, or a hafnium aluminum film is preferred. Using a film or similar material is preferable because it allows for a reduction in the driving voltage.

[0202] For example, the metal oxide layer 114 may be indium oxide or indium tin oxide (ITO). or conductive oxides such as silicon-containing indium tin oxide (ITSO) It can also be used. Conductive oxides containing indium are particularly preferred due to their high conductivity. .

[0203] As the metal oxide layer 114, an oxide material containing one or more of the same elements as the semiconductor layer 108 is used. It is preferable to use an oxide semiconductor material applicable to the semiconductor layer 108. Preferably, the metal oxide layer 114 is made using the same sputtering process as the semiconductor layer 108. By applying a metal oxide film formed using a ring target, the equipment can be standardized. Therefore, it is preferable.

[0204] The metal oxide layer 114 is preferably formed using a sputtering apparatus. For example, When forming an oxide film using a puttering device, the film is formed in an atmosphere containing oxygen gas. This allows for the appropriate addition of oxygen to the insulating layer 110 and the semiconductor layer 108.

[0205] The semiconductor layer 108 consists of a region superimposed on the conductive layer 112 and a pair of low-resistance regions flanking that region. It has 108n. The region of the semiconductor layer 108 that overlaps with the conductive layer 112 is transistor 1 It functions as a channel formation region for 00. On the other hand, the low-resistance region 108n is for transistor 1 It functions as a source or drain area for 00.

[0206] The low-resistance region 108n is a region with lower resistance than the channel-forming region and a higher carrier concentration. This region is also called the region with high oxygen defect density, the region with high impurity concentration, or the n-type region. It is possible.

[0207] The low-resistance region 108n of the semiconductor layer 108 is a region containing impurity elements. Examples of elements include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, and aluminum. Examples include noble gases. Representative examples of noble gases include helium, neon, and a Examples include argone, krypton, and xenon. It is particularly preferred that they contain boron or phosphorus. It may also contain two or more of these elements.

[0208] As will be described later, the process of adding impurities to the low-resistance region 108n masses the conductive layer 112. This can be done via the insulating layer 110.

[0209] In the low resistance region 10⁸n, the impurity concentration is 1 × 10⁻⁶. 19 atoms / cm 3 The above 1 x 10 23 atoms / cm 3 The following is preferably 5 × 10 19 atoms / cm 3 The above 5 x 10 22 atoms / cm 3 More preferably 1 × 10 20 atoms / cm 3 The above 1× 10 22 atoms / cm 3 Preferably, the region includes the following:

[0210] The concentration of impurities in the low-resistance region 10⁸n can be determined, for example, by secondary ion mass spectrometry (SIM). It can be analyzed by analytical methods such as S) and X-ray photoelectron spectroscopy (XPS). When using analysis, combine ion sputtering from the front or back side with XPS analysis. By combining these, it is possible to determine the concentration distribution in the depth direction.

[0211] In the low-resistance region 10⁸n, it is preferable that impurity elements exist in an oxidized state. For example, boron, phosphorus, magnesium, aluminum, or silicon as impurity elements. It is preferable to use easily oxidizable elements such as condensate. Because it can exist stably in an oxidized state by bonding with oxygen in the semiconductor layer 108, it can be used in subsequent processes. When exposed to high temperatures (for example, 400°C or higher, 600°C or higher, or 800°C or higher) However, the desorption is suppressed. Also, impurity elements remove oxygen from semiconductor layer 108. As a result, many oxygen vacancies are generated in the low-resistance region 10⁸n. These oxygen vacancies and the membrane Because it becomes a carrier source by bonding with hydrogen, the low-resistance region 10⁸n has extremely low resistance. This is the state it will be in.

[0212] For example, when boron is used as an impurity element, the boron contained in the low resistance region 10⁸n It can exist in a state bound to oxygen. This means that in XPS analysis, the B2O3 bond... This can be confirmed by observing the resulting spectral peak. Furthermore, in XPS analysis, The spectral peaks caused by the element boron existing in its elemental form are not observed, or are not measured. The peak intensity is so low that it is buried in the background noise observed near the lower limit. It becomes smaller.

[0213] The insulating layer 110 is in contact with the channel formation region of the semiconductor layer 108, i.e., the conductive layer 1 It has a region that overlaps with 12. In addition, the insulating layer 110 has a low-resistance region 10 of the semiconductor layer 108. It has a region that is in contact with 8n and does not overlap with the conductive layer 112.

[0214] The region of the insulating layer 110 that overlaps with the low-resistance region 108n contains the aforementioned impurity elements. In this case, the impurity elements in the insulating layer 110 may be similar to those in the low-resistance region 108n. It is preferable that it exists in a state of being bonded with oxygen. Such easily oxidized elements are insulating. Because it can exist stably in an oxidized state by bonding with oxygen in layer 110, it can be subjected to high temperatures in subsequent processes. Even if heat is applied, detachment is suppressed. In particular, detachment in the insulating layer 110 due to heating If the mixture contains oxygen that can be released (also called excess oxygen), the excess oxygen and the impurity elements will In order to bond and stabilize, oxygen is supplied from the insulating layer 110 to the low-resistance region 108n. This can suppress the oxidized state of impurity elements in the insulating layer 110. Because the part is in a state where oxygen does not easily diffuse, the insulating layer 110 is above the insulating layer 11 The supply of oxygen to the low-resistance region 108n via 0 is suppressed, and the low-resistance region 108n This also prevents the resistance from increasing.

[0215] The insulating layer 118 functions as a protective layer to protect the transistor 100. Insulating layer 110 For example, inorganic insulating materials such as oxides or nitrides can be used. More specifically Typical examples include silicon oxide, silicon oxide nitride, silicon nitride, silicon oxide nitride, and acid Aluminum oxide, aluminum nitride, aluminum nitride, hafnium oxide, hafnium Inorganic insulating materials such as aluminum oxide can be used.

[0216] [Configuration Example 2-2] Figure 9A is a top view of transistor 100A, and Figure 9B is a top view of transistor 100A. Figure 9C is a cross-sectional view in the channel length direction, and Figure 9C is a cross-sectional view of transistor 100A in the channel width direction. That is the case.

[0217] The transistor 100A has a conductive layer 106 between the substrate 102 and the insulating layer 103. Therefore, it differs mainly from configuration example 2-1. The conductive layer 106 is semiconductor layer 108 and conductive layer 112 It has an overlapping area.

[0218] In transistor 100A, the conductive layer 112 is the second gate electrode (top gate electrode The conductive layer 106 functions as a first gate electrode (also called a bottom gate electrode), and the conductive layer 106 has the function of a first gate electrode (bottom gate electrode). It functions as a pole (also called a pole). In addition, a part of the insulating layer 110 is a second gate insulating layer It functions as such, and a portion of the insulating layer 103 functions as the first gate insulating layer.

[0219] The portion of the semiconductor layer 108 that overlaps with at least one of the conductive layer 112 and the conductive layer 106 is It functions as a channel formation region. For the sake of simplicity, semiconductor layer 108 will be referred to below. The portion that overlaps with the conductive layer 112 is sometimes called the channel formation region, but in reality the conductive layer 1 In addition to the portion that does not overlap with 12, there is also a portion that overlaps with the conductive layer 106 (the portion that includes the low-resistance region 108n). A channel can be formed.

[0220] As shown in Figure 9C, the conductive layer 106 consists of a metal oxide layer 114, an insulating layer 110, and an insulating layer. Even though it is electrically connected to the conductive layer 112 through the opening 142 provided in layer 103 Good. This allows the conductive layer 106 and the conductive layer 112 to be given the same potential.

[0221] The conductive layer 106 is made of the same material as conductive layer 112, conductive layer 120a, or conductive layer 120b. This can be used. In particular, if a material containing copper is used for the conductive layer 106, the wiring resistance can be reduced. It is preferable for this reason.

[0222] As shown in Figures 9A and 9C, in the channel width direction, conductive layer 112 and conductive layer 1 It is preferable that 06 protrudes outward beyond the edge of the semiconductor layer 108. In this case, Figure As shown in 9C, the entire channel width direction of the semiconductor layer 108 is connected to the insulating layer 110 and the insulating layer 1 The structure is covered by conductive layer 112 and conductive layer 106 via 03.

[0223] With this configuration, the semiconductor layer 108 is protected from the electric field generated by the pair of gate electrodes. And it can be electrically surrounded. In particular, the conductive layer 106 and the conductive layer 112 are the same It is preferable to apply an electric potential. This induces a channel in the semiconductor layer 108. Because the electric field can be effectively applied, the on-current of the 100A transistor can be increased. Yes, it is possible. Therefore, it becomes possible to miniaturize the 100A transistor.

[0224] Furthermore, the conductive layer 112 and the conductive layer 106 may not be connected. In this case, one pair A constant potential is applied to one of the gate electrodes, and a signal to drive transistor 100A is applied to the other. This may be applied. In this case, the potential applied to one gate electrode will affect transistor 100. The threshold voltage when driving A with the other gate electrode can also be controlled.

[0225] [Configuration Example 2-3] Figure 10A is a top view of transistor 100B, and Figure 10B is a top view of transistor 100B Figure 10C is a cross-sectional view in the channel length direction, and Figure 10C is a cross-sectional view of transistor 100B in the channel width direction. This is a cross-section.

[0226] Compared to transistor 100 illustrated in Configuration Example 2-1, transistor 100B has an extremely low capacitance. The main differences lie in the different configuration of the margin layer 110 and the presence of an insulating layer 116.

[0227] The insulating layer 110 is designed so that its upper surface shape is substantially the same as that of the conductive layer 112 and the metal oxide layer 114. The insulating layer 110 is processed by, for example, processing the conductive layer 112 and the metal oxide layer 114. It can be formed by processing using a resist mask.

[0228] The insulating layer 116 consists of the conductive layer 112, the metal oxide layer 114, and the insulating layer 1 of the semiconductor layer 108. It is provided in contact with the top and side surfaces that are not covered by 10. The insulating layer 116 is an insulating layer The upper surface of layer 103, the side surface of insulating layer 110, the side surface of metal oxide layer 114, and conductive layer 112 It is provided to cover the top and sides.

[0229] The insulating layer 116 has the function of reducing the resistance of the low-resistance region 108n. As layer 116, by heating during or after the deposition of the insulating layer 116, a low-resistance region is formed. An insulating film that can supply impurities into region 10⁸n can be used. Alternatively, an insulating film can be used. By heating the edge layer 116 during or after film formation, oxygen is introduced into the low-resistance region 108n. An insulating film capable of causing defects can be used.

[0230] For example, as an insulating layer 116, a source for supplying impurities to the low-resistance region 108n is used. An insulating film capable of this can be used. In this case, the insulating layer 116 releases hydrogen upon heating. It is preferable that the film is such that an insulating layer 116 is formed in contact with the semiconductor layer 108. By doing so, impurities such as hydrogen are supplied to the low-resistance region 108n, and the low-resistance region 108n is reduced to low resistance It can be made resistant.

[0231] The insulating layer 116 uses a gas containing impurity elements such as hydrogen as the film-forming gas during film formation. It is preferable that the film is formed by lowering the substrate temperature of the insulating layer 116. This allows for the effective supply of many impurity elements to the semiconductor layer 108. The substrate temperature is preferably, for example, 200°C to 500°C, and more preferably 220°C to 450°C. Preferably below ℃, more preferably between 230℃ and 430℃, and even more preferably below 250℃. A temperature of 400°C or lower is preferable.

[0232] By forming the insulating layer 116 under reduced pressure and heating, the resistance in the semiconductor layer 108 is reduced. This can promote the desorption of oxygen from the region that becomes region 10⁸n. A large amount of oxygen deficiency is formed. By supplying impurities such as hydrogen to the semiconductor layer 108, the low-resistance region 108n The carrier density increases, making it possible to more effectively reduce the resistance of the low-resistance region 108n. .

[0233] For example, silicon nitride, silicon oxide nitride, silicon oxide nitride, Preferably, insulating films containing nitrides, such as aluminum nitride and aluminum nitride oxide, are used. This is possible. In particular, silicon nitride has blocking properties for hydrogen and oxygen, so external This prevents both the diffusion of hydrogen from the semiconductor layer and the desorption of oxygen from the semiconductor layer to the outside. This makes it possible to create highly reliable transistors.

[0234] The insulating layer 116 has the function of attracting oxygen from the semiconductor layer 108 and creating an oxygen deficiency. An insulating film may be used. In particular, the insulating layer 116 may be made of metal nitride such as aluminum nitride. Using objects is particularly preferable.

[0235] When using metal nitrides, aluminum, titanium, tantalum, tungsten, chromium, Alternatively, it is preferable to use ruthenium nitride. In particular, aluminum or titanium It is particularly preferable to include it. For example, when aluminum is used as the sputtering target, Aluminum nitride formed by reaction sputtering using a gas containing nitrogen as the film gas. By appropriately controlling the flow rate of nitrogen gas relative to the total flow rate of the film-forming gas, the um film can achieve extremely high performance. To create a film that combines excellent insulating properties with extremely high blocking properties against hydrogen and oxygen. This is possible. Therefore, an insulating film containing such a metal nitride is provided in contact with the semiconductor layer. This not only makes it possible to reduce the resistance of the semiconductor layer, but also allows oxygen to be removed from the semiconductor layer, and semi This effectively prevents hydrogen from diffusing into the conductive layer.

[0236] When aluminum nitride is used as the metal nitride, the insulating material containing the aluminum nitride It is preferable that the layer thickness be 5 nm or more. Even with such a thin film, hydrogen and acid This material can achieve both high blocking properties for the element and low resistance of the semiconductor layer. The thickness of the insulating layer can be any thickness, but considering productivity, it is preferably 500 nm or less. It is preferable that the wavelength be 200 nm or less, and more preferably 50 nm or less.

[0237] When an aluminum nitride film is used for the insulating layer 116, the composition formula is AlN x (x is greater than 0) A film is used that satisfies the condition x is a real number less than or equal to 2, preferably a real number greater than 0.5 and less than or equal to 1.5. It is preferable to have this. This makes it possible to create a film with excellent insulating properties and excellent thermal conductivity. Therefore, it is possible to improve the heat dissipation of the heat generated when driving the transistor 100B. Cut.

[0238] Alternatively, an aluminum titanium nitride film, a titanium nitride film, or the like can be used as the insulating layer 116. It is possible.

[0239] By providing such an insulating layer 116 in contact with the low-resistance region 108n, the insulating layer 116 By drawing oxygen from the low-resistance region 10⁸n, an oxygen deficiency is formed in the low-resistance region 10⁸n. This can be achieved. Furthermore, by performing a heat treatment after forming such an insulating layer 116, low resistance The anti-region 108n can form more oxygen deficiencies, promoting resistance reduction. Yes, it is possible. Also, if a film containing a metal oxide is used for the insulating layer 116, the insulating layer 116 becomes a semiconductor. As a result of aspirating oxygen in layer 108, the insulating layer between the insulating layer 116 and the low-resistance region 108n When a layer containing an oxide of a metal element (e.g., aluminum) included in 116 is formed be.

[0240] Here, when a metal oxide film containing indium is used as the semiconductor layer 108, low resistance A region where indium oxide is deposited near the interface on the insulating layer 116 side of region 108n, or In some cases, regions with high indium concentration may be formed. This results in extremely low resistance. A resistive region 108n can be formed. The presence of such a region is useful, for example, in X-ray photoelectric fields. It can sometimes be observed using analytical methods such as xenopsis spectroscopy (XPS).

[0241] [Configuration Example 2-4] Figure 11A is a top view of transistor 100C, and Figure 11B is a top view of transistor 100C. Figure 11C is a cross-sectional view in the channel length direction, and Figure 11C is a cross-sectional view of transistor 100C in the channel width direction. This is a cross-section.

[0242] Transistor 100C is the same as transistor 100B as exemplified in Configuration Example 2-3, This is an example of a case where a conductive layer 106, which functions as a second gate electrode, is provided, as illustrated in -2. .

[0243] This configuration allows for the creation of transistors with high on-current. This can be a transistor capable of controlling the threshold voltage.

[0244] <Modification 1 of Configuration Example 2> In the above configuration examples 2-1 to 2-4, the semiconductor layer 108 was shown as a single layer, It is preferable that layer 108 has a stacked structure in which semiconductor layer 108a and semiconductor layer 108b are stacked. It seems so.

[0245] The transistor 100_a shown in Figure 12A is the same as the transistor 10 exemplified in Configuration Example 2-1. This is an example where the semiconductor layer 108 is in a stacked structure. In Figure 12A, the dashed line is The left side clearly shows a cross-section along the channel length, while the right side clearly shows a cross-section along the channel width.

[0246] Similarly, transistor 100A_a shown in Figure 12B and transistor 10 shown in Figure 12C 0B_a and transistor 100C_a shown in Figure 12D are transistors 10 The semiconductor layer 108 of transistor 0A, transistor 100B, or transistor 100C is stacked. This is an example of what is meant by "construction".

[0247] <Modification 2 of Configuration Example 2> As described above, the metal oxide layer 114 located between the insulating layer 110 and the conductive layer 112 is The insulating layer 110 can also be removed after oxygen has been supplied to it.

[0248] The transistor 100_b shown in Figure 13A is the same as the transistor 100_ exemplified in Figure 12A. This is an example of the case where the metal oxide layer 114 in (a) is removed.

[0249] Similarly, transistor 100A_b shown in Figure 13B and transistor 10 shown in Figure 13C 0B_b and transistor 100C_b shown in Figure 13D are transistors 10 In transistor 0A_a, transistor 100B_a, or transistor 100C_a, the metal This is an example of the case where the oxide layer 114 is removed.

[0250] <Example of manufacturing method 1> The following describes an example of a method for manufacturing a transistor according to one aspect of the present invention. This will be explained using transistor 100A, which was illustrated in Configuration Example 2-2, as an example.

[0251] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices are produced by sputtering. Chemical vapor deposition (CVD) method Vacuum deposition, pulsed laser deposition (PLD) tion) method, Atomic Layer Deposition (ALD) method It can be formed using methods such as the CVD method. These include the VD (Plasma Enhanced CVD) method and the thermal CVD method. One of the thermal CVD methods is metal-organic chemical vapor deposition (MOCVD). There is also the CVD method.

[0252] Thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices are coated using spin coating, DIT coating, etc. Printing methods: spray coating, inkjet, dispensing, screen printing, offset printing. Doctor's knife coat, slit coat, roll coat, curtain coat, knife coat, etc. It can be formed by law.

[0253] When processing thin films that make up semiconductor devices, methods such as photolithography are used. It is possible to do this using other methods such as nanoimprint lithography, sandblasting, and lift-off lithography. The thin film may be processed by any method. Alternatively, a film deposition method using a shielding mask such as a metal mask may be used. This may be used to directly form island-like thin films.

[0254] There are two main methods of photolithography. One is to process the image A resist mask is formed on a thin film, and the thin film is processed by etching or the like, and the resist This is a method for removing the mask. Another method involves forming a photosensitive thin film and then exposing it to light. This method involves developing the film and then processing it into a desired shape.

[0255] In photolithography, the light used for exposure is, for example, the i-line (wavelength 365 nm). Using g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture thereof This can be done by using ultraviolet light, KrF laser light, or ArF laser light, etc. It is also possible to perform exposure using immersion lithography. Furthermore, the light used for exposure and Then, using extreme ultraviolet (EUV) light and X-rays... It is also possible to use an electron beam instead of light for exposure. Extreme ultraviolet Using light, X-rays, or electron beams is preferable because it allows for extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, the photomask is It is unnecessary.

[0256] Thin film etching methods include dry etching, wet etching, and sandblasting. Laws and other regulations can be used.

[0257] Figures 14 to 16 show the steps in the manufacturing process of transistor 100A. The cross-sections in the channel length direction and channel width direction are shown side by side.

[0258] [Formation of conductive layer 106] A conductive film is formed on the substrate 102, and this is processed by etching to form a gate electrode. A functional conductive layer 106 is formed (Figure 14A).

[0259] At this time, as shown in Figure 14A, the edges of the conductive layer 106 are processed to have a tapered shape. It is preferable to do so. This improves the stepped coverage of the insulating layer 103 to be formed next. It is possible.

[0260] By using a conductive film containing copper as the conductive film that forms the conductive layer 106, the wiring resistance can be reduced. It is possible to do so, for example, when applying it to large display devices or high-resolution display devices. In such cases, it is preferable to use a conductive film containing copper. Even when an electrolytic film is used, the insulating layer 103 causes copper to diffuse towards the semiconductor layer 108. Because this is suppressed, highly reliable transistors can be realized.

[0261] [Formation of insulating layer 103] Next, an insulating layer 103 is formed by covering the substrate 102 and the conductive layer 106 (Figure 14B). The insulating layer 103 is formed using methods such as PECVD, ALD, and sputtering. It is possible.

[0262] Here, the insulating layer 103 consists of insulating film 103a, insulating film 103b, insulating film 103c, The insulating film 103d is then laminated to form the structure.

[0263] In particular, each insulating film constituting the insulating layer 103 is preferably formed by the PECVD method. The method for forming the insulating layer 103 can be described by referring to the above example configuration 1.

[0264] After forming the insulating layer 103, a process of supplying oxygen to the insulating layer 103 may be performed. For example, plasma treatment or heat treatment in an oxygen atmosphere can be performed. This involves supplying oxygen to the insulating layer 103 using plasma ion doping or ion implantation. That's good too.

[0265] [Formation of semiconductor layer 108] Next, a metal oxide film 108f is formed on the insulating layer 103 (Figure 14C).

[0266] The metal oxide film 108f is formed by a sputtering method using a metal oxide target. It is preferable to do so.

[0267] The metal oxide film 108f is preferably a dense film with as few defects as possible. Furthermore, the metal oxide film 108f has impurities such as hydrogen and water reduced as much as possible, resulting in a high-purity film. It is preferable that the metal oxide film 108f is a crystalline metal oxide. It is preferable to use a membrane.

[0268] When forming a metal oxide film, oxygen gas and an inert gas (e.g., helium gas, aluminum oxide) are used. (Gon gas, xenon gas, etc.) may be mixed in. The higher the oxygen flow rate ratio, the more metal oxides This can improve the crystallinity of the film and enable the realization of highly reliable transistors. On the other hand, oxygen flow The lower the ratio, the lower the crystallinity of the metal oxide film, resulting in a transistor with a higher on-current. It can be done this way.

[0269] When depositing a metal oxide film, the higher the substrate temperature, the higher the crystallinity and density of the metal oxide film. This can be done. On the other hand, the lower the substrate temperature, the lower the crystallinity and the higher the electrical conductivity of the metal. It can form an oxide film.

[0270] The conditions for depositing the metal oxide film are: substrate temperature above room temperature and below 250°C, preferably above room temperature and above 2°C. The substrate temperature should be 0°C or lower, more preferably between room temperature and 140°C. Setting the temperature above room temperature but below 140°C is preferable as it increases productivity. Also, the substrate temperature By forming a metal oxide film at room temperature or without intentional heating, crystallinity is achieved. It can be lowered.

[0271] Before forming the metal oxide film 108f, water, hydrogen, and organic matter adsorbed on the surface of the insulating layer 103 are removed. Either a treatment to remove material components, or a treatment to supply oxygen into the insulating layer 103. It is preferable to perform one or more of the following: For example, in a reduced-pressure atmosphere at a temperature of 70°C to 200°C. Heat treatment can be performed. Alternatively, plasma treatment can be performed in an oxygen-containing atmosphere. Alternatively, plastic in an atmosphere containing an oxidizing gas such as nitrous oxide (N2O) may be used. Oxygen may be supplied to the insulating layer 103 by Zuma treatment. Plasma containing nitrous oxide gas The treatment involves suitably removing organic matter from the surface of the insulating layer 103 while supplying oxygen. This can be done. After this process, the surface of the insulating layer 103 can be continuously treated without being exposed to the atmosphere. It is preferable to form a metal oxide film 108f.

[0272] Furthermore, if the semiconductor layer 108 is a stacked structure in which multiple semiconductor layers are stacked, After forming the metal oxide film, the surface is continuously exposed to the atmosphere and then the next It is preferable to form a metal oxide film.

[0273] Next, by etching a portion of the metal oxide film 108f, an island-shaped semiconductor layer 1 Forms O8 (Figure 14D).

[0274] The metal oxide film 108f can be processed using either a wet etching method or a dry etching method. Either one or both may be used. When processing the metal oxide film 108f, the semiconductor layer In some cases, a portion of the insulating layer 103 that does not overlap with 108 may be etched and become thinner. Of the insulating layer 103, the insulating film 103d is lost by etching, and the surface of the insulating film 103c In some cases, the surface may be exposed.

[0275] Here, after the metal oxide film 108f is formed, or after the semiconductor layer 108 is processed, heating It is preferable to perform the treatment. By heat treatment, the metal oxide film 108f or semiconductor layer 10 It can remove hydrogen or water contained in or adsorbed on the surface of 8. Heat treatment improves the film quality of the metal oxide film 108f or semiconductor layer 108 (for example, defects (This may result in a reduction of defects, an improvement in crystallinity, etc.)

[0276] Heat treatment causes the metal oxide film 108f or the semiconductor layer 108 to be converted from the insulating layer 103 by acid It is also possible to supply the raw material. In this case, heat treatment is performed before processing into semiconductor layer 108. That is preferable.

[0277] The heat treatment temperature is typically 150°C or higher but below the strain point of the substrate, or 200°C or higher but below 5°C. The temperature must be below 00°C, or between 250°C and 450°C, or between 300°C and 450°C. It is possible.

[0278] The heat treatment can be carried out in an atmosphere containing a noble gas or nitrogen. After heating with gas, it may be heated in an oxygen-containing atmosphere. Alternatively, it may be heated in a dry air atmosphere. It is also preferable that the atmosphere during the above heat treatment contains as little hydrogen, water, etc. as possible. The heat treatment is performed using an electric furnace, RTA (Rapid Thermal Annealing) Equipment can be used. By using an RTA device, the heat treatment time can be shortened. It is possible.

[0279] Note that this heat treatment may be omitted if it is not necessary. Also, heat treatment is not performed here. Furthermore, it may be combined with the heat treatment performed in a later step. Also, high-temperature treatment in a later step (e.g.) In some cases, such as in the film deposition process, this heat treatment can be carried out in conjunction with other processes.

[0280] [Formation of insulating layer 110] Next, the insulating layer 110 is formed by covering the insulating layer 103 and the semiconductor layer 108 (Figure 14). E).

[0281] Here, the insulating layer 110 consists of insulating film 110a, insulating film 110b, and insulating film 110 It is formed by stacking c.

[0282] In particular, each insulating film constituting the insulating layer 110 is preferably formed by the PECVD method. The method for forming each layer constituting the insulating layer 110 can be described by referring to the above example of configuration 1. Cut.

[0283] Plasma treatment is performed on the surface of the semiconductor layer 108 before the deposition of the insulating layer 110. This is preferable. The plasma treatment removes impurities such as water adsorbed on the surface of the semiconductor layer 108. This can be reduced. Therefore, impurities at the interface between the semiconductor layer 108 and the insulating layer 110 can be reduced. Because material can be reduced, highly reliable transistors can be realized. In particular, semiconductor layer 108 When the surface of the semiconductor layer 108 is exposed to the atmosphere between formation and deposition of the insulating layer 110 This is preferable. For plasma treatment, for example, oxygen, ozone, nitrogen, nitrous oxide, algonium It can be carried out in an atmosphere such as [unclear]. Also, plasma treatment and the deposition of the insulating layer 110 are [unclear]. It is preferable that the process be carried out continuously without exposure to the elements.

[0284] Here, it is preferable to perform a heat treatment after forming the insulating layer 110. This allows for the removal of hydrogen or water contained in or adsorbed on the insulating layer 110. This also reduces defects in the insulating layer 110.

[0285] The conditions for heat treatment can be applied as described above.

[0286] Note that this heat treatment may be omitted if it is not necessary. Also, heat treatment is not performed here. Furthermore, it may be combined with the heat treatment performed in a later step. Also, high-temperature treatment in a later step (e.g.) In some cases, such as in the film deposition process, this heat treatment can be carried out in conjunction with other processes.

[0287] [Formation of metal oxide film 114f] Next, a metal oxide film 114f is formed on the insulating layer 110 (Figure 15A).

[0288] The metal oxide film 114f is preferably formed in an atmosphere containing oxygen, for example. In particular, It is preferable to form it by sputtering in an oxygen-containing atmosphere. Oxygen can be supplied to the insulating layer 110 during the formation of the oxide film 114f.

[0289] The metal oxide film 114f is made of an oxide containing the same metal oxide as in the case of the semiconductor layer 108. When forming by sputtering using a target, refer to the above description. It is possible.

[0290] For example, as a film deposition condition for metal oxide film 114f, oxygen is used as the deposition gas, and the metal target... A metal oxide film may be formed by a reactive sputtering method using a metal target. For example, if aluminum is used as the base material, an aluminum oxide film is formed. It is possible.

[0291] When forming the metal oxide film 114f, the total flow rate of the deposition gas introduced into the deposition chamber of the deposition apparatus is The higher the ratio of oxygen flow rate (oxygen flow rate ratio), or the higher the oxygen partial pressure in the deposition chamber, the more insulating layer 1 The amount of oxygen supplied to 10 can be increased. The oxygen flow ratio or oxygen partial pressure can be, for example, Preferably 50% to 100%, more preferably 65% ​​to 100%, and further Preferably, the ratio is 80% to 100%, and more preferably 90% to 100%. In particular, the oxygen flow rate ratio is set to 100%, and the partial pressure of oxygen in the deposition chamber is brought as close to 100% as possible. It is preferable.

[0292] In this way, a metal oxide film 114f is formed by sputtering in an oxygen-containing atmosphere. By doing so, oxygen is supplied to the insulating layer 110 during the formation of the metal oxide film 114f. Furthermore, it is possible to prevent oxygen from detaching from the insulating layer 110. As a result, the insulating layer 11 An extremely large amount of oxygen can be trapped in 0.

[0293] It is preferable to perform a heat treatment after the formation of the metal oxide film 114f. By performing the heat treatment, The oxygen contained in the insulating layer 110 can be supplied to the semiconductor layer 108. When 114f is heated while covering the insulating layer 110, acid is released from the insulating layer 110 to the outside. This prevents the element from being detached and allows for a large supply of oxygen to the semiconductor layer 108. As a result, oxygen vacancies in the semiconductor layer 108 can be reduced, enabling the realization of highly reliable transistors.

[0294] The conditions for heat treatment can be applied as described above.

[0295] Note that this heat treatment may be omitted if it is not necessary. Also, heat treatment is not performed here. Furthermore, it may be combined with the heat treatment performed in a later step. Also, high-temperature treatment in a later step (e.g.) In some cases, such as in the film deposition process, this heat treatment can be carried out in conjunction with other processes.

[0296] After the metal oxide film 114f is formed, or after the heat treatment, the metal oxide film 114f is removed You may leave.

[0297] [Formation of opening 142] Next, the metal oxide film 114f, the insulating layer 110, and a portion of the insulating layer 103 are etched. This creates an opening 142 that reaches the conductive layer 106 (Figure 15B). The conductive layer 106 and the conductive layer 112 to be formed later are electrically connected via the opening 142. It is possible.

[0298] [Formation of conductive layer 112 and metal oxide layer 114] Next, a conductive film 112f, which will become the conductive layer 112, is formed on the metal oxide film 114f. Figure 15C).

[0299] It is preferable to use a low-resistance metal or alloy material as the conductive film 112f. The conductive film 112f is made of a material that does not easily release hydrogen and also does not easily diffuse hydrogen. It is preferable to use it. Furthermore, it is preferable to use a material that is less prone to oxidation as the conductive film 112f. preferable.

[0300] For example, the conductive film 112f is produced using a sputtering target containing a metal or alloy. It is preferable to deposit the film by the puttering method.

[0301] For example, the conductive film 112f is a conductive film that is resistant to oxidation and hydrogen diffusion, and has low resistance. It is preferable to form a laminated film by stacking a conductive film.

[0302] Next, by etching a portion of the conductive film 112f and the metal oxide film 114f, A conductive film 112f and a metal oxide film 114 are formed. It is preferable to process each of f using the same resist mask. Alternatively, etching The conductive layer 112 after etching is used as a hard mask to etch the metal oxide film 114f. That's fine.

[0303] As etching of the conductive film 112f and the metal oxide film 114f, particularly wet etching It is preferable to use the G method.

[0304] This results in the formation of a conductive layer 112 and a metal oxide layer 114 with substantially matching upper surface shapes. It is possible.

[0305] In this way, without etching the insulating layer 110, the top and side surfaces of the semiconductor layer 108, and By having a structure in which an insulating layer 103 is covered, when etching the conductive film 112f, etc., the semiconductor This prevents the body layer 108 and the insulating layer 103 from being etched and becoming thin. .

[0306] [Processing of supplying impurity elements] Next, using the conductive layer 112 as a mask, impurities are introduced into the semiconductor layer 108 via the insulating layer 110. The process involves supplying (adding or injecting) element 140 (Figure 15D). Therefore, a low-resistance region 108n is formed in the region of the semiconductor layer 108 that is not covered by the conductive layer 112. This is possible. At this time, in the region of the semiconductor layer 108 that overlaps with the conductive layer 112, the conductive layer 11 2 acts as a mask, and the impurity element 140 is not supplied.

[0307] The supply of impurity element 140 is preferably by plasma ion doping or ion implantation. These methods can be used to obtain a depth-direction concentration profile, and to accelerate ions. It can be controlled with high precision by adjusting voltage and dose. Plasma ion doping By using this method, productivity can be increased. Also, ion implantation using mass separation can be used. By using this method, the purity of the supplied impurity elements can be increased.

[0308] In the supply process of impurity element 140, at the interface between the semiconductor layer 108 and the insulating layer 110, The portion of the semiconductor layer 108 near the interface, or the portion of the insulating layer 110 near the interface, It is preferable to control the processing conditions to achieve the highest possible concentration. The principle is to supply both the semiconductor layer 108 and the insulating layer 110 with an optimal concentration of impurity elements 140. It is possible.

[0309] The 140 impurity elements are hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, and Examples include luminium, magnesium, silicon, or noble gases. Representative examples include helium, neon, argon, krypton, and xenon. It is preferable to use boron, phosphorus, aluminum, magnesium, or silicon. .

[0310] As a raw material gas for impurity element 140, a gas containing the above-mentioned impurity element can be used. When supplying boron, typical gases such as B2H6 gas and BF3 gas can be used. Furthermore, when supplying phosphorus, pH3 gas can typically be used. A mixed gas obtained by diluting these source gases with a noble gas may also be used.

[0311] Other raw material gases include CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF, H2, (C5H5)2Mg, and noble gases can be used. Furthermore, the ion source is not limited to gases; solids or liquids that have been heated and vaporized can also be used. good.

[0312] The addition of impurity element 140 affects the composition, density, and thickness of the insulating layer 110 and the semiconductor layer 108. By taking these factors into consideration and setting conditions such as acceleration voltage and dose amount, it can be controlled.

[0313] For example, when adding boron using ion implantation or plasma ion doping, The acceleration voltage is, for example, 5kV to 100kV, preferably 7kV to 70kV, Preferably, the voltage can be in the range of 10kV to 50kV. Also, the dose amount is, for example... ba 1 × 10 13 ions / cm 2 The above 1 x 10 17 ions / cm 2 The following is preferably 1 ×10 14 ions / cm 2 The above 5 x 10 16 ions / cm 2 More convenient 1 ×10 15 ions / cm 2 The above is 3 x 10 16 ions / cm 2 The following range It is possible.

[0314] When adding phosphorus ions using ion implantation or plasma ion doping, acceleration The voltage is, for example, 10kV to 100kV, preferably 30kV to 90kV. Preferably, the voltage can be in the range of 40kV to 80kV. Also, the dose amount is, for example, e.g. 1 x 10 13 ions / cm 2 The above 1 x 10 17 ions / cm 2 The following, preferably 1 x 10 14 ions / cm 2 The above 5 x 10 16 ions / cm 2 The following is more 1 x 10 15 ions / cm 2 The above is 3 x 10 16 ions / cm 2 The following ranges apply. It is possible.

[0315] Furthermore, the method of supplying impurity element 140 is not limited to this; for example, plasma processing or heating... Treatment methods utilizing thermal diffusion may also be used. In the case of plasma treatment, the impurities to be added By generating plasma in an element-containing gas atmosphere and performing plasma processing, Pure elements can be added. As a device for generating the above plasma, dry etching is used. Using quenching equipment, ashing equipment, plasma CVD equipment, high-density plasma CVD equipment, etc. It is possible.

[0316] In one aspect of the present invention, impurity elements 140 are supplied to the semiconductor layer 108 via the insulating layer 110. Therefore, even if the semiconductor layer 108 has crystalline properties, impurities The damage to the semiconductor layer 108 during the supply of element 140 is reduced, and its crystallinity is not impaired. This can suppress the occurrence of this problem. Therefore, the decrease in crystallinity can increase electrical resistance. It is suitable in such cases.

[0317] [Formation of insulating layer 118] Next, the insulating layer 110, the metal oxide layer 114, and the conductive layer 112 are covered by the insulating layer 11 Formation 8 (Figure 16A).

[0318] When forming the insulating layer 118 by plasma CVD, if the substrate temperature is too high, low resistance occurs. Impurities contained in region 108n, etc., in the peripheral region including the channel formation region of the semiconductor layer 108 There is a risk of diffusion, and a risk of the electrical resistance in the low-resistance region of 10⁸n increasing. Therefore Therefore, the substrate temperature during the formation of the insulating layer 118 should be determined taking these factors into consideration.

[0319] For example, the substrate temperature of the insulating layer 118 is preferably, for example, 150°C to 400°C. Furthermore, a temperature of 180°C to 360°C is preferred, and even more preferably 200°C to 250°C. It is possible to form an insulating layer 118 at a low temperature, even in transistors with short channel lengths. Even so, good electrical characteristics can be imparted.

[0320] After the formation of the insulating layer 118, a heat treatment may be performed. This heat treatment will create a low-resistance region 1 In some cases, the O8n can be made more stable and have lower resistance. For example, by performing heat treatment. As a result, impurity element 140 diffuses appropriately and becomes locally homogenized, creating an ideal impurity source. A low-resistance region 108n with a primary concentration gradient can be formed. Note that if the heat treatment temperature is high When the temperature rises (for example, above 500°C), impurity element 140 diffuses into the channel-forming region. This could lead to a deterioration in the electrical characteristics and reliability of the transistor.

[0321] The conditions for heat treatment can be applied as described above.

[0322] Note that this heat treatment may be omitted if it is not necessary. Also, heat treatment is not performed here. Furthermore, it may be combined with the heat treatment performed in a later step. Also, high-temperature treatment in a later step (e.g.) For example, if there is a film formation process, it may be possible to combine it with the heat treatment.

[0323] [Formation of openings 141a and 141b] Next, by etching a portion of the insulating layer 118 and the insulating layer 110, a low-resistance region 1 is formed. Openings 141a and 141b are formed, reaching 08n.

[0324] [Formation of conductive layer 120a and conductive layer 120b] Next, a conductive film is applied to the insulating layer 118 so as to cover the openings 141a and 141b. By forming a film and processing the conductive film into a desired shape, conductive layer 120a and conductive layer 120b are formed. It forms (Figure 16B).

[0325] By following the above steps, transistor 100A can be manufactured. For example, When applying Sta100A to the pixels of a display device, a protective insulating layer, a planarizing layer, The process can be simplified by adding a step to form one or more of the pixel electrodes or wiring.

[0326] The above is an explanation of manufacturing method example 1.

[0327] Furthermore, when manufacturing the transistor 100 exemplified in Configuration Example 2-1, the above manufacturing method is used. The steps for forming the conductive layer 106 and the opening 142 in Example 1 can be omitted. Furthermore, transistors 100 and 100A are formed on the same substrate through the same process. It is possible.

[0328] <Example of manufacturing method 2> The following describes an example where some steps differ from the above example of manufacturing method 1. Here, the above structure We will explain using transistor 100C, which was illustrated in Example 2-4, as an example.

[0329] In the following sections, we will omit explanations of parts that overlap with the above manufacturing method example 1, and will only explain the parts that differ. I will now explain the details of the minutes.

[0330] First, similar to the above example of manufacturing method 1, conductive layer 106, insulating layer 103, semiconductor layer 108, insulating The edge layer 110, the metal oxide film 114f, and the conductive film 112f are formed in order. A cross-sectional view is shown in Figure 17A.

[0331] Next, a portion of the conductive film 112f and the metal oxide film 114f is etched to form the conductive layer 1 Forming 12 and a metal oxide layer 114, and further etching a portion of the insulating layer 110, half A portion of the conductor layer 108 is exposed (Figure 17B). This results in a conductor with a roughly matching top surface shape. A voltage layer 112, a metal oxide layer 114, and an insulating layer 110 can be formed.

[0332] Etching of the insulating layer 110 is performed using a resist mask to etch the conductive film 112f. It is preferable to use [a specific method] for etching the insulating layer 110, the conductive film 112f, and gold The etching process may be carried out in the same manner as the etching of the oxide film 114f, or the conductive film 112f and the metal After etching the oxide film 114f, etching is performed using a different etching method. You may do so.

[0333] For example, conductive film 112f and metal oxide film 114f are made using the same etchant. After etching by the etching method, the insulating layer 110 is etched by the dry etching method. It can be dry-etched. In particular, the conductive film 112f and the metal oxide film 114f can be dry-etched. When processed by the cutting method, reaction products containing metal are generated, resulting in the semiconductor layer 10 There is a risk of contaminating 8 and the insulating layer 110. Therefore, before etching the insulating layer 110 The conductive film 112f and the metal oxide film 114f are processed by a wet etching method. It is preferable.

[0334] Depending on the etching conditions, the conductive layer 112, the metal oxide layer 114, and the insulating layer 1 The edges of 10 may not coincide. For example, the conductive layer 112 may be different from the edge of the insulating layer 110. and the shape such that at least one end of the metal oxide layer 114 is located on the inside or outside. There are cases where this occurs.

[0335] During etching of the insulating layer 110, a portion of the exposed semiconductor layer 108 is etched, resulting in a thin layer. In some cases, a film may form. At this time, the semiconductor layer 108 has a thickness of low-resistance region 108n, The shape can be thinner than the thickness of the flannel-forming region.

[0336] During etching of the insulating layer 110, a portion of the insulating layer 103 that is not covered by the semiconductor layer 108 is etched. This can occur, resulting in thinning. For example, the insulating film 103d of the insulating layer 103 may disappear. In some cases, it may be the case.

[0337] Next, an insulating layer 116 is formed in contact with the exposed portion of the semiconductor layer 108, and then insulating... Layer 118 is formed (Figure 17C). The formation of the insulating layer 116 exposes the semiconductor layer 108. The reduced resistance of this portion creates a low-resistance region 108n.

[0338] The insulating layer 116 releases impurity elements that have the function of reducing the resistance of the semiconductor layer 108. An insulating film can be used. In particular, a silicon nitride film that can release hydrogen, It is preferable to use an inorganic insulating film such as a silicon nitride film or a silicon oxide nitride film. At that time, by using a plasma CVD method with a hydrogen-containing film-forming gas, the insulating layer 116 Hydrogen can be supplied to the semiconductor layer 108 during film formation, which is preferable.

[0339] For example, when silicon nitride is used as the insulating layer 116, silicon such as silane is used. A mixed gas containing a gas and a nitrogen-containing gas such as ammonia or nitrous oxide is used to form a film. It is preferable to form it by the PECVD method used in the previous step. At this time, the nitride silicate film that is formed is It is preferable that hydrogen is contained in the concrete. This allows the hydrogen in the insulating layer 116 to act as a semiconductor. By diffusing into the body layer 108, it becomes easier to reduce the resistance of a portion of the semiconductor layer 108.

[0340] As the insulating layer 116, an insulating film having the function of causing oxygen vacancies in the semiconductor layer 108 is used. It can also be used. In particular, it is preferable to use an insulating film containing a metal nitride. For example, Using a sputtering target containing metal, nitrogen gas and a mixture of diluent gases such as noble gases are used. An insulating layer 116 is formed by a reactive sputtering method using a combined gas as the film-forming gas. This is preferable. By controlling the flow rate ratio of the film-forming gas, the film quality of the insulating layer 116 can be controlled. This makes it easier to control.

[0341] For example, in reactive sputtering using an aluminum target as the insulating layer 116 When using an aluminum nitride film formed from this material, the flow rate of nitrogen gas relative to the total flow rate of the film deposition gas is The amount is preferably 30% to 100%, and more preferably 40% to 100%. Furthermore, a percentage of 50% to 100% is preferable.

[0342] Here, insulating layer 116 and insulating layer 118 are formed continuously without exposure to the atmosphere. It is preferable.

[0343] Heat treatment may be performed after the formation of the insulating layer 116 or after the formation of the insulating layer 118. Heat treatment can accelerate the reduction of resistance in the low-resistance region 10⁸n.

[0344] The conditions for heat treatment can be applied as described above.

[0345] Note that this heat treatment may be omitted if it is not necessary. Also, heat treatment is not performed here. Furthermore, it may be combined with the heat treatment performed in a later step. Also, high-temperature treatment in a later step (e.g.) In some cases, such as in the film deposition process, this heat treatment can be carried out in conjunction with other processes.

[0346] Next, openings 141 reaching the low-resistance region 108n are made in the insulating layer 118 and the insulating layer 116. a and opening 141b are formed.

[0347] Next, on the insulating layer 118, the conductive layer 120a and conductive layer 120 are added in the same manner as in manufacturing method example 1. b is formed (Figure 17D).

[0348] By following the above steps, transistor 100C can be manufactured.

[0349] Furthermore, when manufacturing transistor 100B as exemplified in Configuration Example 2-3, the above manufacturing method applies. The steps for forming the conductive layer 106 and the opening 142 in the example of the law can be omitted. Furthermore, transistors 100B and 100C are manufactured on the same substrate through the same process. It can be formed as follows.

[0350] <Components of a semiconductor device> The following describes the components included in the semiconductor device of this embodiment.

[0351] 〔substrate〕 There are no major restrictions on the material of the substrate 102, but it should at least be able to withstand subsequent heat treatment. It must have heat resistance. For example, a single crystal made of silicon or silicon carbide. Semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI groups Plates, glass substrates, ceramic substrates, quartz substrates, sapphire substrates, etc., are used as substrate 102. It is also acceptable to have semiconductor elements mounted on these substrates as substrate 102. You may use it.

[0352] Even if a flexible substrate is used as the substrate 102 and a semiconductor device is formed directly on the flexible substrate, That's fine. Alternatively, a release layer may be provided between the substrate 102 and the semiconductor device. The release layer is on top of that. After partially or completely completing the semiconductor device, it is separated from the substrate 102 and transferred to another substrate. It can be used for this purpose. In this case, the semiconductor device is a substrate with poor heat resistance or a flexible substrate. It can also be reprinted.

[0353] [Conductive film] Conductive layers 112 and 106 function as gate electrodes, and source electrodes or A conductive layer 120a that functions as one of the rain electrodes, and a conductive layer 120 that functions as the other b includes chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, A metallic element selected from tungsten, manganese, nickel, iron, and cobalt, or the above Using alloys composed of the aforementioned metal elements, or alloys combining the aforementioned metal elements, It can be formed.

[0354] The conductive layer 112, conductive layer 106, conductive layer 120a, and conductive layer 120b contain In-Sn Oxides, In-W oxides, In-W-Zn oxides, In-Ti oxides, In-Ti-Sn Oxides such as In-Zn oxide, In-Sn-Si oxide, In-Ga-Zn oxide, etc. A material conductor or a metal oxide film can also be applied.

[0355] Here, we will explain oxide conductors (OC). For example, an oxygen vacancy is formed in a metal oxide having semiconductor properties, and hydrogen is added to the oxygen vacancy. Then, a donor level is formed near the conduction band. As a result, the metal oxide becomes highly conductive. It becomes conductive. A metal oxide that has been made conductive can be called an oxide conductor.

[0356] The conductive layer 112, etc., is a conductive film containing the above oxide conductor (metal oxide) and a metal or A laminated structure of conductive films containing an alloy may also be used. By using a conductive film containing a metal or alloy, This allows for reduced wiring resistance. At this time, the insulating layer that functions as a gate insulating film and It is preferable to apply a conductive film containing an oxide conductor to the contacting side.

[0357] The conductive layers 112, 106, 120a, and 120b contain the aforementioned metal elements. Among these, the selection is particularly made from titanium, tungsten, tantalum, and molybdenum. It is preferable to have one or more of these. In particular, it is preferable to use a tantalum nitride film. The tantalum nitride film is electrically conductive and has high resistance to copper, oxygen, or hydrogen. It has real properties and releases little hydrogen from itself, and therefore is conductive when in contact with semiconductor layer 108. It can be suitably used as a film or a conductive film in the vicinity of the semiconductor layer 108.

[0358] [Semiconductor layer] If the semiconductor layer 108 is In-M-Zn oxide, then to deposit the In-M-Zn oxide film... For the sputtering target used, the atomic ratio of metal elements can be, for example, In:M:Z n=5:1:1, In:M:Zn=5:1:2, In:M:Zn=5:1:3, In:M :Zn=5:1:4, In:M:Zn=5:1:5, In:M:Zn=5:1:6, In :M:Zn=10:1:1, In:M:Zn=10:1:2, In:M:Zn=10:1 :3, In:M:Zn=10:1:4, In:M:Zn=10:1:5, In:M:Zn =10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In :M:Zn=10:1:10, In:M:Zn=10:1:12, In:M:Zn=10 :1:15, or a vicinity thereof, can be preferably used. Also, the semiconductor layer 108 In the case of indium oxide, the sputtering target used to deposit the indium oxide film Indium oxide can be used as a base material. Also, if the semiconductor layer 108 is In-M oxide In the case of materials, the metal element of the sputtering target used to deposit In-M oxide films. For example, the atomic ratios are In:M=2:1, In:M=7:2, In:M=5:1, In:M=7:1, In:M=10:1, or a range of these can be preferably used. Furthermore, if the semiconductor layer 108 is In-Zn oxide, in order to deposit the In-Zn oxide film... For the sputtering target used, the atomic ratio of metal elements is, for example, In:Zn= 2:3, In:Zn=3:2, In:Zn=7:2, In:Zn=4:1, In:Zn= Preferably, use a ratio of 11:2, In:Zn=7:1, In:Zn=14:1, or a ratio close to these. It is possible to be there.

[0359] When a target containing a polycrystalline oxide is used as a sputtering target, the crystal This is preferable because it facilitates the formation of a semiconductor layer 108 having properties. The atomic ratio of 10⁸ is the atomic ratio of the metal elements contained in the above sputtering target. Includes a variation of plus or minus 40%. For example, the sputtering process used for semiconductor layer 108 When the composition of the film is In:Ga:Zn=5:1:3 (atomic ratio), the resulting semiconductor film is formed. The composition of layer 108 is close to In:Ga:Zn = 5:1:2.4 (atomic ratio). be.

[0360] Using the above target, sputtering is performed with the substrate temperature set to between 100°C and 130°C. The metal oxide formed by the ng process has either an nc structure or a CAAC structure. or a structure in which these are mixed is likely to be formed. On the other hand, if the substrate temperature is room temperature (RT), Metal oxides formed by the puttering method tend to adopt an nc crystal structure. In this context, room temperature (RT) includes the temperature when the substrate is not heated.

[0361] The semiconductor layer 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more. Thus, by using metal oxides with a wider energy gap than silicon, This can reduce the transistor's off-current.

[0362] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., are at least a part of them. This can be implemented by combining it with other configuration examples or drawings as appropriate.

[0363] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0364] (Embodiment 3) In this embodiment, an example of a display device having a transistor as illustrated in the previous embodiment is provided. I will explain about that.

[0365] <Example Configuration> Figure 18A shows a top view of the display device 700. The display device 700 is sealed by a sealing material 712 It has a first substrate 701 and a second substrate 705 that are bonded together. In the region sealed by the second substrate 705 and the sealing material 712, on the first substrate 701 The pixel section 702, source driver circuit section 704, and gate driver circuit section 706 are provided. Furthermore, the pixel section 702 is provided with multiple display elements.

[0366] In the portion of the first substrate 701 that does not overlap with the second substrate 705, FPC716 (FPC:F The FPC terminal section 708 to which the lexible printed circuit is connected It is provided. FPC716 is provided via FPC terminal section 708 and signal line 710 , the same as the pixel section 702, the source driver circuit section 704, and the gate driver circuit section 706 Various signals are supplied to each of them.

[0367] Multiple gate driver circuits 706 may be provided. The path section 706 and the source driver circuit section 704 are each formed separately on a semiconductor substrate or the like. The IC chip may be in the form of a packaged IC chip. The IC chip is on the first substrate 70 It can be implemented on 1 or on FPC716.

[0368] The pixel section 702, the source driver circuit section 704, and the gate driver circuit section 706 have A transistor, which is a semiconductor device according to one aspect of the present invention, can be applied to the transistor. ru.

[0369] Examples of display elements provided in the pixel section 702 include liquid crystal elements and light-emitting elements. The liquid crystal elements used include transmissive liquid crystal elements, reflective liquid crystal elements, and semi-transmissive liquid crystal elements. It is possible to use LEDs (Light Emitting Diodes) as light-emitting elements. de), OLED (Organic LED), QLED (Quantum-dot L Examples include self-luminous light-emitting elements such as EDs and semiconductor lasers. Also, shutter-type or optical interferometry MEMS (Micro Electro Mechanical Systems) (Systems) elements, microcapsule method, electrophoresis method, electrowetting Display elements using methods such as the GL method or the electronic powder fluid (registered trademark) method can also be used. Cut.

[0370] The display device 700A shown in Figure 18B uses a flexible resin instead of the first substrate 701. An example of a display device to which layer 743 is applied and which can be used as a flexible display. That is the case.

[0371] The display device 700A has a pixel section 702 that is not rectangular in shape, but has an arc-shaped corner. Furthermore, as shown in region P1 in Figure 18B, the pixel portion 702 and a part of the resin layer 743 It has a notched portion. A pair of gate driver circuit sections 706 are located in the pixel section 702 It is provided on both sides of the . The gate driver circuit section 706 is located at the corner of the pixel section 702. It is provided along an arc-shaped contour.

[0372] The resin layer 743 has a shape in which the portion where the FPC terminal portion 708 is provided protrudes. Furthermore, a portion of the resin layer 743, including the FPC terminal portion 708, is folded to the back side in area P2 in Figure 18B. It can be folded back. By folding back a part of the resin layer 743, the FPC 716 can be folded back into the pixel section 70 With the display device 700A placed on top of the back of 2, it can be mounted on the electronic device. This allows for space-saving in electronic devices.

[0373] The FPC716 connected to the display device 700A has the IC717 mounted on it. 717 has a function, for example, as a source driver circuit. At this time, the display device 700 The source driver circuit section 704 in A includes a protection circuit, a buffer circuit, and a demultiplexer. The configuration may include at least one circuit or the like.

[0374] The display device 700B shown in Figure 18C is suitable for use in electronic devices having a large screen. It is a display device capable of doing so. For example, television equipment, monitor equipment, personal computers Tablet devices (including notebook and desktop models), digital signage, etc. It can be suitably used for the following purposes.

[0375] The display device 700B consists of multiple source driver ICs 721 and a pair of gate driver circuits. It has part 722.

[0376] Multiple source driver IC721s are each attached to the FPC723. Furthermore, multiple FPC723s have one terminal connected to the first substrate 701 and the other terminal connected to the printed circuit board Each is connected to board 724. By bending FPC723, the printed circuit board 7 By placing 24 on the back side of the pixel unit 702, it can be mounted on electronic devices, reducing the size of the electronic device. This allows for a more controlled pace.

[0377] On the other hand, the gate driver circuit section 722 is formed on the first substrate 701. This makes it possible to create electronic devices with even narrower bezels.

[0378] This configuration makes it possible to realize a large and high-resolution display device. For example, Surface size is 30 inches or more diagonally, 40 inches or more, 50 inches or more, or 60 inches or more diagonally. It can also be applied to the above display devices. Furthermore, resolutions such as 4K2K or 8K4K are also supported. This makes it possible to realize extremely high-resolution display devices.

[0379] <Example of cross-sectional configuration> The following describes configurations using liquid crystal elements and EL elements as display elements. This will be explained using Figures 19 to 22. Note that Figures 19 to 21 are based on Figure 18A. Figure 22 is a cross-sectional view along the dashed line QR. Figure 22 also shows the display device 7 shown in Figure 18B. This is a cross-sectional view along the dashed line ST in 00A. Figures 19 and 20 show the display elements as The configuration uses liquid crystal elements, while Figures 21 and 22 show configurations using electroluminescent (EL) elements.

[0380] [Explanation of common parts of display devices] The display device shown in Figures 19 to 22 comprises a wiring section 711, a pixel section 702, and a saw It has a screwdriver circuit section 704 and an FPC terminal section 708. The routing wiring section 711 is , has a signal line 710. The pixel section 702 has a transistor 750 and a capacitive element 790. The source driver circuit section 704 has a transistor 752. In Figure 20, the capacitance This shows the case where element 790 is absent.

[0381] Transistors 750 and 752 are the transistors exemplified in Embodiment 2. It can be applied.

[0382] The transistor used in this embodiment is made of an oxide that has been purified to suppress the formation of oxygen vacancies. It has a semiconductor film. The transistor can reduce the off-current. Therefore, it can handle electrical signals such as image signals. The holding time for signal signals can be extended, and the writing interval for image signals, etc., can also be set to be longer. This reduces the frequency of fresh cycles, resulting in lower power consumption.

[0383] The transistor used in this embodiment can obtain relatively high field-effect mobility, High-speed driving is possible. For example, if such a high-speed driving transistor is used in a display device... By doing so, the transistors used in the pixel section and the transistors used in the drive circuit section are placed on the same circuit board. It can be formed in this way. That is, a drive circuit formed from a silicon wafer or the like can be applied. A configuration without this is also possible, which can reduce the number of components in the display device. In addition, by using transistors capable of high-speed operation, high-quality images can be provided. It is possible.

[0384] The capacitive element 790 shown in Figures 19, 21, and 22 is a part of the transistor 750. The lower electrode is formed by processing the same film as the gate electrode of 1, and the same metal oxide as the semiconductor layer. It has an upper electrode formed by processing a material. The upper electrode is the saw of transistor 750 The resistance is reduced, similar to the drain region. Also, between the lower electrode and the upper electrode A portion of the insulating film, which functions as the first gate insulating layer of transistor 750, is provided therein. In other words, the capacitive element 790 has an insulating film that functions as a dielectric film sandwiched between a pair of electrodes. It has a stacked structure. In addition, the upper electrode has the source electrode and drain electrode of the transistor. Wiring obtained by processing the same film as the electrodes is connected.

[0385] A planarizing insulating film 7 is applied to transistors 750, 752, and capacitive element 790. 70 is provided.

[0386] The transistor 750 in the pixel section 702 and the source driver circuit section 704 Transistors with different structures than the 752 transistor may be used. For example, any one of them A top-gate transistor is applied to one side, and a bottom-gate transistor is applied to the other side. A configuration using the above gate driver circuit section 706 may also be used. Similar to the IBA circuit section 704, a transistor with the same structure as transistor 750 may be used. Alternatively, transistors with different structures may be used.

[0387] Signal line 710 is the same as the source and drain electrodes of transistors 750 and 752. It is formed of a conductive film. In this case, if a low-resistance material such as a material containing copper elements is used, This is preferable because it minimizes signal delays caused by line resistance, allowing for display on a large screen.

[0388] The FPC terminal section 708 includes wiring 760, part of which functions as a connecting electrode, and an anisotropic conductive film 78. It has 0 and FPC716. Wiring 760 is connected to FPC71 via an anisotropic conductive film 780. It is electrically connected to the terminals of 6. Here, wiring 760 is connected to transistor 750. It is formed of the same conductive film as the source electrode and drain electrode of 752.

[0389] The first substrate 701 and the second substrate 705 are, for example, a glass substrate or a plastic substrate. Flexible substrates such as acrylic substrates can be used. When using a substrate, water or hydrogen is placed between the first substrate 701 and the transistor 750, etc. It is preferable to provide an insulating layer that has barrier properties against [the element].

[0390] On the second substrate 705 side, there is a light-shielding film 738, a colored film 736, and an insulating film 7 in contact with them. 34 and are provided.

[0391] [Example configuration of a display device using liquid crystal elements] The display device 700 shown in Figure 19 has a liquid crystal element 775 and a spacer 778. The sub-element 775 has a conductive layer 772, a conductive layer 774, and a liquid crystal layer 776 between them. The electrode layer 774 is provided on the second substrate 705 side and functions as a common electrode. The conductive layer 772 is electrically connected to the source electrode or drain electrode of the transistor 750. The conductive layer 772 is formed on the planar insulating film 770 and functions as a pixel electrode. ru.

[0392] The conductive layer 772 may be made of a material that is transparent to visible light or a material that is reflective to visible light. Yes, it is possible. For example, an oxide material containing indium, zinc, tin, etc., can be used as a translucent material. It would be good to have one. For example, using a reflective material containing aluminum, silver, etc. would be beneficial. stomach.

[0393] If a reflective material is used for the conductive layer 772, the display device 700 becomes a reflective liquid crystal display device. On the other hand, if a translucent material is used for the conductive layer 772, a transmissive liquid crystal display device is obtained. In the case of a transmissive liquid crystal display device, a polarizing plate is provided on the viewing side. On the other hand, in the case of a transmissive liquid crystal display device... A pair of polarizing plates are provided so as to sandwich the liquid crystal element.

[0394] The display device 700 shown in Figure 20 uses a transverse electric field method (for example, FFS mode) liquid crystal element 77 An example using 5 is shown. A common electrode is formed on the conductive layer 772 via an insulating layer 773. A conductive layer 774 is provided. Due to the electric field generated between the conductive layer 772 and the conductive layer 774, The orientation state of the liquid crystal layer 776 can be controlled.

[0395] In Figure 20, the laminated structure of conductive layer 774, insulating layer 773, and conductive layer 772 provides retention capacity. It can be configured in terms of quantity. Therefore, there is no need to provide a separate capacitive element, and the aperture ratio can be increased. It is possible.

[0396] Although not shown in Figures 19 and 20, the configuration includes an alignment film in contact with the liquid crystal layer 776. This is also fine. In addition, optical components (optical substrates) such as polarizing members, phase difference members, and anti-reflective members, and Light sources such as backlights and sidelights can be provided as needed.

[0397] The liquid crystal layer 776 contains thermotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, and polymer dispersion liquid. Crystal (PDLC: Polymer Dispersed Liquid Crystal) Polymer Network Liquid Crystal (PNLC) d Crystal), ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. When employing a transverse electric field method, a liquid crystal exhibiting a blue phase without an alignment layer may be used.

[0398] The modes of liquid crystal elements include TN (Twisted Nematic) mode and VA (V (Certical Alignment) mode, IPS (In-Plane-Switc Fing mode, FFS (Fringe Field Switching) mode, ASM(Axially Symmetric aligned Micro-cell ) Mode, OCB (Optically Compensated Birefringence) ence) mode, ECB (Electrically Controlled Bir You can use modes such as efringence mode and guest host mode.

[0399] A scattering type liquid crystal layer 776 using polymer dispersed liquid crystal or polymer network liquid crystal A liquid crystal can also be used. In this case, a configuration that displays in black and white without providing a colored film 736 is also possible. Alternatively, a configuration may be used in which a colored film 736 is used to display color.

[0400] As a method for driving liquid crystal elements, color display is performed based on the time-division table, which uses a time-division table. A display method (also called a field sequential drive method) may be applied. In that case, A configuration without a color film 736 is possible. When a time-division display method is used, for example, There is no need to provide subpixels that exhibit the respective colors R (red), G (green), and B (blue). Therefore, it offers advantages such as improving the aperture ratio of pixels and increasing the resolution.

[0401] [Display devices using light-emitting elements] The display device 700 shown in Figure 21 has a light-emitting element 782. The light-emitting element 782 is a conductive layer It has 772, an EL layer 786, and a conductive film 788. The EL layer 786 is an organic compound, and It contains luminescent materials such as inorganic compounds.

[0402] As luminescent materials, fluorescent materials, phosphorescent materials, and thermally activated delayed fluorescence (thermally ac activated delayed fluorescence (TADF) materials, mineralization Hybrid materials (such as quantum dot materials) can be used.

[0403] The display device 700 shown in Figure 21 has a conductive layer 772 covering a portion of the planar insulating film 770. An insulating film 730 is provided. Here, the light-emitting element 782 has a light-transmitting conductive film 788, This is a top-emission type light-emitting element. The light-emitting element 782 emits light towards the conductive layer 772. The bottom emission structure that is ejected emits light, and light is emitted to both the conductive layer 772 side and the conductive film 788 side. It may also be a dual-emission structure.

[0404] The colored film 736 is provided in a position that overlaps with the light-emitting element 782, and the light-shielding film 738 is an insulating film 730 It is provided in the overlapping position, the routing wiring section 711, and the source driver circuit section 704. Furthermore, the colored film 736 and the light-shielding film 738 are covered with an insulating film 734. The space between element 782 and insulating film 734 is filled with sealing film 732. Furthermore, the EL layer 786 When forming island-like structures for each pixel or striped structures for each row of pixels, that is, when forming them by color separation: In this configuration, the colored film 736 may not be provided.

[0405] Figure 22 shows a display device configuration that is suitably applicable to a flexible display. Figure 22 is a cross-sectional view of the display device 700A shown in Figure 18B along the dashed line ST. be.

[0406] The display device 700A shown in Figure 22 replaces the first substrate 701 shown in Figure 21 with a support base The structure has a laminated configuration consisting of a plate 745, an adhesive layer 742, a resin layer 743, and an insulating layer 744. The transistor 750 and the capacitive element 790 are located on the insulating layer 744 provided on the resin layer 743. It is located at [location].

[0407] The support substrate 745 is a substrate containing organic resin, glass, etc., and is thin enough to be flexible. The resin layer 743 is a layer containing organic resins such as polyimide and acrylic. Insulating layer 744 This includes an inorganic insulating film such as silicon oxide, silicon oxide nitride, and silicon nitride. Resin layer 74 3 and the support substrate 745 are bonded together by an adhesive layer 742. The resin layer 743 is It is preferable that the substrate is thinner than the support substrate 745.

[0408] The display device 700A shown in Figure 22 has a protective layer 7 instead of the second substrate 705 shown in Figure 21. It has 40. The protective layer 740 is bonded to the sealing film 732. Furthermore, glass substrates and resin films can be used. Also, as the protective layer 740, Optical components such as polarizing plates and scattering plates, input devices such as touch sensor panels, or these A configuration with two or more layers stacked on top of each other may also be applied.

[0409] The EL layer 786 of the light-emitting element 782 is provided in an island-like manner on the insulating film 730 and the conductive layer 772. It is made that the EL layer 786 is made so that each sub-pixel emits a different color of light. Color display can be achieved without using the color film 736. Also, the light-emitting element 782 is covered. A protective layer 741 is provided. The protective layer 741 protects the light-emitting element 782 from impurities such as water. It has the function of preventing diffusion. It is preferable that the protective layer 741 be an inorganic insulating film. Furthermore, it is preferable to have a laminated structure that includes one or more inorganic insulating films and one or more organic insulating films. stomach.

[0410] Figure 22 shows the foldable region P2. In region P2, the support substrate 745, In addition to the adhesive layer 742, there are portions where no inorganic insulating film such as an insulating layer 744 is provided. Furthermore, in region P2, a resin layer 746 is provided covering the wiring 760. In the functional region P2, an inorganic insulating film is provided as little as possible, and a conductive layer containing a metal or alloy is provided. By constructing a structure in which only layers containing organic materials are laminated, cracks will not occur when bent. This can be prevented. Also, by not providing the support substrate 745 in region P2, extremely small curves can be prevented. By adjusting the radius, a portion of the 700A display device can be bent.

[0411] [Example of a configuration in which an input device is provided to the display device] An input device is provided to the display device 700 or display device 700A shown in Figures 19 to 22. This is also acceptable. Examples of such input devices include touch sensors.

[0412] For example, sensor types include capacitive, resistive, surface acoustic wave, and infrared. Various methods can be used, such as optical and pressure-sensitive methods. Or, two or more of these can be used. They may be used in combination.

[0413] The touch panel configuration is a so-called in-cell type, where the input device is formed between a pair of circuit boards. A so-called on-cell type touch panel, which forms the touch panel and input device on the display device 700. A so-called out-cell type touch, in which a ru or input device is attached to the display device 700. There are panels and other things.

[0414] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., are at least a part of them. This can be implemented by combining it with other configuration examples or drawings as appropriate.

[0415] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0416] (Embodiment 4) In this embodiment, Figure 23 shows a display device having a semiconductor device according to one aspect of the present invention. We will use this to provide an explanation.

[0417] The display device shown in Figure 23A comprises a pixel unit 502, a drive circuit unit 504, and a protection circuit 506. It has a terminal section 507 and a protective circuit 506.

[0418] Transistors in the pixel section 502 and the drive circuit section 504 are configured according to one aspect of the present invention. A transistor can be applied. Also, a transistor according to one aspect of the present invention can be used in the protection circuit 506. You may apply this.

[0419] The pixel section 502 is arranged in X rows and Y columns (where X and Y are independent natural numbers greater than or equal to 2). It has several pixel circuits 501. Each pixel circuit 501 is a circuit that drives a display element. To possess.

[0420] The drive circuit section 504 outputs a scanning signal to the gate lines GL_1 to GL_X. Source driver 504a, which supplies data signals to data lines DL_1 to DL_Y. It has a drive circuit such as 04b. The gate driver 504a has at least a shift register The configuration should include, for example, multiple analog switches. It is constructed using switches, etc. Furthermore, it uses shift registers, etc., to configure the source driver 504 You may also construct b.

[0421] The terminal section 507 inputs power, control signals, and image signals, etc., from an external circuit to the display device. This refers to the part that is equipped with terminals for that purpose.

[0422] The protection circuit 506, when a potential outside a certain range is applied to the wiring to which it is connected, This is a circuit that creates a conductive state between two wires. The protection circuit 506 shown in Figure 23A is, for example, The gate lines GL_1 to G are the wiring between the gate driver 504a and the pixel circuit 501. L_X, or data line DL, is the wiring between source driver 504b and pixel circuit 501. It is connected to various wirings such as _1 to DL_Y. Note that in Figure 23A, the protection circuit 506 and Hatching is applied to the protection circuit 506 to distinguish it from the basic circuit 501.

[0423] The gate driver 504a and the source driver 504b are based on the same base as the pixel unit 502. It may be provided on the board, or the gate driver circuit or source driver circuit may be provided separately. The completed substrate (for example, a drive circuit board formed from a single-crystal semiconductor or polycrystalline semiconductor) COG and TAB (Tape Automated Bonding) are used to control the pixel area 5 It may also be configured to be mounted on a circuit board on which 02 is provided.

[0424] Figures 23B and 23C show one of the pixel circuit configurations that can be applied to the pixel circuit 501. Here is an example.

[0425] The multiple pixel circuits 501 shown in Figure 23A have, for example, the configurations shown in Figures 23B and 23C. It is possible.

[0426] The pixel circuit 501 shown in Figure 23B consists of a liquid crystal element 570, a transistor 550, and a capacitive element. It has a sub-unit 560 and a gate line GL_m. The pixel circuit 501 also has a data line DL_n and a gate line GL_m The potential supply line VL and other connections are connected.

[0427] The potential of one of the pair of electrodes of the liquid crystal element 570 is set appropriately according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set according to the data being written to it. A common potential is set on one of the pairs of electrodes of the liquid crystal element 570 that each of the pixel circuits 501 possesses. (Common potential) may be applied. Also, a pair of liquid crystal elements 570 of the pixel circuit 501 in each row One of the electrodes may be given a different potential.

[0428] The pixel circuit 501 shown in Figure 23(C) consists of transistors 552 and 554 and a capacitive element 56 It has 2 and a light-emitting element 572. The pixel circuit 501 also has data line DL_n, and The following are connected: wire GL_m, potential supply wire VL_a, potential supply wire VL_b, etc.

[0429] Furthermore, a high power supply potential VDD is supplied to one of the potential supply lines VL_a and VL_b. On the other hand, a low power supply potential VSS is applied to the gate of transistor 554. Depending on the potential, the current flowing through the light-emitting element 572 is controlled, thereby controlling the light-emitting element 5 The luminescence is controlled from 72 onwards.

[0430] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., are at least a part of them. This can be implemented by combining it with other configuration examples or drawings as appropriate.

[0431] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0432] (Embodiment 5) Below, we have a pixel circuit equipped with memory for correcting the gradation displayed in the pixel, and this The display device will be described below. The transistor exemplified in Embodiment 2 is exemplified below. This can be applied to transistors used in pixel circuits.

[0433] <Circuit Configuration> Figure 24A shows the circuit diagram of the pixel circuit 400. The pixel circuit 400 consists of transistor M1, It has a transistor M2, a capacitor C1, and a circuit 401. The pixel circuit 400 also has wiring S1, wiring S2, wiring G1, and wiring G2 are connected.

[0434] Transistor M1 has its gate connected to wiring G1, and one of its sources or drains connected to wiring S1. The other end is connected to one electrode of capacitance C1. Transistor M2 has a gate that is wired G2, one of the source and drain is connected to wiring S2, the other electrode is connected to capacitance C1, and rotation It connects to Route 401, respectively.

[0435] Circuit 401 is a circuit that includes at least one display element. Various elements can be used as the display element. While various types can be used, typically light-emitting elements such as organic EL elements and LED elements, and liquid crystal elements are used. Child, or MEMS (Micro Electro Mechanical System) ms) elements and the like can be applied.

[0436] The node connecting transistor M1 and capacitor C1 is node N1, and the node connecting transistor M2 and... Let node N2 be the node connecting to path 401.

[0437] The pixel circuit 400 maintains the potential of node N1 by turning off transistor M1. It can be maintained. Also, by turning off transistor M2, the power of node N2 can be controlled. It can maintain its position. Also, with transistor M2 in the OFF state, By writing a predetermined potential to node N1 via station M1, capacitive coupling via capacitor C1 is achieved. This allows the potential of node N2 to be changed in accordance with the potential displacement of node N1.

[0438] Here, in the embodiment, one or both of transistors M1 and M2 are The transistor using oxide semiconductors, as exemplified in 2, can be applied. Therefore, the extremely low off-current maintains the potential of nodes N1 and N2 for a long period of time. This is possible. However, if the period for which the potential of each node is maintained is short (specifically, the frame When the frequency is 30Hz or higher, a transistor using a semiconductor such as silicon is used. You may also use "ta".

[0439] <Example of driving method> Next, an example of how the pixel circuit 400 operates will be explained using Figure 24B. This is a timing chart related to the operation of the pixel circuit 400. For simplicity of explanation, this chart is presented here. Therefore, various resistors such as wiring resistance, parasitic capacitance of transistors and wiring, and transistors The effects of the threshold voltage of the staccato are not considered.

[0440] In the operation shown in Figure 24B, one frame period is divided into period T1 and period T2. Period T2 is the period during which the potential is written to node N2, and period N1 is the period during which the potential is written to node N1. That is the case.

[0441] [Period T1] During period T1, a potential is applied to both wire G1 and wire G2 that turns the transistor ON. Also, the wiring S1 has a fixed potential V ref It supplies the first day to wiring S2. Potential V w To supply.

[0442] Node N1 receives a potential V from wiring S1 via transistor M1. ref It is given. Furthermore, node N2 has a first data potential V via transistor M2. w It is given. Therefore, capacitance C1 has a potential difference V w -V ref This state is maintained.

[0443] [Period T2] Next, during period T2, a potential is applied to wiring G1 to turn on transistor M1, and The wire G2 is given a potential that turns off transistor M2. Also, the wiring S1 is supplied with the second diode DATA potential V data It supplies a predetermined constant potential to the wiring S2, or a floating It may also be in a ling state.

[0444] Node N1 has a second data potential V via transistor M1. data It is given. At this time, due to capacitive coupling by capacitance C1, the second data potential V data Node N The potential of point 2 changes by a potential dV. That is, in circuit 401, the first data potential Vw and the current The input will be the potential with the potential dV added. Note that in Figure 24B, the potential dV is a positive value. Although it is indicated as such, a negative value is also acceptable. That is, the second data potential V data but Potential V ref It can be lower.

[0445] Here, the potential dV is roughly determined by the capacitance value of capacitor C1 and the capacitance value of circuit 401. If the capacitance value of capacitor C1 is sufficiently larger than the capacitance value of circuit 401, the potential dV is the second dV. DATA potential V data The potential will be close to that.

[0446] Thus, the pixel circuit 400 combines two types of data signals to form a display element. Since it is possible to generate the potential supplied to path 401, grayscale correction can be performed within the pixel circuit 400. It becomes possible to do so.

[0447] The pixel circuit 400 is supplied by the source driver connected to wiring S1 and wiring S2. It also becomes possible to generate potentials exceeding high potentials. For example, when using a light-emitting element, It can display HDR (High Dynamic Range) and other features. In combination, overdrive operation and other similar features can be achieved.

[0448] <Examples of application> [Examples using liquid crystal elements] The pixel circuit 400LC shown in Figure 24C has circuit 401LC. Circuit 401LC is It has a liquid crystal element LC and a capacitance C2.

[0449] In a liquid crystal element (LC), one electrode is the electrode of node N2 and capacitance C2, and the other electrode is Potential V com2 Connect to the wiring provided. Capacitor C2 is connected when the other electrode is at potential V com1 Connect to the provided wiring.

[0450] Capacity C2 functions as the retention capacity. Note that capacity C2 can be omitted if it is not needed. Cut.

[0451] The pixel circuit 400LC can supply a high voltage to the liquid crystal element LC, for example High-speed display is achieved through overdrive operation, and high-voltage liquid crystal materials are applied. It is possible to do things like this. Also, by supplying a correction signal to wiring S1 or wiring S2, The gradation can also be corrected according to the operating temperature and the degradation state of the liquid crystal elements (LC).

[0452] [Examples using light-emitting elements] The pixel circuit 400EL shown in Figure 24D has circuit 401EL. Circuit 401EL is It has a light-emitting element EL, a transistor M3, and a capacitor C2.

[0453] Transistor M3 has a gate that connects to one electrode of node N2 and capacitance C2, and a source and a dot. One end of the wire is a wire to which a potential VH is applied, and the other end is one electrode of the light-emitting element EL, and They are connected. Capacitor C2 is connected when the other electrode is at potential V com Connect to the provided wiring. In the light-emitting element (EL), the other electrode is at potential V. L Connect to the provided wiring.

[0454] Transistor M3 has the function of controlling the current supplied to the light-emitting element EL. Capacitor C2 This functions as a holding capacity. Capacity C2 can be omitted if it is not needed.

[0455] Note that this configuration shows the anode side of the light-emitting element EL connected to transistor M3. However, transistor M3 may be connected to the cathode side. In that case, the potential V H and potential V L The value can be changed as needed.

[0456] The pixel circuit 400EL generates light by applying a high potential to the gate of transistor M3. Because it can supply a large current to the sub-EL, it can enable features such as HDR display. It can be done. Also, by supplying a correction signal to wiring S1 or wiring S2, transistor M3 and It can also compensate for variations in the electrical characteristics of light-emitting elements (ELs).

[0457] Note that the circuits are not limited to those illustrated in Figures 24C and 24D, and may also include transistors, capacitors, etc. A configuration with the addition of this element is also acceptable.

[0458] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0459] (Embodiment 6) In this embodiment, a display module that can be manufactured using one aspect of the present invention is provided. I will explain.

[0460] The display module 6000 shown in Figure 25A consists of an upper cover 6001 and a lower cover 6002 Between them are the display device 6006, frame 6009, and print, with the FPC6005 connected. It has a circuit board 6010 and a battery 6011.

[0461] For example, a display device manufactured using one aspect of the present invention may be used in the display device 6006. This is possible. The display device 6006 enables the realization of an extremely low-power display module. It is possible.

[0462] The upper cover 6001 and the lower cover 6002 are sized to fit the display device 6006. The shape and dimensions can be changed as needed.

[0463] The display device 6006 may also have the functionality of a touch panel.

[0464] Frame 6009 is determined by the protection function of the display device 6006 and the operation of the printed circuit board 6010. It may also have functions such as blocking electromagnetic waves generated, or functioning as a heat sink.

[0465] Printed circuit board 6010 is a power supply circuit and a signal for outputting video signals and clock signals. It includes a processing circuit, a battery control circuit, and the like.

[0466] Figure 25B is a schematic cross-sectional view of a display module 6000 equipped with an optical touch sensor. ru.

[0467] The display module 6000 includes a light-emitting section 6015 and a receiver provided on the printed circuit board 6010. It has a light-emitting section 6016. It is also surrounded by an upper cover 6001 and a lower cover 6002. The region has a pair of light guides (light guide 6017a, light guide 6017b).

[0468] The display device 6006 connects to the printed circuit board 6010 and the battery via the frame 6009. - It is installed overlapping with 6011. The display device 6006 and frame 6009 are connected to the light guide section 6 017a is fixed to the light guide section 6017b.

[0469] Light 6018 emitted from the light-emitting unit 6015 is directed by the light guide unit 6017a to the display device 600. It passes through the upper part of 6, through the light guide part 6017b, and reaches the light receiving part 6016. For example, a finger or a stand Touch operation is detected when light 6018 is blocked by an object to be detected, such as an illustration. It is possible.

[0470] Multiple light-emitting units 6015 are provided, for example, along two adjacent sides of the display device 6006. Multiple light-receiving units 6016 are provided at positions opposite to the light-emitting unit 6015. This allows for... Information about the location where the operation was performed can be obtained.

[0471] The light-emitting section 6015 can use a light source such as an LED element, and in particular, infrared light It is preferable to use a light source that emits light. The light receiving unit 6016 receives the light emitted by the light emitting unit 6015. A photoelectric element that converts light into an electrical signal can be used. Preferably, one that can receive infrared light. A photodiode can be used.

[0472] The light-emitting section 6015 and the light-emitting section 6015 are separated by the light-transmitting light-emitting section 6017a and light-transmitting section 6017b. The light receiving unit 6016 can be positioned below the display device 6006, and ambient light can be received by the light receiving unit 601 Reaching 6 can suppress the malfunction of the touch sensor. In particular, it absorbs visible light and infrared light. Using a resin that allows light to pass through can more effectively suppress malfunctions in touch sensors.

[0473] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0474] (Embodiment 7) This embodiment describes an example of an electronic device to which a display device according to one aspect of the present invention can be applied. I will reveal it.

[0475] The electronic device 6500 shown in Figure 26A is a portable device that can be used as a smartphone. It is a news terminal device.

[0476] The electronic device 6500 consists of a housing 6501, a display unit 6502, a power button 6503, and a button 6 It includes 504, speaker 6505, microphone 6506, camera 6507, and light source 6508, etc. The display unit 6502 is equipped with a touch panel function.

[0477] A display device according to one aspect of the present invention can be applied to the display unit 6502.

[0478] Figure 26B is a schematic cross-sectional view of the housing 6501, including the end on the microphone 6506 side.

[0479] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501, and the housing 650 Within the space surrounded by 1 and protective member 6510, display panel 6511, optical member 6512, The touch sensor panel 6513, printed circuit board 6517, battery 6518, etc. are arranged. Yes, they are.

[0480] The protective member 6510 includes a display panel 6511, an optical member 6512, and a touch sensor panel. Nel 6513 is fixed by an adhesive layer (not shown).

[0481] In the area outside the display unit 6502, a portion of the display panel 6511 is folded back. It is there. Also, the FPC6515 is connected to the folded portion. FPC651 IC6516 is mounted on board 5. FPC6515 is mounted on printed circuit board 6517. It is connected to a terminal provided there.

[0482] A flexible display panel according to one aspect of the present invention is applied to the display panel 6511. This makes it possible to create extremely lightweight electronic devices. Also, the display panel 651 Because it is extremely thin, it allows for a reduction in the thickness of electronic devices while incorporating a large-capacity 6518 battery. It is also possible to fold back a portion of the display panel 6511 and place an FPC on the back of the pixel area. By positioning the connection point with 6515, it is possible to realize electronic devices with narrow bezels.

[0483] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0484] (Embodiment 8) In this embodiment, an electronic device equipped with a display device manufactured using one aspect of the present invention is provided. I will explain.

[0485] The electronic device described below is equipped with a display device according to one embodiment of the present invention in its display unit. Therefore, it is an electronic device that achieves high resolution. Also, high resolution and a large screen It can be made into an electronic device that is compatible with both systems.

[0486] The display unit of an electronic device according to one aspect of the present invention may display, for example, Full HD, 4K2K, 8K4 It can display video with resolutions of K, 16K, 8K, or higher.

[0487] Examples of electronic devices include television equipment, notebook personal computers, and more. Features include relatively large screens such as those found on NITA devices, digital signage, pachinko machines, and game machines. In addition to electronic devices, digital cameras, digital video cameras, digital photo frames, and mobile phones Examples include telephones, portable game consoles, personal digital assistants, and audio playback devices.

[0488] An electronic device to which one aspect of the present invention is applied includes the interior or exterior walls of houses and buildings, the interior of automobiles, etc. It can be incorporated along the flat or curved surfaces of the fittings or exterior.

[0489] Figure 27A shows the external appearance of the camera 8000 with the viewfinder 8100 attached. That is the case.

[0490] The camera 8000 consists of a housing 8001, a display unit 8002, operation buttons 8003, and a shutter. It has buttons 8004, etc. The camera 8000 also has a detachable lens 8006. It is attached.

[0491] The camera 8000 may have the lens 8006 and the body integrated into a single unit.

[0492] Camera 8000 can be operated by pressing the shutter button 8004, or by using the touch panel function. Image capture can be performed by touching the display unit 8002.

[0493] The housing 8001 has a mount with electrodes, and in addition to the viewfinder 8100, it also has a strobe It can be connected to devices such as power supply units.

[0494] The viewfinder 8100 has a housing 8101, a display unit 8102, buttons 8103, etc. .

[0495] The housing 8101 engages with the mount of the camera 8000 via a mount, and the camera 800 It is attached to the 0. The viewfinder 8100 receives images and other data from the camera 8000. This can be displayed on the display unit 8102.

[0496] Button 8103 functions as a power button, etc.

[0497] The display unit 8002 of the camera 8000 and the display unit 8102 of the viewfinder 8100 are equipped with this A display device according to one embodiment of the invention can be applied. Note that a camera with a built-in viewfinder can also be used. It could also be 8000.

[0498] Figure 27B shows the external appearance of the head-mounted display 8200.

[0499] The head-mounted display 8200 consists of a mounting part 8201, lenses 8202, and a main body 82 03, it has a display unit 8204, a cable 8205, etc. Also, the mounting part 8201 has It has a built-in 8206 battery.

[0500] Cable 8205 supplies power from battery 8206 to main unit 8203. Unit 203 is equipped with a wireless receiver and can display the received video information on the display unit 8204. It can do that. Furthermore, the main unit 8203 is equipped with a camera that inputs information about the user's eyeball and eyelid movements. It can be used as a step.

[0501] The attachment part 8201 is located at a position that touches the user, and current flows in accordance with the user's eye movements. Multiple electrodes capable of detecting gaze may be provided, and the device may have a function to recognize gaze. The device may also have a function to monitor the user's pulse rate based on the current flowing through the electrode. The mounting section 8201 has various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor. It may also have a function to display the user's biometric information on the display unit 8204, and to detect the user's head movements. The display unit 8204 may also have a function to change the image displayed on it.

[0502] A display device according to one aspect of the present invention can be applied to the display unit 8204.

[0503] Figures 27C, 27D, and 27E show the appearance of the head-mounted display 8300. This is a diagram. The head-mounted display 8300 consists of a housing 8301 and a display unit 8302 It also includes a band-shaped fastener 8304 and a pair of lenses 8305.

[0504] The user can view the display on the display unit 8302 through the lens 8305. Furthermore, by arranging the display unit 8302 in a curved shape, the user can experience a high level of realism. This is preferable. Also, another image displayed in a different area of ​​the display unit 8302 is displayed by the lens 8 By viewing through the 305, it is also possible to perform 3D displays using parallax. The configuration is not limited to having one display unit 8302, but can also have two display units 8302, allowing one of the users to... One display unit may be placed for each eye.

[0505] Furthermore, a display device according to one embodiment of the present invention can be applied to the display unit 8302. A display device having a semiconductor device according to one embodiment has extremely high resolution, as shown in Figure 27E. Even when magnified using lens 8305, the user cannot see the individual pixels, resulting in a more detailed view. It can display highly realistic images.

[0506] The electronic equipment shown in Figures 28A to 28G consists of a housing 9000, a display unit 9001, and a speaker 9 003, Operation key 9005 (including power switch or operation switch), Connection terminal 900 6. Sensor 9007 (force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, Magnetism, temperature, chemicals, sound, time, hardness, electric field, electric current, voltage, power, radiation, flow rate, humidity (Including functions for measuring degrees, inclines, vibrations, odors, or infrared radiation), Microphone 900 8, etc.

[0507] The electronic devices shown in Figures 28A to 28G have various functions. For example, various information ( Functions to display still images, videos, text images, etc. on the display unit, touch panel function, calendar A function that displays the date or time, etc., through various software (programs) Functions that control processing, wireless communication functions, programs or data recorded on recording media It can have functions such as reading and processing data. Furthermore, the functions of electronic devices are related to these. It is not limited and can have a variety of functions. Even if an electronic device has multiple display units Good. Also, an electronic device can be equipped with a camera, etc., to take still images and videos, and the recording medium (external or It has features such as saving to the camera (built-in), and displaying the captured image on the display unit. That's good too.

[0508] Details of the electronic equipment shown in Figures 28A to 28G will be explained below.

[0509] Figure 28A is a perspective view showing the television equipment 9100. 0 is a display unit 9001 with a large screen, for example, 50 inches or larger, or 100 inches or larger. It is possible to insert it.

[0510] Figure 28B is a perspective view showing a personal digital assistant (PDA) 9101. For example, For example, it can be used as a smartphone. Note that the mobile information terminal 9101 is a speed A connector (9003), connection terminal (9006), sensor (9007), etc. may be provided. Also, a portable information terminal may be provided. The 9101 can display text and image information on its multiple surfaces. Figure 28B shows three of them. This shows an example of displaying icon 9050. Also, information 9051, indicated by a dashed rectangle, is shown. The information can also be displayed on other sides of the display unit 9001. An example of information 9051 is electronic mail. Notifications of incoming calls, SNS messages, and phone calls; subject, sender name, and date / time for emails and SNS messages. This includes the time, battery level, and antenna signal strength. Alternatively, information 9051 may be displayed. You may display icons such as icon 9050 in the designated location.

[0511] Figure 28C is a perspective view showing the personal digital assistant 9102. The personal digital assistant 9102 is a table The display unit 9001 has the function of displaying information on three or more sides. Here, information 9052, information This shows an example where information 9053 and information 9054 are displayed on different sides. For example, the user With the mobile information terminal 9102 stored in the breast pocket of his clothing, the mobile information terminal 9102 Information 9053, displayed in a position visible from above, can also be viewed. The user can, You can check the display without taking the 9102 personal digital assistant out of your pocket, for example, to answer a phone call. It is possible to determine whether or not to do so.

[0512] Figure 28D is a perspective view showing a wristwatch-type personal information terminal 9200. Personal information terminal 92 00 can be used, for example, as a smartwatch. Also, the display unit 9001 is The display surface is curved, allowing the display to follow the curved surface. The personal information terminal 9200 communicates with, for example, a wireless communication headset. It also allows for hands-free calling. Furthermore, the 9200 mobile information terminal has a connection terminal 9 006 allows for mutual data transmission with other information terminals and also enables charging. Charging may also be performed via wireless power supply.

[0513] Figures 28E, 28F, and 28G are perspective views showing the foldable portable information terminal 9201. This is a diagram. Figure 28E shows the mobile information terminal 9201 in its unfolded state, and Figure 28G shows it in its folded state. In this state, Figure 28F is a perspective view of the intermediate state in which one of Figures 28E and 28G changes to the other. Yes. The 9201 personal digital assistant offers excellent portability when folded and is convenient when unfolded. The seamless, wide display area provides excellent readability of the display. The indicator part 9001 is supported by three housings 9000 connected by hinges 9055. For example, the display unit 9001 can be bent with a radius of curvature of 1 mm or more and 150 mm or less. ru.

[0514] Figure 29A shows an example of a television system. The television system 7100 has a housing 710 The display unit 7500 is incorporated into 1. Here, the stand 7103 connects to the housing 710. This shows the configuration that supports option 1.

[0515] The television device 7100 shown in Figure 29A is operated by the operation switches provided on the housing 7101. This can be done by using the remote control unit 7111 or by using the display unit 7500. A touch panel can be applied to it, allowing the television device 7100 to be operated by touching it. The remote control unit 7111 may have a display unit in addition to the operation buttons.

[0516] The television equipment 7100 is a television broadcast receiver and for network connectivity. It may have a communication device.

[0517] Figure 29B shows the 7200 notebook personal computer. The Computer 7200 consists of a casing 7211, a keyboard 7212, and a pointing device 7 It has external connection ports 7214, etc. The display unit 7500 is incorporated into the housing 7211. It is being made.

[0518] Figures 29C and 29D show digital signage. An example of a small sign is shown.

[0519] The digital signage 7300 shown in Figure 29C consists of a housing 7301, a display unit 7500, and It has a speaker 7303, etc. Furthermore, it has an LED lamp, operation keys (power switch, or It may include an operating switch, connection terminals, various sensors, a microphone, etc. .

[0520] Figure 29(D) shows a digital signage 7400 mounted on a cylindrical column 7401. Yes. The digital signage 7400 has a display unit 75 that is installed along the curved surface of the column 7401. It contains 00.

[0521] The larger the display unit 7500, the more information can be provided at once, and the more human eyes... Because it is easily absorbed, it can, for example, enhance the effectiveness of advertising.

[0522] It is preferable to apply a touch panel to the display unit 7500 so that the user can operate it. This allows for use not only in advertising, but also in route information, traffic information, and commercial facility information. It can also be used to provide information that users are seeking.

[0523] As shown in Figures 29C and 29D, the digital signage 7300 or digital signage The Neige 7400 communicates wirelessly with the user's smartphone or other information terminal 7311. It is preferable that the information displayed on the display unit 7500 is linked. To display this on the screen of the information terminal 7311, or by operating the information terminal 7311 The display on the 7500 display unit can be switched.

[0524] Digital signage 7300 or digital signage 7400, information terminal 731 It is also possible to run a game using 1 as the control device (controller). A large number of users can participate in and enjoy the game simultaneously.

[0525] A display device according to one embodiment of the present invention is applied to the display unit 7500 in Figures 29A to 29D. It is possible.

[0526] Although the electronic device in this embodiment has a display unit, electronic devices that do not have a display unit can also be used. An embodiment of the present invention can also be applied.

[0527] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination. [Examples]

[0528] In this embodiment, a metal oxide film that can be used in a semiconductor device according to one aspect of the present invention is The composition was evaluated.

[0529] In this example, X-ray photoelectron spectroscopy (XPS) was performed on metal oxide films produced by different methods. Analysis was performed to evaluate the composition. For the evaluation, a 100 nm thick layer of metal oxide was placed on a glass substrate. Samples with a film formed on them (A1 to A5, samples B1 and B2) were used.

[0530] <Sample preparation> Samples A1 to A5 are metal oxide films with an In-Ga-Zn oxide target (In:Ga Formed by sputtering using Zn=5:1:3 (atomic ratio). Sample B1 And B2 is a metal oxide film that forms an In-Zn oxide target (In:Zn=2:3[number of atoms] It was formed by a sputtering method using [ratio]).

[0531] The film deposition conditions for the metal oxide films of Samples A1 to A5, and Samples B1 and B2 are as follows: This is shown in Table 1. In Table 1, the composition of the target is referred to as Target, and the composition of the metal oxide film is referred to as Tsub is the substrate temperature during film formation, O2 / (Ar+O2) is the oxygen flow rate ratio, and Pressur is the pressure. e. Power is written as "Power".

[0532] [Table 1]

[0533] For sample A1, the substrate temperature during metal oxide film deposition was set to room temperature (hereinafter also referred to as RT). A mixed gas of oxygen and argon was used as the film-forming gas, with an oxygen flow rate ratio of 10%. The film deposition pressure was set to 0.6 Pa, and the power supply was set to 2.5 kW.

[0534] For sample A2, the substrate temperature during metal oxide film deposition was set to room temperature (RT). The deposition gas was... A mixed gas of oxygen gas and argon gas was used, and the oxygen flow rate ratio was set to 50%. The pressure during film formation was set to 0.6 Pa, and the power supply power was set to 2.5 kW.

[0535] For Sample A3, the substrate temperature during the formation of the metal oxide film was set to room temperature (RT). As the film-forming gas oxygen gas (oxygen flow rate ratio: 100%) was used. The pressure during film formation was set to 0.6 Pa, and the power supply power was set to 2.5 kW.

[0536] For Sample A4, the substrate temperature during the formation of the metal oxide film was set to 130 °C. As the film-forming gas, oxygen gas and argon gas mixed gas was used, and the oxygen flow rate ratio was set to 10%. The pressure during film formation was 0 .6 Pa, and the power supply power was set to 2.5 kW.

[0537] For Sample A5, the substrate temperature during the formation of the metal oxide film was set to 130 °C. As the film-forming gas, oxygen gas (oxygen flow rate ratio: 100%) was used. The pressure during film formation was set to 0.6 Pa, and the power supply power was set to 2.5 kW.

[0538] For Sample B1, the substrate temperature during the formation of the metal oxide film was set to room temperature (RT). As the film-forming gas oxygen gas and argon gas mixed gas was used, and the oxygen flow rate ratio was set to 2%. The pressure during film formation was 0.6 Pa, and the power supply power was set to 2.5 kW.

[0539] For Sample B2, the substrate temperature during the formation of the metal oxide film was set to room temperature (RT). As the film-forming gas oxygen gas (oxygen flow rate ratio: 100%) was used. The pressure during film formation was set to 0.6 Pa, and the power supply power was set to 2.5 kW.

[0540] <X-ray Photoelectron Spectroscopy Analysis> Next, X-ray photoelectron spectroscopy (XPS) analysis of Samples A1 to A5, B1, and B2 was performed.

[0541] XPS analysis was performed using a monochromatic Mg Kα radiation source (λ=1253.6eV). The detection area was set to 8 mm square or less, and the extraction angle was set to 45°. The detection depth was approximately 4 nm to 5 nm. It's possible.

[0542] Indium (In) and gallium (G) of each sample obtained from XPS analysis a) The atomic ratios of zinc (Zn) and oxygen (O) are shown in Table 2. In Table 2, sample A1 Values ​​up to A5 represent values ​​normalized with an indium atomic ratio of 5.00. Sample B1 And B2 represents values ​​normalized with an atomic ratio of indium of 2.00.

[0543] [Table 2]

[0544] As shown in Table 2, the atomic ratio of the metal oxide film is smaller than the atomic ratio of the target for zinc. It was confirmed that this would decrease. In this example, the atomic ratio of zinc contained in the target was approximately 81 The ratio was between 94% and 100%. Gallium also showed a higher atomic ratio than the target metal oxide film. A tendency for the atomic ratio to decrease was observed. However, in the quantitative determination of gallium, waveform separation was required. Since the In4d peak has been removed, there is a possibility that the quantitative error is large. Therefore, the gallium ratios shown in Table 2 are lower than the actual gallium content. There is a possibility that this will happen.

[0545] The configuration shown in this embodiment may be used in appropriate combination with other embodiments and models. It is possible. [Examples]

[0546] In this embodiment, the crystallinity of the composition of the metal oxide film that can be used in the semiconductor device, which is one aspect of the present invention, was evaluated. The crystallinity of the composition was evaluated.

[0547] In this embodiment, X-ray diffraction (XRD) analysis was performed on metal oxide films with different manufacturing methods to evaluate their crystallinity. For the evaluation, samples (Samples C1 to C3, D1 to D3, E1 to E3) in which a metal oxide film with a thickness of 100 nm was formed on a glass substrate were used. The crystallinity of the composition was evaluated. For the evaluation, samples (Samples C1 to C3, D1 to D3, E1 to E3) in which a metal oxide film with a thickness of 100 nm was formed on a glass substrate were used. were used.

[0548] <Sample Preparation> Samples C1 to C3 were formed by a sputtering method using an In-Ga-Zn oxide target (In:Ga:Zn = 5:1:3 [atomic ratio]). Samples D1 to D3 were formed by a sputtering method using an In-Zn oxide target (In:Zn = 2:3 [atomic ratio]). Samples E1 to E3 were formed by a sputtering method using an In-Zn oxide target (In:Zn = 4:1 [atomic ratio]). Samples C1 to C3 were formed by a sputtering method using an In-Ga-Zn oxide target (In:Ga:Zn = 5:1:3 [atomic ratio]). Samples D1 to D3 were formed by a sputtering method using an In-Zn oxide target (In:Zn = 2:3 [atomic ratio]). Samples E1 to E3 were formed by a sputtering method using an In-Zn oxide target (In:Zn = 4:1 [atomic ratio]). Samples D1 to D3 were formed by a sputtering method using an In-Zn oxide target (In:Zn = 2:3 [atomic ratio]). Samples E1 to E3 were formed by a sputtering method using an In-Zn oxide target (In:Zn = 4:1 [atomic ratio]). Samples D1 to D3 were formed by a sputtering method using an In-Zn oxide target (In:Zn = 2:3 [atomic ratio]). Samples E1 to E3 were formed by a sputtering method using an In-Zn oxide target (In:Zn = 4:1 [atomic ratio]). Samples E1 to E3 were formed by a sputtering method using an In-Zn oxide target (In:Zn = 4:1 [atomic ratio]). Samples E1 to E3 were formed by a sputtering method using an In-Zn oxide target (In:Zn = 4:1 [atomic ratio]).

[0549] The film formation conditions of the metal oxide films of Samples C1 to C3, D1 to D3, and E1 to E3 are shown in Table 3. In Table 3, the composition of the target is denoted as Target, the substrate temperature during the film formation of the metal oxide film is denoted as Tsub, the oxygen flow ratio is denoted as O2 / (Ar + O2), the pressure is denoted as Pressure, and the power supply power is denoted as Power. The film formation conditions of the metal oxide films of Samples C1 to C3, D1 to D3, and E1 to E3 are shown in Table 3. In Table 3, the composition of the target is denoted as Target, the substrate temperature during the film formation of the metal oxide film is denoted as Tsub, the oxygen flow ratio is denoted as O2 / (Ar + O2), the pressure is denoted as Pressure, and the power supply power is denoted as Power. The film formation conditions of the metal oxide films of Samples C1 to C3, D1 to D3, and E1 to E3 are shown in Table 3. In Table 3, the composition of the target is denoted as Target, the substrate temperature during the film formation of the metal oxide film is denoted as Tsub, the oxygen flow ratio is denoted as O2 / (Ar + O2), the pressure is denoted as Pressure, and the power supply power is denoted as Power. The film formation conditions of the metal oxide films of Samples C1 to C3, D1 to D3, and E1 to E3 are shown in Table 3. In Table 3, the composition of the target is denoted as Target, the substrate temperature during the film formation of the metal oxide film is denoted as Tsub, the oxygen flow ratio is denoted as O2 / (Ar + O2), the pressure is denoted as Pressure, and the power supply power is denoted as Power.

[0550]

Table 3

[0551] <X-ray Diffraction Analysis> Next, X-ray diffraction (XRD) analysis was performed on Samples C1 to C3, D1 to D3, and E1 to E3. .

[0552] For XRD analysis, we used the θ-2θ scan method, a type of out-of-plane method. The θ-2θ scanning method involves changing the incident angle of the X-rays and also installing a device opposite the X-ray source. This method measures the X-ray diffraction intensity by setting the angle of the detector to be the same as the angle of incidence. θ-2θ The scanning method is sometimes called the powder method. XRD analysis uses Cu Kα rays as the X-ray source. Using (λ=0.15418nm), the scanning range is 2θ=15deg to 50deg, and The top width was set to 0.01 degrees, and the scanning speed to 6.0 degrees / minute.

[0553] The XRD analysis results are shown in Figure 30. In Figure 30, the horizontal axis shows the diffraction angle 2θ, and the vertical axis... The intensity of the diffracted X-rays is shown. Also, in Figure 30, 2θ is used as an auxiliary line. The value =31 degrees is shown with a dashed line.

[0554] As shown in Figure 30, a peak was observed around 2θ = 31deg in all samples, indicating crystallization. It was confirmed that it possesses this property. Furthermore, samples D1 to D3 showed high peak intensities. Therefore, the vertical axis scale in Figure 30 is different from that of the other samples. Note that 2θ = approximately 24 degrees. The broad peak is a peak caused by the glass substrate.

[0555] The configuration shown in this embodiment may be used in appropriate combination with other embodiments and models. It is possible. [Examples]

[0556] In this example, transistors (samples F, G, and H) were fabricated, and the drain current - gate current was measured. The pressure characteristics (ID-VG characteristics) were evaluated. Note that the transistor 100 shown in Figure 8 and Figure 9 Transistors corresponding to each of the transistors 100A shown were fabricated. In this example, samples (F, G, and H) with different configurations of the semiconductor layer 108 were prepared.

[0557] <Sample preparation>

[0558] First, a tungsten film with a thickness of approximately 100 nm is applied to a glass substrate by sputtering. It was formed and processed to obtain the first gate electrode. Subsequently, a thick first gate insulating layer was formed. A first silicon nitride film with a thickness of approximately 240 nm and a second silicon nitride film with a thickness of approximately 60 nm, A silicon oxide-nitride film with a thickness of approximately 3 nm was formed by layering using plasma CVD.

[0559] The deposition of the first silicon nitride film is carried out by controlling the flow rates of silane gas, nitrogen gas, and ammonia gas. The pressures were set to 290 sccm, 2000 sccm, and 2000 sccm respectively, and the pressure was set to 200 Pa. The film power was set to 3000W and the substrate temperature to 350°C.

[0560] The deposition of the second silicon nitride film is carried out by controlling the flow rates of silane gas, nitrogen gas, and ammonia gas. The pressures were set to 200 sccm, 2000 sccm, and 100 sccm respectively, and the pressure was 100 Pa for film deposition. The power was set to 2000W and the board temperature to 350°C.

[0561] The silicon oxidizride film is deposited by flowing silane gas and nitrous oxide gas at flow rates of 20 s. Set to ccm, 3000 sccm, pressure to 40 Pa, deposition power to 3000 W, substrate temperature to 3 The temperature was set to 50℃.

[0562] Next, a first metal oxide film with a thickness of 30 nm is deposited on the first gate insulating layer, A semiconductor layer was obtained by processing this. Here, three different conditions were used to form the first metal oxide film. Samples (F, G, and H) were prepared. Sample F was prepared by coating the first metal oxide film with In-Ga-Zn acid. Sputtering using a chromium target (In:Ga:Zn=5:1:3 [atomic ratio]) It was formed by the method. Sample G had a first metal oxide film formed on an In-Zn oxide target (In It was formed by sputtering using Zn=2:3 (atomic ratio). Sample H was the first A metal oxide film of 1 is used on an In-Zn oxide target (In:Zn=4:1 [atomic ratio]) It was formed using the sputtering method employed.

[0563] Table 4 shows the film deposition conditions for the first metal oxide films of Samples F, G, and H. In Table 4, the composition of the target is referred to as Target, and the composition of the first metal oxide film is referred to as Target. Substrate temperature is Tsub, oxygen flow rate ratio is O2 / (Ar+O2), pressure is Pressure, electricity The power source is written as "Power".

[0564] [Table 4]

[0565] After the semiconductor layer is formed, it is heated in a nitrogen gas atmosphere at 350°C for 1 hour, and then nitrogen The sample was heated at 350°C for 1 hour in a mixed atmosphere of nitrogen gas and oxygen gas. The mixed atmosphere of gas and oxygen gas was set to nitrogen gas:oxygen gas = 4:1 (by volume).

[0566] Next, as the second gate insulating layer, a first silicon oxide nitride film with a thickness of approximately 5 nm, thickness A second silicon oxide nitride film with a thickness of approximately 140 nm, and a third silicon oxide nitride film with a thickness of approximately 5 nm. The films were deposited using plasma CVD.

[0567] The deposition of the first silicon oxidizride film is performed by controlling the flow rates of silane gas and nitrous oxide gas, respectively. The film deposition rate was set to 24 sccm and 18000 sccm, with a pressure of 200 Pa and a deposition power of 130 W, and the substrate was set to 18000 sccm. The temperature was set to 350°C.

[0568] The deposition of the second silicon oxidnitride film was performed by controlling the flow rates of silane gas and nitrous oxide gas, respectively. The film deposition rate was set to 200 sccm and 4000 sccm, the pressure to 300 Pa, and the deposition power to 750 W, on a substrate. The temperature was set to 350°C.

[0569] The deposition of the third silicon oxidizride film involves controlling the flow rates of silane gas and nitrous oxide gas, respectively. The film deposition rates were set to 20 sccm and 3000 sccm, with a pressure of 40 Pa, a deposition power of 500 W, and a substrate temperature of 20 sccm and 3000 sccm. The temperature was set to 350°C.

[0570] Next, a second metal layer with a thickness of 20 nm is applied to the second gate insulating layer by sputtering. An oxide film was deposited. The second metal oxide film was deposited on an In-Ga-Zn oxide target. The process was carried out using a sputtering method with (In:Ga:Zn=4:2:4.1 [atomic ratio]). The substrate temperature during film deposition was set to 100°C. Oxygen gas was used as the deposition gas (oxygen flow rate ratio 100%). The %) value was used. Furthermore, the power supply was set to 2.5 kW and the pressure to 0.6 Pa.

[0571] Subsequently, the material was heat-treated at 350°C for 1 hour in a nitrogen-containing atmosphere.

[0572] Next, a molybdenum film with a thickness of approximately 100 nm is applied as a conductive film on the second metal oxide film. The film was deposited using the puttering method.

[0573] Next, a resist pattern was formed on the conductive film.

[0574] Subsequently, using the resist pattern as a mask, the conductive film was etched to obtain a conductive layer. For the etching, the dry etching method was used, and SF6 gas was used as the etching gas.

[0575] Subsequently, the second metal oxide film was etched to obtain a metal oxide layer. For the etching, the wet etching method was used.

[0576] Subsequently, using the conductive layer as a mask, an impurity element addition process was performed. Boron was used as the impurity element, and for the addition process, a plasma ion doping apparatus was used. B2H6 gas was used as the gas for supplying boron.

[0577] Subsequently, a silicon oxynitride film with a thickness of approximately 300 nm was formed by plasma CVD as a protective insulating layer covering the transistor.

[0578] For the film formation of the protective insulating layer, the flow rates of silane gas and nitrogen gas were set to 290 sccm and 400 sccm, respectively, the pressure was set to 133 Pa, the film formation power was set to 1000 W, and the substrate temperature was set to 350°C.

[0579] Subsequently, an opening was made by etching a part of the protective insulating layer and the second gate insulating layer, and after forming a molybdenum film by sputtering, it was processed to obtain source electrodes and drain electrodes. Then, an acrylic film with a thickness of approximately 1.5 μm was formed as a planarization layer, and heat treatment was performed under the conditions of a nitrogen atmosphere, a temperature of 250°C, and 1 hour.

[0580] Through the above processes, samples F, G, and H each having a transistor formed on a glass substrate were obtained.

[0581] <ID-VG Characteristic Evaluation> Next, the ID-VG characteristics of the transistors fabricated as described above were measured.

[0582] The ID-VG characteristic of a transistor is measured by the voltage applied to the gate electrode (hereinafter referred to as gate voltage). The voltage (also called VG) was applied in steps of 0.25V from -15V to +20V. Also, the voltage applied to the source electrode (hereinafter also called the source voltage (VS)) is set to 0V (com Let m) be the voltage applied to the drain electrode (hereinafter also called drain voltage (VD)), and set to 0 The voltages were set to 0.1V and 10V.

[0583] The ID-VG characteristics of samples F, G, and H are shown in Figure 31. In Figure 31, the horizontal direction of the sample (S The conditions for the ampere and semiconductor layer 108 are shown. The transistor structure differs in the vertical direction. The ID-VG characteristics under the specified conditions are shown, with the upper row corresponding to transistor 100 shown in Figure 8. Regarding the transistor shown in the lower section, the transistor corresponding to transistor 100A shown in Figure 9 is... It also shows that the transistor has a channel length of 50 μm and a channel width of 50 μm. This shows the inverter. In the ID-VG characteristic in Figure 31, the horizontal axis is the gate voltage (V). G) is shown, with the drain current (ID) on the left vertical axis and the field effect mobility ( The μFE value is shown. Note that the ID-VG characteristics of one transistor were measured for each sample. Ta.

[0584] The field-effect mobility (μFE) of samples F, G, and H is shown in Figure 32. In Figure 32, horizontal The axis shows the conditions for the sample and semiconductor layer 108, and the vertical axis shows the field-effect mobility (μFE). Also, in Figure 32, the transistor 100 shown in Figure 8 is a Single, and the transistor shown in Figure 9 is a Trans 100. The ZISTA 100A is labeled as S-channel. The field-effect mobility (μFE) is... A transistor with a channel length of 50 μm and a channel width of 50 μm, where VG = 10 This shows the maximum value obtained using V.

[0585] As shown in Figures 31 and 32, it was confirmed that all samples exhibited good electrical characteristics. Furthermore, it was confirmed that the higher the indium content, the higher the field-effect mobility (μFE). came.

[0586] The configuration shown in this embodiment may be used in appropriate combination with other embodiments and models. It is possible. [Examples]

[0587] In this example, a transistor corresponding to transistor 100C_a shown in Figure 12D is created. The device was manufactured, and its drain current-gate voltage characteristics (ID-VG characteristics) and reliability were evaluated. In this example, samples (J and K) with different configurations of the semiconductor layer 108 were fabricated. Furthermore, gate insulation was also considered. The insulating layer 110, which functions as a layer, has a single-layer structure.

[0588] <Sample Preparation 1> The preparation methods for samples J and K will be explained.

[0589] First, a 30nm thick titanium film and a 100nm thick copper film are placed on a glass substrate in that order. The first gate electrode (bottom gate) is obtained by forming it using the sputtering method and then processing it. Ta.

[0590] Next, as the first gate insulating layer, a first silicon nitride film with a thickness of 50 nm and a thickness of 15 A second silicon nitride film with a thickness of 0 nm, a third silicon nitride film with a thickness of 100 nm, and a film with a thickness of 3 nm The first silicon oxidizride film of m was deposited in this order.

[0591] The first silicon nitride film and the third silicon nitride film were each subjected to a flow rate of 200 sccm. Lan gas, nitrogen gas at a flow rate of 2000 sccm and ammonia gas at a flow rate of 100 sccm The film was deposited using the PECVD method with a mixed gas. The deposition pressure was 100 Pa, and the deposition power was... The power supply was set to 2000W and the substrate temperature to 350°C.

[0592] The second silicon nitride film was subjected to silane gas at a flow rate of 290 sccm and a flow rate of 2000 sccm. In the PECVD method using a mixed gas of nitrogen gas and ammonia gas at a flow rate of 2000 sccm... The film was deposited using the following settings: film deposition pressure of 200 Pa, deposition power of 3000 W, and substrate temperature of 350°C. That's what I decided.

[0593] The first silicon oxidizride film was subjected to silane gas at a flow rate of 20 sccm and a flow rate of 3000 sccm. The film was deposited by PECVD using a mixed gas of nitrous oxide at a pressure of cm. The pressure was set to 40 Pa, the deposition power to 3000 W, and the substrate temperature to 350°C.

[0594] Next, a first metal oxide film was deposited on the first silicon oxidoxide film. Two samples (samples J and K) were prepared using different film deposition conditions for the metal oxide film 1. K represents one aspect of the present invention, and sample J is a comparative example.

[0595] The first metal oxide film of sample J is an In-Ga-Zn oxide target (In:Ga:Z The film was deposited by sputtering using n=1:1:1 (atomic ratio). Pressure during film deposition The pressure was set to 0.6 Pa, the power supply to 2.5 kW, and the substrate temperature to room temperature. Oxygen gas was used as the deposition gas. A mixed gas of argon and argon was used, with an oxygen flow rate ratio of 30%. The first metal oxide film The thickness was set to 25 nm.

[0596] The first metal oxide film of sample K consists of the first oxide film and the second oxide on the first oxide film. A layered film structure was adopted. The first oxide film was an In-Ga-Zn oxide target (In:G The film was deposited by sputtering using a:Zn=1:1:1 (atomic ratio). The pressure was set to 0.6 Pa, the power supply to 2.5 kW, and the substrate temperature to room temperature. A mixture of oxygen and argon gas was used, with an oxygen flow rate ratio of 30%. Second oxide The film is made using a spalling method with an In-Zn oxide target (In:Zn=4:1 [atomic ratio]). The film was deposited using the taring method. The deposition pressure was 0.6 Pa, the power supply was 3.0 kW, and the substrate was... The temperature was set to room temperature. A mixed gas of oxygen and argon was used as the film-forming gas, and oxygen flow The quantity ratio was set to 5%. The thickness of the first oxide film was 20 nm, and the thickness of the second oxide film was 5 nm. did.

[0597] Next, the first metal oxide film was processed into an island-like structure to form the first metal oxide layer.

[0598] Next, the mixture was heated at 370°C for 1 hour under a nitrogen atmosphere, followed by mixing of nitrogen and oxygen. Heat treatment at 370°C for 1 hour under a gas atmosphere (nitrogen gas flow rate:oxygen gas flow rate = 4:1). The process was carried out using an oven.

[0599] Next, a second silicon oxide-nitride film with a thickness of 140 nm is deposited as the second gate insulating layer. The second silicon oxidnitride film undergoes nitrogen oxide (NO) formation when heat is applied. X , Deposition conditions were used that resulted in high emission of X (where X is greater than 0 and less than or equal to 2). Second silicon oxidnitride film This involves silane gas at a flow rate of 200 sccm and nitrous oxide gas at a flow rate of 8000 sccm. The film was deposited using the PECVD method with a mixed gas. The deposition pressure was 250 Pa, and the deposition power was... The power supply was set to 2000W and the substrate temperature to 240°C.

[0600] Furthermore, the second silicon oxide-nitride film in contact with the first metal oxide layer will change when heat is applied. It is preferable to minimize the release of nitrogen oxides. Nitrogen oxides include, for example, NO2 or NO2. These include the nitrogen oxides contained in the second silicon oxidnitride film, A level is formed in the film, etc. This level is located within the energy gap of the first metal oxide layer. Therefore, nitrogen oxides are located between the second silicon oxidnitride film and the first metal oxide layer. When it diffuses into the interface, the energy level traps electrons on the second silicon oxidizride film side. In some cases, the trapped electrons can be trapped between the second silicon oxide nitride film and the first metal. Because it remains near the interface of the oxide layer, the transistor's threshold voltage fluctuates in the positive direction. Put it away.

[0601] In this example, an insulating film that releases a large amount of nitrogen oxides is used for the second silicon oxidnitride film, Under conditions with a high concentration of metal oxides, the effect of the composition of the first metal oxide layer on the characteristics of the transistor is as follows: I confirmed it.

[0602] To evaluate the second silicon oxidizride film itself, a different sample (sample L) was used, separate from samples J and K. A sample was prepared. Details of sample L will be described later.

[0603] Next, the samples were heat-treated at 370°C for 1 hour under a nitrogen atmosphere. The heat treatment was performed using an oven. A device was used.

[0604] Next, a second metal oxide film with a thickness of 20 nm is deposited on the second silicon oxidizride film. The second metal oxide film is an In-Zn oxide target (In:Zn=2:3 [number of atoms]). The film was deposited by sputtering using [ratio]. The pressure during film deposition was 0.3 Pa, and the power supply was [power supply]. The power was set to 4.5 kW and the substrate temperature to room temperature. Oxygen gas was used as the film deposition gas (oxygen flow rate ratio 100%). ) was used.

[0605] Next, under a mixed gas atmosphere of nitrogen and oxygen (nitrogen gas flow rate:oxygen gas flow rate = 4:1) The samples were then heat-treated at 370°C for 1 hour. An oven was used for the heat treatment.

[0606] Next, a 100 nm thick copper film and a 30 nm thick third gold film are placed on the second metal oxide film. The copper film and the third metal oxide film were deposited in this order. The copper film and the third metal oxide film were deposited by sputtering. The copper film was deposited using a sputtering method with a Cu target. The third metal oxide film is deposited using an In-Zn oxide target (In:Zn=2:3[atom] The film was deposited by sputtering using a numerical ratio. The pressure during film deposition was 0.6 Pa, and the power supply was also used. The power was set to 2.5 kW and the substrate temperature to room temperature. Oxygen gas and argon gas were used as the film deposition gas. A mixed gas was used, with an oxygen flow rate ratio of 30%.

[0607] Next, a resist mask is formed on the third metal oxide film, followed by the second metal oxide film and the copper film. The second metal oxide layer, the copper layer, and the third metal oxide layer are processed to form the second metal oxide layer, the copper layer, and the third metal oxide layer. The material was formed using a wet etching method.

[0608] Next, washing was performed. For washing, 85% by weight phosphoric acid was diluted 500 times. An aqueous solution was used. The etching temperature was room temperature, and the processing time was 15 seconds. Ta.

[0609] Next, using the aforementioned resist mask as a mask, the second silicon oxide nitride film is etched. Then, a second gate insulating layer was formed. Also, when forming the second gate insulating layer, the resin Remove the first silicon oxide-nitride film in the region that does not overlap with the stock mask, and then remove the third silicon nitride film. A portion of the film was exposed. Dry etching was used for the process. After this, a resist mask was applied. It was removed.

[0610] Next, as a protective layer covering the transistor, a fourth silicon nitride film with a thickness of 100 nm and Then, a third silicon oxidizride film with a thickness of 300 nm was deposited in this order.

[0611] The fourth silicon nitride film was subjected to silane gas at a flow rate of 150 sccm and a flow rate of 5000 sccm. By the PECVD method using a mixed gas of nitrogen gas and ammonia gas at a flow rate of 100 sccm The film was deposited using a pressure of 200 Pa, a deposition power of 2000 W, and a substrate temperature of 350°C. did.

[0612] The third silicon oxidizride film was subjected to silane gas at a flow rate of 290 sccm and a flow rate of 4000 s. The film was deposited by PECVD using a mixed gas of ccm nitrous oxide. The pressure during film deposition was... The force was set to 133 Pa, the deposition power to 1000 W, and the substrate temperature to 350°C.

[0613] Next, a portion of the protective layer covering the transistor is opened, and a 100nm thick molybdenum film is inserted. After forming a film by sputtering, the source electrode and drain electrode were obtained by processing the film. Subsequently, an acrylic resin film with a thickness of approximately 1.5 μm is formed as a planarization layer, and under a nitrogen atmosphere, Heat treatment was carried out under the conditions of a temperature of 250 °C for 1 hour.

[0614] Through the above steps, sample J and K having transistors formed on a glass substrate were obtained.

[0615] <Fabrication of Samples 2> The method for fabricating sample L will be described.

[0616] A silicon oxynitride film with a thickness of 100 nm was formed on the glass substrate. Note that the silicon oxynitride film used the same film formation conditions as the second silicon oxynitride film used as the second gate insulating layer of samples J and K.

[0617] <TDS Analysis> Subsequently, the desorbed gas from sample L was evaluated using thermal desorption spectrometry (TDS). In the TDS analysis, the substrate temperature was raised from about 50 °C to about 520 °C at a heating rate of 30 °C / min.

[0618] The TDS analysis results of sample L are shown in Fig. 33. In Fig. 33, the TDS analysis results for a mass-to-charge ratio of 30 (M / z = 30) are shown on the left side, and the TDS analysis results for a mass-to-charge ratio of 32 (M / z = 32) are shown on the right side. The gas with a mass-to-charge ratio of 30 (M / z = 30) is mainly nitric oxide molecules. The gas with a mass-to-charge ratio of 32 (M / z = 32) is mainly oxygen molecules. Also, in Fig. 33, the horizontal axis represents the substrate temperature (Tsub), and the vertical axis represents the detection intensity (Intensity) for a mass-to-charge ratio of 30 (M / z = 30) or the detection intensity (Intensity) for a mass-to-charge ratio of 32 (M / z = 32).

[0619] As shown in FIG. 33, it was found that the sample L releases oxygen and nitrogen oxides when heated. Therefore, the second silicon oxynitride film used as the second gate insulating layer of the transistors (samples J and K) is considered to release oxygen and also release nitrogen oxides when heated.

[0620] <ID-VG Characteristic Evaluation> Subsequently, the ID-VG characteristics of the transistors (samples J and K) were measured.

[0621] The measurement of the ID-VG characteristics of the transistor was performed by applying the voltage applied to the gate electrode (hereinafter also referred to as the gate voltage (VG)) in steps of 0.25 V from -15 V to +20 V. Also, the voltage applied to the source electrode (VS) was set to 0 V (comm), and the voltages applied to the drain electrode (VD) were set to 0.1 V and 5.1 V.

[0622] The ID-VG characteristics of sample J are shown in FIG. 34. The ID-VG characteristics of sample K are shown in FIG. 35. FIGS. 34 and 35 show the conditions of the sample and the semiconductor layer 108. Also, in FIGS. 34 and 35, the conditions where the channel length and channel width of the transistor are different in the vertical direction are shown, and three types of transistors with a channel length of 2 μm and a channel width of 3 μm, a channel length of 3 μm and a channel width of 3 μm, and a channel length of 6 μm and a channel width of 3 μm are shown. On the horizontal axis, the gate voltage (VG) is shown, on the left vertical axis, the drain current (ID) is shown, and on the right vertical axis, the saturation mobility (μFE) at VG = 15 V is shown. In each sample, the ID-VG characteristics of 20 transistors were measured.

[0623] ​​​​​​​​​ Figures 34 and 35 show the threshold voltage (Vth) for each transistor size, respectively. The mean (ave) and 3σ of the saturation mobility (μFE) are shown. σ represents the standard deviation. Furthermore, Figures 34 and 35 show the difference between the design channel length and the effective channel length (2 △L) is also shown. For the effective channel length, TLM (Transmission This was determined by line model analysis.

[0624] <Reliability Evaluation> Next, the reliability of the transistors (samples J and K) was evaluated. In this example, The gate is given a positive potential relative to the drain potential and the gate potential, and the system is maintained at a high temperature. PBTS (Positive Bias Temperature Stress) Test They did that.

[0625] PBTS testing involves maintaining a substrate on which transistors are formed at 60°C, and then testing the transistors. A voltage of 0.1V was applied to the drain and 20V to the gate, and this state was maintained for 1 hour. The experiment was conducted in a dark environment. The PBTS test used a channel length of 2 μm and a channel width of 3 μm. Using the transistor, the amount of change in threshold voltage before and after the gate bias stress test ( ΔVth) was evaluated.

[0626] Figure 36 shows the threshold voltage fluctuation (ΔVth) for samples J and K. In Figure 36, The horizontal axis shows the conditions for the sample and semiconductor layer 108, and the vertical axis shows the change in threshold voltage in the PBTS test. This shows the momentum (ΔVth).

[0627] As shown in Figure 34, compared to sample J, which is a comparative example, sample K, which is one embodiment of the present invention, High field-effect mobility (μFE) was confirmed. Sample K was subjected to the channel-forming region. By using a metal oxide film having the composition shown in Form 1, a high field effect mobility (μFE) was achieved. This is thought to indicate that...

[0628] As shown in Figure 36, compared to sample J, sample K showed a change in threshold voltage in the PBTS test. We were able to confirm that the motion (△Vth) was small.

[0629] In samples J and K, an insulating film with high nitrogen oxide emission was used for the second silicon oxidizrind film. Therefore, the transistor's threshold voltage fluctuates in the positive direction due to the energy levels caused by nitrogen oxides. The conditions are favorable. However, sample K, which is one embodiment of the present invention, undergoes a second oxidation. A second oxide layer in contact with the silicon nitride film is provided, having the composition shown in Embodiment 1. By using a film, the trapping of electrons in energy levels caused by nitrogen oxides is suppressed. It is thought that the threshold voltage fluctuation in the PBTS test has decreased.

[0630] As described above, sample K, which is one embodiment of the present invention, achieves both high electrical characteristics and high reliability. It was confirmed to be a transistor.

[0631] The configuration shown in this embodiment may be used in appropriate combination with other embodiments and models. It is possible. [Examples]

[0632] In this example, a transistor corresponding to transistor 100C_a shown in Figure 12D is created. The device was manufactured, and its drain current-gate voltage characteristics (ID-VG characteristics) and reliability were evaluated. In this example, samples with different configurations of the semiconductor layer 108 (samples L, M1 to M4) were prepared. The insulating layer 110, which functions as a gate insulating layer, has a single-layer structure.

[0633] In this embodiment, the conductive layer 106 (bottom gate electrode) is the conductive layer 112 (top gate electrode). A transistor electrically connected to the electrode, the conductive layer 106 (bottom gate electrode) is the conductive layer A transistor electrically connected to 120a or conductive layer 120b (source electrode), and a conductive Three types of transistors were fabricated that do not have an electrode layer 106 (bottom gate electrode).

[0634] <Sample preparation> The preparation methods for samples L, M1 to M4 will be explained.

[0635] First, a 100 nm thick tungsten film is formed on a glass substrate using the sputtering method. This was then processed to obtain the first gate electrode (bottom gate).

[0636] Next, as the first gate insulating layer, a first silicon nitride film with a thickness of 50 nm and a thickness of 15 A second silicon nitride film with a thickness of 0 nm, a third silicon nitride film with a thickness of 100 nm, and a film with a thickness of 3 nm The first silicon oxidizride film of m was deposited in this order. For details on the formation of the silicon oxide film and the first silicon oxide nitride film, please refer to the description in Example 4. Since it is possible, a detailed explanation will be omitted.

[0637] Next, a first metal oxide film was deposited on the first silicon oxidoxide film. Five samples (samples L, M1 to M4) were prepared, each with a different metal oxide film composition. Samples M1 to M4 represent one embodiment of the present invention, and sample L is a comparative example.

[0638] The first metal oxide film of sample L is an In-Ga-Zn oxide target (In:Ga:Z The film was deposited by sputtering using n=1:1:1 (atomic ratio). The pressure during film deposition was The force was set to 0.6 Pa, the power supply to 2.5 kW, and the substrate temperature to room temperature. Oxygen gas was used as the film deposition gas. A mixed gas of sulfur and argon gas was used, with an oxygen flow rate ratio of 30%. First metal oxide film The thickness was set to 25 nm.

[0639] The first metal oxide films of samples M1 to M4 each consist of a first oxide film and a first oxide A layered structure was formed by adding a second oxide film on top of the first film. The first oxide film was deposited using In-Ga-Zn acid. Sputtering using a chromium target (In:Ga:Zn=1:1:1 [atomic ratio]) The film was deposited according to the specified method. The deposition pressure was 0.6 Pa, the power supply was 2.5 kW, and the substrate temperature was controlled to room temperature. The temperature was set to 3.5°C. A mixed gas of oxygen and argon was used as the film-forming gas, with an oxygen flow rate ratio of 3. It was set to 0%. The second oxide film is an In-Zn oxide target (In:Zn=4:1 [original The film was deposited by sputtering using a specific particle ratio. The deposition pressure was 0.6 Pa, and the electrical current was used. The power source was set to 3.0 kW, and the substrate temperature was set to room temperature. Oxygen gas and argon gas were used as the film deposition gases. A mixed gas was used, with an oxygen flow rate ratio of 5%.

[0640] Sample M1 had a first oxide film with a thickness of 22 nm and a second oxide film with a thickness of 3 nm. Sample M2 had a first oxide film thickness of 20 nm and a second oxide film thickness of 5 nm. In sample M3, the thickness of the first oxide film was 15 nm, and the thickness of the second oxide film was 10 nm. Material M4 had a first oxide film thickness of 10 nm and a second oxide film thickness of 15 nm.

[0641] Next, the first metal oxide film was processed into an island-like structure to form the first metal oxide layer.

[0642] Next, under a dry air (CDA: Clean Dry Air) atmosphere, at 370°C for 2 hours. A heat treatment was performed in between. An oven was used for the heat treatment.

[0643] Next, a second silicon oxide-nitride film with a thickness of 140 nm is deposited as the second gate insulating layer. The second silicon oxidnitride film undergoes nitrogen oxide (NO) formation when heat is applied. X , Deposition conditions were used that resulted in high emission of X (where X is greater than 0 and less than or equal to 2). Second silicon oxidnitride film Regarding the film formation, please refer to the description in Example 4; therefore, a detailed explanation will be omitted.

[0644] In this example, an insulating film that releases a large amount of nitrogen oxides is used for the second silicon oxidnitride film, Under conditions with a high concentration of metal oxides, the influence of the composition of the first metal oxide layer on the characteristics of the transistor is... I confirmed it.

[0645] Next, the samples were heat-treated at 370°C for 1 hour under a nitrogen atmosphere. The heat treatment was performed using an oven. A device was used.

[0646] Next, a second metal oxide film with a thickness of 20 nm is deposited on the second silicon oxidizride film. For details on the formation of the second metal oxide film, please refer to the description in Example 4. The "Akira" part will be omitted.

[0647] Next, under a mixed gas atmosphere of nitrogen and oxygen (nitrogen gas flow rate:oxygen gas flow rate = 4:1) The samples were then heat-treated at 370°C for 1 hour. An oven was used for the heat treatment.

[0648] Next, a 100 nm thick copper film and a 30 nm thick third gold film are placed on the second metal oxide film. The copper film and the third metal oxide film were deposited in this order. The copper film and the third metal oxide film were deposited by sputtering. Further film formation was performed. For details on the formation of the copper film and the third metal oxide film, please refer to Example 4. Since this can be found elsewhere, a detailed explanation will be omitted.

[0649] Next, a resist mask is formed on the third metal oxide film, followed by the second metal oxide film and the copper film. The second metal oxide layer, the copper layer, and the third metal oxide layer are processed to form the second metal oxide layer, the copper layer, and the third metal oxide layer. The material was formed using a wet etching method.

[0650] Next, using the aforementioned resist mask as a mask, the second silicon oxide nitride film is etched. Then, a second gate insulating layer was formed. Also, when forming the second gate insulating layer, the resin Remove the first silicon oxide-nitride film in the region that does not overlap with the stock mask, and then remove the third silicon nitride film. A portion of the film was exposed. Dry etching was used for the process. After this, a resist mask was applied. It was removed.

[0651] Next, washing was performed. For washing, 85% by weight phosphoric acid was diluted 500 times. An aqueous solution was used. The etching temperature was room temperature, and the processing time was 15 seconds. Ta.

[0652] Next, as a protective layer covering the transistor, a fourth silicon nitride film with a thickness of 20 nm is used, A fifth silicon nitride film with a thickness of 80 nm and a third silicon oxide nitride film with a thickness of 300 nm The films were deposited in this order.

[0653] The fourth silicon nitride film was subjected to silane gas at a flow rate of 150 sccm and a flow rate of 5000 sccc. The film was deposited using the PECVD method with a nitrogen gas mixture of m. The deposition pressure was 200p. a. The film deposition power was set to 2000W and the substrate temperature to 350°C.

[0654] The fifth silicon nitride film was formed by PECVD using a mixed gas of silane gas with a flow rate of 150 sccm, nitrogen gas with a flow rate of 5000 sccm, and ammonia gas with a flow rate of 100 sccm. The pressure during film formation was 200 Pa, the film formation power was 2000 W, and the substrate temperature was 350 °C.

[0655] The third silicon oxynitride film was formed by PECVD using a mixed gas of silane gas with a flow rate of 290 sccm and dinitrogen monoxide gas with a flow rate of 4000 sccm. The pressure during film formation was 133 Pa, the film formation power was 1000 W, and the substrate temperature was 350 °C.

[0656] Subsequently, a part of the protective layer covering the transistor was opened, and a molybdenum film with a thickness of 100 nm was formed by sputtering. After that, it was processed to obtain source electrodes and drain electrodes. Thereafter, an acrylic resin film with a thickness of about 1.5 μm was formed as a planarization layer, and heat treatment was performed under a nitrogen atmosphere at a temperature of 250 °C for 1 hour.

[0657] Through the above processes, samples L, M1 to M4 having transistors formed on glass substrates were obtained.

[0658] <ID-VG Characteristic Evaluation> Subsequently, the ID-VG characteristics of the transistors (samples L, M1 to M4) were measured.

[0659] The measurement of the ID-VG characteristics of the transistor was performed by applying a voltage applied to the gate electrode (hereinafter also referred to as the gate voltage (VG)) in steps of 0.25 V from -15 V to +20 V. Also, the voltage applied to the source electrode (VS) was set to 0 V (comm), and the voltages applied to the drain electrode (VD) were set to 0.1 V and 5.1 V. ​

[0660] The ID-VG characteristics of samples L, M1 to M4 are shown in Figures 37 to 51. 1 is the conductive layer 106 (bottom gate electrode) and the conductive layer 112 (top gate electrode) electrically Figures 42 to 46 show the ID-VG characteristics of the transistor connected to the conductive layer 1. 06 (bottom gate electrode) is electrically connected to conductive layer 120a or conductive layer 120b (source electrode). Figures 47 to 51 show the ID-VG characteristics of the transistors connected to each other. This shows the ID-VG characteristics of a transistor without 106 (bottom gate electrode).

[0661] Figures 37 to 51 show the sample and the conditions for the semiconductor layer 108, respectively. It also shows conditions where the channel length and channel width of the transistors differ in the vertical direction. The channel length is 2 μm and the channel width is 50 μm, and the channel length is 3 μm and the channel width is 50 μm. Three types of transistors with a channel width of 50 μm, a channel length of 6 μm, and a channel width of 50 μm. This is shown. Also, Figures 37 to 51 each show the gate voltage (VG) on the horizontal axis. The left vertical axis shows the drain current (ID), and the right vertical axis shows the saturation mobility at VG=15V. The μFE value is shown. The ID-VG characteristics of 20 transistors were measured for each sample. did.

[0662] Figures 37 to 51 show the threshold voltage (Vth) for each transistor size, respectively. The mean (ave) and 3σ of the saturation mobility (μFE) are shown. σ represents the standard deviation. .

[0663] <Reliability Evaluation> Next, the reliability of the transistors (samples L, M1 to M4) was evaluated. In this example, The gate is held at a high temperature with a positive potential applied relative to the source and drain potentials. Positive Bias Temperature Stress (PBTS) The test and the NB were held at high temperature with a negative potential applied to the gate in a light-irradiated environment. TIS(Negative Bias Temperature Illuminati) An on-stress test was conducted.

[0664] PBTS testing involves maintaining a substrate on which transistors are formed at 60°C, and then testing the transistors. A voltage of 0.1V was applied to the drain and 20V to the gate, and this state was maintained for 1 hour. The experiment was conducted in a dark environment.

[0665] The NBTIS test involves keeping the substrate on which the transistor is formed at 60°C, and the transistor... A voltage of 10V was applied to the drain and -20V to the gate of the transistor, and this condition was maintained for 1 hour. The test was conducted in a light-irradiated environment (irradiated with approximately 3400 lux of light from a white LED).

[0666] For reliability testing, a transistor with a channel length of 2 μm and a channel width of 3 μm was used. The change in threshold voltage (ΔVth) before and after the gate bias stress test was evaluated. Oh, conductive layer 106 (bottom gate electrode) is conductive layer 120a or conductive layer 120b (source A transistor was used to electrically connect the electrodes.

[0667] Figure 52 shows the threshold voltage fluctuations (ΔVth) for samples L, M1 to M4. In this graph, the horizontal axis shows the sample and semiconductor layer 108, and the vertical axis shows the threshold voltage in the PBTS test. This shows the amount of variation (ΔVth) and the amount of variation (ΔVth) of the threshold voltage in the NBTIS test. Figure 52 also shows the threshold voltage (initial voltage) of the transistor before reliability testing. It also indicates th).

[0668] As shown in Figures 37 to 51, in comparison with sample L, which is a comparative example, one aspect of the present invention It was confirmed that samples M1 to M4 had high field-effect mobility (μFE). M4 is the use of a metal oxide film having the composition shown in Embodiment 1 in the channel formation region. Therefore, it is thought to have exhibited a high field-effect mobility (μFE).

[0669] As shown in Figure 52, compared to the comparative example sample L, samples M1 to M4 are PBTS samples. We were able to confirm that the threshold voltage fluctuation (ΔVth) in the experiment was small. If the oxide film thickness is 5 nm or more, the threshold voltage fluctuation (ΔV) in the PBTS test is particularly important. It was confirmed that th) becomes smaller. Samples M1 to M4, which are one aspect of the present invention, are second A second oxide layer in contact with the silicon oxidizride film is a metal having the composition shown in Embodiment 1. By using an oxide film, the trapping of electrons in energy levels caused by nitrogen oxides is suppressed. Therefore, it is thought that the fluctuation in threshold voltage in the PBTS test has become smaller.

[0670] As described above, samples M1 to M4, which are one aspect of the present invention, exhibit high electrical characteristics and high reliability. We were able to confirm that it is a transistor that achieves both of these conditions.

[0671] The configuration shown in this embodiment may be used in appropriate combination with other embodiments and models. It is possible. [Examples]

[0672] In this embodiment, a metal oxide film that can be used in a semiconductor device according to one aspect of the present invention is Crystallinity and band gap were evaluated.

[0673] In this example, X-ray diffraction (XRD) analysis was performed on metal oxide films produced using different methods. Next, the crystallinity was evaluated. Similarly, for metal oxide films prepared using different methods, The gap was evaluated. The evaluation involved a 100 nm thick metal oxide film on a glass substrate. Samples that formed the following structure (samples P1 to P8, Q1 to Q8) were used.

[0674] <Sample preparation> Samples P1 to P8 are metal oxide films with an In-Ga-Zn oxide target (In:Ga Sample Q was formed by sputtering using Zn=10:1:3 (atomic ratio). 1 to Q8 are metal oxide films that form an In-Ga-Zn oxide target (In:Ga:Zn= It was formed by sputtering using a 10:1:6 (atomic ratio) method.

[0675] For samples P1 and Q1, the substrate temperature during metal oxide film deposition was set to room temperature (RT). Argon gas (oxygen flow rate ratio = 0%) was used as the film-forming gas.

[0676] For samples P2 and Q2, the substrate temperature during metal oxide film deposition was set to room temperature (RT). A mixed gas of oxygen and argon was used as the film-forming gas, with an oxygen flow rate ratio of 10%. .

[0677] For samples P3 and Q3, the substrate temperature during metal oxide film deposition was set to room temperature (RT). A mixed gas of oxygen and argon was used as the film-forming gas, with an oxygen flow rate ratio of 33%. .

[0678] For samples P4 and Q4, the substrate temperature during metal oxide film deposition was set to room temperature (RT). Oxygen gas (oxygen flow rate ratio = 100%) was used as the film-forming gas.

[0679] For samples P5 and Q5, the substrate temperature during the formation of the metal oxide film was set to 300 °C. Argon gas (oxygen flow rate ratio = 0%) was used as the film-forming gas.

[0680] For samples P6 and Q6, the substrate temperature during the formation of the metal oxide film was set to 300 °C. A mixed gas of oxygen gas and argon gas was used as the film-forming gas, and the oxygen flow rate ratio was set to 10%.

[0681] For samples P7 and Q7, the substrate temperature during the formation of the metal oxide film was set to 300 °C. A mixed gas of oxygen gas and argon gas was used as the film-forming gas, and the oxygen flow rate ratio was set to 33%.

[0682] For samples P8 and Q8, the substrate temperature during the formation of the metal oxide film was set to 300 °C. Oxygen gas (oxygen flow rate ratio = 100%) was used as the film-forming gas.

[0683] For all samples, the pressure during the formation of the metal oxide film was set to 0.4 Pa, and the power supply power was set to 2 00 W (DC).

[0684] <X-ray Diffraction Analysis> Next, X-ray diffraction (XRD) analysis of samples P1 to P8 and Q1 to Q8 was performed.

[0685] The θ-2θ scan method was used for the XRD analysis. For the XRD analysis, Cu K α rays (λ = 0.15418 nm) were used, the scanning range was 2θ = 15 deg to 50 deg, the step width was 0.01 deg, and the scanning speed was 6.0 deg / min.

[0686] The XRD analysis results of samples P1 to P8 are shown in Fig. 53. The XRD analysis The results are shown in Figure 54. In Figures 53 and 54, the substrate temperature during metal oxide film formation is shown in the lateral direction. The temperature (Tsub) is shown, and the oxygen flow rate ratio (O2) during metal oxide film formation is shown in the vertical direction. Furthermore, in Figures 53 and 54, the horizontal axis shows the diffraction angle 2θ, and the vertical axis shows the intensity of the diffracted X-rays. This indicates the intensity. Note that the vertical axis scale differs for each sample. Furthermore, in Figures 53 and 54, the auxiliary line 2θ = 31deg is shown as a dashed line.

[0687] As shown in Figures 53 and 54, a peak was observed around 2θ = 31 degrees in all samples. It was confirmed that it possesses crystalline properties. Furthermore, a broad peak around 2θ = 24 degrees was observed. The peak indicated by "k" is due to the glass substrate.

[0688] <Band Gap Assessment> Next, the transmittance and reflectance of samples P1 to P3 and Q1 to Q3 were measured, and the bandgating The efficiency (Eg) was calculated. A spectrophotometer was used to measure transmittance and reflectance.

[0689] The band gaps (Eg) of samples P1 to P3 and Q1 to Q3 are shown in Figure 55. Figure 55 In this graph, the horizontal axis shows the oxygen flow rate ratio during metal oxide film formation, and the vertical axis shows the band gap (E This shows g).

[0690] As shown in Figure 55, all samples have a band gap (Eg) of approximately 2.5 eV. We were able to confirm this.

[0691] The configuration shown in this embodiment may be used in appropriate combination with other embodiments and models. It is possible. [Examples]

[0692] In this embodiment, a metal oxide film that can be used in a semiconductor device according to one aspect of the present invention is Carrier concentration and mobility were evaluated.

[0693] In this example, Hall effect measurements were performed on metal oxide films manufactured using different methods. Carrier concentration and mobility were evaluated. For the evaluation, a 40 nm thick metal was placed on a glass substrate. Samples with oxide films formed on them (samples R1 to R12, S1 to S12) were used.

[0694] <Sample preparation> Samples R1 to R12 are metal oxide films with an In-Ga-Zn oxide target (In:G The sample was formed by sputtering using a:Zn=10:1:3 (atomic ratio). S1 to S12 are metal oxide films applied to an In-Ga-Zn oxide target (In:Ga:Z It was formed by sputtering using n=10:1:6 (atomic ratio).

[0695] Samples R1 to R4 and S1 to S4 each have different substrate temperatures during metal oxide film formation. The temperature was set to room temperature (RT). Argon gas (oxygen flow rate ratio = 0%) was used as the film deposition gas.

[0696] Samples R5 to R8 and S5 to S8 each have different substrate temperatures during metal oxide film formation. The temperature was set to room temperature (RT). A mixed gas of oxygen and argon was used as the film-forming gas. The flow rate ratio was set to 10%.

[0697] Samples R9 to R12 and S9 to S12 are each related to the substrate temperature during metal oxide film formation. The temperature was set to room temperature (RT). A mixed gas of oxygen and argon was used as the film-forming gas. The oxygen flow rate ratio was set to 33%.

[0698] In addition, for all samples, the pressure during the formation of the metal oxide film was set to 0.4 Pa, and the power supply power was set to 2 00 W (DC).

[0699] Subsequently, heat treatment was performed. An oven device was used for the heat treatment.

[0700] Samples R1, R5, R9, S1, S5, and S9 were heat-treated at 350°C for 1 hour in a nitrogen gas atmosphere.

[0701] Samples R2, R6, R10, S2, S6, and S10 were heat-treated at 350°C for 1 hour in a nitrogen gas atmosphere, and then heat-treated at 350°C for 1 hour in a mixed gas atmosphere of nitrogen gas and oxygen gas (nitrogen gas flow rate: oxygen gas flow rate = 4:1).

[0702] Samples R3, R7, R11, S3, S7, and S11 were heat-treated at 450°C for 1 hour in a nitrogen gas atmosphere.

[0703] Samples R4, R8, R12, S4, S8, and S12 were heat-treated at 450°C for 1 hour in a nitrogen gas atmosphere, and then heat-treated at 450°C for 1 hour in a mixed gas atmosphere of nitrogen gas and oxygen gas (nitrogen gas flow rate: oxygen gas flow rate = 4:1).

[0704] <Hall Effect Measurement> Next, Hall effect measurements were performed on samples R1 to R12 and S1 to S12.

[0705] Note that Hall effect measurement is a method of measuring electrical properties such as carrier density, mobility, and resistivity by applying a magnetic field perpendicular to the direction of current flow in a current-carrying object, thereby causing an electromotive force to appear in a direction perpendicular to both the current and the magnetic field. This actual measurement utilizes the Hall effect. ​In the example, the Hall effect was measured at room temperature using the Van der Pauw method. For measuring the effects of all tests, we used ResiTest manufactured by Toyo Technica Co., Ltd.

[0706] The carrier concentrations of samples R1 to R12 are shown in Figure 56A. The mobility is shown in Figure 56B. The carrier concentrations of samples S1 to S12 are shown in Figure 57A. The Hall mobility of samples S1 to S12 is shown in Figure 57B. Figures 56A and 57A show the odor The horizontal axis shows the oxygen flow rate ratio during metal oxide film formation, and the vertical axis shows the carrier concentration (Carri Figures 56B and 57B show the (er density) of the metal oxide film. This shows the oxygen flow rate ratio during formation, with Hall mobility shown on the vertical axis. vinegar.

[0707] As shown in Figures 56B and 57B, the Hall mobility of the sample in this embodiment is 20 cm². 2 / It was found to be Vs or higher.

[0708] The configuration shown in this embodiment may be used in appropriate combination with other embodiments and models. It is possible. [Explanation of symbols]

[0709] L1: Line, L2: Line, L3: Line, L4: Line, L5: Line, L6: Line, L7: Line, L8: Line, L9: wire, L10: wire, L11: wire, L12: wire, 10: transistor, 10A: transistor Zista, 10B: Transistor, 10C: Transistor, 11: Range, 13: Range, 15 : range, 17: range, 100: transistor, 100_a: transistor, 100_b: Transistor, 100A: Transistor, 100A_a: Transistor, 100A_b: Transistor, 100B: Transistor, 100B_a: Transistor, 100C: Transistor Transistor, 100C_a: Transistor, 100C_b: Transistor, 102: Circuit board, 103: insulating layer, 103a: insulating film, 103b: insulating film, 103c: insulating film, 103d: Insulating film, 106: conductive layer, 108: semiconductor layer, 108a: semiconductor layer, 108b: semiconductor layer ,108f: metal oxide film, 108n: low resistance region, 110: insulating layer, 110a: insulating film , 110b: insulating film, 110c: insulating film, 112: conductive layer, 112f: conductive film, 114: Metal oxide layer, 114f: Metal oxide film, 116: Insulating layer, 118: Insulating layer, 120a: Conductive layer, 120b: conductive layer, 140: impurity element, 141a: opening, 141b: opening , 142: Opening

Claims

[Claim 1] It comprises a first conductive layer, a semiconductor layer, and a second conductive layer. The first conductive layer has a region located below the semiconductor layer and functions as the first gate of the transistor. The second conductive layer has a region located above the semiconductor layer and functions as the second gate of the transistor. The semiconductor layer has a channel formation region for the transistor, The semiconductor layer comprises indium, gallium, zinc, and oxygen. The semiconductor layer has a composition within the range of a straight line connecting, in this order, the first coordinate (44:11:10), the second coordinate (4:1:4), the third coordinate (1:0:1), the fourth coordinate (11:0:2), and the first coordinate, in a triangular diagram showing the atomic ratios of indium, gallium, and zinc. A semiconductor device wherein, in a cross-sectional view taken along the channel length direction of the transistor, the width of the first conductive layer is greater than the width of the second conductive layer.

Images