Quantum computation system with non-adiabatic single-flux quantum (SFQ) readout for superconducting qubits

Abstract

The present invention provides a computation or information processing system that includes a quantum computation module that performs information processing or computation using the quantum states of quantum mechanical devices or circuits. [Solution] The computation or information processing system uses a superconducting-based quantum computation module (e.g., a superconducting Josephson junction) and constructs quantum computation modules or devices and classical digital computation modules or devices for various applications based on quantum computation. Such a quantum system includes an ensemble of qubits based on a superconducting Josephson junction and performs complex computations based on the superposition and correlation / entanglement of the quantum states of the qubits. The qubit device is controlled by a qubit control circuit, and a qubit readout circuit measures the quantum state of the qubit device under the control of the qubit control circuit and provides qubit readout based on the measurement.

Description

[Technical Field]

[0001] (Claim of priority and related patent applications) This patent document claims priority and benefits of U.S. Provisional Patent Application No. 63 / 078,587, titled "QUANTUM COMPUTING SYSTEMS WITH DIABATIC SINGLE FLUX QUANTUM (SFQ) READOUT FOR SUPERCONDUCTING QUANTUM BITS," filed on 15 September 2020.

[0002] (Technical field) This patent document relates to a computation or information processing system, including a quantum computation module that performs information processing or computation using the quantum states of a quantum mechanical device or circuit. [Background technology]

[0003] (background) Classical digital computers, including general-purpose digital computers and high-performance digital supercomputers, perform calculations based on Boolean logic. While Boolean-based computational techniques have revolutionized a wide range of industries and technologies over the past few decades, they also present certain limitations when performing highly complex or numerous calculations, such as molecular modeling of the structure and properties of chemical compounds or biological structures, cryptography, or modeling complex systems for weather forecasting, climate change, and other applications. Various new computational techniques are being investigated to complement or replace Boolean-based digital computation.

[0004] Quantum mechanical systems can be used to construct novel computational systems for complex information processing. A suitable quantum system for quantum computation has an ensemble of subsystems that exhibit different quantum states that correlate with or "entangle" each other due to quantum coherence, including long-range quantum coherence. In various implementations for quantum computers, each subsystem in the ensemble of subsystems may be a quantum system that exhibits two or more different quantum states to act as a qubit, and information can be represented, stored, processed, and transmitted by the superposition and correlation of the quantum states of different qubits. Some embodiments of qubit implementations include superconducting qubits based on superconducting Josephson junctions, developed by IBM, Google, Intel, and others; ion trapping devices based on laser beams and electromagnetic trapping fields, developed by Honeywell and IonQ; semiconductor-based quantum dots; and other devices capable of quantum computational operation. [Overview of the Initiative] [Means for solving the problem]

[0005] (summary) The technology disclosed in this patent document can be implemented to combine quantum computation and classical digital computation in a scalable computation system, based on superconducting qubits using Josephson junctions, which exhibit low diffusion and long coherence times and can be fabricated using well-developed integrated circuit fabrication techniques. More specifically, the disclosed technology can be implemented by using two radio frequency (RF) superconducting quantum interference device (SQUID) circuits symmetrically coupled to form a quantum readout circuit for reading superconducting qubits with improved readout fidelity and sensitivity.

[0006] In one aspect, the disclosed technology can be implemented to provide a system capable of information processing based at least in part on quantum computation using the quantum states of qubits. The system includes a quantum computation module comprising a plurality of qubit circuits, each qubit circuit being structured as a superconducting circuit such that it exhibits a different quantum state as a qubit and interacts quantum mechanically with other qubit circuits via quantum entanglement, causing a superposition or correlation of different quantum states of the qubit circuits, and each qubit readout circuit is coupled to and communicates with a qubit circuit. Each qubit readout circuit includes an inductor and two radio frequency (RF) superconducting quantum interference device (SQUID) circuits forming a phase detector symmetrically coupled to the inductor and operable to measure the phase of a signal. Each qubit readout circuit generates a readout signal at a signal frequency between resonant frequencies associated with the excited and ground states of the corresponding qubit circuit, is instructed by the corresponding qubit circuit to detect the phase of the reflected readout signal, and indicates the quantum state of the corresponding qubit circuit based on the detected phase.

[0007] In another aspect, the disclosed technology can be implemented to provide a method for performing information processing based on quantum computation, using the quantum states of qubits, at least in part. The method includes operating a quantum computation module comprising multiple superconducting qubit circuits such that each qubit circuit exhibits a different quantum state as a qubit, interacts quantum mechanically with other qubit circuits, and causes a superposition or correlation of different quantum states of the qubit circuits; and operating qubit readout circuits, each interacting with a qubit circuit and reading out information about the qubit circuit. In the method, each qubit readout circuit includes an inductor and two radio frequency (RF) superconducting quantum interference device (SQUID) circuits forming a phase detector coupled to the inductor and operable to measure the phase of a signal, each qubit readout circuit is instructed to generate a readout signal at a signal frequency between resonant frequencies associated with the excited and ground states of the corresponding qubit circuit, and to detect the phase of the reflected signal of the readout signal from the corresponding qubit circuit, and based on the detected phase, to indicate the quantum state of the corresponding qubit circuit.

[0008] In another aspect, the disclosed technology can be implemented to provide a system capable of information processing based at least in part on quantum computation using the quantum states of qubits. The system includes a cryostat system structured to include different cryogenic stages that are operable to provide lower and higher cryogenic temperatures, and a quantum computation module surrounded by the cryostat system at lower cryogenic temperatures. The quantum computation module comprises a first integrated chip structured to support a plurality of qubit circuits, each qubit circuit structured as a superconducting circuit at lower cryogenic temperatures such that, as a quantum mechanical system, it exhibits a different quantum state and interacts quantum mechanically with other qubit circuits via quantum entanglement, causing a superposition or correlation of different quantum states of the qubit circuits. The system includes a qubit management circuit module, surrounded by a cryostat system, located adjacent to a quantum computation module and coupled to be maintained at cryogenic temperatures; a qubit control circuit, supported by a second integrated chip and structured to instruct the qubit circuit to control a control signal to the qubit circuit; and a qubit readout circuit, supported by a second integrated chip and structured to output a readout signal from the qubit circuit. Each readout signal represents a quantum state of the qubit circuit, and the qubit control circuit and qubit readout circuit are structured to operate at low cryogenic temperatures, including superconducting circuits, and to operate in a non-quantum classical manner based on digital processing using the control signal and the readout signal. A second integrated chip engages with the first integrated chip to form a multi-chip module, between which control and read signals are transferred, and each qubit read circuit includes (1) an inductor, and (2) two radio frequency (RF) superconducting quantum interference device (SQUID) circuits that form a phase detector coupled to the inductor and operable to measure the phase of a signal, and (3) a bias circuit coupled to the two RF SQUID circuits to bias one or both of the two RF SQUID circuits and reduce the difference in current between the two RF SQUID circuits.The system further includes a circuit module surrounded by a cryostat system at higher cryogenic temperatures and structured to communicate with a qubit management circuit module in association with control signals and readout signals; conductive bumps formed to connect to first and second integrated chips, at least a portion of which forms a conductive path between the qubit management circuit module and the quantum computation module for transferring a portion of the control signals and readout signals without using other wiring between the qubit management circuit module and the quantum computation module; and conductive wires coupled between the qubit management circuit module and at least one of the circuit modules placed in a higher temperature stage of the cryostat system, providing communication and transfer signals between them.

[0009] The above and other aspects, as well as their implementation, will be described in more detail in the drawings, descriptions, and claims. The present invention provides, for example, the following items: (Item 1) A system capable of information processing, at least partially, based on quantum computation using the quantum states of qubits, A quantum computing module comprising multiple qubit circuits, wherein each qubit circuit, as a qubit, exhibits a different quantum state and interacts quantum mechanically with other qubit circuits via quantum entanglement, and is structured as a superconducting circuit to cause superposition or correlation of the different quantum states of the qubit circuits, Each qubit readout circuit is coupled to and communicates with the qubit circuit, each qubit readout circuit comprising an inductor and two radio frequency (RF) superconducting quantum interference device (SQUID) circuits forming a phase detector symmetrically coupled to the inductor and operable to measure the phase of a signal, each qubit readout circuit generates a read signal at a signal frequency between resonant frequencies associated with the excited and ground states of the corresponding qubit circuit, and reads from the corresponding qubit circuit. A qubit readout circuit is commanded to detect the phase of the reflected signal of the read signal, and based on the detected phase, it indicates the quantum state of the corresponding qubit circuit. A system that includes these features. (Item 2) The system according to item 1, wherein each qubit readout circuit includes a bias circuit that is coupled to compensate for the difference in current between the two RF SQUID circuits and maintains symmetry between the two RF SQUID circuits. (Item 3) The system according to item 1, wherein each qubit readout circuit includes two bias circuits coupled to the two RF SQUID circuits, supplying bias current to the two RF SQUID circuits, compensating for the difference in current between the two RF SQUID circuits, and maintaining symmetry between the two RF SQUID circuits. (Item 4) The system according to item 1, wherein each qubit readout circuit is structured such that the signal frequency of the generated readout signal is midway between the resonant frequencies associated with the excited state and ground state of the corresponding qubit circuit, respectively. (Item 5) The system as described in item 1, wherein each qubit readout circuit is structured such that the generated readout signal is a microwave signal. (Item 6) The system as described in item 1, wherein each qubit readout circuit is structured such that the generated readout signal is a sequence of single-flux quantum (SFQ) pulses. (Item 7) A cryostat system is provided, which is structured to include different cryogenic stages that are capable of operating to provide lower and higher cryogenic temperatures. The system according to item 1, wherein the qubit readout circuit and the quantum computation module are surrounded by the cryostat system, and the qubit readout circuit and the quantum computation module are coupled to each other so as to be maintained at a common low cryogenic temperature. (Item 8) The quantum computing module is structured to include a first integrated chip structured to support the quantum bit circuit. The quantum bit readout circuit is structured to include a second integrated chip that supports the quantum bit readout circuit. The system according to item 7, wherein the second integrated chip is engaged with the first integrated chip to form a multi-chip module. (Item 9) The system according to item 1, comprising two identical Josephson junctions symmetrically coupled to the inductor. (Item 10) Each quantum bit readout circuit includes two bias circuits respectively coupled to the two RF SQUID circuits. Each bias circuit is coupled to the corresponding RF SQUID circuit such that the two RF SQUID circuits receive individual bias fluxes, compensate for the difference in current in the two RF SQUID circuits, and reduce the asymmetry between the two RF SQUID circuits, and is structured to produce a bias flux. The system according to item 1. (Item 11) A method for performing information processing based on quantum computing that at least partially uses the quantum state of a quantum bit, comprising: Operating a quantum computing module comprising a plurality of superconducting quantum bit circuits such that each quantum bit circuit exhibits different quantum states as quantum bits and interacts quantum mechanically with other quantum bit circuits to induce a superposition or correlation of different quantum states of the quantum bit circuit. Operating a quantum bit readout circuit to interact with each of the quantum bit circuits and read out information about the quantum bit circuits. And including Each qubit readout circuit includes an inductor and two radio frequency (RF) superconducting quantum interference device (SQUID) circuits that are coupled to the inductor and form a phase detector operable to measure the phase of a signal. Each qubit readout circuit generates a read signal at a signal frequency between resonance frequencies associated with the excited state and the ground state of a corresponding qubit circuit, respectively, and is instructed to detect the phase of a reflected signal of the read signal from the corresponding qubit circuit, and based on the detected phase, indicates the quantum state of the corresponding qubit circuit, method. (Item 12) The method according to item 11, including generating a bias current in at least one of the two RF SQUID circuits when operating each qubit readout circuit, reducing the current difference in the two RF SQUID circuits, and maintaining the symmetry between the two RF SQUID circuits. (Item 13) The method according to item 11, including generating two bias currents in the two RF SQUID circuits respectively when operating each qubit readout circuit, reducing the current difference in the two RF SQUID circuits, and maintaining the symmetry between the two RF SQUID circuits. (Item 14) Each of the qubit readout circuits includes two bias circuits coupled to the two RF SQUID circuits, The method according to item 11, when operating each qubit readout circuit, the method further includes operating the two bias circuits to produce two bias magnetic fluxes in the two RF SQUID circuits respectively, compensating for the current difference in the two RF SQUID circuits, and reducing the asymmetry between the two RF SQUID circuits. (Item 15) A system capable of information processing based at least in part on quantum computation using the quantum state of qubits, A cryostat system structured to include different cryogenic temperature stages operable to provide a low cryogenic temperature and a higher cryogenic temperature, A quantum computing module, surrounded by the cryostat system at the aforementioned low cryogenic temperature, comprises a first integrated chip structured to support a plurality of qubit circuits, each qubit circuit being structured as a superconducting circuit at the aforementioned low cryogenic temperature, such that each qubit circuit exhibits a different quantum state as a quantum mechanical system, interacts quantum mechanically with other qubit circuits via quantum entanglement, and causes superposition or correlation of the different quantum states of the qubit circuits. A qubit management circuit module, surrounded by the cryostat system, located adjacent to the quantum computation module, and coupled to be maintained at cryogenic temperatures, wherein the qubit control circuit is supported by a second integrated chip and each is structured to instruct a control signal to the qubit circuit to control the qubit circuit, the qubit readout circuit is supported by the second integrated chip and each is structured to output a readout signal from the qubit circuit, the readout signal each representing the quantum state of the qubit circuit, and the qubit control circuit and qubit readout circuit are operable to operate in a non-quantum classical manner using the control signal and readout signal, based on digital processing, and include a superconducting circuit at the low cryogenic temperatures. Structured such that the second integrated chip engages with the first integrated chip to form a multi-chip module, between which control signals and read signals are transferred, and each qubit read circuit includes a qubit management circuit module comprising: (1) an inductor; (2) two radio frequency (RF) superconducting quantum interference device (SQUID) circuits which form a phase detector coupled to the inductor and which is operable to measure the phase of a signal; and (3) a bias circuit which is coupled to the two RF SQUID circuits which biases one or both of the two RF SQUID circuits and reduces the difference in current within the two RF SQUID circuits. At the above-mentioned ultra-low temperatures, a circuit module is surrounded by the cryostat system and structured to communicate with the qubit management circuit module in relation to the control signals and readout signals, A conductive bump formed to connect to the first and second integrated chips, wherein at least a portion of the conductive bump forms a conductive path between the qubit management circuit module and the quantum computation module for transferring a portion of the control signals and read signals without using other wiring between the qubit management circuit module and the quantum computation module; A conductive wire is coupled between the qubit management circuit module and at least one of the circuit modules placed in a higher temperature stage of the cryostat system, providing communication and transmission signals between them. A system that includes these features. (Item 16) The system according to item 15, wherein each bias circuit is structured to produce two bias fluxes within the two RF SQUID circuits, thereby reducing the difference in critical currents within the two RF SQUID circuits. (Item 17) The system according to item 15, wherein the bias circuit is structured to generate a bias current in at least one of the two RF SQUID circuits, reduce the current difference between the two RF SQUID circuits, and maintain symmetry between the two RF SQUID circuits. (Item 18) The system according to item 11, wherein each bias circuit is structured to generate two bias currents within the two RF SQUID circuits and to reduce the difference in critical currents within the two RF SQUID circuits. (Item 19) The system according to item 1, wherein the qubit management circuit module and the quantum computation module are maintained at the same low cryogenic temperature. (Item 20) The system according to item 15, wherein each qubit readout circuit generates a readout signal at a signal frequency between resonant frequencies associated with the excited and ground states of the corresponding qubit circuit, is instructed by the corresponding qubit circuit to detect the phase of the reflected signal of the readout signal, and indicates the quantum state of the corresponding qubit circuit based on the detected phase. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 shows a partial example of a quantum computing system.

[0011] [Figure 2] Figure 2 shows an example of a symmetrical radio frequency (RF) superconducting quantum interference device (SQUID) as the qubit readout circuit in Figure 1.

[0012] [Figure 3] Figures 3, 4, 5A, 5B, 5C, 6A, 6B, 6C, 7A, 7B, 7C, 7D, and 7E illustrate examples of implementing the design in Figure 2 and their characteristics or properties. [Figure 4] Figures 3, 4, 5A, 5B, 5C, 6A, 6B, 6C, 7A, 7B, 7C, 7D, and 7E illustrate examples of implementing the design in Figure 2 and their characteristics or properties. [Figure 5] Figures 3, 4, 5A, 5B, 5C, 6A, 6B, 6C, 7A, 7B, 7C, 7D, and 7E illustrate examples of implementing the design in Figure 2 and their characteristics or properties. [Figure 6A] Figures 3, 4, 5A, 5B, 5C, 6A, 6B, 6C, 7A, 7B, 7C, 7D, and 7E illustrate examples of implementing the design in Figure 2 and their characteristics or properties. [Figure 6B] Figures 3, 4, 5A, 5B, 5C, 6A, 6B, 6C, 7A, 7B, 7C, 7D, and 7E illustrate examples of implementing the design in Figure 2 and their characteristics or properties. [Figure 6C]Figures 3, 4, 5A, 5B, 5C, 6A, 6B, 6C, 7A, 7B, 7C, 7D, and 7E illustrate examples of implementing the design in Figure 2 and their characteristics or properties. [Figure 7A] Figures 3, 4, 5A, 5B, 5C, 6A, 6B, 6C, 7A, 7B, 7C, 7D, and 7E illustrate examples of implementing the design in Figure 2 and their characteristics or properties. [Figure 7B] Figures 3, 4, 5A, 5B, 5C, 6A, 6B, 6C, 7A, 7B, 7C, 7D, and 7E illustrate examples of implementing the design in Figure 2 and their characteristics or properties. [Figure 7C] Figures 3, 4, 5A, 5B, 5C, 6A, 6B, 6C, 7A, 7B, 7C, 7D, and 7E illustrate examples of implementing the design in Figure 2 and their characteristics or properties. [Figure 7D] Figures 3, 4, 5A, 5B, 5C, 6A, 6B, 6C, 7A, 7B, 7C, 7D, and 7E illustrate examples of implementing the design in Figure 2 and their characteristics or properties. [Figure 7E] Figures 3, 4, 5A, 5B, 5C, 6A, 6B, 6C, 7A, 7B, 7C, 7D, and 7E illustrate examples of implementing the design in Figure 2 and their characteristics or properties.

[0013] [Figure 8A] Figures 8A, 8B, and 8C illustrate embodiments of a quantum computing system based on the disclosed technology. [Figure 8B] Figures 8A, 8B, and 8C illustrate embodiments of a quantum computing system based on the disclosed technology. [Figure 8C] Figures 8A, 8B, and 8C illustrate embodiments of a quantum computing system based on the disclosed technology. [Modes for carrying out the invention]

[0014] (Detailed explanation) The techniques disclosed herein for computation or information processing systems utilize superconducting-based quantum computation modules (e.g., superconducting Josephson junctions) to construct quantum computation modules or devices for various applications, as well as classical digital computation modules or devices, based on quantum computation. Such quantum systems include an ensemble of qubits based on superconducting Josephson junctions, and can perform complex computations based on the superposition and correlation / entanglement of the quantum states of the qubits. The qubit device can be controlled by a qubit control circuit, and a qubit readout circuit can be used to measure the quantum state of the qubit device under the control of the qubit control circuit and to provide qubit readouts based on the measurements.

[0015] Figure 1 shows part of an embodiment of a quantum computing system that operates a superconducting qubit circuit or device as part of a quantum computing module 102 for performing quantum computations. A qubit management circuit module 104 is provided, which communicates with the quantum computing module 102. The qubit management module 104 includes a qubit control circuit for providing control signals to individual qubit circuits of the quantum computing module 102, and a qubit readout circuit for reading out individual qubit circuits, which is implemented by using a non-quantum mechanical processing circuit network such as a digital circuit network or an analog circuit network, or a combination of digital and analog circuits. More specifically, Figure 1 illustrates, as an embodiment, a pair of qubit control and readout circuits for one qubit circuit, and the qubit management circuit module 104 and the quantum computing module 102 include multiple pairs of qubit control and readout circuits to form multiple qubit circuits.

[0016] In Figure 1, the qubit control circuit of the qubit management module 104 can be structured in different configurations. For example, one well-known technique for controlling qubits is to direct a low-energy analog microwave signal to induce selective excitation of individual transitions between the quantum states of the qubit device. In various implementations, the hardware for generating and directing such analog microwave signals to the qubits may require a complex network and intricate wiring for generating and transmitting the analog microwave signals through cryogenic equipment. In addition, analog microwave signals are susceptible to interference and noise, and therefore additional signal conditioning and filtering are required within the qubit control circuit. These and other aspects of qubit control based on analog microwave signals present challenges for complex quantum computing systems with a large number of qubits. As another embodiment for controlling qubits, a single-flux quantum (SFQ) logic circuit based on a superconducting Josephson junction can be used to generate resonant digital voltage SFQ pulses or pulse sequences and coherently control the qubits. For example, "System and method for controlling superconducting quantum circuits" U.S. Patent No. 9,425,804B2, titled "Using Single Flux Quantum Logic Circuits" and issued to the Wisconsin Alumni Research Foundation, discloses controlling a superconducting quantum circuit by using an SFQ control circuit to generate a voltage pulse sequence of voltage pulses that are temporally separated by intervals between pulses, timed to the resonant period so that the SFQ pulses resonate with the qubit frequency. The pulse width of the SFQ pulse is set to be much smaller than the oscillation or resonant period of the qubit, and each qubit is insensitive to the very fine shape of the individual SFQ pulse, and the qubit response is a function of the time integral of the SFQ pulse. Other circuit designs based on SFQ technology and other techniques may also be used to construct the qubit control circuit of the qubit management module 104.

[0017] The qubit readout circuit in Figure 1 can be implemented based on different designs to achieve accurate measurement of the quantum state of a qubit without destroying its quantum state, i.e., quantum non-destructive ("QND") measurement of a qubit. For example, the qubit readout circuit can be constructed based on a Josephson photomultiplier tube (JPM) that can dictate a qubit readout tone or signal that resonates with the |1> state of the qubit. The readout pulse is then scattered from the qubit encoding its state within the amplitude of the readout pulse, producing a clothed pulse. This clothed pulse interacts with the JPM, which will only experience phase slip if the qubit is in |1>, i.e., if the input pulse is sufficiently strong. An example of this JPM readout implementation is described in U.S. Patent No. 9,692,423, entitled "System and method for circuit quantum electrodynamics measurement," issued to Universitaet des Saarlandes (Germany), Syracuse University, and Wisconsin Alumni Research Foundation.

[0018] In another embodiment, a suitable qubit readout circuit for implementing a quantum computation system based on the technology disclosed herein may include a symmetric radio frequency (RF) superconducting quantum interference device (SQUID) comprising one superconducting loop and a single Josephson junction within the superconducting loop. The Josephson junction includes a thin non-superconducting layer (e.g., an insulating barrier) sandwiched between two superconductors so that electrons can tunnel through the barrier. The disclosed symmetric RF SQUID readout circuit may be directly coupled to a qubit for readout (e.g., a transmission line of the qubit) or to a resonant cavity coupled to the qubit for readout, thereby transferring or directly reading quantum state information of the qubit circuit to the resonant cavity occupancy. A single-flux quantum (SFQ) circuit may be coupled to the symmetric RF SQUID readout circuit and configured to synchronize the RF readout circuit and receive the readout signal.

[0019] Figure 2 shows an embodiment of a symmetric RF SQUID readout circuit with two RF SQUIDs coupled to share a common inductor L. The two RF SQUIDs should be substantially identical, but practical fabrication often makes them non-identical. Each RF SQUID contains one superconducting Josephson junction within a closed superconducting loop or ring, and the magnetic flux of the loop or ring can be measured with high accuracy. The readout circuit operates based on the interaction with the phase of the pulse reflected from the qubit under measurement and can have different potential shapes depending on the external magnetic flux Φ0 in the two closed superconducting loops of the symmetric RF SQUID readout circuit.

[0020] Figure 3 shows the spectral diagram of the symmetric RF SQUID readout circuit of Figure 2 during readout operation. Due to the phase-sensitive scattering signal, the frequency of the readout signal is the resonant frequency ω for the excited state |1> and ground state |0>. e and ω g It is tuned to a frequency between ω, and in some implementations, the frequency of this readout signal is the same as the two resonant frequencies ω e and ωg It may be located midway between the two points.

[0021] This symmetric RF SQUID readout circuit, when homogeneously flux-biased, can be operated to change the potential shape non-adiabatically using high-speed SFQ pulses without directly generating back-action pulses, due to the symmetry of the device. The term "non-adiabatic" derives from the fact that the symmetric RF SQUID is driven with SFQ pulses that have a much shorter pulse duration than typical microwave readout pulses. In various implementations, such readout pulses are typically 1–10 GHz (periods of 1,000–100 ps), while SFQ pulses can be easily generated with pulse durations of less than 10 ps, ​​which is about one to two orders of magnitude shorter than the period of a single readout pulse.

[0022] In some implementations of the disclosed technology, the spectrum of a symmetric RF SQUID can be designed to have frequencies much higher than the qubit frequencies. Thus, the entire phase evolution of the RF SQUID will generate back-action photons (indirect back-action, the opposite of direct back-action) that will not be able to reach qubits with frequencies outside the qubit and resonator absorption spectra. These photons will eventually dissipate over the shunt resistance of the Josephson junction of the symmetric RF SQUID (Figure 2).

[0023] During operation, the symmetric RF SQUID in Figure 2 is biased using SFQ pulses to "digitally" control the shape of the potential. Referring to the potential as a function of phase in Figure 4, when a potential inversion is provided at time t0, the phase particles descend either to the left or right of the potential peak depending on the sign of the initial condition on phase φ(t0), and as a result, the current flowing into the inductance L can exist in either direction. This directional dependence of the current is used as the readout mechanism for the symmetric RF SQUID in Figure 2, and by transmitting phase-sensitive readout pulses to the symmetric RF SQUID, two different initial conditions for phase φ exist depending on the phase of the readout tone. Thus, the coupling between the two symmetric RF SQUID circuits and the inductor forms a phase detector that can be operated to measure the phase of the reflected signal from the qubit carrying information about the quantum state of the qubit.

[0024] The operation of the symmetric RF SQUID readout circuit in Figure 2 was simulated using the PSCAN2 superconducting circuit simulator, and the simulation results are shown in Figures 5A, 5B, and 5C. Figure 5A shows the frequency ω=(ω) such that the phase of the readout pulse and the phase of the reflected pulse will depend on the quantum state of the qubit. g +ω e ) / 2 indicates that it is transmitted to the qubit. The reflected pulse from the qubit (or the resonant cavity coupled to the qubit) then injects a current into a symmetric RF SQUID readout circuit, the phase of which will begin to oscillate depending on the state of the qubit, as shown in Figure 5B. Note that if the plasma frequency of the device is much greater than ω, the φ(t) oscillation will be in phase with the input current (induced behavior), as shown in Figure 5C.

[0025] The signal generated by the SFQ controller provides a Φ0 / 2 flux bias to the symmetric RF SQUID readout circuit, causing a non-adiabatic (and back-action-free) change in the potential shape. At this point, the phase particles will have a positive or negative offset relative to the φ=0 state, resulting in a drop to either the left or right dip adjacent to the potential peak. The current flowing into the central inductor L of the symmetric RF SQUID readout circuit then has a direction dependent on the qubit state, and via the flux converter, the current is fed into the SFQ comparator for processing and storage.

[0026] The symmetric RF SQUID readout circuit described above may be constructed to achieve one or more advantages. For example, the unwanted backaction of the symmetric RF SQUID readout circuit is state-independent and can be reduced simultaneously for both states. For example, unlike the JPM readout design described above, this symmetric RF SQUID readout circuit does not require to be in a resonant state with the qubit itself in order to function properly. As a result, the potential spectrum after switching can be far from resonance with the qubit, thus avoiding the need for precise control of the magnetic flux at short time intervals relative to the resonant condition. In another embodiment, unlike the JPM readout design described above, which requires complex preparation of the JPM readout circuit to reduce backaction photons, the symmetric RF SQUID readout circuit described above does not require any difficult preparation of the device before readout and can start, for example, from a ground state where no magnetic flux is applied at all. In another embodiment, the symmetry of the symmetric RF SQUID readout circuit described above allows qubit readout to be triggered using a steep SFQ pulse without any backaction, enabling very fast operation without increasing backaction to the JPM. In yet another embodiment, this symmetric RF SQUID readout circuit can be phase-sensitive and used to measure ultra-low power signals (the readout pulse does not need to excite anything, it simply provides a phase shift to the phase particle).

[0027] The symmetric RF SQUID readout circuits described above can also be used to take advantage of additional features. For example, the device can be operated to compensate for or reduce noise by performing multiple measurements on the same readout pulse, and the readout can be based on the average of the multiple measurements to reduce noise. In another embodiment, the readout pulse can be fabricated as a microwave pulse generated by a CMOS circuit or superconducting on-chip clock source, which may be located on a separate cryogenic chip (e.g., the qubit management module 104 in Figure 1) coupled to the qubit chip (i.e., the quantum computation module 102 in Figure 1) in some implementations. In addition, the readout pulse can also be fabricated by an SFQ pulse, as its phase response may be sensitive to phase variations of non-sinusoidal signals.

[0028] In particular, the two Josephson junctions of the symmetric RF SQUID readout circuit C1 and I C2 Deviations from symmetry can significantly affect the performance of the readout operation. Such undesirable asymmetry between two RF SQUID devices can be caused by various factors. For example, when fabricating actual devices, there may be some differences in the physical circuit components of two RF SQUID devices that are intended to be identical and symmetrical in their properties by the design for this symmetric RF SQUID readout circuit. Such differences can be caused by unavoidable variations in the physical fabrication of those circuit components due to practical limitations in the fabrication equipment or process. As a result, the two final fabricated RF SQUIDs may differ from each other in one or more aspects, such as different critical currents, and thus may cause asymmetry in the circuit that can degrade the desired behavior of an ideally symmetric RF SQUID readout circuit. The undesirable asymmetry between two RF SQUIDs can be mitigated in practical devices by implementing bias or compensation networks.

[0029] For example, in some designs, an unwanted asymmetric critical current can be compensated by applying an input current as an asymmetric DC flux bias, canceling out the difference in currents in the two RF SQUIDs on either side of a shared common inductor L, thus ensuring the desired operation. Figure 6A shows an embodiment of an SFQ bias circuit coupled to the symmetric RF SQUID readout circuit of Figure 2 to equalize the unwanted asymmetric critical currents in the two RF SQUIDs. A readout pulse generator is coupled to the qubit and transmits readout pulses to the qubit, and a readout resonator is coupled to the qubit and transmits readout pulses from the qubit to the symmetric RF This describes a SQUID readout circuit. In this embodiment, the qubit and readout resonator form a basic qubit unit, many such basic qubit units form a quantum computation module as part of a quantum processor or chip, as shown in Figures 1 and 8A-8C, and the symmetric RF SQUID readout circuit is part of a qubit management circuit module, as shown in Figures 1 and 8A-8C. The SFQ bias circuit provides an SFQ flux bias and digitally changes the potential shape by control outputs to two inductors L1 and L2 connected to the SFQ bias circuit, modeling magnetic coupling to two loops that form a symmetric RF SQUID. These two inductors L1 and L2 can operate together with the same SFQ bias circuit coupled to them, as shown in Figure 6A. The SFQ bias circuit is coupled to at least one of the two coupled inductors L1 and L2 and modulates the current so that the two currents in the two RF SQUIDs are substantially or nearly symmetric. Alternatively, these two inductors L1 and L2 can each be coupled to two independent SFQ bias circuits, i.e., one SFQ bias circuit per inductor, to compensate for the asymmetry of the critical current at the junction. As shown, the SFQ bias circuits are also coupled to detect or read the sign of the current in the common inductor L of the symmetric RF-SQUID, the sign of which depends on a quantum non-destructive (QND) measurement of the qubit.

[0030] Figure 6B shows additional implementation details of the design in Figure 6A, where the SFQ bias circuit is explicitly formed by two subcircuits, namely an SFQ generator and an SFQ comparator. The SFQ generator provides SFQ bias to two inductors L1 and L2, which are coupled to a symmetric RF-SQUID. In this implementation, the SFQ generator can be implemented as two separate SFQ generators, each driving the two inductors L1 and L2 independently, resulting in one SFQ bias circuit per inductor. In this embodiment, the SFQ generator is also synchronized to a readout pulse generator to provide precise timing for the SFQ bias pulse and to change the potential shape at opportune moments. As shown, the readout pulse generator produces readout pulses to the qubit for readout operations.

[0031] The SFQ comparator in Figure 6B of the SFQ bias circuit is provided to read the sign of the current in the common inductor L of the symmetric RF-SQUID, the sign of which depends on the quantum non-destructive (QND) measurement of the qubit.

[0032] Figure 6C shows a single measurement of the qubit across different stages in time. In this measurement, the potential starts from the RESET condition, and the applied magnetic flux is zero. Next, the potential of the symmetric RF SQUID is prepared (READY) to start from an impedance condition that will maximize the current flowing from the readout pulse into the common inductor of the symmetric RF SQUID. The READOUT pulse is sent to the qubit and eventually reaches the symmetric RF-SQUID, causing the phase particle to start oscillating depending on the phase of the readout pulse, encoding the measurement result of the qubit. The potential of the symmetric RF SQUID changes after time t0 from the start of the readout pulse, and then the phase particle descends onto either the left or right depression. This process effectively digitizes the measurement result of the qubit. The position of the phase particle is sensed by a subcircuit of the SFQ comparator. The protocol can then be restarted again, directly from the harmonic case.

[0033] Figure 7A shows an embodiment of another design of an RF SQUID readout circuit, which involves two RF SQUIDs and two independently adjustable bias current circuits to reduce the asymmetry between the two RF SQUIDs in an actual device based on the symmetric design of FIG. 2. FIG. 7B shows a conceptual layout of the physical components of a demonstration method by which these two biases can be coupled to the loops of the two RF SQUIDs of a symmetric RF SQUID. Two independently adjustable DC bias circuits may be implemented by including two independent DC current generators i1 and i2 that are coupled to two RF SQUID devices to apply two DC magnetic fluxes φ1 and φ2, respectively, to bias the RF SQUID readout circuit at a desired operating point that can compensate for the asymmetry between the two RF SQUID devices. I C whereas, I C1 and I C2 are assumed to be the nominal desired values of the critical currents of the two RF SQUID devices that exhibit actual critical currents at I C =I C1 -I C2 represents the difference in their individual critical currents and takes into account the asymmetry due to processing or other factors in a practical device. The corresponding magnetic flux biases provided by the two independent DC current generators i1 and i2 are φ1 and φ2, respectively. These magnetic flux biases can be used to prepare the circuit in an optimal "ready" configuration, as shown in FIG. 6C.

[0034] Considering a critical current asymmetry of ΔI C / I C = ±10%, the PSCAN2 circuit simulation is used to find a combination of DC magnetic fluxes φ1 and φ2 that reduces the circuit behavior of the undesired asymmetry of the circuit and can achieve or approach the desired behavior of the readout system. The simulation results of the inventors are shown in FIGS. 7C and 7D.

[0035] Figure 7C shows ΔI C / I C The simulation for =0% is shown, and in this case, the region of DC flux bias for the device in Figure 7A that is necessary for it to work properly is marked in yellow. For an identical junction, the region of flux (yellow) where the device works as intended is symmetric with respect to the vertical axis, and there is no need to apply a DC bias, i.e., the value for (φ1-φ2) / π is zero.

[0036] Figures 7D and 7E show ΔI, respectively. C / I C Figure 2 shows a similarly designed device exhibiting a critical current difference of ±10%. In the case of non-identical junctions, shown in Figure 7C with a -10% difference and Figure 7E with a +10% difference, the region of flux (yellow) where the device works as intended is asymmetrical. Here, it can be seen how the difference between the two junctions can be compensated by applying a differential flux bias (φ1-φ2) / π with a suitable sign and value to restore the optimal DC bias point, ensuring accurate operation of the readout device.

[0037] In the implementation of the bias circuit, the DC current bias that generates the flux value may be calibrated only once (to have the most symmetrical and harmonic potential shape in the “ready” configuration of Figure 6C). These calibrated DC flux biases can potentially be generated locally by an SFQ superconducting network located on a classical chip (as shown in Figures 8A-8C) or by a low-temperature CMOS chip located at the 4K stage. Fast flips will still be provided by an additional “fast flux line” driven by an SFQ pulse generator.

[0038] The above features of a quantum computing system, including a symmetric RF SQUID readout circuit, can be used to implement a computing or information processing system with a superconducting-based quantum computing module (e.g., a superconducting Josephson junction). Such a system can combine quantum computing modules or devices with classical digital computing modules or devices by strategically dividing the system into different quantum and classical digital computing modules, devices, or components at different cryogenic stages and different cryogenic temperatures, in a manner that enables the system to be scalable for complex computing applications and to achieve superconducting conditions at their cryogenic stages. Such implementations can be used to simplify and reduce the complex and bulky cryogenic systems commonly used in various quantum computer systems using superconducting quantum computing devices, and to reduce the use, or level of use, of complex superconducting cable systems for linking different computing or processing modules. Implementations of the disclosed technology can be designed to enable commercially scalable fabrication using IC fabrication processes and equipment when manufacturing critical modules or devices for quantum computer systems based on superconducting Josephson junctions.

[0039] Figures 8A, 8B, and 8C illustrate an embodiment of a quantum computing system based on the disclosed technology and an interconnection design for connecting different hardware modules within a multi-stage cryogenic system.

[0040] Figure 8A shows an embodiment of a quantum computing system 110 for producing a scalable hybrid quantum-classical computing system for commercial use. As its name implies, the quantum computing system 110 includes a plurality of qubit circuits, performs computational operations based on the quantum states of the qubit circuits, and communicates with an external computer or computing system 130 via a communication link or network 120. The communication link and network 120 may include circuits to which signals are transmitted in the form of electromagnetic signals, including electrical signals, carried, for example, by conductive wires and / or optical signals. During operation, the quantum computing system 110 receives computation requests or tasks from one or more external computers or computing systems 130, performs the requested computational operations, and returns the computation results to one or more requesting external computers or computing systems 130. The communication and / or interaction between the quantum computing system 110 and the external computers or computing systems 130 is via the communication link or network 120, which may constitute the longest communication cycle in time during the operation of the quantum computing system 110 and is labeled as a long communication link or loop. As will be further explained below, the quantum computing system 110 is structured to separate different internal computing modules, thereby enabling these internal computing modules to communicate via shorter internal communication links or loops, such as medium-length communication links or loops with moderate delays in time, and high-speed communication links or loops with the shortest possible delays in time.

[0041] The quantum computation system 110 includes a multi-stage cryogenic system to provide different cryogenic stages at different locations and maintain different modules or devices at different cryogenic temperatures to keep them at their respective desired temperatures (e.g., T1, T2, T3, and T4, as shown). In some implementations, the different cryogenic stages may be designed to produce temperatures from millikelvin to tens of kelvin. The exemplary system 110 includes a quantum computation module 102 which includes a plurality of qubit circuits or devices as a quantum qubit ensemble to perform a desired quantum computation operation through their separate qubit states. In many implementations, the quantum computation module 102 is engaged or coupled to a cryogenic stage at a low cryogenic temperature T1 to ensure that the qubit circuits or devices are under acceptable quantum computation operating conditions, under desired superconducting states and with sufficiently low noise and interference levels.

[0042] The qubit management circuit module 104 communicates with the quantum computation module 102, provides control signals to the individual qubit circuits or devices of the quantum computation module 102, and is provided for reading out individual qubit circuits or devices. It may be implemented by using non-quantum mechanical processing circuits such as digital circuits, analog circuits, or a combination of digital and analog circuits. In the implementation, the symmetric RF SQUID readout circuit and operation described in Figure 2-7E can be implemented as part of the qubit management circuit module 104.

[0043] The qubit management circuit module 104 may be implemented using a superconducting network and, in some implementations, is coupled to a cryogenic stage at a cryogenic temperature T2, which may be different from a low cryogenic temperature T1, or in other implementations, may be the same as temperature T1. As will be further described below, in some designs, the quantum computation module 102 and the qubit management circuit module 104 may be engaged to share a common cryogenic stage so that both modules are kept at the same cryogenic temperature. The qubit management circuit module 104 may be structured to include (1) a qubit control circuit for directing control signals to qubit circuits in order to control the qubit circuits, and (2) a qubit readout circuit for outputting readout signals from the qubit circuits, respectively. In this embodiment, quantum computation operations are performed within the quantum computation module 102 based on control signals from the qubit management circuit module 104 to the qubit circuit, and the reading of the qubit circuit is performed by the qubit management circuit module 104. Therefore, the quantum computation module 102 and the qubit management circuit module 104 together partially form the “heart” or “core” of the quantum computation system 110. Communication between the quantum computation module 102 and the qubit management circuit module 104 is essential to quantum computation operations in terms of the quality and speed of such communication. Therefore, in the implementation, the quantum computation module 102 and the qubit management circuit module 104 may be installed or positioned in close proximity or adjacent to each other to shorten the signal path between the two modules 102 and 104 and reduce any interference or noise to such communication. In addition, the functions or operations of the qubit management circuit module 104 may be intentionally limited to certain core functions or operations in relation to quantum computation performed by the quantum computation module 102, thereby enabling the qubit management circuit module 104 to achieve short or fast response or processing times and ensuring fast input / output signaling in the quantum computation module 102.The consideration of this intentionally reduced functional design for the qubit management circuit module 104 is also based on the desire to reduce power consumption and energy dissipation to its surroundings by the qubit management circuit module 104 in light of its proximity to the quantum computation module 102, the desire to reduce noise or interference from the qubit management circuit module 104 to the quantum computation module 102, and the need to maintain appropriate cryogenic conditions for both the qubit management circuit module 104 and the adjacent quantum computation module 102. Based on the above and other considerations, the interconnection and signal paths between the two modules 102 and 104 are designed to form a high-speed communication link or loop with the shortest possible delay in time to the quantum computation system 110. For example, in some implementations, the quantum computation module 102 may include at least one integrated chip supporting one or more qubit circuits, and the qubit management circuit module 104 may be formed on another integrated chip, mechanically or electrically coupled to the integrated chip with the qubit circuits as a multi-chip module via superconducting bumps, capacitive coupling, or magnetic coupling over a vacuum, and transfer control and read signals between them. The multi-chip module formed by the two modules 102 and 104 can be coupled to the same cryogenic stage at low cryogenic temperatures T1. The design may be commercially important because the chip fabrication for the multi-chip module formed by the two modules 102 and 104 is a scalable platform that allows a wide range of qubit circuits to be fabricated and incorporated into the quantum computation module 102, and similarly, the qubit management circuit module 104 can also be scaled based on the number of qubit circuits present.

[0044] The quantum computing system 110 in Figure 8A further includes a digital processing module 106 that provides certain signal and data processing functions or operations to the quantum computing system 110 in relation to quantum computing, which is performed by the quantum computing module 102 via a qubit management circuit module 104. In this regard, the digital processing module 108 forms a core processing module for non-quantum computing and / or processing functions within the quantum computing system 110 and is therefore designed with a much more complex network and higher processing power than the qubit management circuit module 104. Specifically, certain functions and / or processing operations that cannot be built into the qubit management circuit module 104 may be included in the network of the digital processing module 108. In addition, the digital processing module 108 also functions as an interface between the quantum computing system 110 and one or more external computers or computing systems 130 via a communication link or network 120. As such, the digital processing module 108 is designed to further include processing functions associated with communication and interaction between the quantum computing system 110 and the external computers or computing systems 130. Therefore, unlike the installation and design of the qubit management circuit module 104, the digital processing module 108 is complex and designed to be a classical counterpart and coprocessor to the quantum computation module 102 of the quantum computation system 110. The increased functions and / or processing operations, as well as processing power, packed into the digital processing module 108 add complexity and size to the circuitry of the digital processing module 108, further increasing its power consumption and energy dissipation. Therefore, in order to reduce the noise and interference that the digital processing module 108 may impose on the quantum computation module 102, it is desirable to install the digital processing module 108 physically separated from the quantum computation module 102 and its adjacent neighboring qubit management circuit module 104.The digital processing module 108 may be designed with various functions and capabilities, including, for example, error correction functions for the quantum computing system 110, as well as non-quantum computation and / or processing functions within the quantum computing system 110, including functions related to the control and readout of the quantum computing module 102, performed, for example by the qubit management circuit module 104, and data management for quantum computations, performed by the quantum computing module 102. In some implementations, the digital processing module 106 may be coupled to the cryogenic stage at a higher temperature T4 than that for the quantum computing module 102 (at T1) and the qubit management circuit module 104 (at T2). The digital processing module 108 may be designed to include a superconducting network and be enclosed within the multi-stage cryogenic system of the quantum computing system 110.

[0045] The intentional design to position the digital processing module 108 separately from the qubit management circuit module 104 results in a longer signal path or link between the digital processing module 108 and the qubit management circuit module 104. Within the enclosure of the multi-stage cryogenic system, such a signal path or link may be formed by using superconducting wires or cables. In particular, the long length of such a signal path or link may cause some degree of signal degradation, and one option to address this is to add one or more interconnection repeaters or signal conditioning circuits 106 between the digital processing module 108 and the qubit management circuit module 104 to adjust the signals. As with other modules in the multi-stage cryogenic system, each interconnection repeater or signal conditioning circuit 106 may engage or couple with the cryogenic stage at a temperature T3 that is higher than the temperature of the qubit management circuit module 104 (at T1 or T2) and lower than the temperature of the digital processing module 108 (at T4). For example, the digital signal adjustment circuit module 106 may include a superconducting circuit that adjusts control or readout signals.

[0046] The combination of positioning the digital processing module 108 separately from the qubit management circuit module 104 and the complex circuitry and processing operations within the digital processing module 108 leads to longer time or delays in the internal communication link or loop between the digital processing module 108 and the qubit management circuit module 104. As indicated in Figure 8A, such an internal communication link or loop between the digital processing module 108 and the qubit management circuit module 104 forms a moderate communication link or loop with a moderate time delay, which is longer than the delay in the high-speed communication link or loop between the qubit management circuit module 104 and the quantum computation module 102, and shorter than the delay in the long communication link or loop between the digital processing module 108 and the external computer or computation system 130 via the communication link or network 120.

[0047] Accordingly, the embodiment of the quantum computing system 110 in Figure 8A includes special design features that provide a hybrid computing environment that combines processing functions and / or operations by a quantum computing portion (e.g., a quantum computing module 102) and a non-quantum classical processing portion (e.g., a qubit management circuit module 104 and a digital processing module 108), strategically partitioning and distributing different amounts and types of processing functions and / or operations of the non-quantum classical processing portion between the qubit management circuit module 104 and the digital processing module 108, in light of the intentional design to place the qubit management circuit module 104 in physical proximity to the quantum computing module 102, while placing the quantum computing module 102 away from the digital processing module 108.

[0048] In various implementations, the quantum computation module 102 and the non-quantum classical processing parts (e.g., the qubit management circuit module 104 and the digital processing module 108) are structured to include superconducting circuits or devices coupled to different cryogenic stages of a multi-stage cryogenic system, and superconducting interconnect wires 112, 114, and 116 are provided and maintained at different temperatures in different locations for transferring signals between different modules or stages. The multi-stage cryogenic system for the quantum computation system 110 may be implemented in various configurations, including a multi-stage dilution refrigerator designed on a helium-3 and helium-4 mixture to provide different cryogenic stages at different graded cryogenic temperatures. In some implementations, the cryostat system may include a nuclear demagnetizing refrigerator or an adiabatic demagnetizing refrigerator.

[0049] Modules within the quantum computing system 110 may be implemented in various configurations. For example, each qubit circuit for a qubit in the quantum computing module 102 may include a superconducting Josephson junction circuit or a switching superconducting circuit that is different from a Josephson junction circuit. For example, the qubit management circuit module 104 may be implemented to include a superconducting Josephson junction circuit or a single-flux quantum (SFQ) logic circuit or a quantum flux parametron circuit such as an adiabatic quantum flux parametron circuit, or a nanowire switch, or a superconducting ferromagnetic transistor, or a superconducting spintronic device, or a field-effect superconducting device. The digital processing module 108 may be implemented to include an SFQ network, a field-programmable gate array (FPGA), or one or more application-specific integrated circuits (ASICs).

[0050] In some implementations, the quantum computing system 110 may further include a digital processing subsystem outside the multi-stage cryogenic system or cryostat system to perform operations associated with communicating with a digital processing module 108 and assisting in the execution of quantum or quantum-classical algorithms and / or communication with one or more other computers or networks 130. This digital processing subsystem outside the cryostat system may include one or more CMOS digital processors, one or more field-programmable gate arrays (FPGAs), one or more application-specific integrated circuits (ASICs), or one or more central processing units (CPUs).

[0051] In the system of Figure 8A, an optical communication link may be used for signal transmission either as a replacement for a conductive wire or cable, or as an additional link in combination with a conductive wire or cable. The optical communication link can provide faster data transmission and increase communication bandwidth. For example, optical communication can be used between a cryogenic stage (e.g., module 108 in Figure 8A) and a room temperature stage, accompanied by a highest temperature stage. In the implementation, optical transmitter and receiver devices are provided in such a stage or circuit module to enable the transmission and reception of optical signals between the cryogenic stage, which is placed at the highest temperature of the cryostat system, and room temperature electronic equipment to provide communication between them. In Figure 1B, such an optical communication link is provided between module 108 and CMOS It may also be implemented between the FPGA subsystem and the subsystem.

[0052] Figure 8B shows an embodiment of a quantum computing system that uses the quantum states of qubits and is capable of information processing based on quantum computation, at least in part, using the design of Figure 8A. The cryostat system of this embodiment is structured and operable to provide different cryogenic stages at different temperatures of 20 mK, 0.1 K, 0.7 K, and 3 K. Different circuit modules at different cryogenic stages are interconnected by superconducting wires such as NbTi / Kapton strips. Surrounded by the cryostat system, the quantum computing module includes a first integrated chip structured to support qubit circuits. Each qubit circuit is structured as a superconducting circuit, exhibits a different quantum state as a qubit, and interacts quantum mechanically with other qubit circuits via quantum entanglement, causing superposition or correlation of different quantum states of the qubit circuits. A qubit management circuit module is located adjacent to the quantum computing module and coupled to be maintained at the same low cryogenic temperature as the quantum computing module. The qubit management circuit includes a second integrated chip, a qubit control circuit supported by the second integrated chip and structured to instruct the qubit circuit to control a control signal to the qubit circuit, and a qubit readout circuit supported by the second integrated chip and structured to output a readout signal from the qubit circuit. During operation, the readout signal represents the quantum state of the qubit circuit, and the qubit control circuit and the qubit readout circuit include superconducting circuits and are structured to operate using the control signal and the readout signal in a non-quantum classical manner based on digital processing. In particular, the second integrated chip engages with the first integrated chip to form a multi-chip module and transfers the control signal and the readout signal.

[0053] Figure 8C shows an embodiment for interconnection that links different hardware components of classical and quantum circuits. The system includes at least one classical non-quantum digital processing module 108 labeled as a "classical processor chip," at least one SFQ repeater as part of an interconnection network or module 104, and at least one classical superconducting controller as part of a qubit management circuit module 104, which controls a quantum computation processor or module 102 with multiple qubit circuits or devices.

[0054] The interconnection is designed with superconducting connection nodes or pads 140 and superconducting connection cables 150 for connecting classical circuits 104, 106, and 108 to the quantum computation processor or module 102. As illustrated, the superconducting connection nodes or pads 140 may be implemented as superconducting bumps that are in direct contact with one or more hardware components (102, 104, 106, 108) to be connected and can be used to provide connections between the hardware components and the superconducting cables. As illustrated with reference to Figure 7A, the quantum computation module 102 and the qubit management circuit module 104 can be installed adjacent to each other, allowing for short connection paths between them for high-speed inter-module communication and can be thermally coupled to the same cryogenic stage at the same low cryogenic temperature. In particular, the communication link or loop between the classical superconducting controller as part of the qubit management circuit module 104 and the quantum processor chip 102 should be a high-speed communication link or loop, and superconducting bumps can be used to interconnect the two modules 102 and 104 to enable high-speed exchange of information for quantum computation operations and readouts. In some implementations, the qubit management circuit module 104, which contains the classical controller chip, is positioned on a cooling plate of a cryocooler directly beneath the quantum computation module 102, which can reduce noise and interference to quantum computation operations by qubit circuits or devices inside the quantum computation module 102. In some implementations, superconducting bumps can be configured or used in the form of fences or walls that produce fragments or micro-fragment lines, or other on-chip transmission lines, as well as components that isolate qubits or systems of multiple qubits from one another, in order to reduce mutual crosstalk between superconducting elements or systems and to improve the quality factor of the resonator.

[0055] In addition to the direct electrical connection between the quantum computation module 102 and the qubit management circuit module 104, non-contact connections, including, for example, differential capacitive coupling and magnetic coupling between qubits and passive transmission lines, may be used to achieve high-speed communication, both of which provide a communication link without direct connection and allow for compensation of geometric mismatches between modules 102 and 104 and other components as a result of the manufacturing process.

[0056] Unlike deterministic Turing machines and classical computers based on Boolean bits with "0" and "1" states, the quantum computation operations performed by the qubit circuits or devices inside the quantum computation module 102 utilize quantum mechanical phenomena such as the superposition of "0" and "1" states, entanglement between qubits, and interference between the probability amplitudes of nondeterministic measurement results to carry out computational operations. The superconducting qubits inside the quantum computation module 102 can be implemented by superconducting Josephson junctions. A Josephson junction is a system of weakly coupled superconductors that exhibit correlated or coherent states and behaves similarly to a nonlinear inductor, enabling the construction of quantum nonharmonic oscillators. The two discrete energy level states of this nonharmonic oscillator and their quantum superposition are used to create qubits. Using Josephson junctions, several versions of superconducting qubits can be constructed, such as transmon, exmon, quantronium, flaxonium, and C-shunt flux qubits.

[0057] As explained above, the state of a qubit is controlled by the application of a microwave signal or by a digital SFQ pulse sequence. Typically, the microwave signal generator is a room-temperature device, but the quantum circuit, which contains the qubit, operates at very low cryogenic temperatures to reduce unwanted decoherence of the qubit. However, the wiring required to supply the microwave signal and extending from room temperature to the low-temperature stage where the quantum circuit resides occupies a lot of space, causing electrical noise and excessive thermal load, which leads to decoherence and raises significant problems for scaling up quantum computers. To overcome this problem, various techniques may be used to control qubits in fully integrated cryogenic and hybrid quantum classical processors, such as those shown in Figures 14A-14C, for example, the integration of superconducting qubits with classical superconducting digital logic families such as reciprocal quantum logic (RQL) disclosed by Quentin P. Herr and Anna Y. Herr in "Ultra-low-power superconductor logic" J. Appl. Phys. 109, 103903 (2011), the use of adiabatic quantum flux parametrons (AQFP) by O. Chen, R. Cai, Y. Wang, F. Ke, T. Yamae, R. Saito, N. Takeuchi, and N. Yoshikawa in "Adiabatic Quantum-Flux-Parametron: Towards Building Extremely Energy-Efficient Circuits and Systems" Sci. Rep. 9, 10514 (2019), or "Energy-Efficient Single Flux Quantum Technology” This includes the use of energy-efficient single-flux quantum (SFQ) techniques, including eSFQ and ERSFQ, as described by OA Mukhanov in IEEE Trans. Appl. Supercond. 21, 760 (2011). As part of the interconnection design for the system in Figures 14A–14C, qubit control can be implemented via an SFQ system for controlling the qubit state by applying a sequence of SFQ pulses, without the conventional use of microwave signals as disclosed in U.S. Patent No. 9,425,804. Techniques for applying magnetic flux to quantum coherent superconducting circuits, as described in U.S. Patent Application Publication 2015 / 0263736A1, may also be implemented. Qubit readout may be implemented by quantum electrodynamic measurements, as disclosed in U.S. Patent No. 9,692,423. Cryogenic CMOS (cryoCMOS) techniques may also be implemented, for example, in the system in Figures 7A–7C, including the control of superconducting qubits. "Cryo-CMOS for quantum computing" Technical Digest - E. Charbon, F. Sebastiano, A. Vladimirescu, H. Homulle, S. Visser, L. Song, and RM Incandela. International Electron Devices Meeting, IEDM (2017), pp. 1-13. doi: 10.1109 / IEDM.2016.7838410, and JC Bardin, E. Jeffrey, E. Lucero, T. Huang, O. Naaman, R. Barends, T. White, M. Giustina, D. Sank, P. Roushan, K. Arya, B. Chiaro, J. Kelly, J. Chen, B. Burkett, Y. Chen, A. Dunsworth, A. Fowler, B. Foxen, C. Gidney, R. Graff, P. Klimov, J. Mutus, M. McEwen, A. Megrant, M. Neeley, C. See "A 28nm Bulk-CMOS 4-to-8GHz 2mW Cryogenic Pulse Modulator for Scalable Quantum Computing" by Neill, C. Quintana, A. Vainsencher, H. Neven, and J. Martinis, IEEE J. Solid-St. Circuits 54, 3043-3060 (2019).

[0058] Practical implementation of the systems in Figures 8A–8C requires careful design of the interconnection or interface between the quantum device, which is placed at millikelvin temperature, and the classical processing circuit, which is placed at liquid helium temperature. The interconnection in the embodiment of Figure 8C involves placing the quantum computation module 102 and the qubit management circuit module 104 adjacent to each other on the same cryogenic stage of the dilution refrigerator, without using any superconducting cables or wires 150 between modules 102 and 104. Instead, superconducting bumps or pads 140 are used to physically join or fasten the two modules 102 and 104 together. Signal paths between the two modules 102 and 104 can be implemented in various ways, including signal transduction via a conductive path formed through the superconducting bumps or pads 140 between modules 102 and 104, or signal transduction via capacitive and / or magnetic coupling between modules 102 and 104. The signal path between the two modules 102 and 104 is designed to minimize signal transmission time (for example, by reducing or eliminating the amount of wiring between modules 102 and 104) and to form a high-speed communication link or loop within the system as described above with respect to Figure 8A.

[0059] In a configuration where two modules 102 and 104 are supported by two IC chips and the two chips are coupled together as an integrated unit in the same low cryogenic stage, they can be stacked and bonded together to form a multi-chip module (MCM), so that modules 102 and 104 both operate under the same low cryogenic conditions. Superconducting bumps or pads 140 may be used as part of the fastening of the two IC chips. The interconnection in the embodiment of Figure 8C also implements a combination of superconducting bumps or pads 140 and superconducting cables or wires 150, where the superconducting bumps or pads 140 are used at the terminals of the superconducting cables or wires 150 to connect the wire terminals to the device. For example, Figure 8C shows that the qubit management circuit module 104 of Figure 8C is connected to an interconnection network or module 106, such as a digital signal conditioning circuit module, via a superconducting cable or wire 150, with two sets of superconducting bumps or pads 140 used to splice the two end terminals of each superconducting cable or wire 150 to contact points on the qubit management circuit module 104 and the corresponding interconnection network or module 106. The use of superconducting bumps or pads 140 and superconducting cables or wires 150 can be applied to connections between digital processing modules 108 and the corresponding interconnection network or module 106, and to connections to other modules, such as connections between different stages of the interconnection network or module 106 or between digital signal conditioning circuit modules. As illustrated, such superconducting cables or wires 150 with superconducting bumps or pads 140 constitute part of a medium-length communication link and loop, as described above with respect to Figure 8A.

[0060] The above embodiments relating to the disclosed quantum computing system provide a unique interconnection design for different modules and enable practical and scalable implementations based on a novel system and interconnection design by reducing complex wiring involving numerous wires extending from room temperature to the low-temperature stage where the quantum chip is located. The disclosed system and interconnection will enable the quantum computing system to be scaled for different applications using different quantum computing powers. In the implementation, qubit control can be implemented by placing an SFQ control chip in close proximity to the quantum circuit chip, with a suitable interconnection that operates by SFQ control and at different cryogenic temperatures, e.g., from liquid He temperature for classical non-quantum processing circuits or modules to millikelvin temperature for the qubits of one or more quantum circuits or processors.

[0061] This patent document contains many details, which should be interpreted not as limitations on the scope of any subject matter or claimed, but rather as descriptions of features that may be specific to particular embodiments of a particular technique. In the context of a separate embodiment, certain features described in this patent document may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately in multiple embodiments or in any preferred secondary combination. Furthermore, features are described above as acting in a combination and may be initially claimed as such, but in some cases one or more features from a claimed combination may be excluded from the combination, and the claimed combination may also cover secondary combinations or variations of secondary combinations.

[0062] Only a few implementations and embodiments are described, but other implementations, improvements, and modifications can be made based on those described and illustrated in this patent document. The claims made are explained and illustrated, and include the following:

Claims

[Claim 1] The invention described herein.

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