Semiconductor equipment

Abstract

During the memory retention period, the memory contents can be retained even when power is not supplied. Furthermore, to provide a new semiconductor device with no limit on the number of write cycles. [Solution] The device comprises a transistor and a capacitive element, wherein the transistor is a first oxide semiconductor A body layer, a source electrode and a drain electrode in contact with the first oxide semiconductor layer, and the first oxide A gate electrode overlapping the semiconductor layer, and a gate electrode provided between the first oxide semiconductor layer and the gate electrode. The capacitive element has a gate insulating layer and a source electrode or drain electrode, and the source electrode Alternatively, a second oxide semiconductor layer in contact with the drain electrode, and a capacitor in contact with the second oxide semiconductor layer. It is a semiconductor device having element electrodes.

Description

[Technical Field]

[0001] The disclosed invention relates to a semiconductor device utilizing a semiconductor element and a method for driving the same. ru. [Background technology]

[0002] Memory devices using semiconductor elements are volatile, meaning that the stored data is lost when the power supply is cut off. They can be broadly classified into two types: physical data and non-volatile data, which retains its contents even when the power supply is cut off. .

[0003] A typical example of a volatile memory device is DRAM (Dynamic Random Access Memory). DRAM has a memory (cess memory). DRAM selects transistors that make up the memory elements. By accumulating electric charge in a capacitive element, information is stored.

[0004] Based on the principle described above, in DRAM, when information is read, the charge of the capacitive element is lost, therefore the information Each time data is read, a write operation is required again. Also, the transistors that make up the memory element In a zista, the leakage current (off current) between the source and drain in the off state is due to... Even when a transistor is not selected, charge flows out or in, so the data The retention period is short. Therefore, a write operation (refresh operation) is required at predetermined intervals. It is essential, and reducing power consumption is difficult. Also, if the power supply is cut off, memory will be lost. Because the capacity is lost, other memory devices using magnetic or optical materials are needed for long-term memory retention. Installation is required.

[0005] Another example of volatile memory is SRAM (Static Random Access Memory). (Memory). SRAM uses circuits such as flip-flops to store the stored content and does not require a refresh operation, which is advantageous over DRAM in this regard . However, since circuits such as flip-flops are used, there is a problem that the unit price per storage capacity becomes high . Also, in terms of the stored content being lost when the power supply is cut off, there is no difference from DRAM .

[0006] A typical example of a non-volatile memory device is a flash memory. A flash memory has a floating gate between the gate electrode and the channel formation region of a transistor, and stores data by holding charges in the floating gate. Therefore, the data retention period is extremely long (semi-permanent), and it has the advantage that the refresh operation required for volatile memory devices is unnecessary (for example, see Patent Document 1) . . . .

[0007] However, since the gate insulating layer constituting the memory element deteriorates due to the tunnel current generated during writing, there is a problem that the memory element stops functioning after a predetermined number of writes . . To mitigate the influence of this problem, for example, a technique for equalizing the number of write operations of each memory element is adopted. However, to realize this, complex peripheral circuits are required . Therefore, even if such a technique is adopted, the fundamental lifetime problem is not solved . That is, flash memory is not suitable for applications where the information rewrite frequency is high .

[0008] Also, in order to inject charges into the floating gate or remove the charges, a high voltage is required, and a circuit for that is also required. Furthermore, for the injection of charges . Alternatively, removal can take a relatively long time, and speeding up writing and erasing is not easy. That's another problem. [Prior art documents] [Patent Documents]

[0009] [Patent Document 1] Japanese Patent Publication No. 57-105889 [Overview of the Initiative] [Problems that the invention aims to solve]

[0010] In view of the above-mentioned problems, in one aspect of the disclosed invention, power is not supplied during the memory retention time. A new structure that can retain memory content even in difficult situations and has no limit on the number of write cycles. One of the objectives is to provide semiconductor devices. [Means for solving the problem]

[0011] The disclosed invention provides a material that can sufficiently reduce the off-current of a transistor, for example For example, a semiconductor device is constructed using oxide semiconductor material, which is a wide-bandgap semiconductor. By using semiconductor materials that can sufficiently reduce the off-current of the inverter, long-term operation is possible. It is possible to retain information over a long period of time. Furthermore, oxide semiconductor materials have a high dielectric constant. Therefore, by using oxide semiconductor materials as the dielectric of the capacitive element, the capacitance per unit area can be increased. It is possible to enlarge it.

[0012] One aspect of the present invention comprises a transistor and a capacitive element, wherein the transistor has a gate electrode And, the gate insulating layer on the gate electrode, and the first oxide that overlaps with the gate electrode on the gate insulating layer A semiconductor layer and a first oxide semiconductor layer electrically connected to the first oxide semiconductor layer The capacitive element has a source electrode and a drain electrode, and the source electrode or drain electrode is the same A first electrode consisting of a conductive layer, a second oxide semiconductor layer in contact with the first electrode, and a second This semiconductor device has a second electrode in contact with an oxide semiconductor layer.

[0013] Another aspect of the present invention comprises a transistor and a capacitive element, wherein the transistor is a gate An electrode, a gate insulating layer on the gate electrode, and a first acid overlapping the gate electrode on the gate insulating layer. An oxide semiconductor layer and a first oxide semiconductor layer that are electrically connected to the first oxide semiconductor layer. Source electrode and drain electrode, first oxide semiconductor layer, source electrode, drain The device has an insulating layer on the electrode and an electrode that overlaps with a first oxide semiconductor layer on the insulating layer, and is a capacitive element This comprises a first electrode, a second oxide semiconductor layer in contact with the first electrode, and the second oxide semiconductor layer A second electrode, which is in contact with the source electrode or drain electrode and is made of the same conductive layer as the source electrode, is provided. It is a semiconductor device.

[0014] Another aspect of the present invention comprises a transistor and a capacitive element, wherein the transistor is a source Electrodes and drain electrodes, and on the source electrode and drain electrode, source electrode and drain A first oxide semiconductor layer electrically connected to the in electrode, and a gate on the first oxide semiconductor layer. It has a gate insulating layer and a gate electrode that overlaps with a first oxide semiconductor layer on the gate insulating layer, The element comprises a first electrode made of the same conductive layer as the source electrode or drain electrode, and a first A second oxide semiconductor layer in contact with the electrode, and a second electrode in contact with the second oxide semiconductor layer, It is a semiconductor device.

[0015] Furthermore, a metal oxide layer may be provided between the first electrode and the second oxide semiconductor layer. .

[0016] Furthermore, a metal oxide layer may be provided between the second electrode and the second oxide semiconductor layer. .

[0017] Furthermore, the gate electrode is composed of an In-Ga-Zn-ON compound conductor. That's good too.

[0018] Furthermore, the second oxide semiconductor layer consists of silicon, germanium, cerium, titanium, and tungsten. One or more of the following elements: tene, aluminum, copper, yttrium, lanthanum, vanadium to 1 × 10 20 atoms / cm 3 The above may also be included.

[0019] Furthermore, the first oxide semiconductor layer and the second oxide semiconductor layer are non-single crystals, and the ab-plane From this perspective, it has a triangular or hexagonal atomic arrangement, and along the c-axis, it is a metallic element. An oxide semiconductor containing a layered or layered arrangement of metal and oxygen elements, It is a non-single crystal having a triangular or hexagonal atomic arrangement when viewed from the ab plane, and The c-axis includes phases in which metallic elements are arranged in layers, or in which metallic elements and oxygen elements are arranged in layers. It may also contain an oxynitride semiconductor.

[0020] Furthermore, the drive circuit, which includes a transistor, a capacitive element, and a material other than an oxide semiconductor, is also composed of a transistor. It may have a road.

[0021] In addition, in the above, an oxide semiconductor may be used to construct a transistor, but disclosure The invention is not limited to this. Materials that can achieve off-current characteristics equivalent to oxide semiconductors, For example, wide-bandgap semiconductor materials with an energy gap Eg greater than 3 electron volts ( More specifically, materials such as silicon carbide may be used.

[0022] In this specification, the terms "above" and "below" refer to the relative positions of the constituent elements, such as "directly above" or This does not necessarily mean "directly below". For example, "gate electrode on the gate insulating layer". If the expression is ", then exclude those that include other components between the gate insulating layer and the gate electrode. do not have.

[0023] Furthermore, in this specification, the terms "electrode" and "wiring" do not limit the functionality of these components. It is not fixed. For example, "electrode" can be used as part of "wiring". The reverse is also true. Furthermore, the terms "electrode" and "wiring" can refer to multiple "electrodes" and "wiring". This also includes cases where the "lines" are formed as a single unit.

[0024] Furthermore, the "source" and "drain" functions are used when employing transistors with different polarities. However, this can change when the direction of current changes during circuit operation. In this specification, the terms "source" and "drain" may be used interchangeably. It is assumed that this is possible.

[0025] In this specification, etc., "electrically connected" means "having some kind of electrical effect." This includes cases where the connection is made via ". Here, "something that has some electrical effect" The term "connection" is not particularly limited as long as it enables the exchange of electrical signals between connected objects.

[0026] For example, "things that have some kind of electrical effect" include electrodes and wiring, as well as transistors. Switching elements, resistive elements, inductors, and other elements with various functions, etc. It is included. [Effects of the Invention]

[0027] Transistors using oxide semiconductors have extremely low off-currents, so we decided to use them. It is possible to retain memory content for an extremely long period of time. In other words, refresh function This eliminates the need for manual operation, or makes it possible to significantly reduce the frequency of refresh operations. Therefore, power consumption can be reduced. Also, in the absence of power supply (however, the potential is Even if it is desirable that the memory contents be fixed, it is possible to retain the memory contents over a long period of time. It is possible.

[0028] Furthermore, because oxide semiconductor materials have a high dielectric constant, oxide semiconductor materials can be used as dielectrics for capacitive devices. By using this, it is possible to increase the volume per unit area. Because the area of ​​the individual elements is reduced, high integration becomes possible, and semiconductor devices can be miniaturized. It is possible to further reduce power consumption by decreasing the frequency of refresh operations. That is the case.

[0029] Furthermore, the semiconductor device according to the disclosed invention does not require a high voltage for writing information, and There are no issues with degradation of the child. For example, unlike conventional non-volatile memory, it does not use floating gates. Because there is no need to inject electrons into it or extract electrons from the floating gate, Problems such as deterioration of the gate insulating layer do not occur at all. In other words, the semiconductor according to the disclosed invention. The device does not have the limitations on the number of rewrite cycles that are a problem with conventional non-volatile memory, and Reliability improves dramatically. Furthermore, the on and off states of the transistors allow information to be transmitted. Because writing is performed, high-speed operation can be easily achieved. Also, to erase information Another advantage is that it requires no action.

[0030] Furthermore, transistors using materials other than oxide semiconductors can operate at sufficiently high speeds. Therefore, it is possible to suitably realize various circuits (logic circuits, drive circuits, etc.) that require high-speed operation. It is possible.

[0031] Therefore, transistors using materials other than oxide semiconductors (transistors using oxide semiconductors) Peripheral circuits such as drive circuits using transistors (which can operate at higher speeds than DISTAs), and oxidation By integrating a transistor using a semiconductor and a memory circuit using a capacitive element, This makes it possible to realize semiconductor devices with unprecedented features. [Brief explanation of the drawing]

[0032] [Figure 1] Cross-sectional view of a semiconductor device. [Figure 2] Cross-sectional view of the manufacturing process for semiconductor devices. [Figure 3] Cross-sectional view of the manufacturing process for semiconductor devices. [Figure 4] Cross-sectional view of a semiconductor device. [Figure 5] Cross-sectional view of the manufacturing process for semiconductor devices. [Figure 6] Cross-sectional view of the manufacturing process for semiconductor devices. [Figure 7] Cross-sectional view of a semiconductor device. [Figure 8] Cross-sectional view of a semiconductor device. [Figure 9] Cross-sectional view, plan view, and circuit diagram of a semiconductor device. [Figure 10] Cross-sectional view and conceptual diagram of a semiconductor device. [Figure 11] Cross-sectional view of a semiconductor device. [Figure 12] Cross-sectional view of a semiconductor device. [Figure 13] Circuit diagram of a semiconductor device. [Figure 14] Block diagram of a semiconductor device. [Figure 15] Block diagram of a semiconductor device. [Figure 16] Block diagram of a semiconductor device. [Figure 17] A diagram illustrating electronic devices using semiconductor devices. [Figure 18] A diagram illustrating the evaluation method for semiconductor layers. [Figure 19] A figure showing the results of the CV measurement. [Figure 20] A figure showing the results of the CV measurement. [Modes for carrying out the invention]

[0033] An example of an embodiment of the present invention will be described below with reference to the drawings. However, the present invention is as follows The description is not limited to the present invention, and without departing from the spirit and scope of the present invention, its form and Those skilled in the art will readily understand that the details can be modified in various ways. Therefore, the present invention is as follows: The description of the embodiment shown is not to be limited to the content described therein.

[0034] Note that the position, size, and scope of each component shown in the drawings, etc., are for ease of understanding. The position, size, and range of the edges may not be shown. Therefore, the disclosed invention is not necessarily However, this is not limited to the location, size, and scope disclosed in drawings, etc.

[0035] Furthermore, the ordinal numbers such as "1st," "2nd," and "3rd" used in this specification, etc., are intended to avoid confusion of constituent elements. This is added to avoid any misunderstandings and does not mean that the number is limited.

[0036] (Embodiment 1) In this embodiment, the configuration of a semiconductor device according to one aspect of the present invention and the method for manufacturing the same are described. This will be explained with reference to Figures 1 to 3.

[0037] <Cross-sectional configuration of a semiconductor device> Figure 1 shows an example of the configuration of a semiconductor device. Figures 1(A) to 1(D) show cross-sections of the semiconductor device. As shown, the semiconductor device shown in Figures 1(A) and 1(C) has an oxide semiconductor in the channel formation region. It has a transistor 160 made of a material and a capacitive element 164 made of an oxide semiconductor as the dielectric. The semiconductor device shown in Figures 1(B) and 1(D) has an oxide semiconductor in the channel formation region. It has a transistor 162 using and a capacitive element 164 using an oxide semiconductor as the dielectric. .

[0038] Note that the above transistor will be described assuming it is an n-channel transistor, but p It goes without saying that channel-type transistors can be used. Also, the disclosure The technical essence of the Ming is that it uses an oxide semiconductor to hold information, transistor 160, Since it is used in the zista 162 and the capacitive element 164, the specific configuration of the semiconductor device is It is not necessary to limit ourselves to what is shown here.

[0039] In Figure 1(A), the transistor 160 has a gate electrode 14 provided on the insulating layer 140. 8a, a gate insulating layer 146 covering the gate electrode 148a, and a gate insulating layer 146 A first oxide semiconductor layer 144a overlapping the electrode 148a, and the first oxide semiconductor layer 144 a Source electrode or drain that is electrically connected to the first oxide semiconductor layer 144a on a It has a drain electrode 142b and a drain electrode or source electrode 142a. The inverter 160 is not limited to being provided on the insulating layer 140, but for example, on an insulating surface It may also be on a circuit board.

[0040] In Figure 1(A), the capacitive element 164 has a first electrode 148b and is in contact with the first electrode 148b. A second oxide semiconductor layer 144b and a source electric field in contact with the second oxide semiconductor layer 144b It has a source electrode or drain electrode 142b. Here, the source electrode or drain electrode 14 2b functions as the second electrode of the capacitive element 164.

[0041] In other words, it can also be said as follows: The capacitive element 164 is connected to the first electrode 148b, It has a second oxide semiconductor layer 144b and a second electrode. The second electrode is a source electrode It consists of the same conductive layer as the electrode or drain electrode 142b.

[0042] Furthermore, the work function of the first electrode 148b is determined by the electron affinity of the second oxide semiconductor layer 144b. It is preferable that the second oxide semiconductor layer 144b is In-Ga- When using Zn-O-based oxides, their electron affinity is approximately 4.6 electron volts. In addition, as a material whose work function is greater than the electron affinity of the second oxide semiconductor layer 144b, nitrogen Indium oxide, zinc nitride, nickel, molybdenum oxide, tungsten oxide, In-Ga- Examples include Zn-ON compound conductors.

[0043] (Work function of the first electrode 148b) - (Electron affinity of the second oxide semiconductor layer 144b) If the voltage is 0.5 electron volts or higher, preferably 1 electron volt or higher, in most cases the second acid No electrons flow into the oxide semiconductor layer 144b. In other words, the second oxide semiconductor layer 144b It exhibits sufficient insulating properties and can be used as a capacitive element.

[0044] (Work function of the first electrode 148b) - (Electron affinity of the second oxide semiconductor layer 144b) Even at temperatures above 0.5 electron volts, the material of the source electrode or drain electrode 142b may affect the voltage. Then, electrons are transferred from the source electrode or drain electrode 142b to the second oxide semiconductor layer 144b. Inflow can occur. This is because the work function of the source electrode or drain electrode 142b is This can occur when the electron affinity of the second oxide semiconductor layer 144b is smaller than that of the second oxide semiconductor layer 144b. In this case, the voltage applied to the first electrode 148b and the source electrode or drain electrode 142b Depending on the polarity of the voltage, it is also possible to make it function as a capacitive element without causing electron inflow. It is possible. However, the source electrode or drain electrode 142b is made of the same material as the first electrode 148b. If the materials listed above, or materials with an equivalent or better work function, are used, then the voltage and voltage It can be used as a capacitive element regardless of its polarity.

[0045] Here, the first oxide semiconductor layer 144a and the second oxide semiconductor layer 144b are hydrogen, etc. It is desirable that the impurities be sufficiently removed to achieve high purity. Furthermore, sufficient oxygen supply reduces the defect levels in the energy gap. It is preferable that the first oxide semiconductor layer 144a and the second The hydrogen concentration in oxide semiconductor layer 144b is 5 × 10⁻⁶ 19 atoms / cm 3 The following is preferable: 5 x 10 18 atoms / cm 3 The following is more preferable: 5 x 10 17 atoms / cm 3 The following applies. Note that the first oxide semiconductor layer 144a and the second oxide semiconductor layer 1 The hydrogen concentration in 44b was measured by secondary ion mass spectrometry (SIMS). Thus, in the first oxide semiconductor layer 144a and the second oxide semiconductor layer 144b in which the hydrogen concentration is sufficiently reduced and purified to high purity, and the defect levels in the energy gap due to oxygen deficiency are reduced by sufficient supply of oxygen, the carrier concentration is less than 1×10 / cm , preferably less than 1×1 0 / cm 12 , more preferably less than 1.45×10 3 / cm . For example, 11 the off-current (the value obtained by dividing the off-current by the channel width of the transistor) at room temperature is on the order of 10 zA / μm 3 to 100 zA / μm (1 zA (zeptoampere) is 1×10 10 A). Thus, by using an i-type (intrinsic) or substantially i-type oxide semiconductor, a transistor 160 with extremely excellent off-current characteristics can be obtained. Also, when the oxide semiconductor layer is i-type (intrinsic) or substantially i-type, the dielectric constant can be increased. Specifically, the relative dielectric constant of the In-Ga-Zn-O-based oxide semiconductor layer can be about 15. This is sufficiently higher compared to the relative dielectric constant of silicon oxide being about 4. Therefore, by using an i-type (intrinsic) or substantially i-type oxide semiconductor layer as the dielectric of the capacitor element 164, the capacitance per unit area of the capacitor element 164 can be increased.

[0046]

[0047] Also, the oxide semiconductor layer can be single crystal, polycrystalline (also referred to as polycrystal), or amorphous.

[0048]

[0049] Which state will it take?

[0048] Preferably, the oxide semiconductor layer is CAAC-OS(C Axis Aligned Cr This will be a ystalline oxide semiconductor layer.

[0049] The CAAC-OS layer is neither a perfect single crystal nor a perfect amorphous material. This is an oxide semiconductor layer with a crystalline-amorphous multiphase structure having a crystalline portion in an amorphous phase. The crystalline portion is often small enough to fit within a cube with sides less than 100 nm long. Transmission Electron Microscope (TEM) Observation images using a scope show the boundary between amorphous and crystalline parts in the CAAC-OS layer. It is not clear. Also, TEM reveals grain boundaries in the CAAC-OS layer. - Also known as. ) cannot be confirmed. Therefore, the CAAC-OS layer does not have electron transfer due to grain boundaries. The decrease in mobility is suppressed.

[0050] The crystalline portion contained in the CAAC-OS layer has a c-axis that is the normal vector to the surface on which the CAAC-OS layer is formed. Aligned in a direction parallel to the normal vector of the plane or surface, and viewed from a direction perpendicular to the ab plane, three It has a horn-shaped or hexagonal atomic arrangement, and when viewed from a direction perpendicular to the c-axis, the metal atoms are layered. Alternatively, metal atoms and oxygen atoms are arranged in layers. Note that between different crystalline regions, a The orientation of the axis and the b-axis may be different. In this specification, when simply referred to as perpendicular... This includes the range between 85° and 95°.

[0051] Furthermore, the distribution of crystalline regions in the CAAC-OS layer does not need to be uniform. For example, CAA In the formation process of the C-OS layer, when crystal growth is performed from the surface side of the oxide semiconductor layer, the shape The proportion of crystalline material may be higher near the surface compared to near the surface of the material. Also, CA By adding impurities to the AC-OS layer, the crystalline region in the impurity-added area becomes amorphous. It can also become qualitative.

[0052] The c-axis of the crystalline portion contained in the CAAC-OS layer is the normal vector to the surface on which the CAAC-OS layer is formed. Because it aligns in a direction parallel to the normal vector of the surface or the layer, the shape of the CAAC-OS layer (formed Depending on the cross-sectional shape of the surface or face, they may face in different directions. Oh, the direction of the c-axis of the crystalline portion is the normal vector to the surface when the CAAC-OS layer is formed. The direction is parallel to the normal vector of the crystalline or surface. The crystalline portion is formed by deposition, and It is formed by performing crystallization treatments such as heat treatment after film formation.

[0053] Transistors using a CAAC-OS layer exhibit changes in electrical properties due to irradiation with visible or ultraviolet light. It is possible to reduce this. Therefore, the transistor in question is highly reliable.

[0054] Furthermore, some of the oxygen constituting the oxide semiconductor layer may be replaced with nitrogen.

[0055] Furthermore, the second oxide semiconductor layer 144b contains more oxygen than the stoichiometric composition ratio. Also good are silicon, germanium, and cerium, titanium, tungsten, aluminum. One or more elements of metals such as titanium, copper, yttrium, lanthanum, and vanadium These elements may be included in the second oxide semiconductor layer 144b. This can improve the insulating properties.

[0056] In terms of concentration, for silicon, germanium, and metallic elements, it is 1 × 10⁻⁶. 20 at oms / cm 3 Preferably 1 × 10 21 atoms / cm 3 In summary, comfortable 5 x 10 21 atoms / cm 3 This can be done.

[0057] Furthermore, in transistor 160 and capacitive element 164, gate electrode 148a, first Electrode 148b, gate insulating layer 146, first oxide semiconductor layer 144a and second oxide The edges of the semiconductor layer 144b are preferably tapered. Here, the taper angle is For example, it should be between 30° and 60°. Note that the taper angle refers to the tapered shape. The layer (for example, gate electrode 148a) is positioned perpendicular to its cross-section (the plane perpendicular to the surface of the substrate). This shows the inclination angle formed by the side and bottom surfaces of the layer when observed from the front. Gate electrode 148a, Electrode 148b, gate insulating layer 146, first oxide semiconductor layer 144a and second acid By making the edges of the ionized semiconductor layer 144b tapered, the source electrode or drain electrode can be used. The coating properties of the drain electrode 142b and the drain electrode or source electrode 142a are improved, and step cutting is achieved. This is because it can prevent that.

[0058] Furthermore, an insulating layer 150 is provided on the transistor 160 and the capacitive element 164. ru.

[0059] The transistor 162 and capacitance element 164 shown in Figure 1(B) are the same as the transistor shown in Figure 1(A). This is a modified version of the zista 160 and the capacitive element 164.

[0060] The difference between the configuration shown in Figure 1(A) and the configuration shown in Figure 1(B) is the transistor in Figure 1(B). Point 162 is located on the insulating layer 150, including the electrode 152. Transistor 162 is a channel Two gates are located above and below the first oxide semiconductor layer 144a having a formation region, separated by an insulating layer. It is a dual-gate transistor with an electrode layer. Specifically, a transistor 162 is the gate electrode 148a, the gate insulating layer 146 on the gate electrode 148a, and A first oxide semiconductor layer 144a overlapping the gate electrode 148a on the insulating layer 146, and On the oxide semiconductor layer 144a, the first oxide semiconductor layer 144a is electrically connected to the first oxide semiconductor layer 144a. It has a source electrode or drain electrode 142b and a drain electrode or source electrode 142a. Furthermore, the first oxide semiconductor layer 144a, source electrode or drain electrode 142b and an insulating layer 150 on the drain electrode or source electrode 142a, and on the insulating layer 150 It has an electrode 152 that overlaps with the oxide semiconductor layer 144a.

[0061] In Figure 1(B), both the gate electrode 148a and the electrode 152 function as gate electrodes. The potential of electrode 152 may be the same as or different from that of gate electrode 148a. It may be GND, 0V, or floating. Token 148a and By controlling the electric field applied to the first oxide semiconductor layer 144a using electrode 152, The threshold voltage of the transistor 162 can be controlled.

[0062] The transistor 160 and capacitance element 164 shown in Figure 1(C) are the same as the transistor in Figure 1(A) This is a modified example of the 160 and 164 capacitive elements.

[0063] The difference between the configuration shown in Figure 1(A) and the configuration shown in Figure 1(C) is the capacitance element 16 in Figure 1(C). In 4, the first electrode 148b has a metal oxide on the surface that is in contact with the second oxide semiconductor layer 144b. It is located at the point where layer 149b is present. Furthermore, in the capacitive element 164 of Figure 1(C), the source electrode is Alternatively, the drain electrode 142b has a metal oxide layer on the surface that contacts the second oxide semiconductor layer 144b. It has point 141b. Furthermore, in transistor 160 in Figure 1(C), the drain current The electrode or source electrode 142a has a metal oxide on the surface that contacts the first oxide semiconductor layer 144a. It may have layer 141a.

[0064] When the second oxide semiconductor layer 144b and the first electrode 148b are in contact, the first electrode 148b This may cause oxygen to be removed from the second oxide semiconductor layer 144b. When oxygen is removed from the conductive layer 144b, the oxygen deficiency increases. The second acid with increased oxygen deficiency The ionized semiconductor layer 144b may become highly conductive and cease to function as a dielectric in the capacitive element. There is.

[0065] Therefore, the first electric layer has a metal oxide layer 149b in contact with the second oxide semiconductor layer 144b. It is preferable to use electrode 148b. The metal oxide layer 149b forms the second oxide semiconductor layer This prevents oxygen from being taken from 144b to the first electrode 148b. Furthermore, gold Oxygen is supplied from the first oxide layer 149b to the second oxide semiconductor layer 144b, and the second oxide semiconductor This also allows for a further reduction in oxygen deficiency in the conductive layer 144b.

[0066] Furthermore, the metal oxide layer 141b and the metal oxide layer 141a are made of highly conductive metal oxides. It is preferable that it be a layer. By using a layer with high conductivity, the capacitive element 164 and the transistor This allows for a good electrical connection with the Ta160.

[0067] Furthermore, the second oxide semiconductor layer 144b and the source electrode or drain electrode 142b are in contact. In this case, the source electrode or drain electrode 142b is used to separate the second oxide semiconductor layer 144b from the source electrode or drain electrode 142b. Oxygen may be removed. When oxygen is removed from the second oxide semiconductor layer 144b, oxygen The vacancies increase. The second oxide semiconductor layer 144b, with its increased oxygen vacancies, becomes highly conductive. This could cause the capacitor element to cease functioning as a dielectric.

[0068] Therefore, a source electric having a metal oxide layer 141b in contact with the second oxide semiconductor layer 144b It is preferable to use the electrode or drain electrode 142b. The metal oxide layer 141b provides Oxygen is removed from the oxide semiconductor layer 144b of 2 to the source electrode or drain electrode 142b. This can prevent the metal oxide layer in contact with the first oxide semiconductor layer 144a. A drain electrode or source electrode 142a having 141a may also be used. The electrode or source electrode 142a can be formed simultaneously with the metal oxide layer 141b. By forming the metal oxide layer 141b and the metal oxide layer 141a, the first oxide semiconductor is formed. Oxygen is supplied to the body layer 144a and the second oxide semiconductor layer 144b, and the first oxide semiconductor This allows for a further reduction in oxygen vacancies in layer 144a and the second oxide semiconductor layer 144b. .

[0069] Whether or not oxygen is removed from the second oxide semiconductor layer 144b depends on the conditions of subsequent processes. Therefore, it can be affected. If oxygen is not removed from the second oxide semiconductor layer 144b, the metal The oxide layer 149b and the metal oxide layer 141b do not need to be formed.

[0070] Furthermore, Figure 1(C) shows the case where metal oxide layers 149b and 141b are present. The illustration shows the following but is not limited to this. It may also include only the metal oxide layer 149b, or the metal oxide layer 141b. It may have only the metal oxide layer 149b, or only the metal oxide layer 141b. Having this feature is preferable because it further increases the capacity per unit area.

[0071] The transistor 162 and the capacitive element 164 shown in Figure 1(D) are the same as the transistor in Figure 1(C) This is a modified example of the 160 and 164 capacitive elements.

[0072] The difference between the configuration shown in Figure 1(C) and the configuration shown in Figure 1(D) is the transistor in Figure 1(D). Point 162 is located on the insulating layer 150, including the electrode 152. Transistor 162 is a channel A dual-gate type having two gate electrode layers arranged above and below the region with insulating layers in between. It is a transistor. Specifically, transistor 162 has a gate electrode 148a and a gate electrode. A first oxide semiconductor layer 144a on electrode 148a, and on the first oxide semiconductor layer 144a A source electrode or drain electrode 1 is electrically connected to the first oxide semiconductor layer 144a. It has 42b and a drain electrode or source electrode 142a. Furthermore, the first oxide semiconductor Conductor layer 144a, source electrode or drain electrode 142b and drain electrode or saw An insulating layer 150 on electrode 142a, and a first oxide semiconductor layer 144a on insulating layer 150 It has overlapping electrodes 152.

[0073] In Figure 1(D), both the gate electrode 148a and the electrode 152 function as gate electrodes. The potential of electrode 152 may be the same as or different from that of gate electrode 148a. It may be GND, 0V, or floating. Token 148a and By controlling the electric field applied to the first oxide semiconductor layer 144a using electrode 152, The threshold voltage of the transistor 162 can be controlled.

[0074] <Methods for fabricating semiconductor devices> Next, transistors 160 and 162 shown in Figures 1(A) and 1(B) The method for producing it will be explained with reference to Figures 2 and 3.

[0075] First, a conductive layer is formed on the insulating layer 140, and the conductive layer is processed to form the first electrode 148b This forms the gate electrode 148a (see Figure 2(A)).

[0076] The insulating layer 140 consists of silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, It is formed using a material containing an inorganic insulating material such as aluminum oxide. Furthermore, the insulating layer 140 It is also possible to form it using organic insulating materials such as polyimide and acrylic. Insulating layer 1 40 can be formed in a single-layer or laminated structure using the above-mentioned materials. In terms of form, we will describe the case where silicon oxide is used as the insulating layer 140.

[0077] The locations where transistors 160 and 162 are formed are on the insulating layer 140. It is not limited to this. For example, it may be fabricated on a substrate having an insulating surface. As for the substrate, Insulating substrates made of insulators such as glass substrates, ceramic substrates, quartz substrates, and sapphire substrates. Semiconductor substrates made of semiconductor materials such as silicon, conductive materials such as metals and stainless steel Substrates, those with their surfaces coated with insulating material, etc., can be used. Flexible substrates such as those made of plastic generally tend to have low heat resistance temperatures, but subsequent manufacturing processes It can be used if it can withstand a certain degree of stress.

[0078] The first electrode 148b and the gate electrode 148a are made of molybdenum, titanium, tantalum, and tan. Metal materials such as gusten, aluminum, copper, neodymium, scandium, or materials mainly composed of these It can be formed using an alloy material. Note that the first electrode 148b and the G The electrode 148a may have a single-layer structure or a multilayer structure. For example, copper-ma It can also be a two-layer structure in which copper is laminated on a magnesium-aluminum alloy layer, or It can also be a three-layer structure with ribdenum, aluminum, and molybdenum stacked in that order.

[0079] Furthermore, the first electrode 148b and the gate electrode 148a are combined with an In-Ga-Zn-ON compound. It may also be formed using a material with a large work function, such as a material conductor. In the gate electrode 148a -By using materials with a large work function, such as Ga-Zn-ON compound conductors, The electrical characteristics of the ZISTRA 160, such as the threshold voltage, can be controlled.

[0080] Next, an insulating layer is formed, and the insulating layer is processed to cover the gate electrode 148a. An insulating layer 146 is formed (see Figure 2(B)). The insulating layer is processed to form the first electrode 148b. By removing the insulating layer from above, the first electrode 148b and the second oxide layer that will be formed later are separated. The conductive layer 144b can be provided in contact with it. This allows the dielectric of the capacitive element 164 to be The only layer that functions is the second oxide semiconductor layer 144b. This allows the induction to be achieved. Compared to the case in which an insulating layer and a second oxide semiconductor layer 144b are stacked as the electrostatic material, The dielectric of the capacitance element 164 can be formed thinly. This allows for an increase in the capacitance per unit area of ​​the capacitive element 164.

[0081] The gate insulating layer 146 can be formed using methods such as CVD or sputtering. Furthermore, the gate insulating layer 146 is made of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide. It is preferable to form it to contain aluminum, etc. The gate insulating layer 146 has a single-layer structure and Alternatively, the above materials may be combined to form a laminated structure. Furthermore, the thickness is not particularly important. While not limited to this, when miniaturizing semiconductor devices, in order to ensure the operation of transistors It is desirable to make it as thin as possible. For example, when using silicon oxide, it should be 1 nm or more and 100 nm thick. The wavelength can be less than or equal to m, preferably between 10 nm and 50 nm.

[0082] Alternatively, an insulating material containing a Group 13 element and oxygen may be used for the gate insulating layer 146. Many oxide semiconductor materials contain Group 13 elements, and insulating materials containing Group 13 elements are acid It has good compatibility with oxide semiconductors, and by using it as an insulating layer in contact with the oxide semiconductor layer, oxidation The state of the interface with the semiconductor layer can be kept in good condition. Here, an insulating material containing a Group 13 element The term "material" means that the insulating material contains one or more Group 13 elements. An example of an insulating material containing an element is aluminum oxide. Aluminum oxide is a water-repellent material. Because it has the characteristic of being difficult to transmit, using this material is an oxide semiconductor layer It is also preferable in terms of preventing water from entering.

[0083] Furthermore, the insulating layer in contact with the first oxide semiconductor layer 144a undergoes heat treatment in an oxygen atmosphere, It is preferable to have an oxygen content in the insulating material that exceeds the stoichiometric composition ratio by adding oxygen, etc. It seems so. The addition of oxygen can be done through doping, ion implantation, or ion doping. This can be done using [a specific method]. Oxygen doping refers to adding oxygen to the bulk material. Oh, the term "bulk" in question clarifies that oxygen is added not only to the surface of the thin layer but also to the interior of the thin layer. It is used with the intention of [doping]. In addition, for oxygen doping, plasma-treated oxygen is added to the bulk. It contains oxygen plasma doping.

[0084] For example, aluminum oxide was used as the insulating layer in contact with the first oxide semiconductor layer 144a. In some cases, by heat treatment in an oxygen atmosphere or oxygen doping, aluminum oxide can be removed. The composition is Al2O X We can set (X = 3 + α, 0 < α < 1).

[0085] By performing oxygen doping treatment, etc., an insulating material has a region where the oxygen content is higher than the stoichiometric composition ratio. A layer can be formed. When an insulating layer having such a region is in contact with an oxide semiconductor layer As a result, excess oxygen in the insulating layer is supplied to the oxide semiconductor layer, and in the oxide semiconductor layer, This reduces oxygen vacancies at the interface between the oxide semiconductor layer and the insulating layer, and makes the oxide semiconductor layer i-type. It can be made to be very close to the i-shape.

[0086] Furthermore, in insulating layers having regions with a higher oxygen content than the stoichiometric composition ratio, the gate insulating layer 146 is replaced. Furthermore, it may be applied to the insulating layer formed as the base layer of transistor 160, in a later process It may be applied to the insulating layer 150 to be fabricated, and may be applied to several or all of these. .

[0087] In this embodiment, the gate insulating layer 146 is formed using the sputtering method. We will use silicon oxide with a wavelength of 10 nm to 50 nm.

[0088] Next, an oxide semiconductor layer is formed, and the oxide semiconductor layer is processed on the gate insulating layer 146. A first oxide semiconductor layer 144a is formed so as to overlap with the gate electrode 148a. In contact with the first electrode 148b or the metal oxide layer 149b, the second oxide semiconductor layer 1 Forms 44b (see Figure 2(C)).

[0089] As a material used for the oxide semiconductor layer, the quaternary metal oxide In-Sn-Ga-Zn -O-based oxides, and ternary metal oxides such as In-Ga-Zn-O oxides, In-Sn- Zn-O oxides, In-Al-Zn-O oxides, Sn-Ga-Zn-O oxides, A l-Ga-Zn-O oxides, Sn-Al-Zn-O oxides, and binary metal oxides In-Zn-O oxides, Sn-Zn-O oxides, Al-Zn-O oxides, Zn- Mg-O oxides, Sn-Mg-O oxides, In-Mg-O oxides, In-Ga-O Use of oxides such as In-O oxides, Sn-O oxides, and Zn-O oxides. This can be done. Furthermore, SiO2 may be added to the above materials. Here, for example, In-Ga -Zn-O oxides are oxides containing indium (In), gallium (Ga), and zinc (Zn). It means an oxide layer, and the composition ratio is not particularly specified. Also, In, Ga, and Zn It may contain other elements.

[0090] Furthermore, the thickness of the oxide semiconductor layer should preferably be between 3 nm and 30 nm. If the conductor layer is made too thick (for example, more than 50 nm thick), the transistor will normally-on This is because there is a risk that this will happen. Also, compared to the thickness of the second oxide semiconductor layer 144b For example, this is because the capacitance of the capacitive element 164 becomes smaller.

[0091] The oxide semiconductor layer is manufactured using a method that minimizes the inclusion of impurities such as hydrogen, water, hydroxyl groups, or hydrides. It is desirable to manufacture it in this way. The oxide semiconductor layer is fabricated using, for example, a sputtering method. It is possible.

[0092] In this embodiment, the oxide semiconductor layer uses an In-Ga-Zn-O oxide target. It is formed by the sputtering method.

[0093] For example, as a target for In-Ga-Zn-O oxides, the composition ratio is In2O Using an oxide target with a molar ratio of 3:Ga2O3:ZnO = 1:1:1 Yes, it is possible. However, the target material and composition do not need to be limited to those described above. For example, In An oxide target with a composition ratio of 2O3:Ga2O3:ZnO = 1:1:2 [molar ratio] It can also be used.

[0094] The relative density of the oxide target is 90% to 100%, preferably 95% to 99%. The concentration should be 9% or less. By using a metal oxide target with a high relative density, the formed acid This is because it allows for the formation of a dense layer of the ion semiconductor.

[0095] Furthermore, the oxide semiconductor layer is preferably a CAAC-OS layer. A CAAC-OS layer with added material, which is of type i (intrinsic) or substantially type i, is, for example, the following: It can be formed in this way.

[0096] First, the substrate is coated with a first oxide semiconductor layer using sputtering, molecular beam epitaxy, and atomic layer It is formed by deposition or pulsed laser deposition. Note that the substrate is heated during the formation process. This allows for the creation of an oxide semiconductor layer in which the proportion of crystalline regions is large relative to amorphous regions. For example, the substrate temperature should be between 150°C and 450°C. Preferably, the substrate temperature The temperature should be between 200°C and 250°C.

[0097] By increasing the substrate temperature, the CAAC-OS oxide can be crystallized more effectively. ru.

[0098] Next, the substrate may undergo a first heat treatment. By performing the first heat treatment, the substrate becomes more amorphous. An oxide semiconductor layer with a high proportion of crystalline regions relative to crystalline regions can be obtained. First heat treatment This can be done, for example, at a temperature of 200°C or higher but below the strain point of the substrate. Preferably, at a temperature of 200°C or higher but below the strain point of the substrate. The temperature should be below 0°C. By performing heat treatment, the hydrogen atoms contained in the oxide semiconductor layer are removed. Further removal of harmful substances is possible. The atmosphere is not limited, but an oxidizing atmosphere is preferable. Perform the process in a normal or reduced pressure atmosphere. Processing time should be between 3 minutes and 24 hours. Increase the processing time. It is possible to form an oxide semiconductor layer in which the proportion of crystalline regions is larger than that of amorphous regions. Heat treatment exceeding 24 hours is undesirable as it leads to a decrease in productivity.

[0099] An oxidizing atmosphere is an atmosphere containing oxidizing gases. Oxidizing gases include oxygen, ozone, or It is preferable that the substance is nitrous oxide or the like, and does not contain water, hydrogen, etc. For example, heat treatment equipment The purity of the oxygen, ozone, and nitrous oxide introduced into the system must be 8N (99.999999%) or higher. Preferably, the oxidizing atmosphere is 9N (99.9999999%) or higher. It may be used in mixture with an inert gas. In that case, the oxidizing gas must be at least 10 ppm or more. It shall be included.

[0100] Here, an inert atmosphere refers to nitrogen, noble gases (helium, neon, argon, krypton, This is an atmosphere primarily composed of inert gases such as xenon. Specifically, oxidizing gases, etc. The atmosphere should contain less than 10 ppm of the reactive gas.

[0101] The first heat treatment is performed using an RTA (Rapid Thermal Annealing) apparatus. This is possible. By using RTA, heat treatment can be performed at a temperature above the strain point of the substrate for a short period of time. Therefore, an oxide semiconductor layer with a higher proportion of crystalline regions compared to amorphous regions can be constructed. This can shorten the time required for formation.

[0102] As an oxide, its chemical formula is InMO3(ZnO) m You may also use materials denoted as (m>0). Here, M is one or more metallic elements selected from Ga, Al, Mn, and Co. For example, M can be Ga, Ga and Al, Ga and Mn, or Ga and Co You may also use the following:

[0103] Also, nitrogen 5 × 10 19 / cm 3 Preferably 1 × 10 20 / cm 3 7 atoms or more In-Ga-Zn-O oxides containing less than a certain amount are oxides containing a c-axis oriented hexagonal crystal structure. Therefore, between the In-O crystal plane (the crystal plane containing indium and oxygen) and the In-O crystal plane or comprising a layer having a single layer of Ga and Zn, or In-G containing nitrogen within the above range. In an a-Zn-O-based oxide, multiple layers are formed between the crystal planes of In-O. It may also include layers having Ga and Zn.

[0104] Furthermore, a second oxide semiconductor layer is formed on the first oxide semiconductor layer to form an oxide laminate. The first oxide semiconductor layer and the second oxide semiconductor layer may be formed in the same manner. It is possible.

[0105] When forming the second oxide semiconductor layer, by forming it while heating the substrate, the first oxide semiconductor The conductive layer can be used as a seed crystal to crystallize the second oxide semiconductor layer.

[0106] Furthermore, a second heat treatment may be performed after forming the second oxide semiconductor layer. This can be done in the same way as the first heat treatment. By performing the second heat treatment, amorphous An oxide laminate can be formed in which the proportion of crystalline regions is large relative to the regions. Alternatively, a second heat By performing the process, the first oxide semiconductor layer is used as a seed crystal, and the second oxide semiconductor layer is bonded to it. It can be crystallized. At this time, the first oxide semiconductor layer and the second oxide semiconductor layer are the same It may also be a homogeneous growth composed of one element. Alternatively, the first oxide semiconductor layer and the second The oxide semiconductor layer 2 is hetero-grown and composed of at least one different element. You can do that.

[0107] By reducing impurities and adding oxygen using the above method, it is possible to obtain type i (intrinsic semiconductor) or substantially A type i CAAC-OS can be formed. This makes it possible to create transistors with extremely superior characteristics.

[0108] Furthermore, when an oxide semiconductor is i-type (intrinsed) or substantially i-type, the dielectric constant is It can be made higher. Specifically, the relative permittivity of In-Ga-Zn-O oxides is about 15. It can be set to a degree. This is ten times compared to the dielectric constant of silicon oxide, which is about 4. It is high in volume. Therefore, an i-type (intrinsed) or substantially i-type oxide semiconductor is used. By using it as the dielectric of element 164, the capacitance per unit area of ​​the capacitive element 164 is increased. It is possible.

[0109] Furthermore, the oxide semiconductor layer is processed to form the first oxide semiconductor layer 144a and the second oxide semiconductor layer After forming the conductive layer 144b, oxygen may be added to the second oxide semiconductor layer 144b. Furthermore, the second oxide semiconductor layer 144b contains silicon, germanium, and cerium, titanium. Metals such as tungsten, aluminum, copper, yttrium, lanthanum, and vanadium One or more of these elements may be added. By adding these elements, the second oxide The insulating properties of the semiconductor layer 144b can be improved.

[0110] Methods of addition include ion implantation or ion doping. In terms of concentration, for oxygen, it is 1 × 10⁻⁶. 16 atoms / cm 3 The above 2 x 10 20 atoms / cm 3 The following is preferable. If the oxygen concentration is within this range, strain will occur in the crystal. It can be incorporated into oxide semiconductors without impairing their properties. (Silicon, Germanium) And in the case of metallic elements, 1 × 10 20 atoms / cm 3 Preferably 1 × 102 1 atoms / cm 3 The above is more comfortable 5x10 21 atoms / cm 3 That concludes this section. It is possible.

[0111] Next, a conductive layer 142 is formed (see Figure 2(D)). The conductive layer 142 is connected to the first electrode 148 b and the gate electrode 148a can be formed from the same materials and configuration as those used for gates b and gate electrode 148a.

[0112] Next, the conductive layer 142 is processed, and the source electrode or drain electrode 142b and drain electrode Form the electrode or source electrode 142a (see Figure 3(A)).

[0113] Next, source electrode or drain electrode 142b, drain electrode or source electrode 142a And an insulating layer 150 is formed to cover the first oxide semiconductor layer 144a. 0 represents silicon oxide, silicon oxide nitride, silicon nitride, silicon oxide, and aluminum oxide. It is formed using a material containing inorganic insulating materials such as nium. The insulating layer 150 has a low dielectric constant ( By using a low-k material, when various electrodes and wiring are placed on the insulating layer 150, overlapping This is preferable because it makes it possible to sufficiently reduce the capacitance caused by the noise. A porous insulating layer using the above-mentioned material may be applied. In a porous insulating layer, density Because the dielectric constant is lower compared to a highly insulating layer, capacitance caused by electrodes and wiring is further reduced. It is possible to do so. Furthermore, the insulating layer 150 is made of an organic insulating material such as polyimide or acrylic. It is also possible to form it using the above-mentioned material. The insulating layer 150 can be formed in a single-layer structure or It can be formed in a layered structure (see Figure 3(B)).

[0114] As described above, the transistor 160 and the capacitor element 164 using the oxide semiconductor layer are completed. (see FIG. 3(B)).

[0115] Furthermore, an electrode 152 may be formed on the insulating layer 150. The electrode 152 can be formed with the same material and configuration as the first electrode 148b and the gate electrode 148a. The transistor 162 can control electrical characteristics such as the threshold voltage by the electrode 152. 8b and the gate electrode 148a. 52.

[0116] As described above, the transistor 162 having the electrode 152 is completed (see FIG. 3(C)).

[0117] Next, a method for manufacturing the transistors 160 and 162 shown in FIGS. 1(C) and 1(D) will be described. will be described.

[0118] First, an insulating layer 140 is formed. Regarding the insulating layer 140, the description of FIG. 1(A) can be referred to. can be referred to.

[0119] Next, a conductive layer is formed on the insulating layer 140, and the conductive layer is processed to form the first electrode 148b and the gate electrode 148a. Next, before the first electrode 148b comes into contact with the oxide semiconductor layer to be formed later, the first electrode 148b is oxidized, or a metal oxide layer 149b is formed using a sputtering method or a CVD method. and the gate electrode 148a. semiconductor layer, the first electrode 148b is oxidized, or a metal oxide layer 149b is formed using a sputtering method or a CVD method. D method.

[0120] Regarding the materials and configurations of the first electrode 148b and the gate electrode 148a, the description of FIG. 1(A) can be referred to. However, when the metal oxide layer 149b is formed by high-density oxygen plasma treatment or thermal oxidation, the first electrode 148b and the gate electrode 148 Regarding the description of FIG. 1(A), the metal oxide layer 149b is formed by high-density oxygen plasma treatment or thermal oxidation. b and the gate electrode 148 It is preferable that a has a structure containing tungsten, titanium or zirconium. This is because these oxides have high conductivity. Also, a layer containing an In-Ga-Zn-O-N-based compound may be formed as the metal oxide layer 149b. When forming the metal oxide layer 149b, it may be before forming the insulating layer or after forming the gate insulating layer 146. Also, a metal oxide layer may be laminated on both the first electrode 148b and the gate electrode 148a, or it may be laminated only on the first electrode 148b.

[0121] The method for forming the metal oxide layer 149b is not particularly limited. For example, it can be performed by high-density oxygen plasma treatment. The high-density oxygen plasma treatment is performed using, for example, a mixed gas of a noble gas such as helium, argon, krypton, xenon and oxygen. In this case, by introducing microwaves to excite the plasma, a high-density plasma at a low electron temperature can be generated. The oxygen radicals (which may contain OH radicals) generated by such a high-density plasma oxidize the surface of the first electrode 148b, thereby forming a metal oxide layer 149b with a thickness of 1 nm or more and 20 nm or less, preferably 5 nm or more and 10 nm or less. This can be done.

[0122] Since the oxidation of the first electrode 148b by the above-described high-density oxygen plasma treatment is solid-phase growth, the interface state density between the first electrode 148b and the metal oxide layer 149b can be made extremely low. Also, by directly oxidizing the first electrode 148b by high-density oxygen plasma treatment, variations in the thickness of the formed metal oxide layer 149b can be suppressed.

[0123] Alternatively, the metal oxide layer 149b can be formed by thermal oxidation of the first electrode 148b. This is also acceptable. In this way, when using thermal oxidation, a substrate with a certain degree of heat resistance is required. It is necessary to use [this].

[0124] Alternatively, the metal oxide layer 149b is formed by processing a layer created by sputtering or CVD. This may be done. Regarding the formation method by sputtering, see the oxide semiconductor described later. The method of layer formation can be taken into consideration.

[0125] In this embodiment, a metal oxide with a size of 5 nm to 10 nm is produced by high-density oxygen plasma treatment. We will form layer 149b.

[0126] The metal oxide layer 149b allows the second oxide semiconductor layer 144b to be formed in a later step to be separated from the metal oxide layer 149b. This prevents oxygen from being removed from electrode 148b. Also, the metal oxide layer 149 Oxygen is supplied from b to the second oxide semiconductor layer 144b which will be formed in a later step, and the second oxide This allows for a further reduction in oxygen vacancies in the semiconductor layer 144b. Furthermore, it utilizes highly conductive metal oxides. By using material layer 149b, it is possible to prevent a decrease in the capacitance of the capacitive element 164.

[0127] Next, an insulating layer is formed, and the insulating layer is processed to cover the gate electrode 148a. An insulating layer 146 is formed. For details regarding the gate insulating layer 146, please refer to the description in Figure 1(A). It is possible to pour drinks.

[0128] Next, an oxide semiconductor layer is formed, and the oxide semiconductor layer is processed on the gate insulating layer 146. A first oxide semiconductor layer 144a is formed so as to overlap with the gate electrode 148a. Next, a second oxide semiconductor layer 144b is formed in contact with the first electrode 148b or the metal oxide layer 149b. For the oxide semiconductor layer, the first oxide semiconductor layer 144a, and the second oxide semiconductor layer 144b, reference can be made to the description of FIG. 1(A). Next, a metal oxide layer is formed. The metal oxide layer can be formed using a CVD method, a sputtering method, or the like. The metal oxide layer preferably has a structure containing tungsten oxide, titanium oxide, zirconium oxide, or an In-Ga-Zn-O-N-based compound. This is because these metal oxides have high conductivity. The thickness of the metal oxide layer is not particularly limited, but can be formed, for example, to be 1 nm or more and 20 nm or less, preferably 5 nm or more and 10 nm or less. Next, a conductive layer 142 is formed. The conductive layer 142 can be formed of the same material and configuration as the first electrode 148b and the gate electrode 148a. Before the conductive layer 142 comes into contact with the first oxide semiconductor layer 144a and the second oxide semiconductor layer 144b, it is preferable to form a metal oxide layer.

[0129] Next, the conductive layer 142 and the metal oxide layer are processed to form a source electrode or drain electrode 142b, a metal oxide layer 141b, a drain electrode or source electrode 142a, and a metal oxide layer 141a. By using the metal oxide layer 141a with high conductivity, good electrical connection between the capacitor element 164 and the transistor 160 can be maintained. Also, the metal oxide layer 141b and the metal Next, a metal oxide layer is formed. The metal oxide layer can be formed using a CVD method, a sputtering method, or the like. The metal oxide layer preferably has a structure containing tungsten oxide, titanium oxide, zirconium oxide, or an In-Ga-Zn-O-N-based compound. This is because these metal oxides have high conductivity. The thickness of the metal oxide layer is not particularly limited, but can be formed, for example, to be 1 nm or more and 20 nm or less, preferably 5 nm or more and 10 nm or less. Next, a metal oxide layer is formed. The metal oxide layer can be formed using a CVD method, a sputtering method, or the like. The metal oxide layer preferably has a structure containing tungsten oxide, titanium oxide, zirconium oxide, or an In-Ga-Zn-O-N-based compound. This is because these metal oxides have high conductivity. The thickness of the metal oxide layer is not particularly limited, but can be formed, for example, to be 1 nm or more and 20 nm or less, preferably 5 nm or more and 10 nm or less. Next, a metal oxide layer is formed. The metal oxide layer can be formed using a CVD method, a sputtering method, or the like. The metal oxide layer preferably has a structure containing tungsten oxide, titanium oxide, zirconium oxide, or an In-Ga-Zn-O-N-based compound. This is because these metal oxides have high conductivity. The thickness of the metal oxide layer is not particularly limited, but can be formed, for example, to be 1 nm or more and 20 nm or less, preferably 5 nm or more and 10 nm or less. Next, a metal oxide layer is formed. The metal oxide layer can be formed using a CVD method, a sputtering method, or the like. The metal oxide layer preferably has a structure containing tungsten oxide, titanium oxide, zirconium oxide, or an In-Ga-Zn-O-N-based compound. This is because these metal oxides have high conductivity. The thickness of the metal oxide layer is not particularly limited, but can be formed, for example, to be 1 nm or more and 20 nm or less, preferably 5 nm or more and 10 nm or less. Next, a metal oxide layer is formed. The metal oxide layer can be formed using a CVD method, a sputtering method, or the like. The metal oxide layer preferably has a structure containing tungsten oxide, titanium oxide, zirconium oxide, or an In-Ga-Zn-O-N-based compound. This is because these metal oxides have high conductivity. The thickness of the metal oxide layer is not particularly limited, but can be formed, for example, to be 1 nm or more and 20 nm or less, preferably 5 nm or more and 10 nm or less.

[0130] Next, a conductive layer 142 is formed. The conductive layer 142 can be formed of the same material and configuration as the first electrode 148b and the gate electrode 148a. Before the conductive layer 142 comes into contact with the first oxide semiconductor layer 144a and the second oxide semiconductor layer 144b, it is preferable to form a metal oxide layer. Next, a conductive layer 142 is formed. The conductive layer 142 can be formed of the same material and configuration as the first electrode 148b and the gate electrode 148a. Before the conductive layer 142 comes into contact with the first oxide semiconductor layer 144a and the second oxide semiconductor layer 144b, it is preferable to form a metal oxide layer. Next, a conductive layer 142 is formed. The conductive layer 142 can be formed of the same material and configuration as the first electrode 148b and the gate electrode 148a. Before the conductive layer 142 comes into contact with the first oxide semiconductor layer 144a and the second oxide semiconductor layer 144b, it is preferable to form a metal oxide layer. Next, a conductive layer 142 is formed. The conductive layer 142 can be formed of the same material and configuration as the first electrode 148b and the gate electrode 148a. Before the conductive layer 142 comes into contact with the first oxide semiconductor layer 144a and the second oxide semiconductor layer 144b, it is preferable to form a metal oxide layer.

[0131] Next, a conductive layer 142 and the metal oxide layer are processed to form a source electrode or drain electrode 142b, a metal oxide layer 141b, a drain electrode or source electrode 142a, and a metal oxide layer 141a. By using the metal oxide layer 141a with high conductivity, good electrical connection between the capacitor element 164 and the transistor 160 can be maintained. Also, the metal oxide layer 141b and the metal Next, a conductive layer 142 and the metal oxide layer are processed to form a source electrode or drain electrode 142b, a metal oxide layer 141b, a drain electrode or source electrode 142a, and a metal oxide layer 141a. By using the metal oxide layer 141a with high conductivity, good electrical connection between the capacitor element 164 and the transistor 160 can be maintained. Also, the metal oxide layer 141b and the metal Next, a conductive layer 142 and the metal oxide layer are processed to form a source electrode or drain electrode 142b, a metal oxide layer 141b, a drain electrode or source electrode 142a, and a metal oxide layer 141a. By using the metal oxide layer 141a with high conductivity, good electrical connection between the capacitor element 164 and the transistor 160 can be maintained. Also, the metal oxide layer 141b and the metal

[0132] Next, a conductive layer 142 and the metal oxide layer are processed to form a source electrode or drain electrode 142b, a metal oxide layer 141b, a drain electrode or source electrode 142a, and a metal oxide layer 141a. By using the metal oxide layer 141a with high conductivity, good electrical connection between the capacitor element 164 and the transistor 160 can be maintained. Also, the metal oxide layer 141b and the metal Next, a conductive layer 142 and the metal oxide layer are processed to form a source electrode or drain electrode 142b, a metal oxide layer 141b, a drain electrode or source electrode 142a, and a metal oxide layer 141a. By using the metal oxide layer 141a with high conductivity, good electrical connection between the capacitor element 164 and the transistor 160 can be maintained. Also, the metal oxide layer 141b and the metal The oxide layer 141a provides a first oxide semiconductor layer 144a and a second oxide semiconductor layer 1 This prevents oxygen from being removed from 44b. Furthermore, the metal oxide layer 141b and From the metal oxide layer 141a, the first oxide semiconductor layer 144a and the second oxide semiconductor Oxygen is supplied to layer 144b, and the first oxide semiconductor layer 144a and the second oxide semiconductor layer This can reduce the oxygen deficiency at 144b.

[0133] Next, the source electrode or drain electrode 142b, the metal oxide layer 141b, and the drain electrode or source electrode 142a, metal oxide layer 141a, and first oxide semiconductor layer 144a An insulating layer 150 is formed to cover it. The insulating layer 150 is made of the same material as the gate insulating layer 146. It can be formed from materials and components.

[0134] With the above steps, the transistor 160 and the capacitive element 164 using an oxide semiconductor layer are completed. (See Figure 1(C)).

[0135] Furthermore, an electrode 152 may be formed on the insulating layer 150. The electrode 152 is the first electrode 14 8b and the gate electrode 148a can be formed from the same materials and configuration. 52 allows transistor 162 to control electrical characteristics such as threshold voltage.

[0136] Thus, the transistor 162 having electrode 152 is completed (see Figure 1(D)).

[0137] (Embodiment 2) This embodiment describes a semiconductor device configuration and a method for manufacturing the same device, which differ from that of Embodiment 1. This will be explained with reference to Figures 4 to 8.

[0138] <Cross-sectional configuration of a semiconductor device> Figure 4 shows an example of the configuration of a semiconductor device. Figures 4(A) and 4(B) show cross-sections of the semiconductor device. The surface is shown. The semiconductor device shown in Figures 4(A) and 4(B) has an oxide in the channel formation region. A transistor 160 using a semiconductor and a capacitive element 164 using an oxide semiconductor as the dielectric are To possess.

[0139] In Figure 4(A), the transistor 160 has a source electrode provided on the insulating layer 140. The drain electrode 142b and the drain electrode or source electrode 142a, and the source electrode Alternatively, the source electrode on the drain electrode 142b and the drain electrode or source electrode 142a. Alternatively, the drain electrode 142b and the drain electrode or source electrode 142a are electrically connected. The first oxide semiconductor layer 144a is connected to the first oxide semiconductor layer 144a, and the layer covering the first oxide semiconductor layer 144a is A gate insulating layer 146 and a gate insulating layer 146 that overlaps with the first oxide semiconductor layer 144a It has an electrode 148a.

[0140] In Figure 4(A), the capacitive element 164 has a source electrode or drain electrode 142b and a source electrode. A second oxide semiconductor layer 144b in contact with the electrode or drain electrode 142b, and a second acid It has a first electrode 148b in contact with the ionized semiconductor layer 144b. Here, the source electrode or The drain electrode 142b functions as the second electrode of the capacitive element 164.

[0141] In other words, it can also be said as follows: The capacitive element 164 is connected to the first electrode 148b, It has a second oxide semiconductor layer 144b and a second electrode. The second electrode is a source electrode It consists of the same conductive layer as the electrode or drain electrode 142b.

[0142] Furthermore, an insulating layer 150 is provided on the transistor 160 and the capacitive element 164. ru.

[0143] The transistor 160 and capacitive element 164 shown in Figure 4(B) are the same as the transistor shown in Figure 4(A). This is a modified version of the zista 160 and the capacitive element 164.

[0144] The difference between the configuration shown in Figure 4(A) and the configuration shown in Figure 4(B) is the capacitance element 16 in Figure 4(B). In step 4, the source electrode or drain electrode 142b is in contact with the second oxide semiconductor layer 144b. The surface has a metal oxide layer 149b. Furthermore, the capacitive element 164 in Figure 4(B) Then, the first electrode 148b is in contact with the second oxide semiconductor layer 144b, and a metal oxide layer It is located at point 141b. Furthermore, in transistor 160 in Figure 4(B), the drain electrode Alternatively, a metal oxide layer 1 is placed on the surface where the source electrode 142a is in contact with the first oxide semiconductor layer 144a. It may have 49a.

[0145] When the second oxide semiconductor layer 144b and the source electrode or drain electrode 142b are in contact, Oxygen is released from the second oxide semiconductor layer 144b by the source electrode or drain electrode 142b. It can be taken away. When oxygen is taken away from the second oxide semiconductor layer 144b, an oxygen vacancy occurs. The oxygen vacancies increase. The second oxide semiconductor layer 144b, with increased oxygen vacancies, becomes more conductive and its capacitance increases. There is a risk that the element will cease to function as a dielectric.

[0146] Therefore, a source electric having a metal oxide layer 149b in contact with the second oxide semiconductor layer 144b It is preferable to use the electrode or drain electrode 142b. The metal oxide layer 149b provides This prevents oxygen from being removed from the oxide semiconductor layer 144b of the first A drain electrode or saw having a metal oxide layer 149a in contact with an oxide semiconductor layer 144a. A 142a electrode may also be used. Form metal oxide layers 149b and 149a. By doing so, oxygen is supplied to the second oxide semiconductor layer 144b, and the second oxide semiconductor layer 14 This can further reduce the oxygen deficiency in 4b.

[0147] Furthermore, when the second oxide semiconductor layer 144b and the first electrode 148b are in contact, the first electrode 1 48b may remove oxygen from the second oxide semiconductor layer 144b. When oxygen is removed from the ion semiconductor layer 144b, the oxygen vacancy increases. The oxide semiconductor layer 144b of layer 2 becomes highly conductive and ceases to function as a dielectric in the capacitive element. There is a risk of that happening.

[0148] Therefore, the first electric element has a metal oxide layer 141b in contact with the second oxide semiconductor layer 144b. It is preferable to use electrode 148b. The metal oxide layer 141b forms the second oxide semiconductor layer This prevents oxygen from being drawn from 144b to the source electrode or drain electrode 142b. Yes, it is possible. Also, simultaneously with the metal oxide layer 141b, the gate insulating layer 146 and the gate electrode 148 A metal oxide layer 141a may be formed between a and the other element.

[0149] Whether or not oxygen is removed from the second oxide semiconductor layer 144b depends on the conditions of subsequent processes. Therefore, it can be affected. If oxygen is not removed from the second oxide semiconductor layer 144b, the metal The oxide layer 149b and the metal oxide layer 141b do not need to be formed.

[0150] <Methods for fabricating semiconductor devices> Next, regarding the method for fabricating the transistor 160 shown in Figure 4(A), please refer to Figures 5 to 6. I will explain.

[0151] First, a conductive layer 142 is formed on top of the insulating layer 140 (see Figure 5(A)).

[0152] The material and structure of the conductive layer 142 can be determined by referring to the description in Embodiment 1.

[0153] Next, the conductive layer 142 is processed to create the source electrode or drain electrode 142b and drain Form the electrode or source electrode 142a (see Figure 5(B)).

[0154] Next, an oxide semiconductor layer is formed, and the oxide semiconductor layer is processed to create a source electrode or drain. The in electrode 142b and the drain electrode or source electrode 142a are electrically connected. A first oxide semiconductor layer 144a is formed. At the same time, the oxide semiconductor layer is processed , in contact with the source electrode or drain electrode 142b, a second oxide semiconductor layer 144b is formed This is achieved (see Figure 5(C)). At this time, it is preferable to perform the first heat treatment. Oxide semiconductor Regarding the material and composition of the body layers and the first heat treatment, refer to the description in Embodiment 1. can.

[0155] Next, an insulating layer is formed on the first oxide semiconductor layer 144a, and the insulating layer is processed to form a gate. A gate insulating layer 146 is formed (see Figure 5(D)). The material and composition of the gate insulating layer 146 are The description of Embodiment 1 can be given due consideration.

[0156] After the insulating layer is formed, a second heat treatment is performed under an inert gas atmosphere or an oxygen atmosphere. This is desirable. The heat treatment can be carried out in the same manner as the first heat treatment. When the insulating layer contains oxygen. Oxygen is supplied to the first oxide semiconductor layer 144a and the second oxide semiconductor layer 144b. The oxygen vacancies in the first oxide semiconductor layer 144a and the second oxide semiconductor layer 144b are filled. This allows for the formation of an i-type (intrinsic semiconductor) or substantially i-type oxide semiconductor layer. .

[0157] As described above, by applying at least one of the first heat treatment and the second heat treatment, The semiconductor layer can be made highly pure so that it contains as little hydrogen atoms as possible. .

[0158] In this embodiment, a second heat treatment is performed after the formation of the insulating layer, but the second heat treatment The timing is not limited to this. For example, the insulating layer is processed and the gate insulating layer 146 is formed It may be done after the first heat treatment. Alternatively, the second heat treatment may be performed immediately after the first heat treatment. The first heat treatment may also serve as the second heat treatment, or the second heat treatment may also serve as the first heat treatment. You may allow it.

[0159] Furthermore, the second oxide semiconductor layer 144b may be oxygen-doped. By oxygen doping layer 144b, the second oxide semiconductor layer 144b becomes more i-type. It can be brought closer. Regarding the oxygen doping method, the gate insulating layer of Embodiment 1 The information provided can be taken into consideration.

[0160] Next, a conductive layer 148 is formed (see Figure 6(A)). The material and composition of the conductive layer 148 are as follows: The description of Embodiment 1 may be given due consideration.

[0161] Next, the conductive layer 148 is processed to create a first oxide semiconductor layer 144a on the gate insulating layer 146. The gate electrode 148a is formed so as to overlap with it. At the same time, the second oxide semiconductor layer 144 The first electrode 148b is formed in contact with b (see Figure 6(B)).

[0162] Next, the first electrode 148b, the second oxide semiconductor layer 144b, the gate insulating layer 146, and the gate An insulating layer 150 is formed to cover the electrode 148a. The material and composition of the insulating layer 150 are The description of Embodiment 1 can be considered (see Figure 6(C)).

[0163] With the above steps, the transistor 160 and the capacitive element 164 using an oxide semiconductor layer are completed. (See Figure 6(C)).

[0164] Next, we will explain the method for fabricating transistor 160 shown in Figure 4(B).

[0165] First, a conductive layer 142 is formed on the insulating layer 140, and then a metal oxide layer is formed on the conductive layer 142. The materials and composition of the conductive layer 142 and the metal oxide layer shall be as described in Embodiment 1. It is possible.

[0166] Next, the conductive layer 142 and the metal oxide layer are processed to form the source electrode or drain electrode 14 2b, metal oxide layer 149b, drain electrode or source electrode 142a and metal oxide It forms layer 149a.

[0167] Next, an oxide semiconductor layer is formed, and the oxide semiconductor layer is processed to create a source electrode or drain. The in electrode 142b and the drain electrode or source electrode 142a are electrically connected. A first oxide semiconductor layer 144a is formed. Simultaneously, the oxide semiconductor layer is processed. Then, a second oxide semiconductor layer 144b is formed in contact with the metal oxide layer 149b. The materials and structure of the semiconductor layer can be described with reference to the description in Embodiment 1.

[0168] Next, an insulating layer is formed on the first oxide semiconductor layer 144a, and the insulating layer is processed to form a gate. A gate insulating layer 146 is formed. The material and structure of the gate insulating layer 146 are as in Embodiment 1. You can also refer to the description in Figure 4(A).

[0169] Next, the first oxide semiconductor layer 144a and the second oxide semiconductor layer 144b, and the conductive layer 1 Before contact with 48, the first oxide semiconductor layer 144a and the second oxide semiconductor layer 14 A metal oxide layer is formed between 4b and the conductive layer 148. Material and composition of the metal oxide layer. The description of Embodiment 1 can be given due consideration.

[0170] Next, a conductive layer 148 is formed. The material and structure of the conductive layer 148 are as described in Embodiment 1. This can be taken into consideration.

[0171] Next, the metal oxide layer and the conductive layer 148 are processed to form the first oxide layer on the gate insulating layer 146. The metal oxide layer 141a and the gate electrode 148a are arranged so as to overlap with the material semiconductor layer 144a. It is formed. At the same time, the metal oxide layer 141b is in contact with the second oxide semiconductor layer 144b. Then, the first electrode 148b is formed.

[0172] Next, the first electrode 148b, the second oxide semiconductor layer 144b, the gate insulating layer 146, and the gate An insulating layer 150 is formed to cover the electrode 148a. The material and composition of the insulating layer 150 are The description of Embodiment 1 can be given due consideration.

[0173] With the above steps, the transistor 160 and the capacitive element 164 using an oxide semiconductor layer are completed. ru.

[0174] <Cross-sectional configuration of a semiconductor device> Figures 7 and 8 show examples of semiconductor device configurations. Figures 7(A), 7(B), and 8 Figures (A) to 8(C) show cross-sections of semiconductor devices. Figures 7(A), 7(B), and 8 (A) to Figure 8(C) shows a semiconductor device using an oxide semiconductor in the channel formation region. A transistor 160 or transistor 162 and a capacitive element 1 using an oxide semiconductor as the dielectric. It has 64.

[0175] In Figure 7(A), the transistor 160 has a gate electrode 14 provided on the insulating layer 140. 8a, a gate insulating layer 146 covering the gate electrode 148a, and a saw on the gate insulating layer 146 The source electrode or drain electrode 142b and the source electrode or drain electrode 142a, On the drain electrode or source electrode 142b and the source electrode or source electrode 142a Source electrode or drain electrode 142b and drain electrode or source electrode 142a A first oxide semiconductor is electrically connected and overlaps with the gate electrode 148a on the gate insulating layer 146. It has a conductive layer 144a and, . The transistor 160 has a gate insulating layer 146 on, Source electrode or drain electrode 142b and drain electrode or source electrode 142a It is also possible to have a configuration that includes a metal oxide layer in contact with the metal oxide layer.

[0176] In Figure 7(A), the capacitive element 164 has a first electrode 148b and is in contact with the first electrode 148b. A second oxide semiconductor layer 144b and a source electric field in contact with the second oxide semiconductor layer 144b It has a source electrode or drain electrode 142b. Here, the source electrode or drain electrode 14 2b functions as the second electrode of the capacitive element 164.

[0177] In other words, it can also be said as follows: The capacitive element 164 is connected to the first electrode 148b, It has a second oxide semiconductor layer 144b and a second electrode. The second electrode is a source electrode It consists of the same conductive layer as the electrode or drain electrode 142b.

[0178] Furthermore, the capacitive element 164 is connected to the first electrode 148b and the second oxide semiconductor. The conductive layer 144b may also have a metal oxide layer on the surface it is in contact with. The element 164 has a configuration in which a metal oxide layer is placed on the second oxide semiconductor layer 144b. It can also be done this way.

[0179] Furthermore, an insulating layer 150 is provided on the transistor 160 and the capacitive element 164. ru.

[0180] The transistor 162 and capacitance element 164 shown in Figure 7(B) are the same as the transistor shown in Figure 7(A). This is a modified version of the zista 160 and the capacitive element 164.

[0181] The difference between the configuration shown in Figure 7(A) and the configuration shown in Figure 7(B) is the transistor in Figure 7(B). Point 162 is located on the insulating layer 150, including the electrode 152. Transistor 162 is a channel Two gates are located above and below the first oxide semiconductor layer 144a having a formation region, separated by an insulating layer. It is a dual-gate transistor with an electrode layer. Specifically, a transistor 162 is the gate electrode 148a, the gate insulating layer 146 on the gate electrode 148a, and Source electrode or drain electrode 142b and drain electrode or so on insulating layer 146 - Electrode 142a, source electrode or drain electrode 142b and drain electrode or On the source electrode 142a, the source electrode or the drain electrode 142b and the drain electrode The first oxide semiconductor layer 144a is electrically connected to the source electrode 142a, and the source electrode Electrode or drain electrode 142b, drain electrode or source electrode 142a and first acid An insulating layer 150 on the oxide semiconductor layer and a first oxide semiconductor layer 144a on the insulating layer 150 It has an electrode 152 and

[0182] In Figure 7(B), both the gate electrode 148a and the electrode 152 function as gate electrodes. The potential of electrode 152 may be the same as or different from that of gate electrode 148a. It may be GND, 0V, or floating. Token 148a and By controlling the electric field applied to the first oxide semiconductor layer 144a using electrode 152, The threshold voltage of the transistor 162 can be controlled.

[0183] The transistor 160 and capacitance element 164 shown in Figure 8(A) are the same as the transistor shown in Figure 7(A). This is a modified version of the zista 160 and the capacitive element 164.

[0184] The difference between the configuration shown in Figure 7(A) and the configuration shown in Figure 8(A) is the capacitance element 164. This is a method for forming electrodes. In Figure 7(A), a source electrode or a dot is placed on the first electrode 148b. While a rain electrode 142b is provided, in Figure 8(A) the source electrode or drain is shown. Electrode 147b is placed on top of electrode 142b.

[0185] The transistor 160 and capacitance element 164 shown in Figure 8(B) are the same as the transistor shown in Figure 7(B). These are modified versions of the zista 162 and the capacitive element 164.

[0186] The difference between the configuration shown in Figure 7(B) and the configuration shown in Figure 8(B) is the capacitance element 164 This is a method for forming electrodes. In Figure 7(B), a source electrode or a dot is placed on the first electrode 148b. While a rain electrode 142b is provided, in Figure 8(B) the source electrode or drain is shown. A first electrode 148b is placed on top of electrode 142b.

[0187] Furthermore, the transistor 162 has a source electrode or drain electrode on the gate insulating layer 146. 142b, a metal oxide in contact with the drain electrode or source electrode 142a and electrode 152 It can also be configured with layers.

[0188] In Figure 8(C), the transistor 160 is provided on the insulating layer 140. Conductor layer 144a and first oxide semiconductor layer 144a on the first oxide semiconductor layer 144a Electrically connected source electrode or drain electrode 142b and drain electrode or so - Electrode 142a, first oxide semiconductor layer 144a, source electrode or drain electrode 1 42b and the gate insulating layer 146 on the drain electrode or source electrode 142a, and the gate On the insulating layer 146, there is a gate electrode 148a that overlaps with the first oxide semiconductor layer 144a, The transistor 160 has a source electrode on the first oxide semiconductor layer 144a. Alternatively, the metal oxide layer 141b in contact with the drain electrode 142b, and the drain electrode or source The configuration may also include a metal oxide layer 141a in contact with the electrode 142a.

[0189] In Figure 8(C), the capacitive element 164 consists of an electrode 147b and a second oxide semiconductor layer 144b. It has a source electrode or drain electrode 142b. The capacitive element 164 is electric On the surface of electrode 147b where electrode 147b and the second oxide semiconductor layer 144b are in contact, a metal oxide It can also be configured with layers. In addition, the capacitive element 164 is a second oxide semiconductor layer 1 A configuration having a metal oxide layer on 44b is also possible.

[0190] In Figure 8(D), transistor 160 and capacitance element 164 are shown in Figure 8(C). This is a modified version of the inverter 160 and the capacitive element 164.

[0191] The difference between the configuration shown in Figure 8(C) and the configuration shown in Figure 8(D) is the transistor in Figure 8(D). ZISTA 160 has an impurity region 144c and an impurity region in the first oxide semiconductor layer 144a. This is a point that has region 144d.

[0192] The impurity region 144c and impurity region 144d are located on the source electrode or drain electrode 142 b. Using the drain electrode or source electrode 142a and gate electrode 148a as a mask, By injecting impurities through the gate insulating layer 146, it can be formed in a self-aligned manner. Cut.

[0193] Impurities include Group V (Group 15) elements such as nitrogen (N), phosphorus (P), and arsenic (As). Antimony (Sb) and the like can be used. In this embodiment, nitrogen is injected. Let's look at an example.

[0194] Methods for impurity injection include ion implantation or ion doping. Yes, it is possible. Ion implantation involves turning the source gas into plasma, and then implanting the ions contained in this plasma. The material is extracted, mass-separated, and ion species with a predetermined mass are accelerated to form an ion beam. This is a method of injecting the material to be treated. In addition, ion doping is a method of using a source gas. The plasma is transformed, and ion species are extracted from the plasma by the action of a predetermined electric field. This method involves accelerating the material without mass separation and injecting it as an ion beam into the object to be treated. By implanting nitrogen using an ion implantation method that involves separation, the desired impurity (in this case, nitrogen) can be removed. If elements other than those specified (for example, metallic elements, etc.) are added to the first oxide semiconductor layer 144a It can prevent this. Also, ion doping is more effective than ion implantation. Since the area irradiated by the ion can be increased, impurities can be removed using the ion doping method. By adding this, the cycle time can be shortened.

[0195] The nitrogen concentrations in impurity region 144c and impurity region 144d are 5 × 10⁻⁶. 19 ate / c m 3 The above is preferable. Note that the nitrogen in impurity region 144c and impurity region 144d The elementary concentration is determined by secondary ion mass spectrometry (SIMS). This was measured using spectroscopy.

[0196] Furthermore, the nitrogen concentrations in the impurity region 144c and impurity region 144d are 1 × 10⁻⁶. 2 0 atoms / cm 3 If the amount is less than 7 atomic%, the impurity region 144c, and By performing heat treatment after the formation of impurity region 144d, the crystal structure becomes a wurtzite-type structure. There are also the following. The heat treatment temperature is 300°C to 600°C, preferably 350°C to 50°C. It is best if the temperature is below 0°C.

[0197] Furthermore, as shown in this embodiment, impurity injection treatment is performed via the gate insulating layer 146. This reduces excessive damage to the first oxide semiconductor layer 144a.

[0198] In this embodiment, the method for introducing impurities via the gate insulating layer 146 is described below. The examples given are limited to these. For example, impurities can be injected through the insulating layer that is formed later. Input processing may be performed.

[0199] Thus, in the first oxide semiconductor layer 144a, the channel formation region is sandwiched between the in By creating a pure material region, the impurity region has a lower energy level compared to the channel formation region. The top is small and carriers flow easily. Therefore, a transistor with this configuration is This allows for high-speed writing of information.

[0200] Furthermore, by providing impurity regions on either side of the channel formation region, the drain electrode end can be accessed. This structure mitigates the concentration of the electric field.

[0201] Furthermore, impurity regions 144c and 144d can be transformed by injecting impurities into the first Because the resistance of the oxide semiconductor layer 144a is low, this region is called the low-resistance region (also called the n-type region). It is also possible.

[0202] In Figure 8(D), the oxide semiconductor has a low-resistance region (impurity region 144c, and impurities Although an example of a method for forming region 144d) was given, a transistor using an oxide semiconductor In this, the impurity region that functions as the source region or drain region is self-aligned One method of fabrication using a process involves exposing the surface of the oxide semiconductor layer and then argonp By performing a plasma treatment, the resistivity of the region of the oxide semiconductor layer exposed to the plasma is reduced. A method is disclosed (S. Jeon et al. "180nm Gate L ength Amorphous InGaZnO Thin Film Transi stor for High Density Image Sensor Appli cation”, IEDM Tech. Dig., p.504, 2010.).

[0203] However, in the above manufacturing method, after forming the gate insulating layer, the source region or Dre In order to expose the area that should become the in-zone, it is necessary to partially remove the gate insulating layer. Therefore, when the gate insulating layer is removed, the underlying oxide semiconductor layer is also partially over-etched. This causes chipping, reducing the thickness of the portion that should be the source or drain region. As a result, the resistance of the source or drain region increases, and over-etching occurs. This makes transistor characteristics more prone to defects.

[0204] To further miniaturize transistors, it is necessary to adopt a dry etching method with high processing precision. However, the above over-etching is due to the selectivity ratio between the oxide semiconductor layer and the gate insulating layer. This is particularly likely to occur when using a dry etching method that cannot be adequately secured.

[0205] For example, if the oxide semiconductor layer is thick enough, over-etching is not a problem. When the channel length is set to 200 nm or less, in order to prevent short-channel effects, the channel The thickness of the oxide semiconductor layer in the region where the layer is formed is 20 nm or less, preferably 10 nm or less. This is required. When dealing with such a thin oxide semiconductor layer, oxide semiconductor Over-etching of a layer increases the resistance of the source or drain region, as described above. Furthermore, this is undesirable because it can cause transistor performance defects.

[0206] However, as in this embodiment, impurities are implanted into the oxide semiconductor layer, and the oxide semiconductor layer By performing the process without exposing the gate insulating layer, over-etching of the oxide semiconductor layer is achieved. This prevents turbulence and reduces excessive damage to the oxide semiconductor layer. Therefore, This can improve the characteristics and reliability of the zista.

[0207] The configuration shown in this embodiment may be used in appropriate combination with the configurations shown in other embodiments. It is possible.

[0208] (Embodiment 3) In this embodiment, a memo is configured using the semiconductor devices of Embodiment 1 and Embodiment 2. An example of Ricell 170 is shown using Figure 9.

[0209] <Memory cell composition> Figure 9(A) shows a cross-sectional view of memory cell 170, and Figure 9(B) shows a top view of memory cell 170. Figure 9(C) shows the circuit diagram of the memory cell 170.

[0210] Figures 9(A) and 9(B) show semiconductor devices corresponding to Figure 1(A), but the present invention The embodiments are not limited to this. Which of the semiconductor devices shown in Figures 1, 3, and 4 These configurations may be applied, or other semiconductor device configurations having similar functionality may be applied. .

[0211] The memory cell 170 shown in Figures 9(A), (B), and (C) is a transistor 160 and It has a capacitive element 164.

[0212] In the memory cell 170 shown in Figure 9(A), the drain electrode of the transistor 160 or The source electrode 142a is distributed through openings made in the insulating layer 150 and the insulating layer 154. It is electrically connected to wire 156. Note that in Figure 9(A), insulating layer 150 and insulating layer 1 The configuration involves stacking 54 layers, but it is not limited to this. Three or more insulating layers can be stacked. That's fine, or even just one layer is fine.

[0213] In the memory cell 170 shown in Figure 9(C), the first wiring (also called the bit line BL) and The second is electrically connected to either the source electrode or the drain electrode of the transistor 160. The wiring (also called the word line WL) and the gate electrode of transistor 160 are electrically connected. It continues. And the other of the source electrode or drain electrode of transistor 160, One of the electrodes of the capacitive element 164 is electrically connected to the third wiring (also called the capacitance line CL). ) and the other electrode of the capacitive element 164 are electrically connected.

[0214] Here, the transistor 160 uses the oxide semiconductor described in Embodiments 1 and 2. Transistors are applied. Transistors using oxide semiconductors as described in Embodiments 1 and 2 The ZISTA has the characteristic of having an extremely low off-current. Therefore, transistor 1 By turning off 60, the potential applied to the capacitive element 164 is maintained for an extremely long period of time. It is possible to hold it in this way. Furthermore, the transistor 160 using an oxide semiconductor is Because the channel length (L) is set to 10nm or more and 1000nm or less, power consumption is low and movement It also has the characteristic of having an extremely high production speed.

[0215] Furthermore, the capacitance element 164 uses the oxide semiconductor described in Embodiments 1 and 2 as the dielectric. A capacitive element is applied. Because oxide semiconductors have a high dielectric constant, the dielectric of the capacitive element 164 and By using it in this way, the capacitance per unit area of ​​the capacitive element 164 can be increased.

[0216] In the semiconductor device shown in Figure 9(C), the potential applied to the capacitive element 164 can be maintained. By utilizing the characteristics, information can be written, stored, and read in the following ways.

[0217] First, we will explain how to write and store information. For simplicity, we will use the third distribution. Assume the potential of the wires is fixed. First, set the potential of the second wire to transistor 160 The potential is set to turn on, and transistor 160 is turned on. This results in the first The potential of the wiring is applied to one of the electrodes of the capacitive element 164. That is, capacitive element 164 A predetermined charge is applied (written) to it. Then, the potential of the second wiring is set by the transistor. By setting the potential to the OFF state of transistor 160, the transistor 160 is turned OFF. The charge applied to the capacitive element 164 is retained (held). Transistor 160 is as described above. As such, the off-current is extremely small, allowing it to retain charge for extended periods.

[0218] Next, we will explain how to read the information. When a predetermined potential (constant potential) is applied to the first wiring... In this state, if the potential of the second wiring is set to the potential at which transistor 160 turns ON, the capacitance element Depending on the amount of charge held in child 164, the first wiring takes on a different potential. Therefore, By observing the potential of the first wire, the stored information can be read.

[0219] Note that once the information is read, the charge on the capacitive element 164 is lost, so writing to it again will not work. It is important to note that this should be done.

[0220] Next, we will explain how to rewrite information. Rewriting information involves writing the information as described above and This is done in the same way as holding. In other words, the potential of the second wiring is set when transistor 160 is ON. The potential is set to such a state, and transistor 160 is turned on. This sets the potential of the first wiring. (A potential related to new information) is applied to one of the electrodes of the capacitive element 164. Then, the second The potential of the wiring is set to the potential at which transistor 160 is in the OFF state, and transistor 160 By turning it off, the capacitive element 164 is in a state where it is given a charge related to new information. To become.

[0221] Thus, the semiconductor device relating to the disclosed invention directly generates information through subsequent writing. It is possible to rewrite the information. This enables high-speed operation of semiconductor devices.

[0222] Note that the above explanation refers to an n-type transistor (n-channel transistor) that uses electrons as carriers. This concerns the case where a large number of holes are used instead of an n-type transistor. It goes without saying that a p-type transistor can be used.

[0223] (Embodiment 4) In this embodiment, the semiconductor is configured using the semiconductor devices of Embodiments 1 to 3. The configuration of the device will be explained with reference to Figures 10 to 12.

[0224] <Configuration of a semiconductor device> Figure 10(A) shows a conceptual diagram illustrating an example of the configuration of a semiconductor device. A semiconductor according to one aspect of the present invention The conductive device has a memory circuit at the top and requires high-speed operation to drive the memory circuit at the bottom. This is a multilayer semiconductor device that has peripheral circuits such as drive circuits and control circuits. The dynamic circuits and control circuits may be logic circuits or may have analog circuits. It may also have an arithmetic circuit.

[0225] The semiconductor device shown in Figure 10(A) has multiple memory cells as a memory circuit at the top. It has a recell array 201, and at the bottom, a first drive circuit 211, a second drive circuit 212, 3 drive circuits 213, 4th drive circuit 214, 5th drive circuit 215, controller 21 8. Memory cell array 201, including address buffer 221, I / O buffer 220, etc. It has peripheral circuits 210 necessary for operation. The first drive circuit 211 is a column deco It has a driver 217a and a sense amplifier group 216a, and the second drive circuit 212 is a column deco It has a driver 217b and a sense amplifier group 216b.

[0226] The substrate on which the peripheral circuit 210 shown in Figure 10(A) is provided can be, for example, silicon or gel. A semiconductor substrate made of the 14th element, such as magnesium, silicon germanium, and silicon carbide, Furthermore, compound semiconductor substrates such as gallium arsenide and indium phosphide, and SOI substrates can be applied. This is possible. Generally speaking, an "SOI substrate" is a structure in which a silicon layer is provided on an insulating surface. This refers to a substrate made of silicon, but in this specification, it refers to a semiconductor made of a material other than silicon on an insulating surface. This also includes substrates having a conductive layer. Furthermore, the SOI substrate may include glass substrates. This includes configurations in which a semiconductor layer is provided on an insulating substrate via an insulating layer. By forming the peripheral circuit 210 using the aforementioned substrate, the peripheral circuit 210 can be operated at high speed. This is preferable because it allows for the production of the product.

[0227] <Cross-sectional configuration of a semiconductor device> Figure 10(B) is a cross-sectional view of a semiconductor device. The semiconductor device shown in Figure 10 has a memory cell at the top. It has a lu array 201 and peripheral circuits 210 at the bottom. The memory cell array 201 is at the top. The transistor 160 uses an oxide semiconductor, and the peripheral circuit 210 at the bottom uses acid It has a transistor 159 made of semiconductor material other than a synthetic semiconductor. Details of the memory cell 170 provided at the top are described in Embodiments 1 to 3. The information provided can be taken into consideration.

[0228] Transistors 159 and 160 are n-channel and p-channel transistors, respectively. Any type of transistor can be used. Here, transistor 159, The ZISTA 160 will be described as an n-channel transistor. In this embodiment, the technical essence is to use an off-current such as an oxide semiconductor to retain information Semiconductor materials that can be sufficiently reduced are used for the transistor 160 and the capacitive element 164. Because it is located at a certain point, the materials used in semiconductor devices and the structure of semiconductor devices, etc. It is not necessary to limit the specific configuration to those shown here.

[0229] The transistor 159 is provided on a substrate 100 containing a semiconductor material (for example, silicon). A channel-forming region 116 and an impurity formed so as to sandwich the channel-forming region 116 Region 120, metal compound region 124 adjacent to impurity region 120, and channel formation region 1 A gate insulating layer 108 provided on 16, and a gate insulating layer 108 provided on the gate insulating layer 108 A source electrode or drain electrode 1 that is electrically connected to the electrode 110 and the metal compound region 124. It has 30b, a drain electrode or source electrode 130a, and transistor 16 An insulating layer 128 is provided to cover 0. Source electrode or drain electrode 130 b. The drain electrode or source electrode 130a is through an opening formed in the insulating layer 128 , is electrically connected to the metal compound region 124. Also, on the insulating layer 128, An electrode 136a is formed in contact with the electrode or drain electrode 130b, and the drain electrode or Electrode 136b is formed in contact with source electrode 130a.

[0230] Furthermore, an element isolation insulating layer 106 is provided on the substrate 100 so as to surround the transistor 159. Furthermore, in order to achieve high integration, transistors are used as shown in Figure 10(B). It is desirable that 159 has a configuration without a sidewall insulating layer. On the other hand, If the characteristics of STA 159 are important, a sidewall insulating layer is applied to the side of the gate electrode 110. A region with a different impurity concentration is formed in the region that overlaps with the sidewall insulating layer. An impurity region 120 may be provided, including the above.

[0231] The transistor 160 in Figure 10(B) is the same as the transistors shown in Embodiments 1 to 3. Transistor 160 or transistor 162 can be used.

[0232] The capacitive element 164 is the same as the capacitive element 164 shown in Embodiments 1 to 3. It is possible.

[0233] An insulating layer 150 and an insulating layer 154 are provided on the transistor 160 and the capacitive element 164. It is connected to the drain electrode or source electrode 142a of transistor 160. The wire 156 is electrically connected through an opening formed in the insulating layer 150, insulating layer 154, etc. Wiring 156 is a wire that electrically connects one memory cell to another memory cell. Yes. Also, wiring 156 is connected to the drain electrode or source electrode 142a and electrode 126. It is electrically connected to electrode 130c via this. This connects to the lower layer peripheral circuit 210. This allows for electrical connection to the upper memory cell array 201.

[0234] In the semiconductor device shown in Figure 10(B), the upper memory cell array 201 and the lower peripheral circuit An insulating layer 140 is provided between the circuit 210 and the other element.

[0235] Transistor 159 uses semiconductor materials other than oxide semiconductors. Examples of semiconductor materials other than the human body include silicon, germanium, and silicon-germanium. Silicon carbide or gallium arsenide can be used, and single-crystal semiconductors can be used. This is preferable. Alternatively, organic semiconductor materials may be used. Transistors are capable of sufficiently high-speed operation. Therefore, materials other than oxide semiconductors are used. The transistors used are suitable for various circuits requiring high-speed operation (logic circuits, drive circuits, etc.). This can be effectively achieved.

[0236] On the other hand, in transistor 160, an oxide semiconductor material is used. The transistor using the oxide semiconductor material shown can achieve extremely low off-current. This characteristic allows the memory cell 170 to retain its stored contents for an extremely long period of time. This is possible. In other words, the refresh operation becomes unnecessary, or the refresh operation is eliminated. Because the frequency of operation can be made extremely low, power consumption can be reduced. Furthermore, even in the absence of power supply (however, it is desirable that the potential be fixed) It is possible to retain memory content over a long period of time.

[0237] Furthermore, the capacitive element 164 can be a capacitive element using the aforementioned oxide semiconductor as the dielectric. Because oxide semiconductors have a high dielectric constant, they can be used as the dielectric material for the capacitance element 164, thus producing capacitance. The capacitance per unit area of ​​element 164 can be increased.

[0238] Thus, transistors using materials other than oxide semiconductors (transistors using oxide semiconductors) Peripheral circuits such as drive circuits using transistors (which can operate at higher speeds than conventional transistors), and acid A transistor using a synthetic semiconductor (more broadly, a transistor with a sufficiently low off-current) ) and a memory circuit having a capacitive element using an oxide semiconductor are integrated together, This makes it possible to realize semiconductor devices with unprecedented features.

[0239] In Figure 10, a single-layer memory cell array 201 is stacked on the peripheral circuit 210. Although examples have been shown, the present invention is not limited thereto. Figures 11 and 12 show... As shown, two or more memory cell arrays may be stacked.

[0240] Figures 11 and 12 are cross-sectional views of the storage device. The storage device shown in Figures 11 and 12 is at the top It has multiple memory cells formed in multiple layers, and peripheral circuits 304 at the bottom. Among the memory cells, memory cell 370a and memory cell 370b are shown as representative examples.

[0241] Furthermore, the transistor 371a and the capacitive element 372a included in the memory cell 370a are replaced The following are shown in the table: Transistor 371b and capacitive element 372b included in memory cell 370b. This is shown as a representative example. Transistors 371a and 371b have a chip in the oxide semiconductor layer. A transistor in which a channel is formed. The configuration of the ZISTA is the same as the configuration described in the other embodiments, The explanation will be omitted. Capacitive elements 372a and 372b use oxide semiconductors as dielectrics. This is a capacitive element that uses a dielectric material. Regarding capacitive elements that use oxide semiconductors as the dielectric material... Therefore, since the configuration is the same as that described in the other embodiments, the explanation will be omitted.

[0242] Electrode 351a formed in the same layer as the source and drain electrodes of transistor 371a It is electrically connected to electrode 303a by electrode 352a. Transistor 37 Electrode 351c, formed in the same layer as the source and drain electrodes of 1b, is the same as electrode 352c It is electrically connected to electrode 303c.

[0243] Furthermore, peripheral circuit 304 uses semiconductor materials other than oxide semiconductors as channel formation regions. It has a transistor 301. The transistor 301 is made of a semiconductor material (for example, silicon). A substrate 300 containing elements such as is provided with an element isolation insulating layer 306, surrounded by the element isolation insulating layer 306. A transistor is obtained by forming a channel region in the region. Yes, it is possible. Note that transistor 301 is a semiconductor layer such as a silicon layer formed on an insulating surface. Alternatively, it may be a transistor in which a channel is formed in the silicon layer of the SOI substrate. Since a known configuration can be used for the radiator 301, the explanation is omitted. To abbreviate.

[0244] Between the layer on which transistor 371a is formed and the layer on which transistor 301 is formed Wiring 310a and wiring 310b are formed. Wiring 310a and transistor 301 Between the formed layers, an insulating layer 340a is provided, and wiring 310a and wiring 310b An insulating layer 341a is provided between them, and the wiring 310b and transistor 371a are formed. An insulating layer 342a is provided between the layers.

[0245] Similarly, the layer on which transistor 371b is formed and the layer on which transistor 371a is formed Wiring 310c and wiring 310d are formed between them. Wiring 310c and the transition An insulating layer 340b is provided between the layer on which the sta 371a is formed and the wiring 310c and An insulating layer 341b is provided between the wire 310d and the transistor 371 An insulating layer 342b is provided between the layer on which b is formed and the other layer.

[0246] Insulating layer 340a, insulating layer 341a, insulating layer 342a, insulating layer 340b, insulating layer 341b, The insulating layer 342b functions as an interlayer insulating layer, and its surface is made planar. can.

[0247] Wiring 310a, wiring 310b, wiring 310c, and wiring 310d connect the cells. It can perform gaseous connections and electrical connections between peripheral circuits 304 and memory cells.

[0248] The electrode 303 included in the peripheral circuit 304 is electrically connected to the circuit provided above. It is possible.

[0249] For example, as shown in Figure 11, electrode 303 is electrically connected to wiring 310a by electrode 355. It can be connected. Wiring 310a is electrically connected to electrode 351b by electrode 353a. It can be connected. Electrode 351b is formed in the same layer as transistor 371a, as shown in Figure Although not shown, it can be electrically connected to transistor 371a or capacitive element 372a. Furthermore, electrode 351b is electrically connected to wiring 353b by electrode 352b. This is possible. Wiring 353b is electrically connected to wiring 310c by electrode 303b. It is possible.

[0250] In Figure 11, the electrical connection between electrode 303 and transistor 371a is via wiring 310a. The example shown is an example of how it is performed, but it is not limited to this. The air connection may be made via wiring 310b, or via both wiring 310a and wiring 310b. This may also be done via the method shown in Figure 12, where the electrode 303 and transistor 37 The electrical connection to 1a may be made without using either wiring 310a or wiring 310b. (See Figure 12) Electrode 303 is electrically connected to wiring 353b by electrode 353. 353b is electrically connected to the source or drain of transistor 371a. This allows for an electrical connection between electrode 303 and transistor 371a.

[0251] Note that in Figures 11 and 12, there are two memory cells (memory cell 370a and memory cell 3 Although a stacked configuration of 70b) was shown as an example, the number of stacked memory cells is not limited to this. I can't.

[0252] Furthermore, in Figures 11 and 12, the layer on which transistor 371a is formed and transistor 3 Between the layer in which 01 is formed, there is a wiring layer in which wiring 310a is formed, and wiring 310b is formed The diagram shows a configuration with two wiring layers, but it is not limited to this. Between the layer on which transistor 371a is formed and the layer on which transistor 301 is formed, There may be one wiring layer, or there may be three or more wiring layers.

[0253] Furthermore, in Figures 11 and 12, the layer on which transistor 371b is formed and transistor 3 Between the layer in which 71a is formed, there is a wiring layer in which wiring 310c is formed, and wiring 310d The diagram shows a configuration with two wiring layers, but it is not limited to this. Between the layer on which transistor 371b is formed and the layer on which transistor 371a is formed There may be one wiring layer, or there may be three or more wiring layers.

[0254] (Embodiment 5) In this embodiment, the semiconductor device described in the previous embodiment is used in a mobile phone, smartphone, Examples of applications to mobile devices such as e-books will be explained using Figures 13 to 16.

[0255] In mobile devices such as cell phones, smartphones, and e-readers, temporary storage of image data SRAM or DRAM is used in these applications. The reason is that flash memory has a slow response time and is unsuitable for image processing. On the other hand, when SRAM or DRAM is used for temporary storage of image data, the following characteristics apply. .

[0256] In a typical SRAM, as shown in Figure 13(A), one memory cell is located in transistors 401-4 It consists of 6 transistors of type 06, which are used for the X decoder 407 and the Y decoder. It is driven by transistor 408. Transistors 403, 405, and 40 4 and transistor 406 form an inverter, enabling high-speed drive. However, one Because the memory cell is composed of 6 transistors, it has the disadvantage of having a large cell area. When the minimum dimension of the design rule is F, the memory cell area of ​​SRAM is typically 100 ~150F 2 Therefore, SRAM has the highest cost per bit among all types of memory. There is a challenge.

[0257] In contrast, DRAM has a memory cell, as shown in Figure 13(B), transistor 411, It is composed of capacitive elements 412, which are then connected to the X decoder 413 and Y decoder 414. It is in operation. Each cell has a configuration of 1 transistor and 1 capacitance, resulting in a small area. The memory cell area of ​​DRAM is typically 10F 2 The following applies. However, DRAM is always refreshed. A scrub is required, and even if no rewriting occurs, power consumption is still incurred, which presents a challenge. ru.

[0258] However, the memory cell area of ​​the semiconductor device described in the previous embodiment is 10F 2 Front and back Furthermore, frequent refreshing is unnecessary. Therefore, it has a small footprint and low power consumption. This can result in a reduced number of memory cells.

[0259] Next, Figure 14 is a block diagram of the portable device. The portable device shown in Figure 14 has an RF circuit 501. Analog baseband circuit 502, digital baseband circuit 503, battery 504 , power supply circuit 505, application processor 506, flash memory 510, D Play controller 511, memory circuit 512, display 513, touch sensor 5 19. It consists of an audio circuit 517, a keyboard 518, etc. Display 513 It consists of a display unit 514, a source driver 515, and a gate driver 516. The application processor 506 is CPU 507, DSP 508, interface It has a 509 (IF509). Generally, memory circuits are composed of SRAM or DRAM. However, the memory circuit 512 employs the semiconductor device described in the previous embodiment. This enables high-speed information writing and reading, and reduced power consumption in portable devices. It can be done this way.

[0260] Next, Figure 15 shows the memory circuit 600 of the display connected to the semiconductor device described in the previous embodiment. This is an example of its use. The memory circuit 600 shown in Figure 15 includes memory 602, memory 603, It consists of switch 604, switch 605 and memory controller 601. The semiconductor device described in the previous embodiment is applied to memory 602 and memory 603. .

[0261] First, some image data is formed by an application processor (not shown). The formed image data (input image data 1) is sent to memory via switch 604. It is stored in 602. And the image data stored in memory 602 (stored image data 1) The display 607 is accessed via switch 605 and display controller 606. It is sent to and displayed.

[0262] If there are no changes to the input image data 1, the stored image data 1 is typically stored at a frequency of about 30-60 Hz. During this period, the memory 602 is read from the display controller 606 via the switch 605. To be revealed.

[0263] Next, for example, when a user performs an operation to rewrite the screen (i.e., when the input image data is If there are any changes, the application processor will use the new image data (input image data 2). The input image data 2 is stored in memory 603 via switch 604. During this time, the stored image data 1 was periodically read from memory 602 via switch 605. It is being stored. When the new image data (storage image data 2) has finished being stored in memory 603, From the next frame on display 607, the stored image data 2 is read out, and switch 605 , and stored image data to the display 607 via the display controller 606. A value of 2 is sent, and the display is performed. This read then sends new image data to memory. This continues until it is stored in 602.

[0264] In this way, memory 602 and memory 603 alternately write and read data. By performing the output, the display 607 will be displayed. Note that memory 602, And memory 603 is not limited to separate memory units, but can be used by dividing a single memory unit. The semiconductor device described in the previous embodiment may be used in memory 602 and memory 603. By using this technology, information can be written and read at high speed, and power consumption can be reduced. It can be used as a display.

[0265] Next, Figure 16 is a block diagram of an e-book. The e-book shown in Figure 16 uses battery 701 , power supply circuit 702, microprocessor 703, flash memory 704, audio circuit 70 5. Keyboard 706, memory circuit 707, touch panel 708, display 709, It is composed of a display controller 710. The device can be used in the memory circuit 707. The memory circuit 707 temporarily stores the contents of the book. It has a function to temporarily retain data. An example of using the function to temporarily retain the content of an e-book is... This may occur when the user uses the highlighting function while reading an ebook. When doing so, there are times when you want to mark a specific location. In such cases, this embodiment... E-books have a highlighting function that allows you to change the display color, underline, and text. Making text bolder or changing the font style can help differentiate it from its surroundings. The highlight function is a feature that remembers and retains information about the parts specified by the user. If you want to store this information for a long period of time, you can copy the information to flash memory 704. i. In such cases as well, adopting the semiconductor device described in the previous embodiment Therefore, ebooks that allow for high-speed writing and reading of information and have reduced power consumption. It is possible.

[0266] (Embodiment 6) In this embodiment, when applying the semiconductor device described in the above embodiment to an electronic device, This will be explained using Figure 17. In this embodiment, a computer and a mobile phone (mobile Telephones (also called mobile phones), personal information terminals (including portable game consoles, audio playback devices, etc.) Cameras such as digital cameras and digital video cameras, e-paper, televisions Electronic devices such as televisions (also called televisions or television receivers) use the aforementioned semiconductors. This section explains when the device will be applied.

[0267] Figure 17(A) shows a notebook-type personal computer, consisting of chassis 801, chassis 802, It consists of a display unit 803, a keyboard 804, etc., and enclosures 801 and 802. At least one of them is provided with the semiconductor device shown in the previous embodiment. A notebook-type personal computer with high-speed data writing and reading, and reduced power consumption. Computers will be realized.

[0268] Figure 17(B) shows a tablet terminal 810. The tablet terminal 810 has a display unit 8 A housing 811 having 12, a housing 813 having a display unit 814, and an operation button 815, It has an external interface 816. It also has a style for operating the tablet terminal 810. It is equipped with components such as the LASS 817. Electronic circuits are provided inside the casings 811 and 813. The electronic circuit is provided with the semiconductor device shown in the previous embodiment. A tablet device that allows for high-speed writing and reading of information, and has reduced power consumption. It will be realized.

[0269] Figure 17(C) shows an e-reader 820 with electronic paper implemented, consisting of a casing 821 and a casing 82 It consists of two enclosures, 821 and 823, respectively. 25 and a display unit 827 are provided. The housing 821 and housing 823 are connected by the shaft portion 837 It is connected and can open and close using the shaft portion 837 as an axis. Also, the housing 8 Unit 21 is equipped with a power supply 831, operation keys 833, speaker 835, etc. (Enclosure 821) At least one of the housings 823 is provided with the semiconductor device shown in the previous embodiment. Therefore, ebooks have high-speed information writing and reading capabilities, and reduced power consumption. This will be realized.

[0270] Figure 17(D) shows a mobile phone, which consists of two casings, casing 840 and casing 841. Furthermore, the casings 840 and 841 slide and unfold as shown in Figure 17(D). It can be transformed from a separate state to an overlapping state, and can be miniaturized to suit portability. The enclosure 841 includes a display panel 842, a speaker 843, a microphone 844, and an operating panel. Key 845, pointing device 846, camera lens 847, external connection terminal 84 It is equipped with 8, etc. Also, the housing 840 has a solar cell 849 that charges the mobile phone. It also features an external memory slot 850, etc. Furthermore, the antenna is built into the housing 841. It is provided. At least one of the housings 840 and 841 is equipped with the semiconductor equipment shown in the previous embodiment. A space is provided for this. Therefore, information can be written and read at high speed, and power consumption is low. A mobile phone with reduced noise will be realized.

[0271] Figure 17(E) shows a digital camera, consisting of a main unit 861, a display unit 867, an eyepiece unit 863, and a control panel. It consists of a power switch 864, a display unit 865, a battery 866, etc. The semiconductor device shown in the previous embodiment is provided inside 861. Therefore, the information book This will enable the creation of digital cameras with high-speed data entry and reading, as well as reduced power consumption. .

[0272] Figure 17(F) shows a television device 870, consisting of a housing 871, a display unit 873, and a stand. It consists of 875 and others. The television device 870 is operated by the casing 871. This can be done using the switch or the remote control unit 880. The housing 871 and the remote control unit The machine 880 is equipped with the semiconductor device shown in the previous embodiment. Therefore, information A television system with high-speed writing and reading capabilities and reduced power consumption has been realized. It can be done.

[0273] As described above, the electronic device shown in this embodiment is equipped with the semiconductor device according to the previous embodiment. It is included. Therefore, electronic devices with reduced power consumption can be realized.

[0274] In Examples 1 and 2 below, oxide semiconductor layers were actually fabricated and their relative permittivity was measured. The results will be explained using Figures 18 to 20. [Examples]

[0275] As shown in Figure 18(A), an oxide semiconductor (denoted as OS in the figure) is placed on a p-type silicon substrate. A 100 nm layer was formed, and its CV (capacitance and voltage) was measured. In this example, an oxide semiconductor layer was formed. An In-Sn-Zn-O oxide was used as the conductor. Specifically, In:Sn:Zn=2: Using an oxide target with a 1:3 (atomic ratio), an oxide semiconductor layer is formed by sputtering. The structure was formed. From the obtained CV measurement results, the storage capacity (C0) (see Figure 18(B)) was determined. The relative permittivity was calculated from the storage capacitance (C0) using Equation 1. Here, the induction of the oxide semiconductor Let ε be the electric constant, ε0 be the permittivity of vacuum, S be the area, and d be the relative permittivity.

[0276]

number

[0277] Figure 19 shows the measurement results for CV. The horizontal axis represents the applied voltage, and the vertical axis represents the capacitance. Sample size: n = 7. The calculation results in an oxide target with In:Sn:Zn = 2:1:3 (atomic ratio). The relative permittivity (d) of the oxide semiconductor layer formed using was approximately 20. [Examples]

[0278] In this embodiment, an oxide semiconductor is used, specifically an oxide with an atomic ratio of In:Ga:Zn = 1:1:1. Using the In-Ga-Zn-O-based oxide formed with the target, the same procedure as in Example 1 was followed. The relative permittivity was measured.

[0279] Figure 20 shows the measurement results for CV. The sample size n=5. The calculation results are In:Ga:Z Ratio of oxide semiconductor layers formed using an oxide target with n=1:1:1 (atomic ratio) The dielectric constant (d) was approximately 15.

[0280] From the results of Example 1 and Example 2, the relative permittivity of the oxide semiconductor layer is approximately 4. It was shown to be sufficiently high compared to silicon oxide. [Explanation of symbols]

[0281] 100 circuit boards 106 element isolation insulating layer 108 Gate Insulation Layer 110 Guard Station 116 Channel formation region 120 Impurity region 124 Metal compound area 126 electrode 128 Insulating layer 130a Drain electrode or source electrode 130b Source electrode or drain electrode 130c electrode 136a electrode 136b Electrode 140 Insulating layer 141a Metal oxide layer 141b Metal oxide layer 142 Conductive layer 142a Drain electrode or source electrode 142b Source electrode or drain electrode 144a First oxide semiconductor layer 144b Second oxide semiconductor layer 144c impurity region 144d Impurity region 146 Gate Insulation Layer 147b Electrode 148 Conductive layer 148a Token 148b First electrode 149a Metal oxide layer 149b Metal oxide layer 150 Insulating layer 152 Electrode 154 Insulating layer 156 Wiring 159 transistors 160 transistors 162 transistors 164 Capacitive elements 170 cell cells 201 Memory Cell Array 210 Peripheral Circuits 211 Drive Circuit 212 Drive Circuit 213 Drive Circuit 214 Drive Circuit 215 Drive Circuit 216a Sense Amplifier Group 216b Sense Amplifier Group 217a Column Decoder 217b Column Decoder 218 Controllers 220 I / O buffers 221 Address Buffer 300 circuit boards 301 Transistors 303 Electrode 303a electrode 303b electrode 303c electrode 304 Peripheral Circuits 306 Element Isolation Insulating Layer 310a wiring 310b Wiring 310c wiring 310d wiring 340a insulating layer 340b Insulating layer 341a Insulating layer 341b Insulating layer 342a Insulating layer 342b Insulating layer 351a electrode 351b electrode 351c electrode 352a electrode 352b electrode 352c electrode 353 Electrode 353a electrode 353b Wiring 355 Electrode 370a memory cell 370b memory cell 371a Transistor 371b Transistor 372a Capacitive element 372b Capacitive element 401 Transistors 402 transistors 403 Transistors 404 transistors 405 transistors 406 transistors 407 X Decoder 408 Y Decoder 411 transistors 412 Capacitive elements 413 X Decoder 414 Y Decoder 501 RF circuit 502 Analog Baseband Circuit 503 Digital Baseband Circuit 504 Battery 505 Power supply circuit 506 Application Processors 507 CPU 508 DSP 509 Interface 510 Flash Memory 511 Display Controller 512 memory circuit 513 displays 514 Display section 515 Source Driver 516 Gate Driver 517 Audio Circuit 518 keyboards 519 Touch Sensor 600 memory circuit 601 Memory Controller 602 memory 603 memory 604 Switch 605 Switch 606 Display Controller 607 display 701 Battery 702 Power supply circuit 703 Microprocessor 704 Flash Memory 705 Audio Circuit 706 keyboard 707 Memory Circuit 708 Touch Panel 709 displays 710 Display Controller 801 cabinet 802 cabinet 803 Display section 804 Keyboard 810 Tablet devices 811 cabinet 812 Display section 813 cabinet 814 Display section 815 Operation Buttons 816 External Interface 817 Stylus 820 eBooks 821 cabinet 823 cabinets 825 Display section 827 Display section 831 Power supply 833 Operation Keys 835 Speakers 837 Shaft 840 cabinets 841 cabinet 842 Display Panel 843 Speakers 844 Microphone 845 Operation Keys 846 Pointing devices 847 Camera Lens 848 External connection terminal 849 solar cells 850 external memory slots 861 Main Unit 863 Eyepiece 864 Operation Switch 865 Display section 866 Battery 867 Display section 870 Television equipment 871 cabinet 873 Display section 875 Stand 880 Remote Control Unit

Claims

1. A first conductive layer and A first oxide semiconductor layer having a region on the first conductive layer, A second oxide semiconductor layer having a region on the first conductive layer, A first insulating layer having a region on the first oxide semiconductor layer and having a single-layer structure, A second conductive layer having a region on the first insulating layer, A second insulating layer having a region on the second conductive layer, A third conductive layer having a region on the second oxide semiconductor layer, The first oxide semiconductor layer has a channel formation region for the transistor, The second conductive layer has a region that overlaps with the first oxide semiconductor layer via the first insulating layer. The second conductive layer has a region that functions as the gate electrode of the transistor, The first oxide semiconductor layer has a region that overlaps with the first region of the first conductive layer, The first oxide semiconductor layer is electrically connected to the first conductive layer. The first oxide semiconductor layer has a region that overlaps with the fourth conductive layer which functions as the source electrode or drain electrode of the transistor. The first oxide semiconductor layer is electrically connected to the fourth conductive layer. The second oxide semiconductor layer has a region that overlaps with the second region of the first conductive layer. The third conductive layer has a region that overlaps with the second region via the second oxide semiconductor layer and without the conductive layer, The third conductive layer has a region that functions as an electrode for a capacitive element, The first conductive layer comprises molybdenum, titanium, or copper. The second conductive layer has the same metallic material as the first conductive layer. The fourth conductive layer has the same metallic material as the first conductive layer. A semiconductor device having a second insulating layer having a region in contact with the second conductive layer, a region in contact with the third conductive layer, a region in contact with the first insulating layer, a region in contact with the second oxide semiconductor layer, and a region in contact with the fourth conductive layer.

2. In claim 1, The first conductive layer has a region that overlaps with the second conductive layer.

3. In claim 1 or 2, The first oxide semiconductor layer comprises Ga and Zn, The second oxide semiconductor layer comprises Ga and Zn in a semiconductor device.

Images