electronic machinery

Abstract

This invention provides an electronic device that can communicate with an I2C device that does not support I3C while it is connected to the bus of an I3C device. [Solution] The electronic device comprises a primary device operating according to the I3C communication specification, a secondary device operating according to the I2C communication specification but not compatible with the I3C communication specification, a clock bus, and a blocking means. The clock bus is connected to the primary device and the secondary device. The blocking means is connected to the clock bus and blocks the clock input to the primary device when the clock transmitted from the secondary device toward the clock bus is in a predetermined logical state.

Description

Technical Field

[0001] The present invention relates to an electronic device, and particularly to an electronic device that performs bus communication.

Background Art

[0002] Conventionally, there are known electronic devices including I2C devices that communicate according to a communication specification of bus communication called I2C (Inter-Integrated Circuit), and electronic devices including I3C devices that communicate according to a communication specification of bus communication which is an advanced version of I2C called I3C (Improved Inter Integrated Circuits). I3C is generally a communication specification that is backward compatible with I2C, but there is no compatibility for some functions.

[0003] Regarding this, Non-Patent Document 1 discloses a part of the communication specification of I3C. As described on page 19 of Non-Patent Document 1, I3C does not have a function called clock stretch employed in I2C. Clock stretch is a function that, when the processing of the secondary device cannot follow the clock transmitted from the primary device, forcibly transitions the logical state of the clock line to the "low" state and waits for the processing of the primary device.

Prior Art Documents

Patent Documents

[0004]

Non-Patent Document 1

Summary of the Invention

[0005] Some I2C devices are I3C-incompatible and cannot disable the clock stretching function. If an I2C device that is not I3C-compatible is connected to a bus used for communication between I3C devices, the I2C device will perform clock stretching, resulting in communication failures. Therefore, conventional electronic devices could not communicate when an I2C device that is not I3C-compatible was connected to a bus used by I3C devices.

[0006] This invention has been made in view of these problems, and its objective is to provide an electronic device that can communicate while an I2C device that does not support I3C is connected to the bus of an I3C device. [Means for solving the problem]

[0007] To solve the above problems, the first electronic device according to the present invention comprises a primary device that operates in accordance with the I3C communication specification, a secondary device that operates in accordance with the I2C communication specification and is not compatible with the I3C communication specification, a clock bus connected to the primary device and the secondary device, and a blocking means connected to the clock bus that blocks the input of the clock to the primary device when the clock transmitted from the secondary device toward the clock bus is in a predetermined logical state.

[0008] Furthermore, in the electronic device according to the second aspect of the present invention, the interruption means is a diode, the cathode terminal of which is connected to the clock terminal of the primary device, and the anode terminal of which is connected to the clock bus.

[0009] Furthermore, in the third electronic device according to the present invention, the predetermined logic state includes all logic states, and the blocking means is an input / output circuit provided between the clock bus and the secondary device, which inputs the clock transmitted from the primary device to the blocking means via the clock bus to the secondary device, and blocks the input of the clock transmitted from the secondary device to the blocking means to the clock bus.

[0010] Furthermore, in the fourth electronic device according to the present invention, when the secondary device performs a clock stretch operation as defined in the I2C communication specification, the clock stretch operation is terminated before the logic state of the clock transmitted from the primary device toward the clock bus becomes high. [Effects of the Invention]

[0011] According to the present invention, electronic devices can communicate while an I2C device that does not support I3C is connected to the bus of an I3C device. [Brief explanation of the drawing]

[0012] [Figure 1] This figure shows an example of the circuit configuration of an electronic device according to the first embodiment. [Figure 2] This is a timing chart showing an example of the logical state transitions of each signal in the electronic device according to the first embodiment. [Figure 3] This figure shows an example of the circuit configuration of an electronic device according to the second embodiment. [Figure 4] This figure shows an example of the circuit configuration of the blocking means according to the second embodiment. [Modes for carrying out the invention]

[0013] Hereinafter, embodiments of the present invention (hereinafter referred to as the "first embodiment" or "second embodiment") will be described with reference to the attached drawings. To facilitate understanding of the description, the same reference numerals are used for identical components and steps in each drawing whenever possible, and redundant explanations are omitted.

[0014] ---First Embodiment--- First, let me describe the first embodiment.

[0015] <Structure> Figure 1 shows an example of the circuit configuration of electronic device 1A according to the first embodiment. As shown in Figure 1, electronic device 1A is composed of, for example, an I3C device 10, a plurality of I2C devices 20, a blocking means 30A, a data bus W_DATA, a clock bus W_CLK, a power line W_VDD, and resistors R1 and R2. Electronic device 1A is, for example, a desktop computer, a laptop computer, a tablet, a smartphone, or a mobile phone. Note that electronic device 1A is not limited to the above example, and any device that includes the above-described components may be used.

[0016] The I3C device 10 is a device that operates according to the I3C communication specification. Specifically, the I3C device 10 is an integrated circuit enclosed in, for example, an electronic component package, and functions as the primary device in the I3C communication specification. The I3C device 10 has a data terminal D and a clock terminal CK as input / output terminals related to the I3C communication specification. The data terminal D of the I3C device 10 is connected to the data bus W_DATA, which is the I3C data bus. The clock terminal CK of the I3C device 10 is connected to the clock bus W_CLK, which is the I3C clock bus. The I3C device 10 transmits the data signal SDA from the data terminal D to the data bus W_DATA as an electrical signal for data according to the I3C communication specification. The I3C device 10 also transmits the clock SCLM from the clock terminal CK to the clock bus W_CLK as an electrical signal for the clock according to the I3C communication specification.

[0017] The I2C device 20 is a device that operates according to the I2C communication specification and is not compatible with the I3C communication specification. Specifically, the I2C device 20 is an integrated circuit enclosed in, for example, an electronic component package, and functions as a secondary device in the I2C communication specification. The I2C device 20 also has a clock stretching function defined in the I2C communication specification and does not have a function to disable the clock stretching function. The I2C device 20 has a data terminal D and a clock terminal CK as input / output terminals related to the I2C communication specification. The data terminal D of the I2C device 20 is connected to the data bus W_DATA. The clock terminal CK of the I2C device 20 is connected to the clock bus W_CLK. The I2C device 20 receives the data signal SDA transmitted to the data bus W_DATA via the data terminal D. The I2C device 20 also receives the clock SCL propagating to the clock bus W_CLK via the clock terminal CK. Furthermore, the I2C device 20 performs clock stretching operation in accordance with the I2C communication specifications. While performing clock stretching operation, the I2C device 20 transmits the clock SCLS from the clock terminal CK to the clock bus W_CLK so that its logic state becomes "low". Note that the electronic device 1A is not limited to having multiple I2C devices 20 connected to the clock bus W_CLK and data bus W_DATA, and may have only one I2C device 20 connected to the clock bus W_CLK and data bus W_DATA.

[0018] The data bus W_DATA is a data bus that conforms to the I3C communication specification. The data bus W_DATA transmits the data signal SDA sent from the I3C device 10 to multiple I2C devices 20. The data bus W_DATA is connected to the data terminal D of the I3C device 10 and to the data terminal D of the multiple I2C devices 20. The data bus W_DATA is also connected to the power line W_VDD via a resistor R1.

[0019] The clock bus W_CLK is a clock bus that conforms to the I3C communication specification. The clock bus W_CLK transmits the clock SCLM transmitted from the I3C device 10 as the clock SCL to a plurality of I2C devices 20. Also, the clock bus W_CLK propagates the clock SCLS transmitted from the I2C device 20 as the clock SCL on the clock bus W_CLK. The clock bus W_CLK is connected to the clock terminals CK of a plurality of I2C devices 20. Also, the clock bus W_CLK is connected to the power line W_VDD via the resistance element R2. Also, the clock bus W_CLK is connected to the clock terminal CK of the I3C device 10 via the blocking means 30A.

[0020] The blocking means 30A blocks the input of the clock SCLS to the I3C device 10 when the clock SCLS transmitted from the I2C device 20 toward the clock bus W_CLK is in a predetermined logic state. In the first embodiment, the predetermined logic state is the "low state". The blocking means 30A is, for example, a diode DI or a transistor connected in diode form. Here, the case where the blocking means 30A is the diode DI will be described. The blocking means 30A conducts the current flowing from the anode terminal to the cathode terminal and blocks the current flowing from the cathode terminal to the anode terminal. The blocking means 30A has the cathode terminal connected to the clock terminal CK of the I3C device 10 and the anode terminal connected to the clock bus W_CLK. Thereby, the blocking means 30A blocks the transmission of the clock SCL to the I3C device 10 when the logic state of the clock SCL propagating on the clock bus W_CLK is the "low state". On the other hand, the blocking means 30A transmits the clock SCL to the I3C device 10 when the logic state of the clock SCL propagating on the clock bus W_CLK is the "high state".

[0021] The resistive elements R1 and R2 are, for example, resistors, and both function as pull-up resistors. The resistive element R1 is a pull-up resistor for the data bus W_DATA, and connects the power supply line W_VDD and the data bus W_DATA via the resistive element R1. When the logical state of the data signal SDA is neither the "high state" nor the "low state", the resistive element R1 supplies the power supply potential VDD from the power supply line W_VDD to the data bus W_DATA to transition the logical state of the data signal SDA to the "high state". The resistive element R2 is a pull-up resistor for the clock bus W_CLK, and connects the power supply line W_VDD and the clock bus W_CLK via the resistive element R2. When the logical state of the clock SCL is neither the "high state" nor the "low state", the resistive element R2 supplies the power supply potential VDD from the power supply line W_VDD to the clock bus W_CLK to transition the logical state of the clock SCL to the "high state". Here, the state where the logical state is neither the "high state" nor the "low state" is, for example, the "high impedance state".

[0022] Here, while referring to FIG. 2, the operation in the electronic device 1A will be described. FIG. 2 is a timing chart showing an example of the transition of the logical states of each signal in the electronic device 1A according to the first embodiment. In FIG. 2, it is assumed that the I3C device 10 is transmitting the data signal SDA to the data bus W_DATA. Also, in FIG. 2, it is assumed that the I3C device 10 is transmitting the clock SCLM to the clock bus W_CLK. Further, in FIG. 2, it is assumed that only one I2C device 20 out of the plurality of I2C devices 20 is transmitting the clock SCLS to the clock bus W_CLK. Also, "H" on the vertical axis in FIG. 2 indicates the "high state" of the logical state. Also, "L" on the vertical axis in FIG. 2 indicates the "low state" of the logical state.

[0023] At time t1, the I3C device 10 transitions the logic state of the data signal SDA from "high" to "low". At time t1, the I3C device 10 maintains the logic state of the clock SCLM in the "high" state. As a result, the I3C device 10 transmits a start condition to the I2C device 20 via the data bus W_DATA and clock bus W_CLK to initiate communication according to the I3C communication specifications. The start condition is a state in which the logic state of the data signal SDA transitions from a "high" state to a "low" state. At time t1, the I2C device 20 maintains a state in which the output of the clock SCLS is stopped. That is, at time t1, the logic state of the clock SCLS is "undefined".

[0024] At time t2, which is after time t1, the I3C device 10 transitions the logic state of the clock SCLM from "high" to "low". At time t3, which is after time t2, the I3C device 10 transitions the logic state of the data signal SDA to the logic state of the data to be transmitted. At time t4, which is after time t3, the I3C device 10 transitions the logic state of the clock SCLM from "low" to "high". As a result, the I3C device 10 transmits the data indicated by the data signal SDA to the I2C device 20 via the data bus W_DATA.

[0025] At time t5, which is after time t4, the I3C device 10 transitions the logic state of the clock SCLM from "high" to "low". At time t6, which is after time t5, the I3C device 10 transitions the logic state of the data signal SDA to the logic state of the data to be transmitted after the data transmitted at time t3. At time t7, which is after time t6, the I3C device 10 transitions the logic state of the clock SCLM from "low" to "high". Thereafter, the I3C device 10 performs the same operations as it did at times t5 to t7, and sequentially transmits data to the I2C device 20.

[0026] At time t20, which is after time t7, the I2C device 20 transitions the logic state of the data signal SDA to either an acknowledgment (ACK) or a negative acknowledgment (NACK). Specifically, if the I2C device 20 successfully receives the data transmitted from the I3C device 10 between time t1 and time t20, it transitions the logic state of the data signal SDA to an acknowledgment. Conversely, if the I2C device 20 fails to successfully receive the data transmitted from the I3C device 10 between time t1 and time t20, it transitions the logic state of the data signal SDA to a negative acknowledgment. An acknowledgment logic state is, for example, a "low state". A negative acknowledgment logic state is a different logic state from the acknowledgment logic state, for example, a "high state".

[0027] At time t21, which is later than time t20, the I3C device 10 transitions the logic state of the clock SCLM from "low" to "high". As a result, the I3C device 10 receives information regarding the response status of the I2C device 20, indicated by the data signal SDA, via the data bus W_DATA. At time t22, which is later than time t21, the I3C device 10 transitions the logic state of the clock SCLM from "high" to "low".

[0028] At time t23, which is after time t22, the I2C device 20 starts clock stretching. Specifically, the I2C device 20 starts outputting clock SCLS so that its logic state becomes "low". As a result, at time t22, the clock bus W_CLK propagates clock SCL, which is in the "low" logic state. At time t22, the propagation of clock SCL is blocked by the blocking means 30A for the I3C device 10, so no clock SCL in the "low" logic state is input to the clock terminal CK of the I3C device 10.

[0029] At time t24, which is later than time t23, the I2C device 20 stops transmitting a logical state indicating an acknowledgment (ACK) or a logical state indicating a negative acknowledgment (NACK). At time t24, the I3C device 10 transitions the logical state of the data signal SDA to the logical state of the data to be transmitted further.

[0030] At time t25, which is after time t24, the I2C device 20 terminates its clock stretching operation. Specifically, the I2C device 20 stops outputting the clock SCLS. As a result, at time t25, the logic state of the clock SCLS transitions from "low" to "undefined". At time t25, the logic state of the clock SCL propagating on the clock bus W_CLK becomes "low" because the I3C device 10 outputs a clock SCLM with a logic state of "low". After starting the clock stretching operation, the I2C device 20 operates in such a way that it terminates the clock stretching operation before the I3C device 10 transitions the logic state of the clock SCLM from "low" to "high" and transmits the next data.

[0031] At time t30, which is later than time t25, the I3C device 10 transitions the logic state of the clock SCLM from "low" to "high". As a result, the I3C device 10 transmits the data indicated by the data signal SDA to the I2C device 20 via the data bus W_DATA.

[0032] <Effects and Effects> In the first embodiment described above, the electronic device 1A comprises an I3C device 10 (primary device), an I2C device 20 (secondary device), a clock bus W_CLK, and a blocking means 30A. The I3C device 10 operates according to the I3C communication specifications. The I2C device 20 operates according to the I2C communication specifications and is not compatible with the I3C communication specifications. The clock bus W_CLK is connected to the I3C device 10 and the I2C device 20. The blocking means 30A is connected to the clock bus W_CLK and blocks the input of the clock SCLS to the I3C device 10 when the clock SCLS transmitted from the I2C device 20 toward the clock bus W_CLK is in a predetermined logical state. If the blocking means 30A is not provided, when a clock SCLS in a predetermined logical state (here, "low state") is transmitted from the I2C device 20 toward the clock bus W_CLK, the predetermined logical state will be input to the I3C device 10, causing a malfunction. In contrast, the electronic device 1A is equipped with a blocking means 30A, which blocks the input of signals in a predetermined logic state to the I3C device 10. Therefore, the electronic device 1A can communicate with a non-I3C compatible I2C device 20 connected to the bus of the I3C device 10.

[0033] Furthermore, in the first embodiment, the blocking means 30A is a diode DI. The cathode terminal of the blocking means 30A is connected to the clock terminal CK of the I3C device 10, and the anode terminal is connected to the clock bus W_CLK. This allows the electronic device 1A to configure the blocking means 30A in a simple and low-component manner. Therefore, the electronic device 1A can communicate with a low-cost, non-I3C compatible I2C device 20 connected to the bus of the I3C device 10.

[0034] Furthermore, in the first embodiment, when the I2C device 20 performs the clock stretch operation defined in the I2C communication specification, it terminates the clock stretch operation before the logic state of the clock SCLM becomes "high". If the blocking means 30A is not provided, the clock stretch operation for the I3C device 10 (in this case, input of clock SCL, which has a logic state of "low") is an operation that is not permitted. In contrast, as long as the electronic device 1A terminates the clock stretch operation before the logic state of the clock SCLM becomes "high" from the drive cycle, it can receive clock SCL with a logic state of "high" via the I2C device 20 and operate normally. Therefore, the electronic device 1A can communicate with the I2C device 20, which is a non-I3C compatible type, connected to the bus of the I3C device 10 while the clock stretch operation by the I2C device 20 is enabled. In addition, the I3C communication specification defines the minimum value of the period during which the logic state of the clock SCLM is "high" and the drive frequency (reciprocal of the drive cycle) as criteria values ​​that must be met. Electronic device 1A can relax the upper limit of the clock stretch operation time for the I2C device 20 by subtracting the minimum period during which the logic state of the clock SCLM is in a "high state" from the drive cycle according to the I3C communication specifications.

[0035] ---Second Embodiment--- Next, a second embodiment will be described.

[0036] <Structure> Figure 3 shows an example of the circuit configuration of the electronic device 1B according to the second embodiment. As shown in Figure 3, the electronic device 1B according to the second embodiment is configured to include a plurality of interruption means 30B provided for each I2C device 20, instead of the interruption means 30A compared to the electronic device 1A according to the first embodiment. In addition, in the second embodiment, the I2C device 20 has an input clock terminal CK1 that functions as an input terminal for a clock according to the I2C communication specifications, and an output clock terminal CK2 that functions as an output terminal for a clock according to the I2C communication specifications.

[0037] The blocking means 30B is, for example, an interface that follows GPIO (General Purpose Input Output). The blocking means 30B connects the clock bus W_CLK to an I2C device 20. Specifically, the output terminal IO of the blocking means 30B is connected to the clock bus W_CLK, the input terminal I is connected to the input clock terminal CK1 of an I2C device 20, and the input terminal O is connected to the output clock terminal CK2 of an I2C device 20.

[0038] The blocking means 30B receives the clock SCLM transmitted from the I3C device 10 via the clock bus W_CLK using the output terminal IO. The blocking means 30B transmits the received clock SCLM to one I2C device 20 via the input terminal I. The blocking means 30B also receives the clock SCLS transmitted from one I2C device 20 toward the blocking means 30B using the input terminal O. The blocking means 30B blocks the input of the received clock SCLS to the clock bus W_CLK. In other words, the blocking means 30B transmits signals from the clock bus W_CLK toward one I2C device 20, but blocks signals from one I2C device 20 toward the clock bus W_CLK without transmitting them.

[0039] The specific circuit configuration of the blocking means 30B will be described with reference to Figure 4. Figure 4 is a diagram showing an example of the circuit configuration of the blocking means 30B according to the second embodiment. As shown in Figure 4, the blocking means 30B is configured to include, for example, a buffer circuit BUF and a transistor TR.

[0040] The buffer circuit BUF is a buffer circuit that includes, for example, a MOS-FET (metal-oxide-semiconductor field-effect transistor). The buffer circuit BUF augments the signal input to its input terminal while maintaining the logic, and outputs the augmented signal from its output terminal. The input terminal of the buffer circuit BUF is connected to the output terminal IO of the blocking means 30B, and the output terminal is connected to the input terminal I of the blocking means 30B.

[0041] The transistor TR is, for example, an N-type MOS-FET. The gate terminal g of the transistor TR is connected to the input terminal O of the blocking means 30B, the source terminal s is connected to a reference line W_GND which has the potential of ground potential GND, and the drain terminal d is not connected to either and is electrically floating. When the state of the signal input to the gate terminal g is "high", the transistor TR draws charge from the drain terminal d towards the source terminal s, while when the state of the signal input to the gate terminal g is "low", it stops this drawing.

[0042] The blocking means 30B, configured as described above, transmits a signal from the input terminal I via the buffer circuit BUF when a signal is input to the output terminal IO. In contrast, when a signal is input to the input terminal O, the blocking means 30B blocks the output of the signal regardless of the logic state of the signal, because the drain terminal d of the transistor TR is not connected to either terminal. In other words, the blocking means 30B blocks the output of the signal from the output terminal IO regardless of the logic state of the signal input to the input terminal O.

[0043] <Effects and Effects> In the second embodiment described above, the blocking means 30B is an input / output circuit provided between the clock bus W_CLK and the I2C device 20 (secondary device). The blocking means 30B inputs the clock SCLM transmitted from the I3C device 10 (primary device) to the blocking means 30B via the clock bus W_CLK to the I2C device 20. The blocking means 30B also blocks the input to the clock bus W_CLK when the clock SCLS transmitted from the I2C device 20 to the blocking means 30B is in a predetermined logic state. In the second embodiment, the predetermined logic state includes all logic states. That is, the blocking means 30B blocks the input of the clock SCLS transmitted from the I2C device 20 to the blocking means 30B to the clock bus W_CLK. As a result, the electronic device 1B does not need to provide components such as diodes DI on the clock bus W_CLK because the blocking means 30B is an input / output circuit. Therefore, electronic device 1B can communicate with a non-I3C compatible I2C device 20 connected to the bus of I3C device 10 at an even lower cost.

[0044] ---Revised Version--- It should be noted that the present invention is not limited to the embodiments described above. That is, any design modifications made to the above embodiments by those skilled in the art are also included within the scope of the present invention, as long as they retain the features of the present invention. Furthermore, the elements of the above embodiments and the modifications described later can be combined to the extent that it is technically possible, and any combination thereof is also included within the scope of the present invention, as long as it retains the features of the present invention.

[0045] For example, in the first embodiment, the blocking means 30A was provided between the I3C device 10 and the clock bus W_CLK, but is not limited to this. The blocking means 30A may be provided, for example, one each between the clock bus W_CLK and a plurality of I2C devices 20. Specifically, the blocking means 30A may be provided for each I2C device 20 such that the anode terminal of the diode DI is connected to the clock terminal CK of the I2C device 20 and the cathode terminal of the diode DI is connected to the clock bus W_CLK.

[0046] With this configuration, since the electronic device 1A does not have a blocking means 30A between the I3C device 10 and the clock bus W_CLK, the electrical influence that the blocking means 30A has on the I3C device 10 is reduced. Therefore, the electronic device 1A can communicate with a non-I3C compatible I2C device 20 connected to the bus of the I3C device 10 while maintaining the performance of the electrical characteristics on the clock bus W_CLK.

[0047] Furthermore, the electronic device 1A may be configured in a manner that combines a configuration in which a blocking means 30A is provided between the I2C device 20 and the clock bus W_CLK, and a configuration in which a blocking means 30B is provided between the I2C device 20 and the clock bus W_CLK as described in the second embodiment. In this configuration, the anode terminal of diode DI is connected to the clock terminal CK of the I2C device 20, and the cathode terminal of diode DI is connected to the clock bus W_CLK.

[0048] In this configuration, the electronic device 1A is configured with a mix of configurations in which a blocking means 30A is provided and configurations in which a blocking means 30B is provided. Therefore, the electronic device 1A can communicate with I2C devices 20 of various types that have different connection methods to the clock bus W_CLK, even when an I2C device 20 that does not support I3C is connected to the bus of the I3C device 10.

[0049] Furthermore, in the second embodiment, the blocking means 30B is an interface that follows GPIO, but is not limited to this. The blocking means 30B can be any circuit that transmits the clock SCL propagating on the clock bus W_CLK to the I2C device 20 and blocks the clock SCLS transmitted from the I2C device 20 to the clock bus W_CLK.

[0050] With this configuration, the electronic device 1B can use various types of blocking means 30B, and can communicate with I2C devices 20 of various interfaces that are not I3C compatible, even when they are connected to the bus of the I3C device 10. [Explanation of symbols]

[0051] 1...Electronic device, 10...I3C device (primary device), 20...I2C device (secondary device), 30A...Blocking means, 30B...Blocking means

Claims

1. A primary device that operates according to the I3C communication specification, A secondary device that operates according to the I2C communication specification and does not support the I3C communication specification, A clock bus connected to the primary device and the secondary device, A blocking means for blocking the input of the clock to the primary device when the clock connected to the clock bus and transmitted from the secondary device toward the clock bus is in a predetermined logical state, Electronic devices equipped with these features.

2. The blocking means is a diode, the cathode terminal of which is connected to the clock terminal of the primary device, and the anode terminal of which is connected to the clock bus. The electronic device according to claim 1.

3. The aforementioned predetermined logical state includes all logical states, The blocking means is an input / output circuit provided between the clock bus and the secondary device, which inputs the clock transmitted from the primary device to the blocking means via the clock bus to the secondary device, and blocks the input of the clock transmitted from the secondary device to the blocking means to the clock bus. The electronic device according to claim 1.

4. When the secondary device performs a clock stretch operation as defined in the I2C communication specification, it terminates the clock stretch operation before the logical state of the clock transmitted from the primary device to the clock bus becomes high. The electronic device according to claim 2 or 3.

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