transistor

Abstract

To stabilize the electrical characteristics of transistors constructed using oxide semiconductors, and improve reliability. To improve. [Solution] A region with a high crystalline component and a region with a high amorphous component in a single oxide semiconductor film. To create different regions: Regions with a high crystalline content are designated as channel-forming regions, while other regions... The region is configured such that there is a large amount of amorphous components. Preferably, the crystalline components are self-aligned. It forms an oxide semiconductor film in which regions with a high proportion of amorphous components and regions with a high proportion of amorphous components coexist. To create regions with different crystalline properties in a semiconductor film, first, an acid containing a large amount of crystalline components is used. After forming the oxide semiconductor film, a process is performed to make a portion of the oxide semiconductor film amorphous. .

Description

Technical Field

[0001] The present invention relates to a transistor and a method for manufacturing the same. In particular, it relates to a transistor in which a channel is formed in an oxide semiconductor layer and a method for manufacturing the same. The present invention also relates to a semiconductor device having such a transistor

[0002] Among the inventions disclosed in this specification, elements composed of compound semiconductors in addition to silicon semiconductors are included as elements constituting semiconductor integrated circuits. As an example, an application using a wide-gap semiconductor is disclosed

[0003] In this specification, the semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. Electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices

Background Art

[0004] Electronic devices and optical devices are manufactured using transistors made of silicon In recent years, in addition to transistors made of silicon, techniques for manufacturing transistors using oxide semiconductors and applying them to electronic devices and optical devices have attracted attention

[0005] In an active matrix type liquid crystal display device, a transistor is provided for each pixel Such transistors are often composed of amorphous silicon, polycrystalline silicon, etc. Note that transistors composed of amorphous silicon can support the enlargement of the area of liquid crystal display devices although their field-effect mobility is low Also, transistors composed of polycrystalline silicon have high field-effect mobility ​​​​​​​It is difficult to accommodate the increasing area of ​​liquid crystal display devices.

[0006] Oxide semiconductors are attracting attention as a component material for transistors, replacing silicon-based materials. This is because transistors, which are constructed using oxide semiconductors, are amorphous silicon It has a higher field-effect mobility than transistors that use capacitors, and is also suitable for liquid crystal displays. This is because it can accommodate large-area applications. For example, oxide semiconductors such as bisulfite oxide Transistors were fabricated using lead and In-Ga-Zn-O oxides, and the pixels of a display device were... Technologies for application to weaving elements and the like are disclosed in Patent Documents 1 and 2.

[0007] Furthermore, Patent Document 3 describes a laminate of oxide semiconductor films in which amorphous components remain at the substrate interface. A transistor has been disclosed.

[0008] However, in transistors constructed using oxide semiconductors, the threshold voltage Controlling this is difficult. Specifically, in oxide semiconductors, some of the hydrogen becomes a donor. Then, it releases electrons, which are carriers. And when the carrier concentration of the oxide semiconductor increases, Channels are formed in the oxide semiconductor even without applying a voltage between the source and the output. The threshold voltage of the transistor in question shifts in the negative direction.

[0009] Even if the field effect mobility is high, the threshold voltage value is high, or the threshold voltage value is negative. Consequently, the circuit containing that transistor becomes difficult to control. The threshold voltage value is high. In the case of a transistor with a large absolute threshold voltage, the transistor will not function properly when the drive voltage is low. It may not be able to perform its switching function as an inverter and could become a load. If the threshold voltage value is negative, even if the gate voltage is 0V, the source electrode and drain electrode Current flows between them, making them prone to what is known as normally-on states.

[0010] In the case of an n-channel transistor, the channel only becomes active when a positive voltage is applied to the gate electrode. A transistor is desirable in which a gap is formed and drain current flows out. The drive voltage should not be high. And transistors where a channel is not formed, or where a channel is formed even in a negative voltage state. Transistors that allow current to flow are unsuitable for use in circuits.

[0011] Furthermore, it is difficult to completely remove hydrogen contained in oxide semiconductors. Therefore, oxidation Transistors, which are constructed using semiconductor materials, are constructed using silicon-based materials. Compared to a DISTRO, controlling the threshold voltage is more difficult. [Prior art documents] [Patent Documents]

[0012] [Patent Document 1] Japanese Patent Publication No. 2007-123861 [Patent Document 2] Japanese Patent Publication No. 2007-96055 [Patent Document 3] Japanese Patent Publication No. 2011-135066 [Overview of the Initiative] [Problems that the invention aims to solve]

[0013] In view of the above-mentioned problems, one aspect of the present invention relates to a transistor constructed using an oxide semiconductor. One of the objectives is to reduce and stabilize fluctuations in the electrical characteristics of the device. One of the objectives is to improve the reliability of [the system / system]. [Means for solving the problem]

[0014] One aspect of the present invention relates to a transistor using an oxide semiconductor layer with different crystallinity in different regions. The gist of this is that it constitutes the following. Specifically, the proportion of the crystalline region in the channel formation region is A transistor is constructed using an oxide semiconductor layer with a higher proportion of crystalline regions than the rest of the region. To compose.

[0015] For example, one aspect of the present invention comprises a gate layer and a gate insulating layer provided on the gate layer. an oxide semiconductor layer provided on the gate insulating layer, and an oxide semiconductor layer provided in isolation on the oxide semiconductor layer The source electrode layer and drain electrode layer are provided, and the region on the oxide semiconductor layer is, The region between the electrode layer and the drain electrode layer includes an etching stop layer. The oxide semiconductor layer exhibits crystal formation in the first region superimposed on the interface with the etching stop layer. The proportion of the region in the second region that overlaps with the interface with the source electrode layer or the drain electrode layer. This transistor has a higher proportion of crystalline regions than the rest of the region.

[0016] In the transistor with the above configuration, the crystal region in the first region (channel formation region) The proportion of this region is higher than the proportion of the crystalline region in the second region (other regions). In other words, Furthermore, the defect density in the first region is lower than the defect density in the second region. Defects in the oxide semiconductor layer are trap sites for impurities contained in the oxide semiconductor layer. This tends to happen. Therefore, in a transistor according to one aspect of the present invention, from the first region to the second While diffusion of impurities such as hydrogen into the first region is likely to occur, diffusion in the reverse direction (second region) is more likely to occur. Diffusion of impurities such as hydrogen from the first region is unlikely to occur. As a result, in one aspect of the present invention In transistors, the concentration of impurities such as hydrogen in the channel formation region is reduced. This makes it possible to stabilize electrical characteristics and improve reliability.

[0017] Another configuration of the present invention includes an oxide semiconductor layer and a gate insulating film on the oxide semiconductor layer. The device has a gate electrode layer on a gate insulating film, and the oxide semiconductor layer has a first region and a second region It has a third region, the first region overlapping with the gate electrode layer, and the first region overlapping with the second region Located between the third region, the first region has a higher proportion of crystalline components than amorphous components, and the second region In the first and third regions, the proportion of amorphous components is greater than that of crystalline components, and in the second and third regions... The semiconductor device is characterized in that the hydrogen concentration in the first region is higher than that in the second region.

[0018] In the above configuration, in the pattern of one oxide semiconductor layer, there are regions with a high crystalline content and non-crystalline regions. It creates distinct regions with a high crystalline content. The regions with a high crystalline content become channel-forming regions. The remaining regions are configured to have a high proportion of amorphous components. Preferably, self-regulating This forms an oxide semiconductor film in which regions with a high proportion of crystalline components and regions with a high proportion of amorphous components are mixed together. do.

[0019] Furthermore, in the above configuration, the second region or the third region is the source electrode layer or the drain. It is electrically connected to the electrode layer and has higher conductivity than the first region, which is the channel-forming region.

[0020] The oxide semiconductor film in the channel-forming region contains a large amount of crystalline components, and these crystalline components are Preferably, the c-axis is aligned in a direction parallel to the normal vector of the surface on which the oxide semiconductor film is formed. When an oxide semiconductor film contains a large amount of crystalline components, metal atoms in the region that forms the channel formation region... This ordering of the oxygen atom's bonding state can suppress the occurrence of oxygen deficiency.

[0021] In addition to oxygen vacancies, oxide semiconductor films generate electrons, which are carriers, using hydrogen. It is known that this occurs. Therefore, the amount of hydrogen in the oxide semiconductor film in the channel formation region is also low. It is preferable to reduce it.

[0022] A region with a high concentration of amorphous components is formed in at least a portion of the oxide semiconductor film containing crystalline components, It attracts and captures hydrogen in regions with a high concentration of amorphous components (also known as intrinsic gettering). Furthermore, the hydrogen concentration in the channel-forming region is compared to the hydrogen concentration in the region with a high concentration of amorphous components. Reduce all of them. Hydrogen diffuses into regions with a high concentration of amorphous components and is trapped in regions with a high concentration of amorphous components. It becomes stable when obtained.

[0023] The minority carrier density is extremely low, and the oxygen deficiency and carrier production sources such as hydrogen are reduced. A transistor using an oxide semiconductor film that includes a channel-forming region has an extremely low off-current. It can be cut.

[0024] In this specification, "hydrogen" refers to a hydrogen atom, and the phrase "containing hydrogen" is used in a manner similar to the above. In this case, it also includes hydrogen derived from hydrogen molecules, hydrocarbons, hydroxyl groups, and water.

[0025] Furthermore, adding hydrogen to an oxide semiconductor film increases its conductivity, indicating that the amorphous components... Regions with a high concentration of crystalline components contain more hydrogen than regions with a high concentration of amorphous components, thus providing a guide to regions with a high concentration of amorphous components. The electrical charge is higher in regions with a higher crystalline content than in regions with a higher crystalline content.

[0026] In a single oxide semiconductor film, regions with a high concentration of crystalline components and regions with a high concentration of amorphous components are created. To achieve this, first, an oxide semiconductor film containing a large amount of crystalline components is formed, and then one of the oxide semiconductor films is formed. A process is carried out to make the part amorphous.

[0027] Oxide semiconductor films containing a large amount of crystalline components require specific deposition conditions, such as keeping the temperature of the substrate to be deposited above 200°C. This can be obtained by doing the above. Also, even if the temperature of the substrate to be coated is below 200°C, acid If an oxide semiconductor film is subjected to heat treatment at 200°C or higher after deposition, an oxide containing a large amount of crystalline components will be formed. A semiconductor film can be obtained. Note that immediately after deposition, oxide semiconductor films exhibit stoichiometric compounds. It is preferable to have a supersaturated state with more oxygen than the target, therefore the oxygen content of the sputtering gas It is preferable to deposit the film under conditions with a high proportion, and the film is deposited in an oxygen atmosphere (100% oxygen gas). It is preferable to do so.

[0028] Furthermore, the formation of oxide semiconductor films with a high crystalline content is difficult because impurities such as copper, aluminum, and chlorine are present. It is preferable to appropriately select a process that does not pose a risk of contamination or adhesion to the oxide semiconductor film surface. If these impurities adhere to the surface of an oxide semiconductor film, exposure to oxalic acid or dilute hydrofluoric acid can cause damage. Alternatively, by performing plasma treatment (such as N2O plasma treatment), the oxide semiconductor film It is preferable to remove impurities from the surface.

[0029] Furthermore, the method for manufacturing a semiconductor device is also part of the present invention, and its structure is such that the oxide semiconductor layer has In contrast, an oxide semiconductor layer containing crystalline components having a roughly perpendicular c-axis is formed, and the oxide semiconductor layer A gate insulating film is formed on top, a gate electrode layer is formed on the gate insulating film, and the gate electrode layer is made As a sket, a portion of the oxide semiconductor layer is made amorphous, and the source electrode layer is in contact with the amorphous region. Alternatively, it is a method for fabricating a semiconductor device in which a drain electrode layer is formed.

[0030] As one process for making a portion of an oxide semiconductor film amorphous, an ion implantation device and This involves adding elements using an ion plasma device, specifically noble gases such as argon, oxygen, and dol. An ion implanter may be added. If an ion implanter or ion plasma device is used, Even if an oxide semiconductor film is covered with an insulating layer, argon can penetrate the oxide semiconductor film through the insulating layer. Oxygen and dopants can be added, and a portion of the oxide semiconductor film can be made amorphous.

[0031] Furthermore, as one of the processes for making a portion of an oxide semiconductor film amorphous, argon plastic The material may be exposed to Zuma or oxygen plasma, and the configuration of the other invention is such that the upper surface of the oxide semiconductor layer is An oxide semiconductor layer containing crystalline components having a roughly perpendicular c-axis is formed on the oxide semiconductor layer. A gate insulating film is formed, a gate electrode layer is formed on the gate insulating film, and the gate of the oxide semiconductor layer The region overlapping with the insulating film is partially exposed, and the region where the oxide semiconductor layer is exposed is made amorphous. Manufacturing of a semiconductor device that forms a source electrode layer or drain electrode layer in contact with an amorphous region. This is the manufacturing method.

[0032] When a portion of an oxide semiconductor film is made amorphous by exposure to argon plasma or oxygen plasma. In this case, only the vicinity of the surface of the exposed oxide semiconductor film becomes amorphous, and below that... The crystalline components remain. When the thickness of the oxide semiconductor film is thin, the exposed area is amorphous. This region has a high concentration of amorphous components, but the amorphous region is thin, and the oxide semiconductor film thickness is thick. In this case, only the surface layer becomes amorphous, while other regions have a high concentration of crystalline components. However, Regions exposed to plasma are different from regions not exposed to plasma (e.g., channel formation regions). This region has a higher proportion of amorphous components and a lower proportion of crystalline components than the source region. Alternatively, it can be used as a drain area.

[0033] Furthermore, if heat treatment is performed after a process to make a portion of the oxide semiconductor film amorphous, re-forming Crystallization improves the crystallinity, but the recrystallized region is less crystallin than the channel-forming region. The coefficient of change is low. This feature is also one of the present inventions, and its structure consists of an oxide semiconductor layer and an oxide semiconductor layer. The oxide semiconductor layer has a gate insulating film on one layer and a gate electrode layer on the gate insulating film, and the oxide semiconductor layer is It has a region 1, a second region and a third region, the first region overlapping with the gate electrode layer, and the first The first region is located between the second and third regions, and the first region is between the second and third regions. This semiconductor device is characterized by having higher crystallinity than the region.

[0034] In the above configuration, the second region or the third region is the source electrode layer or the drain electrode layer A second region or third region that is electrically connected to and in contact with the source electrode layer or drain electrode layer. The vicinity of the interface in the first region is amorphous, and the hydrogen concentration near that interface is the same as the hydrogen concentration in the first region. One of its distinguishing features is that it is higher than [the other feature].

[0035] Furthermore, as one of the processes for making part of an oxide semiconductor film amorphous, high power Sputtering may be performed using - a method that is in contact with a portion of the oxide semiconductor film. When forming a conductive film for wiring, sputtering is performed on a part of the oxide semiconductor film. This is made amorphous. In this case, depending on the deposition conditions of the conductive film, a portion of the oxide semiconductor film is made amorphous. This allows for the amorphous nature of a portion of the oxide semiconductor film without increasing the number of process steps. It is possible.

[0036] Furthermore, by performing a process to make a portion of the oxide semiconductor film amorphous, crystallization Compared to regions with a high concentration of oxygen, regions with a high concentration of amorphous components have a greater oxygen deficiency. An oxygen-rich insulating layer is provided above or below the oxide semiconductor film, and oxygen is removed by heat treatment or other means. This is reduced by diffusing it into an oxide semiconductor film.

[0037] Furthermore, the density of the oxide semiconductor film in the region with a high crystalline content is 6.0 g / cm³. 3 twist Highest at 6.375 g / cm³ 3 It is less than. When the membrane density is low, the amount of oxygen and hydrogen that diffuses is large. Yes.

[0038] Note: 6.375 g / cm³ 3 The density values ​​are In2O3:Ga2O3:ZnO=1:1: In-G has a composition of 2 [molar ratio] (In:Ga:Zn = 1:1:1 [atomic ratio]). This is the theoretical density value of the α-Zn-O compound. Furthermore, the composition of the oxide semiconductor film is determined by the X-ray photoelectron content. Optical method (XPS:X-ray Photoelectron Spectroscopy) It can be measured using this method.

[0039] The film density of oxide semiconductor films is determined by Rutherford backscattering (RBS). (rd Backscattering Spectrometry) and X-ray reflectivity measurement It can be measured by the X-Ray Reflection (XRR) method.

[0040] Furthermore, materials used for oxide semiconductor films include indium oxide, tin oxide, zinc oxide, and dioxide. In-Zn oxides, Sn-Zn oxides, and Al-Zn oxides are oxides of the original metals. Zn-Mg oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides In-Ga-Zn oxides (also written as IGZO), which are oxides of ternary metals, n-Al-Zn oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al -Ga-Zn oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In- La-Zn oxides, In-Ce-Zn oxides, In-Pr-Zn oxides, In-N d-Zn oxides, In-Sm-Zn oxides, In-Eu-Zn oxides, In-Gd -Zn oxides, In-Tb-Zn oxides, In-Dy-Zn oxides, In-Ho- Zn oxides, In-Er-Zn oxides, In-Tm-Zn oxides, In-Yb-Z n-based oxides, In-Lu-Zn ​​oxides, and quaternary metal oxides such as In-Sn-Ga- Zn oxides, In-Hf-Ga-Zn oxides, In-Al-Ga-Zn oxides, I n-Sn-Al-Zn oxides, In-Sn-Hf-Zn oxides, In-Hf-Al- Zn-based oxides and the like can be used.

[0041] For example, an In-Ga-Zn oxide is a material having In, Ga, and Zn. This refers to oxides, and the ratio of In, Ga, and Zn is not specified. Other metal elements besides n may be included.

[0042] For example, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3) or In: In-Ga-Zn acids with an atomic ratio of Ga:Zn = 2:2:1 (= 2 / 5:2 / 5:1 / 5) Oxides or oxides with a similar composition can be used. Alternatively, In:Sn:Zn=1: 1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or In:Sn:Zn=2:1:5 (=1 / 4:1 / 8:5 / 8) It is preferable to use an In-Sn-Zn oxide with a specific ratio or an oxide with a similar composition. However, It is not limited to this.

[0043] Furthermore, as a transistor structure in which the region with a high crystalline content is the channel formation region, in particular, It is not limited to, for example, top-gate transistors, bottom-gate transistors It can be applied as appropriate. Furthermore, a back gate electrode may be provided. Applying voltage to ensure that the transistor is normally off. It is possible.

[0044] One embodiment of the present invention has a transistor or a circuit comprising a transistor. This relates to semiconductor devices. For example, a channel formation region is formed in an oxide semiconductor film. This relates to a semiconductor device having a circuit that includes a dysta or transistor. For example, LSIs, CPUs, power devices mounted on power supply circuits, memory, thyristors, etc. Semiconductor integrated circuits including converters and image sensors, and liquid crystal display panels are representative examples. This relates to electronic devices that incorporate electro-optical devices or light-emitting display devices having light-emitting elements as components. [Effects of the Invention]

[0045] Hydrogen is attracted and immobilized from the channel formation region of the oxide semiconductor film to the region with a high concentration of amorphous components. By removing as much hydrogen as possible from the channel-forming region, a highly purified type I (intrinsic) A conductor) or something close to it. By making it type I, the threshold of the transistor The voltage value can be set to a positive value, enabling the realization of a so-called normally-off switching element. ru.

[0046] If normally-off switching elements can be realized, they can be used to create low-power semiconductor devices. We can provide a place for you. [Brief explanation of the drawing]

[0047] [Figure 1] (A) Top view and (B) Cross-sectional view showing examples of transistor structures. [Figure 2] (A) to (C) Cross-sectional diagrams showing examples of the transistor manufacturing process. [Figure 3] (A) to (C) Cross-sectional diagrams showing examples of the transistor manufacturing process. [Figure 4] (A) to (C) Figures showing examples of display devices. [Figure 5] (A), (B) Figures showing examples of display devices. [Figure 6] (A), (B) Figures showing examples of display devices. [Figure 7] (A) and (B) are diagrams showing examples of image sensors. [Figure 8] (A), (B) Diagrams showing examples of memory devices. [Figure 9] A model diagram used to calculate the movement of excess oxygen. [Figure 10] Calculation results for the model diagram in Figure 9. [Figure 11] A model diagram used to calculate the movement of oxygen deficiency. [Figure 12] Calculation results for the model diagram in Figure 11. [Figure 13] This is a cross-sectional view and a top view illustrating one aspect of the present invention. [Figure 14] This is a cross-sectional view showing one aspect of the present invention. [Figure 15] This is a cross-sectional view showing one aspect of the present invention. [Figure 16]This is a cross-sectional view showing one aspect of the present invention. [Figure 17] This is a cross-sectional view showing one aspect of the present invention. [Figure 18] A cross-sectional view, a top view, and a circuit diagram showing one embodiment of a semiconductor device. [Figure 19] A perspective view showing one embodiment of a semiconductor device. [Figure 20] A cross-sectional view showing one aspect of a semiconductor device. [Figure 21] A block diagram and a partial circuit diagram illustrating one form of a semiconductor device. [Figure 22] A diagram illustrating electronic devices. [Figure 23] A diagram illustrating electronic devices. [Figure 24] A diagram illustrating electronic devices. [Modes for carrying out the invention]

[0048] The present invention is not limited to the following description, and its form and details can be modified in various ways. It will be easily understood by anyone. Furthermore, the present invention is not limited to the contents of the embodiments described below. It should not be interpreted in that way.

[0049] (Embodiment 1) One aspect of the present invention will be described in detail below.

[0050] <1. Transistor> For an example of the structure and manufacturing process of a transistor according to one aspect of the present invention, please refer to Figures 1 to 3. I will explain it.

[0051] <1-1. Examples of transistor structures> Figure 1 shows an example of the structure of a transistor according to one aspect of the present invention. Specifically, Figure Figure 1(A) is a top view of the transistor, and Figure 1(B) is the AB shown in Figure 1(A). This is a cross-sectional view of the transistor along the line.

[0052] The transistors shown in Figures 1(A) and 1(B) have a gate layer 1 provided on the substrate 100. And, a gate insulating layer 2 provided on the gate layer 1, and a gate insulating layer 2 provided on the gate insulating layer 2 The oxide semiconductor layer 3 and the source electrode layer 4 provided isolated on the oxide semiconductor layer 3 The drain electrode layer 5 and the region on the oxide semiconductor layer 3, the source electrode layer 4 and the drain It has an etching stop layer 6 provided in the region between the electrode layers 5. The transistors shown in Figures 1(A) and (B) have an etching stop layer 6 provided. It is an inverse staggered type (etched stop type, channel stop type) transistor.

[0053] In the transistors shown in Figures 1(A) and (B), the etching stop layer 6 is made of oxide. The region on the semiconductor layer 3, not only the region between the source electrode layer 4 and the drain electrode layer 5. It is also provided at the edges of the oxide semiconductor layer 3 and between the source electrode layer 4 and the drain electrode layer 5. In other words, the source electrode layer 4 and the drain electrode layer 5 are provided in the etching stop layer 6. The oxide semiconductor layer 3 is in contact with the opening that is being formed.

[0054] Furthermore, in the oxide semiconductor layer 3 of the transistor shown in Figures 1(A) and (B), E... The region 7 that overlaps with the interface with the ching stop layer 6, and the source electrode layer 4 or drain electrode layer 5 The crystallinity differs between the interface and the superimposed region 8. Specifically, the crystallinity of the region in region 7 The proportion is higher than the proportion of crystalline regions in region 8. Furthermore, region 7 consists of gate layer 1 and saw A region that includes all or most of the region in which a channel is formed depending on the voltage between electrode layers 4. ru.

[0055] In other words, in the transistors shown in Figures 1(A) and (B), all or large of the channels The defect density in region 7, where the part is formed, is lower than the defect density in region 8. Therefore, the defects in the oxide semiconductor layer 3 are impurities such as hydrogen contained in the oxide semiconductor layer 3. It is prone to becoming a trap site. Therefore, the transistor shown in Figures 1(A) and (B) In this case, diffusion of impurities such as hydrogen from region 8 to region 7 is likely to occur, whereas from region 7 Therefore, diffusion of the impurity into region 8 is unlikely. As a result, the traces shown in Figures 1(A) and (B) are not formed. In the inverter, the concentration of impurities such as hydrogen in region 7 is reduced, improving the electrical characteristics. It is possible to improve stability and reliability.

[0056] Furthermore, in the transistors shown in Figures 1(A) and (B), the switching characteristics were improved. It is possible to measure this. The details are described below.

[0057] Transistors in which a channel is formed in an oxide semiconductor depend on the processing conditions or heat treatment conditions. The electrical properties may change. This change is due to impurities during the formation process of the oxide semiconductor. Substances (such as chlorine, fluorine, boron, or hydrogen) may be mixed in, or oxygen may be released from the oxide semiconductor. This is caused by desorption, etc. And such contamination or desorption occurs at the edges of oxide semiconductors. This is more likely to become apparent in transistors where channels are formed in oxide semiconductors. In this case, the edges of the oxide semiconductor become a low-resistance region, and a transient occurs in this low-resistance region. Parasitic channels are easily formed in the transistor. An oxide semiconductor in the region, wherein the voltage between the source and drain depends on the voltage between the gate and source. The channel formed along the shortest path (also called the former channel) and the parasitic channel (the latter) Two types of channels (also called the channel) can be formed.

[0058] In transistors where two types of channels can be formed, in most cases, each channel The threshold voltage between the gate and source where the channel is formed is different. Typically, the former channel The threshold voltage at which the channel is formed is higher than the threshold voltage at which the latter channel is formed. Furthermore, the current-driven capability of the former channel is higher than that of the latter channel. Therefore, the voltage between the gate and source of the transistor, which was in the off state, was increased. In this case, the current between the source and drain will change in two stages. Specifically, the latter The first stage of change occurs near the threshold voltage at which the channel is formed (between source and drain). An increase in current was observed, and furthermore, near the threshold voltage in which the former channel is formed Then, a second stage of change (an increase in the current between the source and drain) will be observed.

[0059] In the transistors shown in Figures 1(A) and 1(B), the etching stop layer 6 It is provided between the edge of the oxide semiconductor layer 3 and the source electrode layer 4 and the drain electrode layer 5. Therefore, even if the edge region of the oxide semiconductor layer 3 becomes a low-resistance region, Figure In the transistors shown in 1(A) and (B), no parasitic channels are formed. In other words, in the transistors shown in Figures 1(A) and (B), the switching characteristics are improved. It is possible to measure this.

[0060] Furthermore, structures that can improve switching characteristics are shown in Figures 1(A) and (B). It is not limited to the structure. Parasitic channels are formed at the edges of oxide semiconductors in the first place. This is because there are source and drain pins of a transistor that are electrically connected to that end. Therefore, at least one of the source electrode layer 4 and the drain electrode layer 5 is at the edge of the oxide semiconductor layer 3. If not electrically connected, it is possible to improve the switching characteristics of the transistor. It is possible. For example, if at least one of the source electrode layer 4 and the drain electrode layer 5 is an oxide semiconductor For transistors with a structure that does not contact the side surface of the conductor layer 3, the switching characteristics can be improved. It is possible.

[0061] <1-1-1. Specific Examples of Substrate 100> The substrate 100 has sufficient heat resistance to withstand the heat treatment during the transistor manufacturing process. Any substrate that possesses the necessary properties can be used. For example, a glass substrate, Laminate substrates, quartz substrates, sapphire substrates, and other substrates can be used. A flexible substrate may be used as 100. Note that impurities contained in the substrate 100 may later form To prevent contamination of the oxide semiconductor layer, an insulating layer is formed on the substrate 100. It is also possible.

[0062] <1-1-2. Specific Example of Gate Layer 1> Gate layer 1 consists of aluminum, copper, titanium, tantalum, tungsten, and molybdenum. , elements selected from chromium, neodymium, and scandium, or alloys containing these elements. A film consisting of these materials can be applied. Furthermore, lamination of these films can also be applied.

[0063] Furthermore, as the gate layer 1, a nitrogen-containing metal oxide, specifically, nitrogen-containing In-Ga -Zn-O film, nitrogen-containing In-Sn-O film, nitrogen-containing In-Ga-O film, nitrogen-containing In-Zn-O film, nitrogen-containing Sn-O film, nitrogen-containing In-O film, or metal nitride film (I (e.g., nN, SnN) can also be applied. These films can be rated at 5 eV (electron volts) or higher. Preferably, it has a work function of 5.5 eV (electron volts) or more, and when used as a gate, The threshold voltage of the transistor can be set to positive, creating a so-called normally-off switch. This makes it possible to realize a ping element.

[0064] <1-1-3. Specific Examples of Gate Insulation Layer 2> As gate insulating layer 2, silicon oxide film, silicon nitride film, silicon oxide nitride film, nitride Silicon oxide film, aluminum oxide film, aluminum oxide nitride film, or gallium oxide film These can be applied. Furthermore, lamination of these materials can also be applied. Silicon oxide nitride and aluminum oxide nitride have a composition that contains more oxygen than nitrogen. It refers to something that is present in large quantities. Also, silicon nitride oxide, in terms of its composition, has more nitrogen than oxygen. This refers to substances with a high content.

[0065] In particular, it is preferable to apply a layer containing an aluminum oxide film as the gate insulating layer 2. The aluminum oxide film is impermeable to both hydrogen and other impurities, as well as oxygen. It has a high blocking effect. Therefore, an aluminum oxide film is used as the gate insulating layer 2. By applying the included layer, the detachment of oxygen from the oxide semiconductor layer 3 is prevented, and oxidation This prevents the contamination of the semiconductor layer 3 with impurities such as hydrogen.

[0066] Furthermore, the gate insulating layer 2 includes a hafnium oxide film, a yttrium oxide film, and hafnium sulfite. Ricate (HfSi x O y (x>0, y>0) membrane, nitrogen-doped hafnium silicate Hafnium aluminate (HfAl x O y (x>0, y>0) film, or oxide film It is also possible to apply films that include nitrate films (films made of so-called high-k materials). By using such a film, it is possible to reduce gate leakage current.

[0067] <1-1-4. Specific Examples of Oxide Semiconductor Layer 3> <(1) About the materials> A film containing at least indium can be applied as the oxide semiconductor layer 3. It is preferable to apply a film containing indium and zinc to the transistor. A film containing gallium in addition to those, as a stabilizer to reduce variations in sex. It is preferable to apply this.

[0068] Furthermore, the oxide semiconductor layer 3 can be made of tin, hafnium, aluminum, or zirconium. Lanthanium, or lanthanoids, lanthanum, cerium, praseodymium, neodymium, sumali Um, Europium, Gadolinium, Terbium, Dysprosium, Holmium, Elbium One or more species of *Thurium*, *Ytterbium*, or *Lutetium* A film containing a vilifier can also be applied.

[0069] For example, as the oxide semiconductor layer 3, an indium oxide film, an oxide of a binary metal, is used. -Zn oxide films, In-Mg oxide films, In-Ga oxide films, ternary metal oxides These are In-Ga-Zn oxide films, In-Al-Zn oxide films, and In-Sn-Zn oxide films. Oxide film, In-Hf-Zn oxide film, In-La-Zn oxide film, In-Ce-Z n-based oxide film, In-Pr-Zn based oxide film, In-Nd-Zn based oxide film, In-Sm -Zn-based oxide film, In-Eu-Zn-based oxide film, In-Gd-Zn-based oxide film, In- Tb-Zn oxide film, In-Dy-Zn oxide film, In-Ho-Zn oxide film, I n-Er-Zn oxide film, In-Tm-Zn oxide film, In-Yb-Zn oxide film In-Lu-Zn ​​oxide films, In-Sn-Ga-Zn oxides which are oxides of quaternary metals In oxide films, In-Hf-Ga-Zn oxide films, In-Al-Ga-Zn oxide films, In -Sn-Al-Zn oxide film, In-Sn-Hf-Zn oxide film, In-Hf-Al -Zn-based oxide films can be applied.

[0070] Here, for example, an In-Ga-Zn oxide is a material whose main components are In, Ga, and Zn. It means an oxide, and the ratio of In, Ga, and Zn is not specified. Also, In and Ga and It may contain metal elements other than Zn.

[0071] Furthermore, some of the oxygen constituting the oxide semiconductor layer 3 may be replaced with nitrogen.

[0072] <(2) Regarding the crystal structure> As described above, the oxide semiconductor layer 3 is a film in which the proportion of crystalline regions differs depending on the region, for example For example, an oxide semiconductor film in which amorphous and crystalline regions coexist. In the crystalline region, The crystal structure of oxide semiconductors is not limited to a specific structure.

[0073] Oxide semiconductor films have crystalline regions such as CAAC (C Axis Aligned Crystal It has crystalline, polycrystalline, and microcrystalline forms. Microcrystalline forms have a higher defect level density than CAAC. Furthermore, an oxide semiconductor containing CAAC is called CAAC-OS (C Axis Aligne It is called (d) Crystalline Oxide Semiconductor.

[0074] The crystalline region of the oxide semiconductor film may have, for example, CAAC-OS. CAAC-OS is For example, the c-axis is oriented, and the a-axis and / or the b-axis are not aligned macroscopically.

[0075] The oxide semiconductor film may have, for example, microcrystals in its crystalline region. A material semiconductor is called a microcrystalline oxide semiconductor. An oxide semiconductor film having a microcrystalline oxide semiconductor is In the crystalline region, for example, microcrystals (also called nanocrystals) with a size of 1 nm to less than 10 nm. The film contains a microcrystalline oxide semiconductor. Alternatively, an oxide semiconductor film having a microcrystalline oxide semiconductor has a crystalline region, for example For example, an oxide semiconductor having a crystalline-amorphous multiphase structure with crystalline portions of 1 nm to less than 10 nm. They are doing it.

[0076] The oxide semiconductor film has at least an amorphous region in the amorphous region. For example, the amorphous region has a micro It may have crystals. Furthermore, an oxide semiconductor having an amorphous portion is referred to as an amorphous oxide semiconductor. This is called [amorphous]. The amorphous region has a higher defect level density than the microcrystalline and CAAC regions. Amorphous oxide semiconductor An oxide semiconductor film having such an amorphous region has, for example, a disordered atomic arrangement and crystalline components It does not have. Or, an oxide semiconductor film having an amorphous oxide semiconductor has an amorphous region, for example It is completely amorphous and does not contain any crystalline parts.

[0077] Furthermore, the oxide semiconductor film is CAAC-OS, microcrystalline oxide semiconductor, amorphous oxide semiconductor. A mixed film may also be used. The mixed film may consist of, for example, regions of amorphous oxide semiconductor and microcrystalline oxide. It comprises the areas of semiconductors and CAAC-OS.

[0078] Furthermore, the oxide semiconductor film may have, for example, a single crystal in its crystalline region.

[0079] The oxide semiconductor film has multiple crystalline regions, and the c-axis of the crystalline region is aligned with the normal vector of the surface on which it is formed. Alternatively, it is preferable that they are aligned in a direction parallel to the surface normal vector. The orientations of the a-axis and b-axis may be different in between. Such an oxide semiconductor film One example is the CAAC-OS film. Applying the CAAC-OS film in the crystalline region... This is possible. The CAAC-OS membrane will be described in detail below.

[0080] CAAC-OS films are not perfectly amorphous. CAAC-OS films have, for example, crystalline regions and It has an oxide semiconductor with a crystalline-amorphous multiphase structure having amorphous parts. The part is often small enough to fit within a cube with sides less than 100 nm. Also, transmission type Electron microscope (TEM: Transmission Electron Microscope) In the observation image using pe, the boundary between the amorphous and crystalline parts contained in the CAAC-OS film, and the crystal The boundary between the crystalline and non-crystalline parts is not clear. Furthermore, TEM reveals a clear boundary between the CAAC-OS film and the crystalline part. Grain boundaries (also called grain boundaries) cannot be observed. Therefore, the CAAC-OS film... This suppresses the decrease in electron mobility caused by grain boundaries.

[0081] The crystalline portion contained in the CAAC-OS film is, for example, located along the c-axis of the surface on which the CAAC-OS film is formed. Aligned so as to be parallel to the line vector or the surface normal vector, and perpendicular to the ab-plane. When viewed from a certain direction, the metal atoms are arranged in a triangular or hexagonal shape, and when viewed from a direction perpendicular to the c-axis... Metal atoms are arranged in layers, or metal atoms and oxygen atoms are arranged in layers. The orientations of the a-axis and b-axis may differ between them. In this specification, simply vertical When referring to a straight line, the range of 80° to 100°, preferably 85° to 95°, is also included. It shall be included. Also, when simply stating "parallel," -10° or more and 10° or less is preferred. This includes the range of -5° to 5°.

[0082] Furthermore, the distribution of crystalline regions in the CAAC-OS film does not need to be uniform. For example, CAA In the formation process of a C-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, the shape The proportion of crystalline material may be higher near the surface compared to the vicinity of the surface formation.

[0083] The c-axis of the crystalline portion contained in the CAAC-OS film is the normal vector to the surface on which the CAAC-OS film is formed. The shape of the CAAC-OS film is aligned so as to be parallel to the normal vector of the film or surface. Depending on the shape (cross-sectional shape of the surface to be formed or the surface itself), they may face in different directions. Furthermore, the crystalline portion undergoes crystallization treatment such as heat treatment when the film is formed or after film formation. It is formed when the CAAC-OS film is formed. Therefore, the c-axis of the crystalline portion is the same as when the CAAC-OS film is formed. They are aligned so as to be parallel to the normal vector of the surface being formed or the normal vector of the surface itself.

[0084] Transistors using CAAC-OS films exhibit changes in electrical properties due to irradiation with visible or ultraviolet light. Its value is small. Therefore, this transistor is highly reliable.

[0085] Furthermore, oxygen desorption in CAAC-OS membranes tends to occur from the side (end) of the membrane. (For more information on this point, see <Supplement: Desorption of Oxygen from Oxide Semiconductor Layer> below) (Details will be provided below). Therefore, when applying a CAAC-OS film as the oxide semiconductor layer 3... As shown in Figures 1(A) and (B), the etching stop layer 6 is at the edge of the oxide semiconductor layer 3. A transistor is preferred in which the part is located between the source electrode layer 4 and the drain electrode layer 5. This is because it is possible to prevent the formation of parasitic channels in the transistor in question. be.

[0086] <(3) Regarding the layered structure> The oxide semiconductor layer 3 can consist of not only a single-layer oxide semiconductor film but also multiple types of oxide semiconductors. Lamination of conductive films can be applied. For example, amorphous oxide semiconductor films, polycrystalline oxide semiconductor films. A layer comprising at least two types of films, a conductive film and a CAAC-OS film, is applied as the oxide semiconductor layer 3. It is possible.

[0087] Furthermore, a layer consisting of stacked oxide semiconductor films with different compositions is applied as the oxide semiconductor layer 3. It is also possible to do so. Specifically, the first oxide semiconductor film in contact with the gate insulating layer 2 (hereinafter referred to as below) The source electrode layer 4, the drain electrode layer 5, and the etching stop layer 6 are in contact with each other. Furthermore, a second oxide semiconductor film (hereinafter referred to as the upper layer) has a different composition from the first oxide semiconductor film. A layer containing (u) can also be applied as an oxide semiconductor layer 3.

[0088] For example, when both the lower and upper layers are composed of indium, gallium, and zinc. In this method, the indium concentration in the lower layer is made higher than the indium concentration in the upper layer, and the upper Making the gallium concentration in one layer higher than the gallium concentration in the lower layer, or / and The indium concentration in the lower layer is made higher than the gallium concentration in the lower layer, and in the upper layer It is preferable to make the gallium concentration higher than the indium concentration in the upper layer.

[0089] This improves the mobility of transistors having oxide semiconductor layer 3 and parasitic channels. This makes it possible to suppress the formation of [unclear]. Specifically, by increasing the indium concentration in the lower layer... This makes it possible to improve the mobility of the transistor. In conductors, the s orbitals of heavy metals primarily contribute to carrier conduction, and increasing the In content... This is due to an increase in s orbital overlap. Also, the gallium concentration in the upper layer By increasing this level, oxygen desorption is suppressed, and the formation of parasitic channels in the upper layer is inhibited. This is possible because Ga has a larger energy for forming oxygen vacancies compared to In. This is due to the fact that oxygen deficiency is less likely to occur.

[0090] <1-1-4. Specific Examples of Source Electrode Layer 4 and Drain Electrode Layer 5> The source electrode layer 4 and the drain electrode layer 5 are made of aluminum, copper, titanium, tantalum, Elements selected from tungsten, molybdenum, chromium, neodymium, and scandium, It is possible to apply an alloy containing these elements, or a film made of a nitride containing these elements. It is possible to apply lamination of these films.

[0091] Furthermore, a transparent conductive film is applied as the source electrode layer 4 and the drain electrode layer 5. It is also possible to do this. For example, indium tin oxide (In2O3-SnO2) film, in A zinc oxide (In2O3-ZnO) film, or a film containing silicon oxide, is suitable. It can be used.

[0092] <1-1-5. Specific Examples of Etching Stop Layer 6> Etching stop layer 6 includes silicon oxide film, silicon nitride film, and silicon oxynitride. Film, silicon nitride film, aluminum oxide film, aluminum oxide nitride film, or gallium oxide A luminum film or similar material can be applied. Furthermore, lamination of these materials can also be applied. .

[0093] In particular, applying a layer containing an aluminum oxide film as the etching stop layer 6 is a good practice. Preferred. By applying a layer containing an aluminum oxide film as the etching stop layer 6. This prevents the detachment of oxygen from the oxide semiconductor layer 3, and also prevents hydrogen from entering the oxide semiconductor layer 3. This is because it prevents the inclusion of any impurities.

[0094] <1-2. Example of the transistor manufacturing process> Figures 2 and 3 show examples of the manufacturing process for the transistor shown in Figure 1. Specifically, Figure 2 Figures (A) to (C), and Figure 3(A) to (C) are cross-sectional views showing the manufacturing process of the transistor. ru.

[0095] <(1) Formation of gate layer 1 (Figure 2(A))> First, a conductive film is formed on the substrate 100. Next, photolithography is performed on the conductive film. A mask is formed using the method. Then, the conductive film in the area not covered by the mask is removed. It is removed by ching. As a result, gate layer 1 is formed.

[0096] The conductive film can be formed using methods such as sputtering. Heat treatment may be performed before or after film formation or after the formation of the gate layer 1. For example, high GRTA (Gas Rapid Thermal Angle) is a method of performing heat treatment using hot gas. A heat treatment may be performed at 650°C for 1 to 5 minutes using an eal (applicable) device. For high-temperature gases used in this process, noble gases such as argon or inert gases such as nitrogen are used. Alternatively, heat treatment may be performed in an electric furnace at 500°C for 30 minutes to 1 hour.

[0097] <(2) Formation of gate insulating layer 2 (Figure 2(B))> Next, a gate insulating layer 2 is formed on the substrate 100 and the gate layer 1.

[0098] The gate insulating layer 2 can be deposited using methods such as plasma CVD or sputtering. Yes, it is possible. In addition, after the formation of the gate insulating layer 2, a thermal treatment is performed to reduce the water or hydrogen content. The following procedure may be performed: For example, under reduced pressure or in an inert atmosphere at a temperature of 300°C to 700°C. The following heat treatment should be performed for less than one hour. This will result in the formation of the oxide semiconductor layer 3. This can suppress the contamination of the system with hydrogen.

[0099] Furthermore, if the gate insulating layer 2 contains an aluminum oxide film, sputtering or the like can be used. The aluminum film is formed by directly depositing it, or by performing an oxidation treatment after depositing the aluminum film. An aluminum oxide film can be formed. The oxidation treatment involves using oxygen plasma. Examples include treatment or oxygen doping.

[0100] Furthermore, aluminum oxide films have high blocking properties. Therefore, aluminum oxide films When a gate insulating layer 2 containing the above is formed, heat is used to reduce the water or hydrogen content. It is preferable to perform the treatment before the formation of the aluminum oxide film. Specifically, gate insulation After the deposition of insulating films other than the aluminum oxide film constituting layer 2, the aluminum oxide film Before film formation, or after aluminum film formation, oxidation treatment of the aluminum film It is preferable to perform the heat treatment before the processing is carried out. This results in the formation of gate insulation This effectively reduces the water or hydrogen content in layer 2.

[0101] <(3) Formation of oxide semiconductor layer 3 (Figure 2(C))> Next, an oxide semiconductor film is formed on the gate insulating layer 2. A mask is formed on top using photolithography. Then, the area covered by the mask is The oxide semiconductor film in the unetched areas is removed by etching. Body layer 3 is formed.

[0102] The oxide semiconductor film can be deposited using methods such as sputtering. Conditions under which the oxide semiconductor film contains a large amount of oxygen (for example, under an atmosphere of 100% oxygen) It is preferable to carry out the process by sputtering (for example). This allows the acid To increase the amount of oxygen contained in the oxide semiconductor film (preferably when the oxide semiconductor is in a crystalline state) (A region with an excess of oxygen content relative to the stoichiometric composition can be included.) To improve the crystallinity of the semiconductor film, the film deposition may be carried out while the substrate 100 is heated. .

[0103] Furthermore, after the formation of the oxide semiconductor film or the oxide semiconductor layer 3, water or hydrogen content Heat treatment may be performed to reduce the amount of heat. For example, under reduced pressure or in an inert atmosphere. Then, heat treatment at 300°C to 700°C for 1 hour or less is sufficient. Also, gate insulation If layer 2 is an insulating layer containing oxygen, this heat treatment will reduce the oxygen contained in the gate insulating layer 2. This can be supplied to the oxide semiconductor film or oxide semiconductor layer 3. Therefore, in the heat treatment Therefore, even if oxygen vacancies occur in the oxide semiconductor film or oxide semiconductor layer 3, The oxygen deficiency can be compensated for by supplying oxygen from the insulating layer 2.

[0104] <(4) Formation of etching stop layer 6 (Figure 3(A))> Next, an insulating film is formed on the gate insulating layer 2 and the oxide semiconductor layer 3. A mask is formed on the border film using photolithography. Then, using this mask... The insulating film in the uncovered areas is removed by etching. As a result, the etching process A top layer 6 is formed.

[0105] This insulating film can be deposited using methods such as plasma CVD and sputtering. Furthermore, after the formation of the etching stop layer 6, the water or hydrogen content is reduced. Heat treatment may be performed. For example, under reduced pressure or in an inert atmosphere, at a temperature of 300°C or higher. A heat treatment at 0°C or below for 1 hour or less is sufficient. This will allow hydrogen to be added to the oxide semiconductor layer 3. Contamination can be suppressed.

[0106] Furthermore, if the etching stop layer 6 contains an aluminum oxide film, the sputtering method By directly forming the film using a method such as, or by performing an oxidation treatment after forming the aluminum film... The aluminum oxide film can be formed by this process. The oxidation treatment involves using oxygen Examples include plasma treatment or oxygen doping treatment.

[0107] In addition, the aluminum oxide film has a high blocking function. Therefore, when the etching stop layer 6 including the aluminum oxide film is formed, it is preferable to perform a heat treatment aimed at reducing the content of water or hydrogen before forming the aluminum oxide film. Specifically, it is preferably performed after forming an insulating film other than the aluminum oxide film constituting the etching stop layer 6 and before forming the aluminum oxide film, or after forming the aluminum film and before performing an oxidation treatment on the aluminum film. Thereby, it is possible to effectively reduce the content of water or hydrogen in the formed etching stop layer 6 .

[0108] <(5) Crystallinity control of oxide semiconductor layer 3 (FIG. 3(B))> Next, plasma treatment is performed. In this plasma treatment, an inert gas such as argon or nitrogen or an oxygen gas is used as the gas species . Thereby, the crystals contained in a specific region of the oxide semiconductor layer 3 are amorphized. Specifically, the crystals contained in the region 8 not covered by the etching stop layer 6 are amorphized. As a result, the ratio of the crystal region in the region 7 covered by the etching stop layer 6 becomes higher than the ratio of the crystal region in the region 8 .

[0109] <(6) Formation of source electrode layer 4 and drain electrode layer 5 (FIG. 3(C))> Next, a conductive film is formed on the oxide semiconductor layer 3 and the etching stop layer 6. Next , a mask is formed on the conductive film using a photolithography method. Then, the conductive film in the portion not covered by the mask is removed by etching. As a result, the source electrode layer ​​​Layer 4 and the drain electrode layer 5 are formed.

[0110] The conductive film can be deposited using methods such as sputtering. When depositing the conductive film using the ring method, the oxide semiconductor layer 3 is formed depending on the conditions set. It is possible to amorphousize the crystals contained in region 8. For example, sputtering By increasing the wattage, it is possible to promote the amorphous formation of region 8. In this case, It is also possible to omit the step described in <(5) Control of the crystallinity of oxide semiconductor layer 3>.

[0111] <2. Semiconductor Equipment> Figure 4 below shows a specific example of a semiconductor device constructed using the transistors described above. Please refer to Figure 8 for further explanation.

[0112] <2-1.Display device> Figure 4 shows an example of a display device constructed using the transistors described above. Specifically, the display device shown in Figure 4 has all or part of the drive circuit and the pixel section mounted on the same substrate. It is a display device that is integrated into the system (a so-called system-on-panel display device). The transistors mentioned above are provided in the drive circuit and the pixel section. It is possible to apply it.

[0113] In Figure 4(A), the pixel portion 4002 provided on the substrate 4001 is surrounded by, A sealing material 4005 is provided and sealed by the substrate 4006. Figure 4(A) In a region different from the region surrounded by the sealing material 4005 on the substrate 4001, An IC chip, or a separately prepared substrate, formed with a single-crystal semiconductor film or a polycrystalline semiconductor film. A scanning line driving circuit 4004 and a signal line driving circuit 4003 are implemented. Also, separately formed signal line driving circuit 4003 and various signals and potentials supplied to the scanning line driving circuit 4004 or the pixel portion 4002 are supplied from FPC (Flexible printed circuit) 4018a and 4018b.

[0114] In FIGS. 4(B) and 4(C), a sealing material 4005 is provided so as to surround the pixel portion 4002 provided on the substrate 4001 and the scanning line driving circuit 4004. Also, a substrate 4006 is provided on the pixel portion 4002 and the scanning line driving circuit 4004. Thus the pixel portion 4002 and the scanning line driving circuit 4004 are sealed together with the display element by the substrate 4001, the sealing material 4005, and the substrate 4006. In FIGS. 4(B) and 4(C), in a region different from the region surrounded by the sealing material 4005 on the substrate 4001 an IC chip or a signal line driving circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is implemented. In FIGS. 4(B) and 4(C) various signals and potentials supplied to the separately formed signal line driving circuit 4003 and the scanning line driving circuit 4004 or the pixel portion 400 2 are supplied from FPC4018. Also, in FIGS. 4(B) and 4(C), an example in which the signal line driving circuit 4003 is separately formed and mounted on the substrate 4001 is shown, but it is not limited to this configuration. The scanning line driving circuit may be separately formed and mounted, or a part of the signal line driving circuit or a part of the scanning line driving circuit

[0115] may be separately formed and mounted. Moreover, in FIGS. 4(B) and 4(C), although an example in which the signal line driving circuit 4003 is separately formed and mounted on the substrate 4001 is shown, it is not limited to this configuration. The scanning line driving circuit may be separately formed and mounted, or a part of the signal line driving circuit or a part of the scanning line driving circuit may be separately formed and mounted.

[0116] Furthermore, the method of connecting the separately formed drive circuit is not particularly limited, and COG(C (hip-on-glass) method, wire bonding method, or TAB (Tape) Methods such as Automated Bonding can be used. Figure 4(A) shows This is an example of implementing the signal line drive circuit 4003 and the scan line drive circuit 4004 using the COG method. Figure 4(B) shows an example of implementing the signal line drive circuit 4003 using the COG method, and Figure 4( C) is an example of implementing the signal line drive circuit 4003 using the TAB method.

[0117] Furthermore, the display device includes a panel in which the display elements are sealed, and a control on the panel This includes modules that have ICs, etc., mounted on them, including those containing R.

[0118] In this specification, the term "display device" refers to an image display device, a display device, or This refers to a light source (including lighting devices). It also refers to a connector, such as an FPC or TCP, that is attached to it. A module that has been cut off, a module with a printed circuit board attached to the TCP, or a display element Modules in which ICs (integrated circuits) are directly mounted using the COG method are also included in the display device. It shall be assumed.

[0119] Furthermore, the pixel section and scanning line driving circuit provided on the substrate have multiple transistors. Therefore, the transistor shown in Embodiment 1 can be applied.

[0120] Display elements provided in a display device include liquid crystal elements (also called liquid crystal display elements) and light-emitting elements. A light-emitting element (also called a light-emitting display element) can be used. The light-emitting element emits light when current or voltage is applied. This category includes elements whose intensity is controlled, specifically inorganic EL (Electroluminescent) elements. This includes uminescence, organic EL, etc. Also, electronic inks and other electrically charged materials. Display media where contrast changes can also be applied.

[0121] Furthermore, one form of the display device will be explained using Figures 4 and 6. Figure 6(A) is a figure This corresponds to the cross-sectional view in MN of 4(B).

[0122] As shown in Figures 4 and 6, the display device has connection terminal electrodes 4015 and 4016 It has, and the connecting terminal electrode 4015 and terminal electrode 4016 are terminals of FPC4018 It is electrically connected via an anisotropic conductive layer 4019.

[0123] The connecting terminal electrode 4015 is formed from the same conductive layer as the first electrode layer 4030, and the terminal electrode 4016 has the same source and drain electrode layers as transistors 4010 and 4011. It is formed of a conductive layer.

[0124] Furthermore, the pixel section 4002 and the scanning line driving circuit 4004 provided on the substrate 4001 are It has multiple transistors, and in Figures 4 and 6, the transistors included in the pixel section 4002 The example shows transistor 4010 and transistor 4011 included in the scan line drive circuit 4004. In Figure 6(A), an insulating layer 4020 is provided on transistors 4010 and 4011. In Figure 6(B), an insulating layer 4021 is also provided.

[0125] The transistors described above can be used as transistors 4010 and 4011. In Figures 6(A) and (B), the oxide semiconductor layer is the source electrode layer and the drain. This shows a transistor with a structure that extends outward beyond the edges of the electrode layer. In transistors with such a structure, the etching stop layer is located at the edge of the oxide semiconductor layer. Parasitic channels in the transistor do not need to be provided between the source electrode layer and the drain electrode layer. It is possible to suppress the formation of the lumen.

[0126] Furthermore, there is an additional conductive layer at a location that overlaps with the oxide semiconductor layer of transistor 4011 for the drive circuit. A layer may be provided. The conductive layer has the same potential as the gate electrode layer of transistor 4011. It can be either that, or it can be different, and it can also function as a second gate electrode layer. Furthermore, the potential of the conductive layer may be GND, 0V, or in a floating state. The layer shields against the external electric field, meaning that the external electric field does not enter the internal circuit (including the transistors). It has a function to prevent action (especially an electrostatic shielding function against static electricity). Shielding of the conductive layer Depending on the function, the electrical characteristics of the transistor may fluctuate due to the influence of external electric fields such as static electricity. This can prevent that from happening.

[0127] The transistor 4010 provided in the pixel section 4002 is electrically connected to the display element, and displays The panel is constructed. The display elements are not particularly limited as long as they can display information, and various display elements are available. The child can be used.

[0128] <2-1-1. Liquid crystal display device> Figure 6(A) shows an example of a liquid crystal display device using liquid crystal elements as display elements. In this, the liquid crystal element 4013, which is a display element, has a first electrode layer 4030 and a second electrode layer 40 31 and the liquid crystal layer 4008 are included. Furthermore, an alignment film is provided to sandwich the liquid crystal layer 4008. Functional insulating layers 4032 and 4033 are provided. The second electrode layer 4031 is on the substrate 40 Located on the 06 side, the first electrode layer 4030 and the second electrode layer 4031 are separated by the liquid crystal layer 4008. The structure is designed to be layered in between.

[0129] Furthermore, the spacer 4035 is a columnar space obtained by selectively etching the insulating layer. It is a control element and is provided to control the film thickness (cell gap) of the liquid crystal layer 4008. A spherical spacer may also be used.

[0130] When using liquid crystal elements as display elements, thermotropic liquid crystals, low molecular weight liquid crystals, and polymer liquid crystals are used. Liquid crystals, polymer-dispersed liquid crystals, ferroelectric liquid crystals, antiferroelectric liquid crystals, etc. can be used. These liquid crystal materials (liquid crystal compositions) can be divided into a cholesteric phase, a smectic phase, and a crystalline phase depending on the conditions. It exhibits phases such as the occult phase, chiral nematic phase, and isotropic phase.

[0131] Furthermore, even if a liquid crystal composition that exhibits a blue phase without using an alignment film is used in the liquid crystal layer 4008, Good. In this case, the liquid crystal layer 4008, the first electrode layer 4030 and the second electrode layer 4031 The structure is in contact with each other. The blue phase is one of the liquid crystal phases, and the cholesteric liquid crystal is heated. In other words, it is a phase that appears just before the transition from the cholesteric phase to the isotropic phase. The blue phase is liquid It can be expressed using a liquid crystal composition that mixes crystal and chiral agents. - To broaden the temperature range in which the blue phase appears, polymerizable monomer is added to the liquid crystal composition that exhibits the blue phase. - And polymerization initiators can be added, and polymer stabilization treatment can be performed to form a liquid crystal layer. The liquid crystal composition that exhibits the blue phase has a short response speed and is optically isotropic, therefore alignment treatment It requires no rubbing and has low viewing angle dependence. Also, it does not require an alignment layer, so rubbing is not necessary. Since no rubbing treatment is required, electrostatic breakdown caused by rubbing treatment can be prevented, and defects and damages of the liquid crystal display device during the manufacturing process can be reduced. Therefore, the productivity of the liquid crystal display device can be improved. A transistor using an oxide semiconductor layer may have its electrical characteristics significantly fluctuated by the influence of static electricity and deviate from the design range. Therefore, it is more effective to use a liquid crystal composition that exhibits a blue phase in a liquid crystal display device having a transistor using an oxide semiconductor layer. Moreover, the resistivity of the liquid crystal material is 1×10 Ω·cm or more, preferably 1×10 Ω·cm or more, and more preferably 1×10 Ω·cm or more. The resistivity value in this specification is the value measured at 20°C. The size of the holding capacitance provided in the liquid crystal display device is set to be able to hold charges for a predetermined period in consideration of leakage current of the transistor arranged in the pixel portion. The size of the holding capacitance may be set in consideration of the off-current of the transistor. By using the transistor having the oxide semiconductor layer disclosed in this specification, a holding capacitance having a size of 1 / 3 or less, preferably 1 / 5 or less, of the liquid crystal capacitance in each pixel is sufficient.

[0132] 9 1 1 12

[0133]

[0134]

[0135] The transistor using the oxide semiconductor layer disclosed in this specification can control the current value (off-current value) in the off state to be low. Therefore, the holding time of an electrical signal such as an image signal can be lengthened, and the writing interval can also be set long in the power-on state. Therefore,

[0136] This reduces the frequency of reshuffling, thus lowering power consumption.

[0135] Furthermore, transistors using the oxide semiconductor layer disclosed herein have a relatively high field effect. Because fruit mobility can be obtained, high-speed driving is possible. For example, such high-speed driving is possible By using transistors in liquid crystal display devices, the switching transistors in the pixel section and the drive transistors are used. The driver transistors used in the dynamic circuit can be formed on the same substrate. In other words, it is necessary to use a semiconductor device formed from a silicon wafer or the like as a separate drive circuit. Because it does not have this, the number of components in the semiconductor device can be reduced. Also, in the pixel area, By using transistors capable of high-speed operation, high-quality images can be provided.

[0136] LCD displays include TN (Twisted Nematic) mode and IPS (In- Plane-Switching) mode, FFS (Fringe Field Switching) tching) mode, ASM(Axially Symmetric aligned) Micro-cell) mode, OCB(Optical Compensated) Birefringence mode, FLC (Ferroelectric Liqu id Crystal) mode, AFLC (AntiFerroelectric Li) You can use modes such as Quid Crystal.

[0137] Furthermore, a normally black type liquid crystal display device, for example, one that employs vertical alignment (VA) mode, It may also be used as a transmissive liquid crystal display device. Several vertical orientation modes can be listed. For example, MVA (Multi-Domain Vertical Alignment) ) Mode, PVA (Patterned Vertical Alignment) Mode You can use modes such as ASV (Advanced Super View). It can also be applied to VA-type liquid crystal display devices. VA-type liquid crystal display devices are... This is a type of method for controlling the arrangement of liquid crystal molecules in a liquid crystal display panel. (VA-type liquid crystal display device) This is a method in which the liquid crystal molecules are oriented perpendicular to the panel surface when no voltage is applied. Furthermore, a pixel is divided into several subpixel regions, and each region is processed in a different way. Multi-domainization or multi-domain design is a method that is designed to tilt molecules in a certain direction. A method can be used that allows for this.

[0138] Furthermore, in a display device, a black matrix (light-shielding layer), a polarizing member, a phase difference member, and a reverse Optical components (optical substrates) such as anti-radiation members shall be provided as appropriate. For example, polarizing substrates and phase difference Circular polarization using a substrate may also be used. Furthermore, backlights, sidelights, etc., may be used as light sources. You may use it.

[0139] Furthermore, the display method used in the pixel area may be a progressive or interlaced method. It is possible to do so. Also, the color elements controlled by pixels when displaying color include RGB(R It is not limited to the three colors (where G represents red, G represents green, and B represents blue). For example, RGBW (where W represents white). ), or RGB with one or more additional colors such as yellow, cyan, and magenta. The size of the display area may differ for each dot of the color element. However, the disclosed This is not limited to color display devices, but also applies to monochrome display devices. It is also possible to do so.

[0140] <2-1-2.EL display device> As a display element included in a display device, a light-emitting element that utilizes electroluminescence is used. It can be applied. A light-emitting device that utilizes electroluminescence has a light-emitting material. They are distinguished by whether they are organic or inorganic compounds; generally, the former are organic EL elements. The latter is called an inorganic EL element.

[0141] Organic EL elements emit electrons and positive voltages from a pair of electrodes when a voltage is applied to the light-emitting element. Each pore is injected into a layer containing a luminescent organic compound, and an electric current flows through it. The recombination of carriers (electrons and holes) causes the luminescent organic compound to form an excited state. It then emits light when the excited state returns to the ground state. From this mechanism, These light-emitting elements are called current-excited light-emitting elements.

[0142] Inorganic EL elements are classified into dispersed inorganic EL elements and thin-film inorganic EL elements depending on their element configuration. It is classified as follows: Dispersed inorganic EL elements have a light-emitting layer in which particles of light-emitting material are dispersed in a binder. It possesses a donor-acceptor level, and the luminescence mechanism utilizes donor-acceptor levels. This is acceptor-recombination type light emission. Thin-film inorganic EL elements sandwich the light-emitting layer between dielectric layers. Furthermore, it has a structure where it is sandwiched between electrodes, and the light emission mechanism involves the inner-shell electron transition of metal ions. The localized light emission method used is localized light emission. For this explanation, an organic EL element is used as the light-emitting element. do.

[0143] A light-emitting element only needs to have at least one of its pair of electrodes that is translucent in order to extract light. Then, transistors and light-emitting elements are formed on the substrate, and light is emitted from the side opposite to the substrate. This includes top-side emission, bottom-side emission which extracts light from the substrate side, and both the substrate side and the opposite side of the substrate. There are light-emitting elements with a double-sided emission structure that extract light from both sides, and any light-emitting element with an emission structure is applicable. It is possible.

[0144] Figures 5(A), (B) and 6(B) show examples of light-emitting devices using light-emitting elements as display elements. show.

[0145] Figure 5(A) is a plan view of the light-emitting device, and the dashed lines S1-T1 and S2-T in Figure 5(A) 2. The cross-section cut at S3-T3 corresponds to Figure 5(B). Note that Figure 5(A) is a plan view. In this diagram, the electroluminescent layer 542 and the second electrode layer 543 are omitted and not shown.

[0146] The light-emitting device shown in Figure 5 consists of a transistor 510, a capacitive element 520, and wiring on a substrate 500. It has a layer intersection 530, and the transistor 510 is electrically connected to the light-emitting element 540. It is present. Figure 5 shows the bottom emission, which extracts light from the light-emitting element 540 after passing through the substrate 500. It is a light-emitting device with a molded structure.

[0147] The transistor described above can be used as transistor 510.

[0148] Transistor 510 consists of a gate layer 511, a gate insulating layer 502, and an oxide semiconductor layer 512. Includes conductive layers 513a and 513b that function as a source electrode layer or a drain electrode layer.

[0149] The capacitive element 520 consists of a conductive layer 521, a gate insulating layer 502, an oxide semiconductor layer 522, and a conductive layer. Including layer 523, the conductive layer 521 and conductive layer 523 form the gate insulating layer 502 and oxide semiconductor The volume is formed by sandwiching the body layer 522.

[0150] The wiring layer intersection 530 is the intersection of the gate layer 511 and the conductive layer 533, and the gate layer Layer 511 and the conductive layer 533 intersect with the gate insulating layer 502 in between.

[0151] An interlayer insulating layer 50 is placed on the transistor 510, the capacitive element 520, and the wiring layer intersection 530. 4 is formed, and a color film is applied to the region on the interlayer insulating layer 504 that overlaps with the light-emitting element 540. A color filter layer 505 is provided. A flat layer is provided on the interlayer insulating layer 504 and the color filter layer 505. An insulating layer 506 is provided that functions as a flattened insulating layer.

[0152] The first electrode layer 541, the electroluminescent layer 542, and the second electrode layer 543 are arranged on the insulating layer 506 in that order. A light-emitting element 540 is provided, which includes a stacked stacked structure. Ta 510 is formed in the insulating layer 506 and the interlayer insulating layer 504 that reach the conductive layer 513a. In the opening, the first electrode layer 541 and the conductive layer 513a come into contact, thereby making electrical contact. It is continued. Furthermore, a partition wall 507 is provided so as to cover a part of the first electrode layer 541 and the opening. It's being kicked.

[0153] The insulating layer 506 has a photosensitive acrylic film with a thickness of 1500 nm, and the partition wall 507 has a thickness of 150 A 0 nm photosensitive polyimide film can be used.

[0154] For the color filter layer 505, for example, a translucent resin with a chromatic color can be used. As a translucent resin with colored pigments, photosensitive and non-photosensitive organic resins can be used, but Using a photosensitive organic resin layer reduces the number of resist masks, thus simplifying the process. It is preferable to transform it.

[0155] Chromatic colors are colors other than achromatic colors such as black, gray, and white, and the color filter layer is colored. It is made of a material that transmits only chromatic light. Chromatic colors include red, green, blue, etc. It can be used. Cyan, magenta, yellow, etc. may also be used. Transmitting only colored, chromatic light means that the transmitted light in the color filter layer is colored. This means that the light has a peak at the wavelength of the color. The color filter layer contains the coloring agent. It is best to appropriately control the optimal film thickness by considering the relationship between the concentration of the material and the light transmittance. For example, The film thickness of the LA filter layer 505 should be between 1500 nm and 2000 nm.

[0156] In the light-emitting device shown in Figure 6(B), the light-emitting element 4513, which is a display element, is a pixel section 4 It is electrically connected to the transistor 4010 located at 002. The configuration of 13 is the product of the first electrode layer 4030, the electroluminescent layer 4511, and the second electrode layer 4031. Although it has a layered structure, it is not limited to the configuration shown. The direction of light extracted from the light-emitting element 4513 is also important. The configuration of the light-emitting element 4513 can be changed as appropriate to suit the requirements.

[0157] Partition wall 4510 (Figure 6(B)) and partition wall 507 (Figure 5(B)) are made of organic insulating material or inorganic It is formed using an insulating material. In particular, a photosensitive resin material is used to form the first electrode layer 4030 (Figure 6). (B)) An opening is formed on the first electrode layer 541 (Figure 5(B)), and the side wall of the opening It is preferable to form the inclined surface so that it has a continuous curvature.

[0158] The electroluminescent layer 4511 (Figure 6(B)) and the electroluminescent layer 542 (Figure 5(B)) are single layers. It can be configured as a single unit or as multiple layers stacked on top of each other; either is acceptable.

[0159] Light-emitting element 4513 (Figure 6(B)), light-emitting element 540 (Figure 5(B)) contain oxygen, hydrogen, water, To prevent carbon dioxide and other substances from entering, the second electrode layer 4031 (Figure 6(B)), the second electrode layer 543 (Figure 5(B)) and on bulkhead 4510 (Figure 6(B)) and bulkhead 507 (Figure 5(B)) A protective film may be formed. Examples of protective films include silicon nitride film, silicon nitride oxide film, die It can form aluminum-like carbon (DLC) films and the like.

[0160] Furthermore, oxygen and hydrogen are supplied to the light-emitting element 4513 (Figure 6(B)) and the light-emitting element 540 (Figure 5(B)). To prevent water, carbon dioxide, etc. from entering, the light-emitting element 4513 (Figure 6(B)), light-emitting element 5 A layer containing an organic compound covering 40 (Figure 5(B)) may be formed by vapor deposition.

[0161] Furthermore, in the space sealed by substrate 4001, substrate 4006, and sealing material 4005 It is sealed with a filler material 4514. In this way, it is airtight so that it is not exposed to the outside air. Protective films with high performance and low degassing (laminated films, UV-curing resin films, etc.) It is preferable to package (seal) the contents with a cover material.

[0162] In addition to inert gases such as nitrogen and argon, filler material 4514 can also be UV-curing resin or Thermosetting resins can be used, such as PVC (polyvinyl chloride), acrylic, and poly Mid, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene Lenvinyl acetate can be used. For example, nitrogen can be used as a filler. .

[0163] Additionally, if necessary, a polarizing plate or circular polarizing plate (including elliptical polarizing plate) may be placed on the emission surface of the light-emitting element. Even if optical films such as phase difference plates (λ / 4 plate, λ / 2 plate) and color filters are appropriately provided, Good. Alternatively, an anti-reflective coating may be provided on the polarizing plate or circular polarizing plate. For example, due to surface irregularities... It is possible to apply an anti-glare treatment that diffuses reflected light and reduces glare.

[0164] <2-1-3. Electrophoresis Display Device> It is also possible to provide electronic paper, which drives electronic ink, as a display device. Electronic paper is also called an electrophoretic display device (electrophoretic display), and is similar to paper. It offers readability, lower power consumption compared to other display devices, and the ability to create a thin and light form factor. It has advantages.

[0165] Electrophoresis display devices can take various forms, but they typically involve detecting a first particle with a positive charge. Multiple microcapsules containing a second particle having a negative charge are present in the solvent or solute. It is a dispersed substance, and by applying an electric field to the microcapsules, the microcapsules Move the particles in the cell in opposite directions and display only the color of the particles that have gathered on one side. Furthermore, the first or second particle contains dye and moves in the absence of an electric field. It does not. Furthermore, the color of the first particle and the color of the second particle are different (including colorless). Let's assume that.

[0166] Thus, electrophoretic devices detect the movement of substances with high dielectric constants into high electric field regions. This is a display that utilizes the so-called dielectrophoretic effect.

[0167] When the above microcapsules are dispersed in a solvent, it is called an electronic ink. This electronic ink can print on surfaces such as glass, plastic, fabric, and paper. Furthermore, color display is possible by using color filters or particles containing pigments.

[0168] The first and second particles in the microcapsules are made of conductive material and insulating material. Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A type of material selected from chromochromic materials, magnetophoretic materials, or a composite material thereof Use it.

[0169] Furthermore, a display device using a twist-ball display method will also be applied as an electronic paper. This is possible. The twist ball display method uses spherical particles painted in white and black as display elements. It is placed between the first electrode layer and the second electrode layer, which are electrode layers used in the device, and the first electrode layer and A method of displaying information by generating a potential difference in two electrode layers to control the orientation of spherical particles. That is the case.

[0170] <2-2. Image Sensor> Figure 7(A) shows an example of an image sensor. Figure 7(A) shows the equivalent circuit of a photosensor. Yes, Figure 7(B) is a cross-sectional view showing a part of the photosensor.

[0171] Photodiode 602 has one electrode connected to the photodiode reset signal line 658. The other electrode is electrically connected to the gate of transistor 640. Transistor 64 0 means that either the source or the drain is connected to the photosensor reference signal line 672, or the source or the drain The other end of the circuit is electrically connected to either the source or the drain of transistor 656. Transistor 656 has its gate connected to the gate signal line 659, and the other of its source or drain connected to the gate signal line 659. It is electrically connected to the photo sensor output signal line 671.

[0172] In the circuit diagrams in this specification, transistors using oxide semiconductor layers are clearly defined. As can be seen, the symbol for a transistor using an oxide semiconductor layer is written as "OS". In Figure 7(A), transistors 640 and 656 are as described above. A rangitor can be applied. Note that in Figure 7(B), the oxide semiconductor layer is Transis structure that extends outward beyond the edges of the electrode layer and drain electrode layer This shows the structure. In transistors with this structure, the etching stop layer is acid Even if the transistor is not provided between the edge of the semiconductor layer and the source electrode layer and drain electrode layer, It is possible to suppress the formation of parasitic channels in the t.

[0173] Figure 7(B) shows the photodiode 602 and transistor 640 in the photosensor. This is a cross-sectional view, showing a substrate 601 (element substrate) having an insulating surface, which functions as a sensor. A photodiode 602 and a transistor 640 are provided. A substrate 613 is provided on top of transistor 640 using an adhesive layer 608. ru.

[0174] An insulating layer 631, an interlayer insulating layer 633, and an interlayer insulating layer 634 are provided on the transistor 640. The photodiode 602 is formed on an electrode layer 641 on an interlayer insulating layer 633. b and the first semiconductor film 606a and the second semiconductor film 606b, which are stacked sequentially on the electrode layer 641b. , and the third semiconductor film 606c, and provided on the interlayer insulating layer 634, the first to third semiconductor Electrode layer 642 is electrically connected to electrode layer 641b via a film, and the same layer as electrode layer 641b It has an electrode layer 641a provided therein, which is electrically connected to the electrode layer 642.

[0175] The electrode layer 641b is electrically connected to the conductive layer 643 formed on the interlayer insulating layer 634, and The polar layer 642 is electrically connected to the conductive layer 645 via the electrode layer 641a. 5 is electrically connected to the gate electrode layer of transistor 640, and photodiode 6 02 is electrically connected to transistor 640.

[0176] Here, the first semiconductor film 606a is a semiconductor film having a p-type conductivity, and the second semiconductor film Film 606b is a high-resistance semiconductor film (Type I semiconductor film), and the third semiconductor film 606c is an n-type semiconductor film. This example illustrates a pin-type photodiode in which semiconductor films having the conductivity type are stacked.

[0177] The first semiconductor film 606a is a p-type semiconductor film and contains an amorphous material that imparts the p-type properties. It can be formed by a fast silicon film. The formation of the first semiconductor film 606a is performed using Group 13 silicon. Using a semiconductor material gas containing impurity elements (e.g., boron (B)), the plasma CVD method It is formed by [method]. Silane (SiH4) can be used as the semiconductor material gas. Alternatively, Si2H6, SiH2Cl2, SiHCl3, SiCl4, SiF4, etc. may also be used. Furthermore, after forming an amorphous silicon film free of impurity elements, diffusion or ion injection is performed. Impurity elements may be introduced into the amorphous silicon film using an implantation method, such as ion implantation. It is advisable to introduce impurity elements and then diffuse them by heating or other methods. In this case, methods for forming amorphous silicon films include LPCVD and vapor phase growth. Alternatively, sputtering or similar methods may be used. The thickness of the first semiconductor film 606a should be 10 nm or more. It is preferable to form the structure so that it is 50 nm or less.

[0178] The second semiconductor film 606b is a type I semiconductor film (intrinsic semiconductor film), and is amorphous silicic. It is formed by an aluminum film. For the formation of the second semiconductor film 606b, a semiconductor material gas is used to form an aluminum film. A rufus silicon film is formed by plasma CVD. As the semiconductor material gas, silamine is used. You can use (SiH4). Alternatively, you can use Si2H6, SiH2Cl2, SiHCl3. SiCl4, SiF4, etc. may be used. The second semiconductor film 606b is formed by LPCVD. This may be carried out by vapor phase growth, sputtering, etc. The thickness of the second semiconductor film 606b is It is preferable to form it so that the wavelength is between 200 nm and 1000 nm.

[0179] The third semiconductor film 606c is an n-type semiconductor film and contains an impurity element that confers n-type properties. It is formed by a Rufus silicon film. The formation of the third semiconductor film 606c involves impurities from Group 15. Formed by plasma CVD using a semiconductor material gas containing an element (e.g., phosphorus (P)). Yes. Silane (SiH4) can be used as the semiconductor material gas. Alternatively, Si2H6 SiH2Cl2, SiHCl3, SiCl4, SiF4, etc. may also be used. After forming an amorphous silicon film that does not contain any elemental material, diffusion and ion implantation methods are used. Impurity elements may be introduced into the amorphous silicon film by ion implantation or the like. It is advisable to diffuse impurity elements by heating or other methods after introducing the elemental material. Methods for forming amorphous silicon films include LPCVD, vapor phase growth, or spallation. A method such as uttering can be used. The thickness of the third semiconductor film 606c should be between 20 nm and 200 nm. It is preferable to form it as follows:

[0180] Furthermore, the first semiconductor film 606a, the second semiconductor film 606b, and the third semiconductor film 606c are It may also be formed using a polycrystalline semiconductor instead of an amorphous semiconductor, or a microcrystalline (semi-amorphous) semiconductor. Morphic semiconductor (Semi-Amorphous Semiconductor: SA) It may also be formed using S)).

[0181] Furthermore, because the mobility of holes generated by the photoelectric effect is smaller than that of electrons, the pin type The photodiode exhibits better characteristics when the p-type semiconductor film side is the light-receiving surface. Here, From the surface of the substrate 601 on which the pin-type photodiode is formed, the photodiode 60 This shows an example of converting the light received by 2 into an electrical signal. It also shows the opposite direction to the semiconductor film side that acts as the light-receiving surface. Since light from the semiconductor film side with an electrochemical pattern becomes ambient light, the electrode layer is a conductive layer with light-shielding properties. It is recommended to use it. Furthermore, the n-type semiconductor film side can also be used as the light-receiving surface.

[0182] The insulating layer 631, interlayer insulating layer 633, and interlayer insulating layer 634 are made of insulating material, Depending on the material, sputtering, plasma CVD, spin coating, dip, etc. Using spray coating, droplet ejection (inkjet method), screen printing, offset printing, etc. It can be formed by doing so.

[0183] As for the insulating layer 631, an inorganic insulating material such as a silicon oxide nitride layer or an acid A single layer or a laminate of silicon nitride layer, aluminum oxide layer, etc., can be used.

[0184] The interlayer insulating layers 633 and 634 function as planar insulating layers to reduce surface irregularities. A suitable insulating layer is preferred. Examples of interlayer insulating layers 633 and 634 include polyimide and acrylic. Heat-resistant organic resins such as benzocyclobutene resin, polyamide, epoxy resin, etc. Insulating materials can be used. In addition to the above organic insulating materials, low dielectric constant materials (low- k-materials), siloxane resins, PSG (phosphorus glass), BPSG (phosphorus boron glass), etc. A single layer or a laminate can be used.

[0185] By detecting the light 622 incident on the photodiode 602, information about the object being detected is obtained. It can read the information of the detected object. You can use it.

[0186] <2-3. Storage device> In the following, using the transistors shown in this specification, memory is maintained even when power is not supplied. An example of a storage device that can retain data and has no limit on the number of write cycles is shown with diagrams. explain.

[0187] Figure 8 shows an example of a memory device configuration. Figure 8(A) shows a cross-sectional view of the memory device, and Figure 8(B) shows a cross-sectional view of the memory device. The circuit diagrams for the memory devices are shown below.

[0188] The memory devices shown in Figures 8(A) and 8(B) have a semiconductor material other than an oxide semiconductor at the bottom. The transistor 3200 used has an oxide semiconductor on top, and the transistor 3202 has an oxide semiconductor on top. and has a capacitive element 3204. Transistor 3202 is, in the embodiment This is an example of applying the structure of transistor 420 shown in 4.

[0189] Here, semiconductor materials other than oxide semiconductors include polycrystalline silicon or single-crystal silicon. By applying this, transistor 3200 can be made into a transistor capable of high-speed operation. Yes, it is possible. On the other hand, the transistor 3200 uses an oxide semiconductor to maintain charge for a long time. It can be made into a transistor that can maintain its shape.

[0190] The above explanation assumes that all transistors are n-channel transistors. However, it goes without saying that p-channel transistors can be used. Aside from using the transistor described above as the Rangitor 3202, the materials used in memory devices are... It is not necessary to limit what is shown here to the specific configuration of the storage device, such as the structure of the data or storage device. stomach.

[0191] In Figure 8(A), transistor 3200 uses a semiconductor material (e.g., silicon). A channel formation region is provided on the substrate 3000, and is provided so as to sandwich the channel formation region. An impurity region, an intermetallic compound region adjacent to the impurity region, and a channel-forming region It has a gate insulating film and a gate electrode layer provided on the gate insulating film. In the diagram, the source electrode layer and drain electrode layer may not be explicitly shown, but for convenience... In some cases, the term "transistor" is used to include the state described above. To explain the connection relationship of the starter, the source electrode layer and drain region are included, along with the source and drain regions. It is sometimes referred to as the rain electrode layer. In other words, in this specification, it is referred to as the source electrode layer. This may include the source area.

[0192] An element isolation insulating layer 3106 is provided on the substrate 3000 so as to surround the transistor 3200. An insulating layer 3220 is provided to cover the transistor 3200. The element isolation insulating layer 3106 is LOCOS (Local Oxidation of S Examples include ilicon and STI (shallow trench isolation). It can be formed using element isolation technology.

[0193] By using a single-crystal semiconductor substrate as substrate 3000, the transistor 3200 can operate at high speed. This becomes possible. Therefore, the transistor can be used as a readout transistor. This allows for high-speed reading of information. Transistor 3202 and capacitive element As a pre-formation treatment for 3204, the insulating layer 3220 covering transistor 3200 is subjected to CMP treatment. By applying this process, the insulating layer 3220 is planarized, and at the same time, the gate electrode layer of transistor 3200 Expose the top surface.

[0194] The transistor 3202 has a low off-current, so using it allows for long-term operation. It is possible to retain the stored contents. In other words, it does not require a refresh operation, or This makes it possible to create a storage device with an extremely low refresh frequency, Power consumption can be significantly reduced.

[0195] One of the source electrode layer or drain electrode layer of transistor 3202 is a gate insulating layer and In the opening provided in the oxide semiconductor layer, electrode 3208 is electrically connected to electrode 32 It is electrically connected to the gate electrode layer of transistor 3200 via 08. Electrode 32 08 can be formed simultaneously with the gate electrode layer of transistor 3202.

[0196] Furthermore, an insulating layer 3222 is provided on the transistor 3202 in a single layer or multi-layer configuration. Then, the source electrode layer or drain electrode of transistor 3202 is connected via the insulating layer 3222. A conductive layer 3210a is provided in the region that overlaps with one of the pole layers, and transistor 32 One of the source electrode layer or drain electrode layer of 02, the insulating layer 3222 and the conductive layer 3210a This constitutes the capacitive element 3204. That is, the source power of transistor 3202 One of the polar layer or drain electrode layer functions as one electrode of the capacitive element 3204, and the conductive layer 3210a functions as the other electrode of the capacitive element 3204. Note that if capacitance is not required... It is also possible to have a configuration without the capacitive element 3204. Alternatively, it may be provided above transistor 3202.

[0197] An insulating layer 3224 is provided on the capacitive element 3204. A wiring 3216 is provided, and this wiring 3216 connects transistor 3202 to other transistors It is provided for connecting the terminals. Wiring 3216 is formed in the insulating layer 3224. Electrode 3214 provided in the mouth, conductive layer 3210a and conductive layer 3210b provided in the same layer and, via the electrode 3212 provided in the opening formed in the insulating layer 3222, It is electrically connected to the source electrode layer or the other drain electrode layer of the 3202.

[0198] In Figure 8(A), transistor 3200 and transistor 3202 are at least It is also provided so that a part of it is superimposed, and the source area or drain of transistor 3200 The in region and a portion of the oxide semiconductor layer contained in transistor 3202 are arranged to overlap. It is preferable that the transistor 3202 and the capacitive element 3204 are connected to the transistor. It is provided so as to overlap with at least a part of the radiator 3200. For example, a capacitive element The conductive layer 3210a of transistor 3204 is at least partially connected to the gate electrode layer of transistor 3200. These are superimposed. By adopting such a planar layout, the memory This allows for a reduction in the occupied area, thus enabling higher concentration.

[0199] Next, an example of a circuit configuration corresponding to Figure 8(A) is shown in Figure 8(B).

[0200] In Figure 8(B), the first line and the saw of transistor 3200 The electrode layer is electrically connected to the second line and transistor 32. The drain electrode layer of 00 is electrically connected. Also, the third wiring (3rd Li The electrical connection between ne) and either the source electrode layer or the drain electrode layer of transistor 3202 is It is connected to the fourth wire (4th Line) and the gate electrode layer of transistor 3202. They are electrically connected. And the gate electrode layer of transistor 3200 and the transistor The source electrode layer or the other drain electrode layer of the converter 3202 is connected to the power supply of the capacitive element 3204. It is electrically connected to one of the poles, the 5th line, and the capacitive element 3204 The other end of the electrode is electrically connected.

[0201] In the memory device shown in Figure 8(B), the potential of the gate electrode layer of transistor 3200 can be maintained. By utilizing its unique characteristics, it is possible to write, store, and read information in the following ways: ru.

[0202] This section explains how to write and retain information. First, the potential of the fourth wiring is determined by the transistor. Set the potential to such that transistor 3202 is ON, and turn on transistor 3202. As a result, the potential of the third wiring is the gate electrode layer of transistor 3200 and the capacitive element 3 It is given to 204. That is, the gate electrode layer of transistor 3200 has a predetermined charge. A charge is given (written). Here, a charge that gives two different potential levels (hereinafter Lo) Let's assume that either a w-level charge or a high-level charge is given. The potential of the fourth wire is set to the potential at which transistor 3202 is in the off state, and the transistor By turning off transistor 3202, the gate electrode layer of transistor 3200 is supplied with The applied charge is retained (retained).

[0203] Because the off-current of transistor 3202 is extremely small, the gate of transistor 3200 The charge in the electrode layer is retained for a long period of time.

[0204] Next, we will explain how to read the information. When a predetermined potential (constant potential) is applied to the first wiring... In this state, when the appropriate potential (readout potential) is applied to the fifth wiring, the gate of transistor 3200 Depending on the amount of charge held in the electrode layer, the second wiring takes on a different potential. Generally, If transistor 3200 is an n-channel type, then the gate electrode layer of transistor 3200 contains Hi Apparent threshold V when a gh-level charge is given th_H is transistor 3 Apparent threshold V when a low-level charge is applied to the 200 gate electrode layer t h_LThis is because it becomes lower. Here, the apparent threshold voltage is defined as transistor 32 This refers to the potential of the fifth wire required to bring 00 into the "on state". The potential of the fifth wiring is V th_H and V th_L By setting the potential V0 between them, The charge applied to the gate electrode layer of the ZISTA 3200 can be determined. For example, the charge applied during writing. Therefore, if a high-level charge is applied, the potential of the fifth wiring is V0 (>V th _H ) If this occurs, transistor 3200 will be in the "on state". Low-level charge is applied. If this is the case, the potential of the fifth wiring is V0( <V th_L Even if that happens, Transis The TA3200 remains in the "off state". Therefore, by determining the potential of the second wiring... The stored information can be read.

[0205] Furthermore, when memory cells are arranged in an array, only the information of the desired memory cell can be read. It becomes necessary to be able to extract the information. If the information is not read in this way, the state of the gate electrode layer Regardless of the state, the potential at which transistor 3200 is in the "off state" is, that is, V th _H A smaller potential can be applied to the fifth wiring. Alternatively, depending on the state of the gate electrode layer... The potential at which transistor 3200 turns "on" is, that is, V th_L Larger A high potential should be applied to the fifth wire.

[0206] In the memory device described above, by applying transistors using oxide semiconductors, extremely It is possible to retain memory content for a long period of time. In other words, refreshing operations are unnecessary. This can be achieved, or the frequency of refresh operations can be made extremely low, thus reducing consumption Power can be significantly reduced. Also, in the case of no power supply (however, the potential is fixed) Even if it is desirable that the memory contents be retained over a long period of time, That is the case.

[0207] Furthermore, the aforementioned memory device does not require high voltage for writing information, and the degradation of the elements is reduced. There are no problems. For example, unlike conventional non-volatile memory, electrons to the floating gate Because there is no need for injection or extraction of electrons from the floating gate, gate isolation is achieved. Problems such as film degradation do not occur at all. In other words, in the memory device described above, conventional non-volatile There are no limitations on the number of rewrite cycles, which is a problem with conventional memory, and reliability is dramatically improved. Furthermore, information is written depending on whether the transistor is on or off. High-speed operation can also be easily achieved.

[0208] Furthermore, a memory device constructed using the transistors shown in this specification is shown in Figure 8. It is not limited to memory devices. For example, as a transistor provided in a memory cell of a DRAM. The transistor may be used.

[0209] <Supplement: Regarding oxygen desorption from oxide semiconductor layers> The following details why oxygen is easily removed from the side (end face) of the CAAC-OS membrane.

[0210] Here, as an example of an oxide semiconductor film, we present In-Ga-Zn, an oxide of a ternary metal. In IGZO (hereinafter referred to as IGZO) films, excess oxygen (existing in amounts exceeding the stoichiometric ratio) The mobility of oxygen atoms (and oxygen vacancies) will be explained by referring to the results of scientific and technical calculations. do.

[0211] Note that the calculation is performed using one of the IGZOs with an atomic ratio of In:Ga:Zn = 3:1:2. - A model with one excess oxygen or oxygen deficiency on the O-plane was created by structural optimization (Figure 9) (See (A) to (C) and Figure 11(A) to (C)) and NEB (Nudged El Energy for intermediate structures along the minimum energy path using the elastic band method The amount of ghee was calculated for each.

[0212] The calculations were performed using "OpenMX," a computational program software based on density functional theory (DFT). This was done using the following method. The parameters are explained below.

[0213] The basis set used was a pseudo-atomic localization basis set. This basis set is the polarization basis set STO(S It is classified as a later Type Orbital.

[0214] The functional is GGA / PBE (Generalized-Gradient-Approximate). Oximation (Perdew-Burke-Ernzerhof) was used.

[0215] The cutoff energy was set to 200Ry.

[0216] The sampling k-points were set to 5 × 5 × 3.

[0217] In the calculation of the mobility of excess oxygen, the number of atoms present in the calculation model is set to 85. In the calculation of the mobility of oxygen vacancies, the number of atoms present in the calculation model is set to 8. I chose 3.

[0218] The mobility of excess oxygen or oxygen deficiency is affected by the movement of excess oxygen or oxygen deficiency to each site. This is evaluated by calculating the height Eb of the energy barrier that must be overcome when moving. In other words, if the height Eb of the energy barrier that must be overcome during movement is high, movement becomes more difficult. If the energy barrier height Eb is low, movement is easier.

[0219] First, let's explain the movement of excess oxygen. Figure 9 shows the model used to calculate the movement of excess oxygen. The calculations were performed for the following two transition forms. The calculation results are shown in Figure 10. In figure 10, the horizontal axis represents the path length (of excess oxygen movement), and the vertical axis represents the state of Model A in Figure 9(A). This is defined as the energy required for movement relative to the energy of the object.

[0220] Regarding the movement of excess oxygen, of the two transition modes mentioned above, the first transition is from Model A. This is a transition to Model B. The second transition is from Model A to Model C.

[0221] Note that the oxygen atom labeled "1" in Figures 9(A) to (C) is the first oxygen atom of Model A. This is called an oxygen atom. The oxygen atom labeled "2" in Figures 9(A) to (C) is Model A. This is called the second oxygen atom. The oxygen atom labeled "3" in Figures 9(A) to (C) is This is called the third oxygen atom in Model A.

[0222] As is clear from Figure 10, the maximum value of the energy barrier height Eb of the first transition (Eb max ) is 0.53 eV, and the maximum value of the energy barrier height Eb of the second transition ( Eb max ) is 2.38 eV. Therefore, the first transition is more energy-efficient than the second transition. Maximum value of energy barrier height Eb (Eb max ) is low. Therefore, the time required for the first transition The energy required for the first transition is less than the energy required for the second transition, meaning the first transition is easier than the second transition. It is more likely to occur than migration.

[0223] In other words, the movement of the first oxygen atom in Model A pushes out the third oxygen atom in Model A. Rather than the direction of movement, it can be said that the second oxygen atom in Model A is more likely to move in the direction that pushes it out. Oxygen atoms tend to move along the layer of indium atoms rather than across the layer of indium atoms. It can be said that it is easy to move around.

[0224] Next, we will explain the movement of oxygen deficiency. Figure 1 shows the model used to calculate the movement of oxygen deficiency. As shown in 1, the calculations were performed for the following two transition forms. The calculation results are shown in Figure 12. In Figure 12, the horizontal axis represents the path length (of oxygen deficiency movement), and the vertical axis represents the length of Model A in Figure 11(A). This is defined as the energy required for movement relative to the energy of the state.

[0225] Regarding the movement of oxygen deficiency, of the two transition modes mentioned above, the first transition is from Model A. This is a transition to Model B. The second transition is from Model A to Model C.

[0226] Note that the dotted circles in Figures 11(A) to (C) represent oxygen deficiencies.

[0227] As is clear from Figure 12, the maximum value of the energy barrier height Eb of the first transition (Eb max ) is 1.81 eV, and the maximum value of the energy barrier height Eb of the second transition ( Eb max ) is 4.10 eV. Therefore, the first transition is more energy-efficient than the second transition. Maximum value of energy barrier height Eb (Eb max ) is low. Therefore, the time required for the first transition The energy required for the first transition is less than the energy required for the second transition, meaning the first transition is easier than the second transition. It is more likely to occur than migration.

[0228] In other words, the oxygen deficiency in Model A is located in a different position than the oxygen deficiency in Model C, compared to the oxygen deficiency in Model B. It can be said that the location of the loss is more easily moved. Therefore, the oxygen vacancy also traverses the layer of indium atoms. It can be said that it is easier for indium atoms to move along the layer of atoms rather than moving in that direction.

[0229] Next, in order to compare the likelihood of the four transition forms mentioned above from a different perspective, these The temperature dependence of the transition will be explained. The four transition modes mentioned above are (1) the first of excess oxygen (1) Transition to oxygen deficiency (2) Second transition to oxygen deficiency (3) First transition to oxygen deficiency (4) Second transition to oxygen deficiency These are the four transitions.

[0230] The temperature dependence of these transitions is compared by the migration frequency per unit time. Here, The migration frequency Z ( / second) at temperature T (K) is the migration frequency of oxygen atoms in chemically stable positions. Using the frequency Zo( / sec), it can be expressed by the following equation (1).

[0231]

number

[0232] Note that in equation (1), Eb max The height Eb of the energy barrier in each transition is This is the maximum value, where k is Boltzmann's constant. Also, Zo = 1.0 × 10⁻⁶ 13 ( / second) Used in calculations.

[0233] Excess oxygen or oxygen deficiency occurs only once per second, at the maximum energy barrier height Eb. Value (Eb maxWhen moving beyond (Z=1( / sec)), equation (1) applies to T. Solving this gives the following result. (1) First transition of excess oxygen: T=206K (-67℃) at Z=1 (2) Second transition of excess oxygen: T=923K (650℃) at Z=1 (3) First transition of oxygen deficiency: T=701K (428℃) at Z=1 (4) Second transition of oxygen deficiency: T=1590K (1317℃) at Z=1

[0234] On the other hand, Z when T=300K (27℃) is as follows: (1) First transition of excess oxygen: Z = 1.2 × 10 at T = 300 K 4 ( / sec) (2) Second transition of excess oxygen: Z = 1.0 × 10 at T = 300 K -27 ( / sec) (3) First transition of oxygen deficiency: Z = 4.3 × 10 at T = 300 K -18 ( / sec) (4) Second transition of oxygen deficiency: Z = 1.4 × 10 at T = 300 K -56 ( / sec)

[0235] Furthermore, the value of Z when T=723K (450℃) is as follows: (1) First transition of excess oxygen: Z = 2.0 × 10 at T = 723 K 9 ( / sec) (2) Second transition of excess oxygen: Z = 2.5 × 10 at T = 723 K -4 ( / sec) (3) First transition of oxygen deficiency: Z = 2.5 ( / sec) at T = 723K (4) Second transition of oxygen deficiency: Z = 2.5 × 10 at T = 723 K -16 ( / sec)

[0236] In light of the calculation results, excess oxygen is present at both T=300K and T=723K. It is easier to move along the layer of indium atoms than to move across the layer of indium atoms. It can be said that oxygen deficiency also occurs at both T=300K and T=723K. It can be said that it is easier to move along the layer of indium atoms than to move across the layer of um atoms. ru.

[0237] Furthermore, at T=300K, the movement of excess oxygen along the indium atom layer is very infrequent. It is prone to complication, but other transition modes are unlikely to occur. At T=723K, indium atoms Not only does excess oxygen move along the layers, but oxygen deficiencies also move along the layers of indium atoms. It is easy to understand, but both excess oxygen and oxygen deficiency involve the movement of indium atoms across the layer. That is difficult.

[0238] Therefore, for example, in a CAAC-OS film, the layer of indium atoms extends to the surface on which the film is formed. Alternatively, if present on a surface parallel to the surface, both excess oxygen and oxygen deficiency will affect the film's coverage. It can be said that it is easily moved along the forming surface or surface.

[0239] As explained above, in CAAC-OS membranes, excess oxygen and oxygen deficiency are present in the membrane. It is easily moved along a surface or plane. Therefore, oxygen leakage from the sides of the film becomes a problem. When oxygen depletion occurs, the amount of excess oxygen decreases, making it difficult to compensate for the oxygen deficiency. It becomes so. If oxygen deficiency is present, it reaches a level that is undesirable for use in switching elements. The conductivity of the CAAC-OS film may increase.

[0240] Furthermore, in the explanation above, when excess oxygen or oxygen deficiency crosses the indium atom layer... As explained above, the same applies to metals other than indium contained in oxide semiconductor films. ru.

[0241] (Embodiment 2) In this embodiment, one aspect of the method for manufacturing a semiconductor device is shown in Figures 13(A) and 13(B). This will be explained using Figures 13(C), 13(D), and 13(E) to illustrate one aspect of a semiconductor device. I will use it to explain.

[0242] Figures 13(C), 13(D), and 13(E) show an example of a semiconductor device, a transistor The plan view and cross-sectional view of transistor 410 are shown. Figure 13(E) is a plan view of transistor 410. Figure 13(C) is a cross-sectional view of Figure 13(E) at X1-X2. Figure 13(D) is This is a cross-sectional view of Y1-Y2 in Figure 13(E).

[0243] The transistor 410 shown in Figures 13(C), 13(D), and 13(E) is located on substrate 40 A base insulating layer 436 is placed on top of 0, and an oxide semiconductor film 403 is placed on top of the base insulating layer 436, and an oxide semiconductor film A gate insulating film 402 is provided on the body film 403, and an oxide semiconductor is transmitted through the gate insulating film 402. A gate electrode layer 401 provided on the conductive film 403, and a gate electrode layer 401 provided on the gate electrode layer 401 Through the insulating film 406, the gate insulating film 402, and the opening in the insulating film 406, the oxide semiconductor A source electrode layer 405a or drain electrode layer 405b that is electrically connected to the film 403, and - Includes an insulating film 407 provided on the electrode layer 405a and the drain electrode layer 405b. It is composed of.

[0244] Furthermore, in transistor 410, the oxide semiconductor film 403 overlaps with the gate electrode layer 401. A channel formation region 409 that is folded over, and a channel formation region 4 sandwiching the channel formation region 409 It has lower resistance than 09, and low-resistance regions 404a and 404b containing the dopant Includes. Dopants are elements that change the conductivity of oxide semiconductor films. Therefore, Group 15 elements (typically nitrogen (N), phosphorus (P), arsenic (As), and antimony) Sodium (Sb), Boron (B), Aluminum (Al), Tungsten (W), Molybdenum (Mo), indium (In), gallium (Ga), fluorine (F), chlorine (Cl), titanium It is one or more selected from either titanium (Ti) and zinc (Zn).

[0245] The oxide semiconductor film 403 is single crystal, polycrystalline (also called polycrystal), or amorphous. Which state is taken? In this embodiment, the low resistance region 404a and the low resistance region with dopant added are The anti-region 404b is almost entirely amorphous, or the proportion of amorphous components is large compared to the crystalline components. This area will be designated as [a specific region].

[0246] Figure 13(A) shows a cross-sectional view of the process before the introduction of impurity elements that act as dopants. The oxide semiconductor film 403 before the introduction of impurity elements to act as dopants is a single crystal film, polycrystalline film. The film (also called polycrystal) or CAAC-OS film is used.

[0247] The thickness of the oxide semiconductor film 403 is 1 nm to 30 nm (preferably 5 nm to 10 nm). (m or less), sputtering method, MBE (Molecular Beam Epitaph) xy) method, CVD method, pulsed laser deposition method, ALD (Atomic Layer Deposition) The spar method and other methods can be used as appropriate. In addition, the oxide semiconductor film 403 is spa Film deposition is carried out with multiple substrate surfaces set approximately perpendicular to the surface of the tarring target. The film may also be deposited using a sputtering apparatus.

[0248] Single crystal films, polycrystalline films, or CAAC-OS films can be deposited by changing the deposition conditions of the deposition method, or by changing the deposition conditions of the film deposition method. This can be achieved by increasing the substrate temperature during film formation, or by performing appropriate heat treatment after film formation.

[0249] Then, as shown in Figure 13(B), the low-resistance region 404a and the low-resistance region 404b are, After forming the gate electrode layer 401, impurity elements are introduced using the gate electrode layer 401 as a mask. By doing so, it can be formed in a self-consistent manner. Methods for introducing impurity elements include Ion implantation or ion doping is used. Furthermore, the region in question is transistor 4. It can function as 10 source or drain regions.

[0250] By providing low-resistance regions 404a and 404b, the pair of low-resistance regions The electric field applied to the channel-forming region 409 located between the regions can be mitigated. Furthermore, the source electrode layer 405a and the drain electrode layer 405b are each in a low-resistance region 404a. By configuring it to be in contact with 404b, the oxide semiconductor layer 403 and the source electrode layer 405a and This reduces the contact resistance with the drain electrode layer 405b.

[0251] Furthermore, in this embodiment, the channel formation region 409 is a low-resistance region 404a and a low-resistance region Compared to region 404b, the proportion of crystalline components is higher than that of amorphous components. Also, see Figure 13(B). Hydrogen is attracted in the direction indicated by the dotted arrow in the middle, and low resistance region 404a and low resistance region 4 The hydrogen concentration in the channel-forming region 409 is lower than that in 04b.

[0252] Furthermore, the oxide semiconductor film 403 is formed when impurities such as hydrogen are sufficiently removed, or By supplying sufficient oxygen and creating a supersaturated state of oxygen, the resulting product is purified to a high degree. It is desirable that the hydrogen concentration of the oxide semiconductor layer be 5 × 10⁻⁶. Specifically, the hydrogen concentration of the oxide semiconductor layer should be 5 × 10⁻⁶. 19 Atom s / cm 3 The following is preferable: 5 x 10 18 atoms / cm 3 The following is more preferable: 5x 10 17 atoms / cm 3 The following applies. Note that the hydrogen concentration in the oxide semiconductor layer mentioned above is: Secondary Ion Mass Spectrometry (SIMS) It is measured by rometry. Also, when sufficient oxygen is supplied and oxygen is supersaturated... To achieve this state, an insulating layer containing excess oxygen (Si) is added to surround the oxide semiconductor film 403. Install it in contact with (Ox, etc.).

[0253] The insulating layer containing excess oxygen consists of the underlayer insulating layer 436 and the gate insulating film 402, and is an oxide semiconductor. It is provided in contact with the film 403, enclosing it. The base insulating layer 436 and the gate insulating film 40 2 involves appropriately setting the film deposition conditions in the PCVD method or sputtering method to include a large amount of oxygen in the film. A SiOx film or silicon oxidnitride film is used. In addition, a large amount of excess oxygen is incorporated into the insulating layer. If you wish to do so, you can use ion implantation, ion doping, or oxygen doping by plasma treatment. Oxygen is added by [this method].

[0254] The above term "oxygen doping" refers to oxygen (at least oxygen radicals, oxygen atoms, oxygen components). One of the following: oxygen, ozone, oxygen ions (oxygen molecular ions), and / or oxygen cluster ions. This refers to adding (including) to the bulk. Note that the term "bulk" refers to the addition of oxygen to a thin film. It is used to clarify that it is added not only to the surface but also to the interior of the thin film. The term "doping" includes "oxygen plasma doping," which involves adding plasma-treated oxygen to the bulk material. .

[0255] For oxygen doping, gases containing oxygen can be used. Examples of oxygen-containing gases include: Oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide, etc., can be used. Furthermore, in the oxygen doping process, a noble gas may be added to the oxygen-containing gas.

[0256] The oxygen doping treatment described above affects the interface between the insulating layer and the oxide semiconductor film, or the bulk of the insulating layer. Within the film, there is an oxygen excess where oxygen levels exceed the stoichiometric ratio of the film at least in one location. A region can be established.

[0257] Furthermore, an insulating film 40 is placed on the oxide semiconductor film 403, the gate insulating film 402, and the gate electrode layer 401. A 6 is provided. The insulating film 406 is planarized to reduce surface irregularities caused by the transistor. It may also be used as an insulating film. Examples of planarizing insulating films include polyimide resins, acrylic resins, and benzylamine resins. Organic materials such as zocyclobutene resins can be used. In addition to the above organic materials, Low dielectric constant materials (low-k materials), etc., can be used. A planar insulating film may be formed by stacking multiple insulating films.

[0258] Furthermore, the oxide semiconductor film is surrounded and positioned outside the insulating layer containing excess oxygen. It is preferable to include a blocking layer (such as AlOx) to suppress the release of oxygen from the oxide semiconductor film. stomach.

[0259] The blocking layer is the insulating film 407, which is an insulating layer containing excess oxygen with aluminum A nium film is laminated, and an insulating layer and an oxygen-doped aluminum film are applied on top of the aluminum film. By doing this, a region containing an excess of oxygen in the insulating layer compared to the stoichiometric composition is formed. In both cases, it is preferable to oxidize the aluminum film to form an aluminum oxide film. This consists of an aluminum oxide film, a titanium oxide film, a tungsten oxide film, a nickel oxide film, and an oxide film. A molybdenum film or a magnesium oxide film is laminated, and the titanium oxide film, tungsten oxide film The resistivity of the nickel oxide film, molybdenum oxide film, or magnesium oxide film is 1 × 10⁻⁶. 10 Ωm or greater: 1 × 10 19 Ωm or less (preferably 1 × 10⁻⁶) 10 Ωm or greater: 1 × 10 18 Ωm or more Below, fer 1 × 10 11 Ωm or greater: 1 × 10 15 It is preferable that the value be less than or equal to Ωm. By providing a film having the above resistivity, electrostatic discharge damage to semiconductor devices can be prevented. .

[0260] By encasing the oxide semiconductor film in an insulating or blocking layer containing excess oxygen, the oxide In the semiconductor layer, a state that closely matches the stoichiometric composition, or a state that is closer to the stoichiometric composition. A supersaturated state with a high oxygen content can be achieved. For example, when the oxide semiconductor film is IGZO. One example of a stoichiometric composition is In:Ga:Zn:O=1:1:1:4 [atomic ratio]. Therefore, in the oxide semiconductor film, the atomic ratio of oxygen is greater than 4.

[0261] In this embodiment, an example of stacking insulating films 406 and 407 is shown, but the embodiment is not particularly limited. The insulating film 406 may be omitted.

[0262] Transistor 410 has a self-aligned region with a high crystalline content (i.e., channel formation region 409) ) and regions with a high concentration of amorphous components (i.e., low-resistance region 404a and low-resistance region 404b) It has a mixed oxide semiconductor film 403, and the hydrogen concentration in the channel formation region 409 is amorphous The hydrogen concentration is reduced compared to the region with high quality. Therefore, the channel of transistor 410 By removing as much hydrogen as possible from the ion-forming region and supplying oxygen, a highly purified Type I or It can be brought closer to that. By making it type I, the threshold voltage value of the transistor can be changed. This allows for a positive value, enabling the realization of a so-called normally-off switching element. Furthermore, The channel formation region of transistor 410 has an extremely low minority carrier density and is oxygen-rich. Defects and carrier generation sources such as hydrogen are reduced, allowing for extremely low off-currents.

[0263] (Embodiment 3) In this embodiment, using Figure 14, a semiconductor having a sidewall on the side wall of the gate electrode layer is shown. An example of a method for fabricating the device is shown.

[0264] First, an underlayment insulating layer 436 is formed on a substrate 400 having an insulating surface.

[0265] There are no major restrictions on the substrates that can be used for the substrate 400 having an insulating surface, however In both cases, it is necessary to have sufficient heat resistance to withstand subsequent heat treatment. For example, burrs Glass substrates such as umborosilicate glass and aluminoborosilicate glass, ceramic substrates, Quartz substrates, sapphire substrates, etc. can be used. Also, silicon and silicon carbide can be used. Which single-crystal semiconductor substrates, polycrystalline semiconductor substrates, and compound semiconductor groups such as silicon germanium Boards, SOI substrates, etc., can also be used, and semiconductor elements are provided on these substrates. This may be used as substrate 400.

[0266] Furthermore, a flexible substrate may be used as the substrate 400 to fabricate a semiconductor device. To fabricate such a semiconductor device, a transistor containing an oxide semiconductor film 403 is placed on a flexible substrate. The 440a may be fabricated directly, or a transistor containing the oxide semiconductor film 403 may be fabricated on another fabrication substrate. Zista 440a may be fabricated, and then peeled off and transferred to a flexible substrate. To peel and transfer from the fabricated substrate to the flexible substrate, the translocator containing the oxide semiconductor film 403 is used. It is preferable to provide a release layer between Zista 440a and the other component.

[0267] As the base insulating layer 436, an oxide silica is formed by plasma CVD or sputtering. Cone, silicon oxide nitride, aluminum oxide, aluminum oxide nitride, hafnium oxide, It can be formed using gallium oxide or a mixture thereof.

[0268] The underlying insulating layer 436 may be a single layer or a multilayer. For example, a silicon oxide film on the substrate 400, The in-Hf-Zn oxide film and the oxide semiconductor film 403 may be stacked in order, or the substrate 40 On top of the 0, there is a silicon oxide film, and the atomic ratio of In:Zr:Zn is 1:1:1 in an In-Zr-Zn system. The oxide film and the oxide semiconductor film 403 may be stacked in order, or silicon oxide may be placed on the substrate 400. Film, In-Gd-Zn oxide film with an atomic ratio of In:Gd:Zn=1:1:1, oxide semi-oxide film The conductive films 403 may be stacked in sequence.

[0269] In this embodiment, the underlying insulating layer 436 is formed using the sputtering method using silica oxide. A film is used.

[0270] Furthermore, a nitride insulating film may be provided between the underlying insulating layer 436 and the substrate 400. The film is made of silicon nitride, silicon nitride oxide, etc., by plasma CVD or sputtering. Formed using aluminum nitride, aluminum oxide nitride, or a mixture thereof. It is possible.

[0271] The underlying insulating layer 436 is in contact with the oxide semiconductor film 403, and therefore contains at least a small amount in the film (bulk). It is preferable that an amount of oxygen exceeding the stoichiometric ratio is present. For example, the base insulating layer 436 and And when using a silicon oxide film, SiO 2+α (However, assume α > 0) By using such an underlay insulating layer 436, oxygen can be supplied to the oxide semiconductor film 403. This can be achieved and its properties can be improved. By supplying oxygen to the oxide semiconductor film 403 This allows for the replenishment of oxygen deficiencies in the membrane.

[0272] For example, the underlying insulating layer 436, which contains a large amount (excess) of oxygen that serves as an oxygen source, is an oxide semiconductor By being provided in contact with the film 403, acid is released from the underlying insulating layer 436 to the oxide semiconductor film 403. It can supply the material. At least one oxide semiconductor film 403 and an underlying insulating layer 436 By performing a heat treatment while the parts are in contact, oxygen is supplied to the oxide semiconductor film 403. That's fine.

[0273] In the region where the oxide semiconductor film 403 is in contact with the underlying insulating layer 436, a planarization treatment is performed. Planarization treatments are not particularly limited, but include polishing treatments (e.g., chemical polishing). Chemical Mechanical Polishing (CMP) Dry etching and plasma treatment can be used.

[0274] Plasma processing can be performed, for example, by introducing argon gas to generate plasma. Sputtering can be performed. Reverse sputtering is a process where RF is applied to the substrate side under an argon atmosphere. This method involves applying a voltage using a power supply to form plasma near the substrate and modify its surface. Note that nitrogen, helium, oxygen, etc. may be used instead of an argon atmosphere. (Reverse sputtering) When the cleaning is performed, powdery substances (particles, dirt) adhering to the surface of the underlying insulating layer 436 are removed. It can remove (also known as).

[0275] For planarization, polishing, dry etching, and plasma treatment can be performed multiple times. Furthermore, these can be combined. Also, when combining them, the order of the steps is not particularly limited. It is not fixed and should be set appropriately according to the unevenness of the surface of the underlying insulating layer 436.

[0276] Planarization is performed, for example, by chemically manipulating the surface of the silicon oxide film used as the underlying insulating layer 436. Polishing treatment by polishing method (polishing conditions: polyurethane polishing cloth, silica slurry, slurry) Temperature: Room temperature, Polishing pressure: 0.001 MPa, Polishing rotation speed (table / spindle): 60 rpm The average surface roughness (R) of the silicon oxide film surface was measured at 56 rpm and a polishing time of 0.5 minutes. a) should be approximately 0.15 nm.

[0277] Next, an oxide semiconductor film 403 is formed on the underlying insulating layer 436.

[0278] In the process of forming the oxide semiconductor film 403, hydrogen or water is added to the oxide semiconductor film 403. To minimize the presence of certain substances, a pretreatment is performed on the oxide semiconductor film 403 before deposition. In the preheating chamber of the taring device, the substrate on which the underlying insulating layer 436 has been formed is preheated, and the substrate and It is preferable to desorb and exhaust impurities such as hydrogen and moisture adsorbed on the underlying insulating layer 436. Furthermore, a cryopump is preferred as the exhaust means for the preheating chamber.

[0279] Furthermore, the underlying insulating layer 436 has reduced impurities such as hydrogen (including water and hydroxyl groups), and oxygen To create an excess state, hydrogen (including water and hydroxyl groups) is removed from the underlying insulating layer 436 (dehydration). Heat treatment (dehydration or dehydrogenation treatment) and / or oxygen treatment for (or dehydrogenation) Dehydration or dehydrogenation treatment and oxygen doping treatment may be performed multiple times. Often, both can be repeated.

[0280] Immediately after deposition, the oxide semiconductor film 403 is in a supersaturated state with a higher oxygen content than its stoichiometric composition. It is preferable to do so. For example, an oxide semiconductor film 403 is deposited using a sputtering method. In this case, it is preferable to deposit the film under conditions where oxygen makes up a large proportion of the film-forming gas, and especially oxygen It is preferable to perform the film deposition in an atmosphere (100% oxygen gas). The proportion of oxygen in the deposition gas. When forming a film under conditions with a high concentration of oxygen, especially in an atmosphere of 100% oxygen gas, for example, the film formation temperature may exceed 300°C. Even with the above configuration, the release of Zn from the film is suppressed.

[0281] Furthermore, in order to supply sufficient oxygen and create a supersaturated state of oxygen, the oxide semiconductor film 403 and The insulating film in contact (a plurality of insulating films provided so as to surround the oxide semiconductor film 403) is It is preferable to use an insulating film that contains excess oxygen.

[0282] In this embodiment, the oxide semiconductor film 403 is fabricated by sputtering. As a target, the composition is In:Ga:Zn=3:1:2 [atomic percentages] An In-Ga-Zn oxide film (IGZO film) is deposited using an oxide target.

[0283] Furthermore, the relative density (filling rate) of the metal oxide target is preferably 90% to 100%. The percentage is between 95% and 99.9%. Use a metal oxide target with a high relative density. As a result, the deposited oxide semiconductor film can be made into a dense film.

[0284] The sputtering gas used when depositing the oxide semiconductor film 403 is hydrogen, water, hydroxyl group or It is preferable to use a high-purity gas from which impurities such as hydrides have been removed.

[0285] The substrate is held in a deposition chamber under reduced pressure. Then, any residual moisture in the deposition chamber is removed. Sputtered gas from which hydrogen and moisture have been removed is introduced, and the substrate 40 is cut using the target described above. An oxide semiconductor film 403 is deposited on 0. In order to remove residual moisture in the deposition chamber, adsorption Vacuum pumps of various types, such as cryopumps, ion pumps, and titanium sublimation pumps. It is preferable to use a turbo molecular pump. Furthermore, as an exhaust means, a cold turbo is used with a turbo molecular pump. A pump may be added. The deposition chamber, which has been evacuated using a cryopump, for example, Hydrogen atoms, water (H2O), and other compounds containing hydrogen atoms (more preferably compounds containing carbon atoms) Because substances such as [unclear] are exhausted, impurities are contained in the oxide semiconductor film 403 deposited in the deposition chamber. It can reduce the concentration of substances.

[0286] Furthermore, the underlying insulating layer 436 and the oxide semiconductor film 403 are formed continuously without being exposed to the atmosphere. Preferably, the underlying insulating layer 436 and the oxide semiconductor film 403 are made continuous without being exposed to the atmosphere. When formed in this way, it prevents impurities such as hydrogen and moisture from adsorbing onto the surface of the underlying insulating layer 436. It is possible.

[0287] The oxide semiconductor film 403 is formed by a photolithography process into island-like structures. It can be formed by processing an oxide semiconductor film.

[0288] Furthermore, a resist mask for forming island-shaped oxide semiconductor films 403 is prepared by an inkjet method. It may also be formed by an inkjet method. If the resist mask is formed by an inkjet method, a photomask is used. Therefore, manufacturing costs can be reduced.

[0289] Note that etching of oxide semiconductor films can be done by either dry etching or wet etching. Both may be used. For example, the etching of oxide semiconductor films. As a quenching solution, a solution of phosphoric acid, acetic acid, and nitric acid can be used. O-07N (manufactured by Kanto Chemical Co., Ltd.) may also be used. In addition, ICP (Inductively Coupled Plasma (Inductively Coupled Plasma) Etching Method: Dry Etching Etching may also be performed by etching. For example, the IGZO film may be etched by the ICP etching method. Etching (Etching conditions: Etching gas (BCl3:Cl2 = 60 sccm): (20 sccm), power supply 450W, bias power 100W, pressure 1.9 Pa), island-shaped It can be processed into this.

[0290] In the oxide semiconductor film 403, impurities such as copper, aluminum, and chlorine are almost entirely present. It is desirable that it be highly purified. Therefore, a process that does not risk these impurities being mixed in or adhering to the surface of the oxide semiconductor film 403. It is preferable to select as appropriate, and if it adheres to the surface of the oxide semiconductor film 403, oxalic acid By exposing it to dilute hydrofluoric acid or performing plasma treatment (such as N2O plasma treatment), Therefore, it is preferable to remove impurities from the surface of the oxide semiconductor film 403. Specifically, oxide The copper concentration of semiconductor film 403 is 1 × 10⁻⁶ 18 atoms / cm 3 The following is preferably 1 × 10 1 7 atoms / cm 3 The following applies. Furthermore, the aluminum concentration of the oxide semiconductor film 403 is 1 ×10 18 atoms / cm 3 The following applies. Furthermore, the chlorine concentration of the oxide semiconductor film 403 is 2 ×10 18 atoms / cm 3 The following applies:

[0291] Furthermore, excess hydrogen (including water and hydroxyl groups) is removed from the oxide semiconductor film 403 (dehydration or Heat treatment may be performed to dehydrogenate the product. The heat treatment temperature should be 300°C or higher and 700°C or higher. The temperature should be below °C or below the substrate's strain point. Heat treatment should be performed under reduced pressure or in a nitrogen atmosphere. This is possible. For example, by introducing a substrate into an electric furnace, which is one of the heat treatment devices, an oxide semiconductor can be introduced. The film 403 is subjected to a heat treatment at 450°C for 1 hour under a nitrogen atmosphere.

[0292] Furthermore, the heat treatment device is not limited to electric furnaces, but also includes heat conduction or heat from heat-generating elements such as resistance heating elements. A device that heats the object to be processed by radiation may also be used. For example, GRTA(Gas R apid Thermal Anneal) equipment, LRTA (Lamp Rapid T RTA (Rapid Thermal Annealing) devices such as hermal annealing equipment al) equipment can be used. LRTA equipment uses halogen lamps, metal halide lamps. Lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure mercury lamps This is a device that heats an object to be processed by radiating light (electromagnetic waves) from a lamp or similar light source. The GRTA device is a device that performs heat treatment using high-temperature gas. Noble gases such as argon, or nitrogen, which do not react with the material being treated by heat treatment. An active gas is used.

[0293] For example, as a heat treatment, the substrate is placed in an inert gas heated to a high temperature of 650°C to 700°C. Alternatively, after heating for several minutes, a GRTA (Ground Removal and Exposure) may be performed to remove the substrate from the inert gas.

[0294] In addition, during the heat treatment, water is added to nitrogen or a noble gas such as helium, neon, or argon. It is preferable that it does not contain hydrogen, etc. Alternatively, nitrogen or helium introduced into the heat treatment apparatus. The purity of noble gases such as lium, neon, and argon is preferably 6N (99.9999%) or higher. This is 7N (99.99999%) or higher (i.e., impurity concentration of 1 ppm or less, preferably 0.1 ppm). It is preferable that the amount be less than or equal to ppm.

[0295] Furthermore, after heating the oxide semiconductor film 403 in the heat treatment, high-purity oxygen gas is placed in the same furnace. Dinitrate gas or ultra-dry air (CRDS (cavity ring down laser) The moisture content measured using a light-based dew point meter was 20 ppm (equivalent to a dew point of -55°C). The following may be introduced: preferably air at a concentration of 1 ppm or less, more preferably 10 ppb or less. It is preferable that the oxygen gas or nitrous oxide gas does not contain water, hydrogen, etc. Alternatively, the purity of the oxygen gas or nitrous oxide gas introduced into the heat treatment apparatus should preferably be 6N or higher. The concentration is 7N or higher (i.e., the impurity concentration in oxygen gas or nitrous oxide gas is 1 ppm or less). Preferably, the concentration is 0.1 ppm or less. Through this process, impurities are simultaneously reduced by the dehydration or dehydrogenation treatment. By supplying oxygen, which is the main component material that makes up the oxide semiconductor, The semiconductor film 403 can be made highly pure and electrically type I (intrinsic).

[0296] The timing for heat treatment for dehydration or dehydrogenation depends on the film-like oxide semiconductor film. This can be done after formation or after the formation of the island-shaped oxide semiconductor film 403.

[0297] Furthermore, the heat treatment for dehydration or dehydrogenation may be carried out multiple times, and may be combined with other heat treatments. You may sleep.

[0298] A heat treatment for dehydration or dehydrogenation is performed to process the oxide semiconductor film 403 into island-like structures. Previously, when the film-like oxide semiconductor film 403 covers the underlying insulating layer 436, the underlying insulating layer It is preferred because it prevents the release of oxygen contained in 436 through heat treatment. It's nice.

[0299] Next, a gate insulating film 442 is formed to cover the oxide semiconductor film 403.

[0300] Furthermore, in order to improve the coverage of the gate insulating film 442, the surface of the oxide semiconductor film 403 is also The above planarization process may be performed. In particular, a thin insulating film may be used as the gate insulating film 442. In this case, it is preferable that the surface of the oxide semiconductor film 403 has good flatness.

[0301] The thickness of the gate insulating film 442 shall be between 1 nm and 20 nm, and the method of sputtering or MBE shall be used. Methods such as CVD, pulsed laser deposition, and ALD can be used as appropriate.

[0302] The materials for the gate insulating film 442 include silicon oxide film, gallium oxide film, and aluminum oxide. Aluminum film, silicon nitride film, silicon oxide nitride film, aluminum oxide nitride film, or silicon nitride oxide film It can be formed using a silicon film. The gate insulating film 442 is an oxide semiconductor film 40 It is preferable that oxygen is contained in the portion in contact with 3. In particular, the gate insulating film 442 is in the film It is preferable that the amount of oxygen (in bulk) exceeds the stoichiometric ratio, for example If a silicon oxide film is used as the gate insulating film 442, SiO 2+α (just And, α > 0). In this embodiment, the gate insulating film 442 is SiO 2+α (Ta Therefore, a silicon oxide film with α > 0 is used. This silicon oxide film is used as the gate insulating film 44 By using it as 2, oxygen can be supplied to the oxide semiconductor film 403, resulting in good properties. It can be made that way. Furthermore, the gate insulating film 442 can be used to determine the size of the transistor being fabricated and It is preferable to form the gate insulating film 442 considering the step coverage.

[0303] Furthermore, the gate insulating film 442 is made of hafnium oxide, yttrium oxide, and hafnium. Silicate (HfSi x O y (x>0, y>0), nitrogen-added hafnium silicate Hafnium aluminate (HfAl x O y(x>0, y>0), lanthanum oxide By using any high-k material, gate leakage current can be reduced. Furthermore, gate insulation... The border film 442 may be a single-layer structure or a laminated structure.

[0304] Furthermore, the gate insulating film 442 has reduced impurities such as hydrogen (including water and hydroxyl groups), and is acidic. To create an excess of hydrogen, hydrogen (including water and hydroxyl groups) is removed from the gate insulating film 442 (dehydrogenation). Heat treatment (dehydration or dehydrogenation treatment) and / or oxygen for hydration or dehydrogenation. Doping may be performed. Dehydration or dehydrogenation treatment and oxygen doping treatment may be performed multiple times. You can either do it or repeat both.

[0305] In this embodiment, the gate insulating film 442 is heated at a temperature of 200°C to 400°C while applying a coating. Oxygen plasma treatment is performed using microwaves. As a result of this treatment, the gate insulating film 442 becomes highly dense. The gate insulating film 442 is subjected to dehydration or dehydrogenation treatment, or oxygen doping treatment. can.

[0306] Next, a laminate of a conductive film and an insulating film is formed on the gate insulating film 442, and the conductive film and the insulating film are formed Etching is performed to form a stack of the gate electrode layer 401 and the insulating film 413.

[0307] The materials for the gate electrode layer 401 are molybdenum, titanium, tantalum, tungsten, and aluminum. Metal materials such as um, copper, chromium, neodymium, scandium, or compounds mainly composed of these materials. It can be formed using gold material. Furthermore, impurities such as phosphorus can be used as the gate electrode layer 401. Semiconductor films such as polycrystalline silicon films doped with elements, and nickel silicides. A silicide film may also be used. The gate electrode layer 401 may be a single layer or a multilayer structure. It can also be used as a structure.

[0308] Furthermore, the material of the gate electrode layer 401 includes indium tin oxide and tungsten oxide. Indium oxide, indium zinc oxide containing tungsten oxide, and titanium oxide containing Indium oxide, indium tin oxide containing titanium oxide, indium oxide, zinc oxide, oxide Conductive materials such as silicon-doped indium tin oxide can also be used. A laminated structure of the above conductive material and the above metal material can also be used.

[0309] Furthermore, a nitrogen-containing metallic acid is used as one layer of the gate electrode layer 401 that is in contact with the gate insulating film 442. These are phosphates, specifically In-Ga-Zn-O films containing nitrogen, and In-Sn-O films containing nitrogen. or nitrogen-containing In-Ga-O film, nitrogen-containing In-Zn-O film, nitrogen-containing Sn- O films, nitrogen-containing In-O films, and metal nitride films (InN, SnN, etc.) can be used. These films can be exposed to temperatures of 5 eV (electron volts) or higher, preferably 5.5 eV (electron volts) or lower. Having the above work function, when used as a gate electrode layer, the threshold voltage of the transistor is raised This allows for a raspy design, enabling the realization of a so-called normally-off switching element.

[0310] The insulating film 413 is typically a silicon nitride film, an aluminum nitride film, or a silicon nitride oxide film. Aluminum nitride film, silicon oxide film, silicon oxide nitride film, aluminum oxide film Inorganic insulating films such as aluminum oxide nitride films can be used. The insulating film 413 is a p It can be formed using methods such as razma CVD or sputtering.

[0311] Next, using the gate electrode layer 401 and insulating film 413 as a mask, a dove onto the oxide semiconductor film 403. A pant is introduced to form low-resistance regions 404a and 404b (see Figure 14(A)).

[0312] The dopant introduction process involves injection conditions such as acceleration voltage and dose, as well as the film thickness through which the dopant is passed. The appropriate settings can be used for control. In this embodiment, phosphorus is used as the dopant, Phosphate ions are injected using the ON injection method. The dopant dose is 1 × 10⁻⁶. 13 io ns / cm 2 The above 5 x 10 16 ions / cm 2 The following is correct.

[0313] The dopant concentration in the low-resistance region is 5 × 10⁻⁶ 18 / cm 3 The above 1 x 10 22 / cm 3 The following is preferable:

[0314] When introducing the dopant, the substrate 400 may be heated during the process.

[0315] Furthermore, the process of introducing a dopant into the oxide semiconductor film 403 may be performed multiple times. Multiple types of pantos may be used.

[0316] Furthermore, heat treatment may be performed after the dopant introduction process. The heating conditions include a temperature of 30°C. Refrigerate at 0°C to 700°C, preferably 300°C to 450°C, for 1 hour under an oxygen atmosphere. It is preferable to perform this. Furthermore, heat treatment under a nitrogen atmosphere, under reduced pressure, and in air (ultra-dry air) is also preferable. You may go.

[0317] In this embodiment, phosphorus (P) ions are injected into the oxide semiconductor film 403 by ion implantation. The injection conditions for phosphorus (P) ions are an acceleration voltage of 30kV and a dose of 1.0 × 1 0 15 ions / cm 2 Let's assume that.

[0318] The oxide semiconductor film 403 is a CAAC-OS film, a polycrystalline film, or a single-crystal film. The semiconductor film 403 depends on the conditions of the dopant introduction process and the type of dopant, The introduction of a dopant may cause partial amorphous formation. For example, the introduction of a dopant may result in... Furthermore, in an oxide semiconductor film that does not overlap with the gate electrode layer 401, the upper layer becomes amorphous. However, the lower layer may remain without dopants added, preserving its crystalline components. In cases where amorphization occurs in this manner, the region that has been amorphized by the heat treatment described above is then treated. It is preferable to recrystallize the oxide semiconductor film 403 to improve its crystallinity.

[0319] By going through the above process, the low-resistance regions 404a and 40 are formed, flanking the channel formation region 409. 4b is provided, and a highly crystalline oxide semiconductor film 403 is formed.

[0320] Next, in order to form the sidewall insulating layer (hereinafter also called the sidewall), the insulating film 448 is formed This is achieved (see Figure 14(B)).

[0321] Insulating film 448 is typically a silicon oxide film, a silicon oxide nitride film, or an aluminum oxide film. Aluminum oxide nitride film, silicon nitride film, aluminum nitride film, silicon oxide nitride film Inorganic insulating films such as aluminum nitride film can be used, and they can be single-layer or multi-layer. The insulating film 448 is deposited by plasma CVD, sputtering, or CVD using a deposition gas. Method D can be used. CVD methods include LPCVD and plasma CVD. It can be used, and other methods such as application can also be used.

[0322] Then, anisotropic etching is performed on the insulating film 448 to form side wall insulating layers 414a and 414b. do.

[0323] Furthermore, the gate electrode layer 401, insulating film 413, and side wall insulating layers 414a and 414b are used as a mask. Then, the gate insulating film 442 is etched to form the gate insulating film 402 (Figure 14(C) (See reference). Also, etching of the gate insulating film 442 creates low-resistance regions 404a and 404 Expose a portion of b.

[0324] Next, a process is performed to amorphousize a portion of the exposed low-resistance regions 404a and 404b. As one of the processes to improve quality, exposure to argon plasma or oxygen plasma may be used. Furthermore, exposure to plasma containing dopants is also permitted. The plasma may produce oxygen, argon, and If the oxide semiconductor film 403 is sufficiently thicker than the depth from the surface where the dopant is added, By exposing them to plasma, only the surface layers of the exposed low-resistance regions 404a and 404b become amorphous. The regions become crystalline 445a and 445b, while the other regions remain in a state where the crystalline components are retained. (See Figure 14(D)). By providing amorphous regions 445a and 445b, Figure 14 (D) Hydrogen is attracted in the direction indicated by the dotted arrow, in amorphous regions 445a and 445b By attracting and fixing hydrogen, it is possible to remove as much hydrogen as possible from the channel formation region.

[0325] Furthermore, during the process of amorphousizing a portion of the exposed low-resistance regions 404a and 404b, the insulating film 413 and the side wall insulating layers 414a and 414b protect the gate electrode layer 401 from plasma. This is important in that regard.

[0326] Furthermore, other methods for amorphousizing a portion of the exposed low-resistance regions 404a and 404b are also available. One method involves using an ion implanter or ion plasma device to implant argon, oxygen, or dopamine. It is also possible to add ions.

[0327] Next, a protective insulating film is placed on the oxide semiconductor film 403, the gate insulating film 402, and the gate electrode layer 401. As a highly dense inorganic insulating film (typically an aluminum oxide film), insulating film 407 It forms.

[0328] The insulating film 407 may be a single layer or a multilayer, and preferably contains at least an aluminum oxide film. It seems so.

[0329] High-density aluminum oxide film (film density 3.2 g / cm³) 3 Preferably, 3.6 g / cm³ 3 By doing the above, stable electrical characteristics can be imparted to transistor 440a. Yes, it is possible. Film density can be measured using Rutherford backscattering or X-ray reflectivity. Yes, it is possible. Furthermore, aluminum oxide films contain at least a stoichiometric ratio exceeding the stoichiometric ratio within the film (bulk). It is preferable that a certain amount of oxygen is present. For example, when using an aluminum oxide film, AlO x (However, x > 1.5)

[0330] The aluminum oxide film used as insulating film 407 contains impurities such as hydrogen, water, and oxygen. It has a high blocking effect that prevents both from passing through the membrane.

[0331] Therefore, the insulating film 407 is protected from fluctuating factors such as hydrogen and moisture during and after the manufacturing process. Which impurities are mixed into the oxide semiconductor film 403, and which are the main component materials constituting the oxide semiconductor? It functions as a protective film that prevents the release of certain oxygen from the oxide semiconductor film 403. The aluminum oxide film also supplies oxygen to the oxide semiconductor film 403 that is in contact with it. can.

[0332] The insulating film 407 is deposited by plasma CVD, sputtering, or vapor deposition. This can be done. Also, gold can be obtained by performing an oxidation treatment on a metal film as the insulating film 407. A type of oxide film may also be used. In this embodiment, the aluminum film is subjected to oxygen doping treatment. The aluminum oxide film obtained by the above method is used.

[0333] Besides aluminum oxide films, typical insulating films 407 include silicon oxide films and nitrogen oxide films. Using an inorganic insulating film such as a silicon oxide film, an aluminum oxide nitride film, or a gallium oxide film. It can be present. Also, hafnium oxide film, magnesium oxide film, zirconium oxide film , lanthanum oxide film, barium oxide film, or metal nitride film (e.g., aluminum nitride film) It can also be used.

[0334] An interlayer insulating film 415 is formed on the insulating film 407. It can be formed using various materials and methods. In this embodiment, the interlayer insulating film 415 The interlayer insulating film 4 is formed with a thickness that can flatten the irregularities caused by transistor 440a. 15 is a silicon oxidizride film formed by the CVD method, or by the sputtering method. A silicon oxide film formed in this manner can be used.

[0335] Furthermore, as the interlayer insulating film 415, a planar insulating film is used to reduce surface irregularities caused by the transistor. A border film may be formed. As the planarizing insulating film, polyimide resin, acrylic resin, etc. Organic materials such as zocyclobutene resins can be used. In addition to the above organic materials, Low dielectric constant materials (low-k materials), etc., can be used.

[0336] An opening is formed in the interlayer insulating film 415 and the insulating film 407 that reaches the oxide semiconductor film 403. A source electrode layer 405a and a drain electrode layer 405b are formed at the mouth. Source electrode layer 405a The drain electrode layer 405b is used to connect to other transistors and elements, and various circuits can be constructed. It is possible.

[0337] Examples of conductive films used in the source electrode layer 405a and the drain electrode layer 405b include, A metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, W, or the above Metal nitride films composed of these elements (titanium nitride film, molybdenum nitride film, tungsten nitride film) A film (or similar material) can be used. Also, either the underside or the topside of a metal film such as Al or Cu. Both sides have high melting point metal films such as Ti, Mo, and W, or metal nitride films of those metals (titanium nitride film). A configuration in which molybdenum nitride film and tungsten nitride film are laminated is also possible. The conductive film used for the drain electrode layer and the drain electrode layer is formed from a conductive metal oxide. These are also good. Examples of conductive metal oxides include indium oxide (In2O3) and tin oxide (SnO3). 2) Zinc oxide (ZnO), indium tin oxide (In2O3-SnO2), i Zinc oxide (In2O3-ZnO) or silicon oxide in these metal oxide materials A product containing this can be used.

[0338] For example, the source electrode layer 405a and the drain electrode layer 405b are made of a single molybdenum film. Layers, lamination of tantalum nitride film and copper film, or lamination of tantalum nitride film and tungsten film, etc. You can use it.

[0339] Furthermore, in order to reduce the number of processes, a portion of the exposed low-resistance regions 404a and 404b were made amorphous. Another method of performing the process involves the source electrode layer 405a and the drain electrode layer 405 When forming the conductive film used in b, sputtering is performed with high power to form the conductive film. A routing can also be used. In this case, a portion of the exposed low-resistance regions 404a and 404b may be made conductive. Since the film can be amorphous depending on the film formation conditions, it does not increase the number of steps. A portion of the semiconductor film can be made amorphous.

[0340] The above steps are used to fabricate a semiconductor device having the transistor 440a of this embodiment. This is possible (see Figure 14(E)).

[0341] Figures 15(A) to (D), Figure 16(A), and Figure 16(B) show transistor 440a and These are transistors 440b, 440c, 440d, 440e, 440f, with different configurations. It shows 440g.

[0342] In transistors 440b, 440c, 440d, and 440e, the source electrode layer 405a , and the drain electrode layer 405b is the upper surface of the exposed oxide semiconductor film 403 and the side wall insulating layer It is provided in contact with 414a and 414b. Therefore, source electrode layer 405a or Dray Amorphous regions 445a and 445b where the electrode layer 405b and the oxide semiconductor film 403 are in contact, The distance to the gate electrode layer 401 is equal to the width of the sidewall insulating layer in the channel length direction, and further miniaturization is possible. In addition to being achievable, it allows for more consistent control during the manufacturing process.

[0343] Thus, the source electrode layer 405a or the drain electrode layer 405b and the oxide semiconductor film 403 To shorten the distance between the amorphous regions 445a and 445b that are in contact with each other and the gate electrode layer 401. Therefore, the source electrode layer 405a or the drain electrode layer 405b and the oxide semiconductor film 40 The region in contact with 3 (amorphous regions 445a and 445b), and the resistance between the gate electrode layer 401. Resistance is reduced, improving the on-characteristics of transistors 440b, 440c, 440d, and 440e. It becomes possible to do so.

[0344] Furthermore, in Figures 15(A) and 15(B), insulating film 407 is the interlayer insulating film 415, and the source electrode layer 405a, drain electrode layer 405b, side wall insulating layers 414a, 414b, insulating film 413 in contact It is established in this manner.

[0345] In the manufacturing process, transistors 440b and 440c consist of a gate electrode layer 401 and an insulating film 41 3. Cutting (grinding, polishing) the conductive film provided on the side wall insulating layers 414a and 414b. By removing and breaking the conductive film, the source electrode layer 405a and drain An electrode layer 405b is formed. The cutting (grinding, polishing) method is chemical mechanical polishing (Chem Preferably use the ical Mechanical Polishing (CMP) method. It is possible.

[0346] In the manufacturing process, transistor 440d comprises a gate electrode layer 401, an insulating film 413, and a side The conductive film provided on the wall insulating layers 414a and 414b is processed using a photolithography process. By etching with a dystomask, the source electrode layer 405a and the drain electrode This is an example of the formation of polar layer 405b.

[0347] In the manufacturing process, transistor 440e is formed by a gate electrode layer 401, an insulating film 413, and a side The conductive film provided on the wall insulating layers 414a and 414b is processed using a photolithography process. By etching while gradually receding the resist mask, the source electrode layer 405 This is an example of forming a and the drain electrode layer 405b.

[0348] Transistor 440f has a source electrode layer and a drain electrode layer made of an oxide semiconductor film 403. This is an example of providing it in a region that does not overlap with the insulating film 402. By sputtering with high power, a metal film (aluminum film, titanium film, etc.) is formed. Amorphization occurs, and metal elements are diffused into the oxide semiconductor film 403 by heat treatment, resulting in low Amorphous region 445a that resists and functions as a source electrode layer, and functions as a drain electrode layer. This forms an amorphous region 445b. After forming amorphous regions 445a and 445b, Remove the genus membrane.

[0349] Transistor 440g has a configuration that includes a barrier film in the sidewall insulating layer, and sidewall insulating layer 414a This is an example of forming an insulating film, which is a barrier film, so as to cover 414b. The insulating film 448 is formed After formation, the insulating film 448 is anisotropically etched to form side wall insulating layers 414a and 414b, After that, an insulating film, which is a barrier film, is formed, and anisotropic etching is performed on the barrier film, resulting in insulating film 417 a, 417b is formed. For example, an aluminum film is formed as a barrier film, and the aluminum An aluminum oxide film can be formed by oxygen doping a nium film. (Insulating film 448) Anisotropic etching is performed on the first layer, and then a second anisotropic etching is performed on the barrier film, and the transistor It consists of side wall insulating layers 414a, 414b and insulating films 417a, 417b as shown in 440g. A side wall insulating layer can be formed.

[0350] As described above, there is a channel-forming region in which crystalline components are retained, and an amorphous region in which amorphous components are abundant. A semiconductor device having transistors 440a to 440g including an oxide semiconductor film having a region In this configuration, stable electrical characteristics can be provided, and high reliability can be achieved.

[0351] Achieving high-speed response and high-speed operation of semiconductor devices having transistors containing oxide semiconductor films. A configuration and a method for manufacturing it can be provided.

[0352] (Embodiment 4) In this embodiment, transistors and capacitors are fabricated on the same substrate without increasing the number of manufacturing steps. An example of this will be explained below using Figures 17(A) and 17(B).

[0353] Even in a single-gate transistor structure where one channel formation region is formed, or where two are formed... It may be a double-gate structure or a triple-gate structure with three gates formed. It has two gate electrode layers arranged above and below the channel formation region, separated by a gate insulating film. A dual-gate type would also be acceptable.

[0354] The transistor 420 shown in Figure 17(B) is a planar type transistor with a top gate structure. This is an example of a gensta.

[0355] The transistor 420 shown in Figure 17(B) has an insulating surface provided with an underlying insulating layer 436. On the substrate 400, a channel formation region 409, low resistance regions 404a, 404b, amorphous Oxide semiconductor film 403 including regions 445a and 445b, source electrode layer 405a, drain The transistor 42 has an electrode layer 405b, a gate insulating film 402, and a gate electrode layer 401. Insulating films 406 and 407 are formed on 0. Also, the same material as the gate electrode layer 401 is used. The capacitive wiring 450 overlaps with the source electrode layer 405a via the gate insulating film 402, A capacitance 451 is formed using the dielectric insulating film 402 as the dielectric.

[0356] Figure 17(A) shows an example of a method for manufacturing a semiconductor device. Note that Embodiment 2 and the substrate Since the fabrication process for the insulating layer 436 and the oxide semiconductor film 403 containing crystalline components is the same, here I will omit the detailed explanation.

[0357] After the formation of the oxide semiconductor film 403 containing crystalline components, a source electrode is placed on the oxide semiconductor film 403. Form a conductive film that will form the layer and the drain electrode layer (including wiring formed from the same layer). The conductive film is a metal film containing elements selected from Al, Cr, Cu, Ta, Ti, Mo, and W. Alternatively, metal nitride films containing the above-mentioned elements (titanium nitride film, molybdenum nitride film, titanium nitride film) A sten film or the like can be used.

[0358] Next, a resist mask is formed on the conductive film by a photolithography process, and selectively E After performing a stirring to form the source electrode layer 405a and the drain electrode layer 405b, the resistor Remove the mask.

[0359] Furthermore, when depositing conductive films by sputtering, or when depositing source electrode layer 405a, drain electrode layer When plasma is used for etching to form 405b, the oxide semiconductor film 403 The surface may become amorphous or impurities may adhere to it. In that case, the amorphous state will The surface is exposed to oxalic acid or dilute hydrofluoric acid, or subjected to plasma treatment (such as N2O plasma treatment). By performing this process, the amorphous surface is removed to expose the crystalline components, or oxidation is performed. It is preferable to remove impurities from the surface of the semiconductor film. The amorphous surface is treated with oxalic acid or dilute acid. Exposure to hydrofluoric acid or plasma treatment (such as N2O plasma treatment) will expose the material. The thickness of the oxide semiconductor film 403 becomes thinner, but this is not shown in Figures 17(A) and 17(B). stomach.

[0360] Next, the oxide semiconductor film 403, the source electrode layer 405a, and the drain electrode layer 405b A gate insulating film 402 is formed to cover it.

[0361] Then, the gate electrode layer 401 is subjected to plasma CVD or sputtering, etc. It is formed on the insulating film 402 (see Figure 17(A)). Also, the thickness of the gate insulating film 402 is When using a thin insulating film, a planarization treatment may be performed before forming the gate insulating film 402. In this embodiment, the capacitive wiring 450 is also gate-insulated using the same material as the gate electrode layer 401. Formed on film 402. Gate insulation sandwiched between source electrode layer 405a and capacitive wiring 450. A portion of the film 402 is used as a dielectric to form a capacitance 451.

[0362] Next, the gate electrode layer 401, source electrode layer 405a, and drain electrode layer 405b are mass As a result, a rare gas or dopant is introduced into the oxide semiconductor film 403 to make it amorphous, It forms crystalline regions 445a and 445b.

[0363] The thickness of the source electrode layer 405a and the drain electrode layer 405b, and the use of noble gas or dopant Depending on the introduction conditions, the oxide beneath the source electrode layer 405a and the drain electrode layer 405b may be If a noble gas or dopant is introduced into the semiconductor film 403, the introduced region will be amorphous. This can also happen.

[0364] By providing amorphous regions 445a and 445b, water can be introduced into amorphous regions 445a and 445b. By attracting and fixing the element, hydrogen in the channel-forming region 409 can be removed as much as possible. .

[0365] Furthermore, in this embodiment, the region reaches the interface between the oxide semiconductor film 403 and the underlying insulating layer 436. The regions are shown as amorphous regions 445a and 445b, but if a noble gas or dopant is introduced... Depending on the conditions under which the material is introduced and amorphous, a noble gas or dopant may be introduced only near the surface. In some cases, only the upper layer becomes an amorphous region. Even in this case, water in the amorphous region By attracting and fixing the element, hydrogen in the channel-forming region 409 can be removed as much as possible. .

[0366] Next, an insulating film 40 is placed on the oxide semiconductor film 403, the gate insulating film 402, and the gate electrode layer 401. Form 6.

[0367] Next, a highly dense inorganic insulating film (typically aluminum oxide) that serves as a protective insulating film is placed on the insulating film 406. An insulating film 407 is formed as a titanium film (see Figure 17(B)). The example shown here illustrates the stacking of insulating films 406 and 407, but it is not particularly limited, and insulating film 406 can be omitted. It can be abbreviated.

[0368] Furthermore, in order to efficiently introduce noble gases or dopants, the gate electrode layer 4 The gate insulating film 402 is etched using 01 and the capacitive wiring 450 as a mask, and the oxide semiconductor A portion of the conductive film 403 may be exposed. Alternatively, a portion of the oxide semiconductor film 403 may be exposed. Afterward, argon plasma treatment or oxygen plasma treatment is performed on the exposed parts of the oxide semiconductor film 403. It may be made amorphous.

[0369] In Figure 17(B), the source electrode layer 405a and the drain electrode layer 405b are in contact with each other. The overlapping regions are shown as low-resistance regions 404a and 404b, and the channel-forming region 40 An amorphous region 445a is provided between 9 and the low-resistance region 404a. Furthermore, channel formation is also performed. An amorphous region 445b is provided between region 409 and the low-resistance region 404b. Amorphous region The hydrogen concentrations contained in 445a and 445b are in the channel-forming region 409 and the low-resistance region 404. a) The concentration should be higher than that of 404b.

[0370] As described above, the channel-forming region 409 retains crystalline components and contains a large amount of amorphous components. The transistor 420 includes an oxide semiconductor film having amorphous regions 445a and 445b. In semiconductor devices, stable electrical characteristics can be provided, and high reliability can be achieved. .

[0371] Furthermore, this embodiment can be freely combined with Embodiment 2 or Embodiment 3. For example, in combination with Embodiment 3, a side wall insulating layer is provided in contact with the side surface of the gate electrode layer. It is also possible to do so, in which case a side wall insulating layer is provided in contact with the side surface of the capacitance wiring 450.

[0372] (Embodiment 5) In this embodiment, an example of a semiconductor device (memory device) different from Embodiment 1 is shown using the drawings. I will explain.

[0373] Figure 18 shows an example of the configuration of a semiconductor device. Figure 18(A) shows a cross-sectional view of the semiconductor device. Figure 18(B) shows a plan view of the semiconductor device, and Figure 18(C) shows a circuit diagram of the semiconductor device. Here, Figure 18(A) shows the cross-sections at C1-C2 and D1-D2 in Figure 18(B). It corresponds to.

[0374] The semiconductor device shown in Figures 18(A) and 18(B) has a lower section using a first semiconductor material. It has a transistor 160 and a transistor 162 made of a second semiconductor material on top. Transistor 162 is adapted to the structure of transistor 420 shown in Embodiment 3. This is an example of its use.

[0375] Here, the first semiconductor material and the second semiconductor material are materials with different band gaps. Desirable. For example, the first semiconductor material is a semiconductor material other than an oxide semiconductor (such as silicon). The second semiconductor material can be an oxide semiconductor. The transistor used is easy to operate at high speed. On the other hand, the transistor using oxide semiconductors Due to its properties, the sta allows for long-term charge retention.

[0376] The above explanation assumes that all transistors are n-channel transistors. However, it goes without saying that p-channel transistors can be used. Also, information Embodiment 1, Embodiment 2, or Embodiment 3 uses an oxide semiconductor to hold the object. Aside from using transistors as shown, the materials and structure of the semiconductor device used in the semiconductor device are different. It is not necessary to limit the specific configuration of semiconductor devices, such as their construction, to what is shown here.

[0377] The transistor 160 in Figure 18(A) contains a semiconductor material (e.g., silicon). A channel formation region 116 is provided on the substrate 185, and the channel formation region 116 is sandwiched between An impurity region 120 is provided therein, and an intermetallic compound region 124 is in contact with the impurity region 120. The gate insulating film 108 provided on the channel formation region 116, and the gate insulating film 108 It has a gate electrode 110 provided on top. Note that in the figure, the source electric Although it may not have electrodes or drain electrodes, for convenience, this state is included in the term "transistor". It is sometimes called "ta". Also, in this case, to explain the connection relationship of the transistor, The source electrode and drain electrode are sometimes referred to as including the drain region and drain region. In this specification, the term "source electrode" may include the source region.

[0378] An element isolation insulating layer 106 is provided on the substrate 185 so as to surround the transistor 160. Furthermore, insulating layers 128 and 130 are provided to cover the transistor 160.

[0379] The transistor 160, which uses a single-crystal semiconductor substrate, is capable of high-speed operation. Therefore, By using this transistor as a readout transistor, information can be read out at high speed. This can be done. As a pre-formation process for transistor 162 and capacitive element 164, The insulating layer covering transistor 160 is subjected to CMP treatment to flatten insulating layers 128 and 130. At the same time, the upper surface of the gate electrode layer of transistor 160 is exposed.

[0380] The transistor 162 shown in Figure 18(A) uses an oxide semiconductor in the channel formation region. This is a top-gate type transistor. Here, the oxide semiconductor contained in transistor 162 The membrane has a channel-forming region in which crystalline components are retained and an amorphous region. Water is present in the amorphous region. By attracting elements, an oxide semiconductor is used in which the hydrogen concentration in the channel formation region is reduced. Thus, a transistor 162 with extremely excellent off-mode characteristics can be obtained.

[0381] Transistor 162 has a low off-current, so by using it, it can be used for long-term recording. It is possible to retain the stored content. In other words, it does not require a refresh operation, or This makes it possible to create a semiconductor memory device with an extremely low refresh frequency, Power consumption can be significantly reduced.

[0382] An insulating layer 150 is provided on the transistor 162 in a single layer or multi-layer configuration. In the region that overlaps with the electrode layer 142a of transistor 162 via layer 150, there is a conductive layer 1 A layer 48b is provided, and the electrode layer 142a, the insulating layer 150, and the conductive layer 148b Thus, the capacitive element 164 is formed. That is, the electrode layer 142a of the transistor 162 is The conductive layer 148b functions as one electrode of the capacitive element 164, and the conductive layer 148b is the other electrode of the capacitive element 164. It functions as an electrode. Note that if capacitance is not required, the capacitive element 164 can be omitted. It is also possible to provide the capacitive element 164 separately above the transistor 162. Good. Also, the conductive layer 148b is made using the same process as the gate electrode 148a of the transistor 162. It may be formed.

[0383] An insulating layer 152 is provided on the transistor 162 and the capacitive element 164. Furthermore, wiring 156 is provided on the insulating layer 152, and this wiring 156 is connected to the transistor 162. It is provided for connecting other transistors. Although not shown in Figure 18(A), Line 156 is an opening formed in the insulating layer 150, insulating layer 152, and gate insulating film 146, etc. The electrode is electrically connected to the electrode layer 142b via an electrode formed therein. At the very least, it is provided so as to overlap with a part of the oxide semiconductor layer 144 of transistor 162. It is preferable.

[0384] In Figures 18(A) and 18(B), transistor 160 and transistor 162 It is provided so that at least a portion of it overlaps, and the source region of transistor 160 Alternatively, it is preferable that the drain region and a portion of the oxide semiconductor layer 144 overlap. It seems that transistor 162 and capacitive element 164 are less than transistor 160. They are provided so as to overlap with a part of them. For example, the conductive layer 148b of the capacitive element 164 At least a portion of the gate electrode 110 of transistor 160 is superimposed on it. By adopting such a planar layout, the occupied area of ​​semiconductor devices can be reduced. Because this is possible, high integration can be achieved.

[0385] Next, Figure 18(C) shows an example of a circuit configuration corresponding to Figures 18(A) and 18(B).

[0386] In Figure 18(C), the first line and the source of transistor 160. The electrodes are electrically connected to the second line and transistor 160. The drain electrode is electrically connected. Also, the third wiring (3rd Line) and One of the source or drain electrodes of transistor 162 is electrically connected, and the fourth The wiring (4th Line) and the gate electrode of transistor 162 are electrically connected. And the gate electrode of transistor 160 and the source electrode of transistor 162 The other electrode or drain electrode is electrically connected to one of the electrodes of the capacitive element 164, and the fifth The wiring (5th Line) and the other electrode of the capacitive element 164 are electrically connected.

[0387] In the semiconductor device shown in Figure 18(C), the potential of the gate electrode of transistor 160 can be maintained. By taking advantage of these characteristics, it is possible to write, store, and read information as follows: .

[0388] This section will explain how to write and retain information. First, the potential of the fourth wire is set to the transistor. The potential is set so that transistor 162 is ON, thereby turning on transistor 162. The potential of the third wiring is applied to the gate electrode of transistor 160 and the capacitive element 164. This is how a predetermined charge is applied to the gate electrode of transistor 160. (Input). Here, a charge that gives two different potential levels (hereinafter referred to as Low-level charge, H) Let's assume that one of the following is given (referred to as a igh-level charge). Then, the power of the fourth wiring... The voltage is set to a level where transistor 162 is in the off state, and transistor 162 is turned off. By doing so, the charge applied to the gate electrode of transistor 160 is retained. Hold).

[0389] Because the off-current of transistor 162 is extremely small, the gate electrode of transistor 160 The electric charge is retained for a long period of time.

[0390] Next, we will explain how to read the information. The first wiring is under the condition that a predetermined potential (constant potential) is applied. Then, when the appropriate potential (readout potential) is applied to the fifth wire, the gate of transistor 160 Depending on the amount of charge held in the electrode, the second wiring takes on a different potential. Generally, If transistor 160 is an n-channel type, then a high-level current is applied to the gate electrode of transistor 160. Apparent threshold V when a load is given th_H This is the gate of transistor 160. Apparent threshold V when a low level charge is applied to the electrode th_L Lower This is for the purpose of the apparent threshold voltage, which is the voltage when transistor 160 is in the "on state". This refers to the potential of the fifth wiring necessary to achieve this. Therefore, the potential of the fifth wiring V th_H and V th_L By setting the potential between them to V0, the gate of transistor 160 The charge applied to the electrode can be determined. For example, during writing, the high-level charge If given, the potential of the fifth wire is V0 (>V th_H ) If that's the case, Zistar 160 enters the "on state". If a low-level charge is applied, the fifth The potential of the wiring is V0( <V th_L Even if this happens, transistor 160 remains in the "off state". It remains as is. Therefore, by looking at the potential of the second wire, the retained information can be read. It is possible.

[0391] When memory cells are arranged in an array, only the information of the desired memory cell is read. It is necessary to be able to output the information. If the information is not read in this way, the state of the gate electrode Regardless, the potential at which transistor 160 is in the "off state" is V th_H Yo A small potential should be applied to the fifth wire. Alternatively, regardless of the state of the gate electrode, The potential at which the ZISTA 160 is in the "on state," that is, V th_L A higher potential You should supply it to wire 5.

[0392] In the semiconductor device shown in this embodiment, an oxide semiconductor is used in the channel formation region for off-current By applying extremely small transistors, it is possible to retain memory contents for extremely long periods of time. This is possible. In other words, the refresh operation becomes unnecessary, or the refresh operation is eliminated. Because the frequency of this can be made extremely low, power consumption can be significantly reduced. Also, in the absence of power supply (however, it is desirable that the potential be fixed) However, it is possible to retain the contents of memories over a long period of time.

[0393] Furthermore, the semiconductor device shown in this embodiment does not require a high voltage for writing information, and There are no issues with degradation of the child. For example, unlike conventional non-volatile memory, it does not use floating gates. Because there is no need to inject electrons into it or extract electrons from the floating gate, Problems such as degradation of the gate insulating film do not occur at all. In other words, the semiconductor according to the disclosed invention. The device does not have the limitations on the number of rewrite cycles that are a problem with conventional non-volatile memory, and Reliability improves dramatically. Furthermore, the on and off states of the transistors allow information to be transmitted. Because writing is performed, high-speed operation can be easily achieved.

[0394] As described above, a semiconductor device that achieves miniaturization and high integration, and is given high electrical characteristics. The invention provides a method for setting up and manufacturing such a semiconductor device.

[0395] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0396] (Embodiment 6) This embodiment describes a different form of storage device structure from that of Embodiment 5.

[0397] Figure 19 is a perspective view of a memory device. The memory device shown in Figure 19 has a memory circuit at the top. Memory cell arrays (memory cell array 3400a or more) that include multiple recells It has multiple layers of (i)3400n (where n is an integer of 2 or more), and a memory cell array 3400a at the bottom. It has a logic circuit 3004 necessary to operate the memory cell array 3400n.

[0398] Figure 19 shows logic circuit 3004, memory cell array 3400a and memory cell array 34 00b is shown in the diagram, and the memory cell array 3400a or memory cell array 3400b Among the multiple memory cells included, memory cell 3170a and memory cell 3170b are used as substitutes. This is shown in the table. Examples of memory cells 3170a and 3170b are as described above. The same configuration as the circuit configuration described in the previous section can also be used.

[0399] Figure 20 shows a representative transistor 3171a included in the memory cell 3170a. The transistor 3171b included in the memory cell 3170b is shown as a representative example. Transistors 3171a and 3171b have channel formation regions in the oxide semiconductor film. Regarding the configuration of a transistor in which a channel formation region is formed in an oxide semiconductor film, the implementation Since the configuration is the same as described in any one of Forms 1 to 3, the explanation will be omitted.

[0400] Electrode 3501a, formed in the same layer as the gate electrode layer of transistor 3171a, is electrode 3 502a is electrically connected to electrode 3003a. Transistor 3171b Electrode 3501c, formed in the same layer as the gate electrode layer, is connected to electrode 3502c by electrode 3502c. It is electrically connected to the 3003c.

[0401] Furthermore, the logic circuit 3004 uses semiconductor materials other than oxide semiconductors as channel formation regions. It has a transistor 3001. The transistor 3001 is made of a semiconductor material (for example, cyanoacrylate). A substrate 3000 including a recon (etc.) is provided with an element isolation insulating layer 3106, and an element isolation insulating layer 31 A channel is obtained by forming a channel-forming region in the region surrounded by 06. It can be made into a transistor. Note that transistor 3001 is formed on an insulating surface. Channel formation regions are formed in semiconductor films such as polycrystalline silicon films and silicon films on SOI substrates. It may also be a transistor. The configuration of transistor 3001 is a known configuration. Since it is possible to use [this method], the explanation will be omitted.

[0402] Between the layer on which transistor 3171a is formed and the layer on which transistor 3001 is formed Wiring 3100a and wiring 3100b are formed there. Wiring 3100a and Trans An insulating film 3140a is provided between the layer on which the sta 3001 is formed, and wiring 3100a An insulating film 3141a is provided between the wiring 3100b and the transient An insulating film 3142a is provided between the layer on which the star 3171a is formed and the other layer.

[0403] Similarly, the layer on which transistor 3171b is formed and the layer on which transistor 3171a is formed Wiring 3100c and wiring 3100d are formed between the layers. An insulating film 3140b is provided between the layer on which transistor 3171a is formed and An insulating film 3141b is provided between wire 3100c and wiring 3100d, and wiring 3100 An insulating film 3142b is provided between d and the layer on which transistor 3171b is formed. Yes, they are.

[0404] Insulating film 3140a, insulating film 3141a, insulating film 3142a, insulating film 3140b, insulating film 3 141b and insulating film 3142b function as interlayer insulating films, and their surfaces are planar. It can be done this way.

[0405] Wiring 3100a, wiring 3100b, wiring 3100c, and wiring 3100d are used to connect the memory It can perform electrical connections between circuits, as well as electrical connections between logic circuit 3004 and memory cells. ru.

[0406] The electrode 3303 included in the logic circuit 3004 is electrically connected to the circuit located above it. It is possible.

[0407] For example, as shown in Figure 20, electrode 3303 is connected to wiring 3100a by electrode 3505. It can be connected electrically. Wiring 3100a is connected by electrode 3503a, transistor The electrode 3501b, formed in the same layer as the gate electrode layer of 3171a, is electrically connected to the electrode 3501b. This can be done. In this way, the wiring 3100a and electrode 3303 are connected to the transistor 3171a. It can be electrically connected to the source or drain. Also, electrode 3501b is a trap The source or drain of the converter 3171a and the electrode 3502b connect to electrode 300 It can be electrically connected to 3b. Electrode 3003b is wired by electrode 3503b. It can be electrically connected to the 3100c.

[0408] In Figure 20, the electrical connection between electrode 3303 and transistor 3171a is via wiring 3100a. An example has been shown of this being done via electrode 3303 and transistor 317, but it is not limited to this. The electrical connection to 1a may be made via wiring 3100b, or wiring 3100a may be connected to This may be done via both wires 3100b, or via both wires 3100a and 3100b. This may also be done using other electrodes without the need for the intermediary.

[0409] Furthermore, in Figure 20, the layer on which transistor 3171a is formed and transistor 3001 are Between the formed layers, a wiring layer with wiring 3100a and wiring 3100b are formed. The diagram shows a configuration with two wiring layers, but is not limited to this. Between the layer on which transistor 3171a is formed and the layer on which transistor 3001 is formed, There may be one wiring layer, or there may be three or more wiring layers.

[0410] Furthermore, Figure 20 shows the layer on which transistor 3171b is formed, and transistor 3171a Between the layer in which the wiring 3100c is formed, there is a wiring layer in which the wiring 3100d is formed. The diagram shows a configuration with two wiring layers, but it is not limited to this. Between the layer on which transistor 3171b is formed and the layer on which transistor 3171a is formed There may be one wiring layer, or there may be three or more wiring layers. .

[0411] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0412] (Embodiment 7) In this embodiment, as an example of a semiconductor device, any one of the embodiments 2 to 4 described above is opened A CPU (Central Processor) that uses at least some of the transistors shown. This explains the ing Unit.

[0413] Figure 21(A) is a block diagram showing the specific configuration of the CPU. The PU is located on circuit board 1190, with ALU1191 (ALU: Arithmetic Logi c unit (arithmetic logic unit), ALU controller 1192, instruction deco -Dra 1193, interrupt controller 1194, timing controller 1195, Register 1196, Register Controller 1197, Bus Interface (Bus I / F)1198, rewritable ROM1199, and ROM interface (ROM It has I / F)1189. The substrate 1190 is a semiconductor substrate, an SOI substrate, a glass substrate A board or similar device is used. The ROM 1199 and ROM interface 1189 are located on separate chips. It is also acceptable to do so. Of course, the CPU shown in Figure 21(A) is just one example, with a simplified configuration. This is merely a generalization; actual CPUs have a wide variety of configurations depending on their intended use.

[0414] Instructions input to the CPU via the bus interface 1198 are instructions The signal is input to decoder 1193, decoded, and then processed by ALU controller 1192, interface Raptor controller 1194, register controller 1197, timing controller It is entered into 1195.

[0415] ALU controller 1192, interrupt controller 1194, register controller R1197 and timing controller 1195 control various commands based on the decoded instructions. To perform the operation. Specifically, the ALU controller 1192 controls the operation of the ALU 1191. It generates a signal for that purpose. Also, the interrupt controller 1194 is the CPU programmer. During execution, interrupt requests from external input / output devices and peripheral circuits are prioritized and masked. The state is judged and processed. The register controller 1197 adds register 1196 It generates a response and reads or writes to register 1196 depending on the CPU state.

[0416] Furthermore, the timing controller 1195 is connected to the ALU 1191 and the ALU controller 119 2. Instruction decoder 1193, interrupt controller 1194, and It generates a signal that controls the timing of the operation of the zista controller 1197. For example, The ming controller 1195 uses the reference clock signal CLK1 to generate the internal clock signal C It is equipped with an internal clock generation unit that generates LK2, and the internal clock signal CLK2 is used by the above-mentioned It supplies power to the seed circuit.

[0417] In the CPU shown in Figure 21(A), a memory cell is provided in register 1196. The memory cell of ZISTA 1196 is the memory cell disclosed in Embodiment 5 above. It is possible.

[0418] In the CPU shown in Figure 21(A), the register controller 1197 is ALU1191 Following the instructions, select a hold operation in register 1196. That is, register In the memory cell of the Ta1196, data is retained by a logic element that inverts logic. Choose whether to perform this operation or to retain data using capacitive elements. Logic element that inverts logic If data retention by the child is selected, the memory cell in register 1196 is charged. The source voltage is supplied. If data retention in the capacitive element is selected, the capacitive element Data is rewritten to the child, and power voltage is supplied to the memory cell in register 1196. It can be stopped.

[0419] Regarding power shutdown, as shown in Figure 21(B) or Figure 21(C), the memory cell group and A switching element is placed between nodes where the power supply potential VDD or power supply potential VSS is given. This can be done by providing the following circuit. The circuits in Figures 21(B) and 21(C) are described below. To do so.

[0420] Figures 21(B) and 21(C) show the switches that control the supply of power potential to the memory cells. The memory element includes a transistor disclosed in any one of the embodiments 2 to 4 described above. An example of a road configuration is shown.

[0421] The memory device shown in Figure 21(B) comprises a switching element 1141 and multiple memory cells 1142. It has a group of memory cells 1143. Specifically, each memory cell 1142 has: The memory cell described in Embodiment 5 can be used. Memory cell group 1143 Each memory cell 1142 in the device is connected to a high level via a switching element 1141. Power supply potential VDD is supplied. Furthermore, each memory cell of memory cell group 1143 1142 is supplied with the potential of signal IN and the potential of the low-level power supply potential VSS. .

[0422] In Figure 21(B), the switching element 1141 is any of the embodiments 2 to 4 described above. The transistor disclosed in one is used, and the gate electrode of the transistor is The switching is controlled by the signal SigA.

[0423] Note that in Figure 21(B), the switching element 1141 has only one transistor. The expression indicates a configuration, but is not particularly limited and may have multiple transistors. When element 1141 has multiple transistors that function as switching elements The above-mentioned transistors may be connected in parallel or in series. Furthermore, a combination of series and parallel connections is also acceptable.

[0424] Furthermore, in Figure 21(B), the memory cell group 1143 is connected by the switching element 1141. The supply of a high-level power potential VDD to each memory cell 1142 is controlled. The switching element 1141 controls the supply of a low-level power supply potential VSS. That's fine.

[0425] Furthermore, Figure 21(C) shows that each memory cell 1142 in the memory cell group 1143 has a sw A low-level power supply potential VSS is supplied via the switching element 1141, An example of the configuration is shown. The switching element 1141 switches each of the memory cells in the memory cell group 1143. The supply of a low-level power potential VSS to the Morisel 1142 can be controlled.

[0426] Between the memory cell group and the node to which the power supply potential VDD or power supply potential VSS is provided, When a switching element is installed, temporarily stopping the CPU's operation and cutting off the power supply voltage, It is possible to retain data even in this state, and power consumption can be reduced. Physically, for example, when a personal computer user interacts with an input device such as a keyboard... Even while inputting information is stopped, the CPU operation can be stopped, thereby eliminating It can reduce power consumption.

[0427] Here, we used the CPU as an example, but DSP (Digital Signal Processor) Processor), custom LSI, FPGA (Field Programmable) It can also be applied to LSIs such as e Gate Arrays.

[0428] This embodiment can be implemented in appropriate combination with the above embodiment.

[0429] (Embodiment 8) The semiconductor devices disclosed herein are applicable to a variety of electronic devices (including amusement machines). This is possible. Examples of electronic devices include televisions, monitors and other display devices, lighting devices, and desktop computers. Alternatively, a notebook personal computer, a word processor, or a DVD (Digital) Playback of still images or videos stored on recording media such as Versatile Disc. Image playback devices, portable CD players, radios, tape recorders, headphone stereos Stereo, cordless phone handset, transceiver, portable radio, mobile phone, car phone Portable game consoles, calculators, personal digital assistants, electronic organizers, e-books, electronic translators, voice input devices High-frequency heating devices such as appliances, video cameras, digital still cameras, electric shavers, and microwave ovens. Kitchen appliances, electric rice cookers, electric washing machines, electric vacuum cleaners, air conditioning equipment such as air conditioners, and tableware. Washing machines, dish dryers, clothes dryers, futon dryers, electric refrigerators, electric freezers, electric refrigerators and freezers Examples include storage units, DNA storage freezers, smoke detectors, radiation detectors, and medical equipment such as dialysis machines. Furthermore, guide lights, traffic lights, conveyor belts, elevators, escalators, industrial equipment Other examples include industrial equipment such as robots and power storage systems. Also, engines that use petroleum and Mobile devices propelled by electric motors using power from non-aqueous secondary batteries also fall under the category of electrical equipment. It shall be included in the category. As the above-mentioned mobile devices, for example, electric vehicles (EVs), internal combustion engines and Hybrid electric vehicles (HEVs) and plug-in hybrid electric vehicles (PHEVs) that also incorporate electric motors. , tracked vehicles that replace these tire wheels with tracks, and motorized vehicles including electric assist bicycles Bicycles, motorcycles, electric wheelchairs, golf carts, small or large vessels, submarines, helicopters Examples include drones, aircraft, rockets, satellites, space probes and planetary probes, and spacecraft. Specific examples of these electronic devices are shown in Figure 22.

[0430] Figure 22(A) shows table 9000 having a display unit. Table 9000 is, The display unit 9003 is incorporated into the housing 9001, and the display unit 9003 displays video. This is possible. Note that the configuration shown is one in which the housing 9001 is supported by four legs 9002. It also has a power cord 9005 for power supply attached to the casing 9001.

[0431] The transistor shown in any of Embodiments 1 to 3 can be used in the display unit 9003. This capability allows for high reliability in electronic devices.

[0432] The display unit 9003 has a touch input function, and the display unit 9003 of table 9000 By touching the displayed button 9004 with your finger, you can operate the screen or input information. This enables communication with or control of other home appliances, and the screen It may also be used as a control device to control other home appliances through operation. For example, an image sensor By using a semiconductor device with a sensor function, the display unit 9003 can be given a touch input function. It is possible.

[0433] Furthermore, a hinge provided on the housing 9001 allows the screen of the display unit 9003 to be lowered relative to the floor. It can stand upright and can also be used as a television set. In a small room, Installing a large-screen television set reduces the available space, but it can be placed on a table. If the display unit is built-in, the space in the room can be used more effectively.

[0434] Figure 22(B) shows a portable music player, the main unit 3021 having a display unit 3023 and earpieces. Mounting part 3022, speaker, operation button 3024, external memory slot 3025 etc. are provided. Transistors shown in any of Embodiments 1 to 3 are displayed. It can be used in part 3023. Transistors of Embodiments 2 to 4, or embodiments The memory shown in Form 5 is applied to the memory and CPU built into the main unit 3021. This allows for a more power-efficient portable music player.

[0435] Furthermore, the portable music player shown in Figure 22(B) has an antenna, microphone function, and wireless function. Furthermore, by linking it with a mobile phone, you can wirelessly use hands-free while driving a car or other vehicle. Conversation is also possible via [platform name].

[0436] Figure 22(C) shows a computer, consisting of a main unit 9201 including the CPU, a casing 9202, and a display unit. 9203, Keyboard 9204, External connection port 9205, Pointing device 92 Including 06, etc. A computer uses a transistor made using one aspect of the present invention. It is manufactured by using it in the display unit 9203. If the CPU shown in Embodiment 7 is used This makes it possible to create a power-saving computer.

[0437] Figures 23(A) and 23(B) show a foldable tablet device. Figure 23(A) The tablet terminal is in an open state, and consists of a housing 9630, a display unit 9631a, and a display unit 9631b, display mode switch 9034, power switch 9035, power saving mode It has a toggle switch 9036, a fastener 9033, and an operating switch 9038.

[0438] In portable devices such as those shown in Figures 23(A) and 23(B), temporary storage of image data SRAM or DRAM is used as memory in such devices. For example, Embodiment 5, Alternatively, the semiconductor device described in Embodiment 6 can be used as a memory. By employing the semiconductor device described in the form of implementation as a memory, information can be written and It offers high-speed reading, long-term data retention, and significantly reduced power consumption. Cut.

[0439] Furthermore, a portion of the display unit 9631a can be designated as a touch panel area 9632a. Data can be entered by touching the indicated operation key 9638. Embodiment 1 The transistors shown in any of the three to three are used in the display unit 9631a and the display unit 9631b. This is possible. Furthermore, in the display unit 9631a, for example, half of the area is for display only. The configuration shows one half having the function of a touch panel, and the other half has the function of a touch panel. The configuration is not limited to this. It is also possible to make it so that the entire surface of the display unit 9631a is covered with keyboard buttons for touch. The panel can be used, and the display unit 9631b can be used as a display screen.

[0440] Furthermore, in the display unit 9631b, similar to the display unit 9631a, a part of the display unit 9631b This can be designated as the touch panel area 9632b. Also, the touch panel keyboard... By touching the location where the display switch button 9639 is displayed with your finger or stylus, Keyboard buttons can be displayed on the display unit 9631b.

[0441] Furthermore, touch panel area 9632a and touch panel area 9632b can be touched simultaneously. You can also input text.

[0442] Additionally, the display mode switch 9034 switches the display orientation, such as portrait or landscape. You can switch between black and white and color displays. Power saving mode switch. The 9036 uses a built-in light sensor in the tablet device to detect ambient light during use. The display brightness can be optimized according to the amount of light. The tablet device uses a light sensor. In addition, it incorporates other detection devices such as gyroscopes, accelerometers, and other sensors that detect tilt. It's okay to store it.

[0443] Furthermore, Figure 23(A) shows an example where the display area of ​​display unit 9631b and display unit 9631a are the same. However, this is not particularly limited, and one size may be different from the other. The quality of these components may also differ. For example, one display panel may be capable of displaying higher resolution than the other. That is also acceptable.

[0444] Figure 23(B) shows the closed state, and the tablet terminal consists of a housing 9630 and a solar cell 96 33. Includes a charge / discharge control circuit 9634, a battery 9635, and a DC-DC converter 9636. In addition, Figure 23(B) shows an example of the charge / discharge control circuit 9634, specifically the battery 9635. This shows a configuration that includes a DC-DC converter 9636.

[0445] Since the tablet device is foldable, the casing 9630 can be closed when not in use. Therefore, the display units 9631a and 9631b can be protected, thus providing durability. We can provide tablet devices that are highly durable and reliable from the perspective of long-term use.

[0446] In addition, the tablet devices shown in Figures 23(A) and 23(B) can also be used for various purposes. Features for displaying information (still images, videos, text images, etc.), calendar, date or time, etc. A function to display information on the display unit, and a touch input function to perform touch input operations or edit the information displayed on the display unit. It has functions such as power control and the ability to control processing by various software (programs). It is possible.

[0447] The solar cell 9633 mounted on the surface of the tablet device powers the touch panel. It can be supplied to the display unit or the video signal processing unit, etc. Note that the solar cell 9633 is housed in a casing. It can be provided on one or both sides of the body 9630, and efficiently charges the battery 9635. This configuration is possible. Note that the battery 9635 uses a lithium-ion battery. Having it offers advantages such as enabling miniaturization.

[0448] Furthermore, the configuration and operation of the charge / discharge control circuit 9634 shown in Figure 23(B) are shown in Figure 23(C). The block diagram is shown and explained in Figure 23(C). The solar cell 9633 and battery 96 35. DC-DC converter 9636, converter 9637, switch SW1 to SW3, The display unit 9631 is shown, along with the battery 9635 and the DC-DC converter 9636. The converter 9637 and switches SW1 to SW3 control the charge / discharge cycle shown in Figure 23(B). This corresponds to the section of road 9634.

[0449] First, let's explain an example of operation when electricity is generated by the solar cell 9633 using ambient light. The electricity generated by the solar panel is converted to a DCD (Digital-to-Collar) voltage to charge the 9635 battery. The C converter 9636 performs either a boost or a buck. Then, the display unit 9631 operates in accordance with the solar power. When power from battery 9633 is used, switch SW1 is turned ON, and converter 96 At step 37, the voltage is increased or decreased to the voltage required for the display unit 9631. Also, the display unit 96 If you do not want to display on 31, turn SW1 off and SW2 on and set the battery 96 A configuration that allows for 35 charges would be appropriate.

[0450] The solar cell 9633 is shown as an example of a power generation method, but it is not particularly limited to this method. Other power generation methods such as electrical elements (piezo elements) and thermoelectric elements (Peltier elements) The configuration may also include charging the Terry 9635. For example, power can be transmitted and received wirelessly (contactlessly). A contactless power transmission module that charges via communication, or a configuration that combines it with other charging methods. That is also acceptable.

[0451] In Figure 24(A), the television device 8000 has a display unit 8002 in the housing 8001. It is integrated, with the display unit 8002 displaying video and the speaker unit 8003 outputting audio. It is possible to output using the transistor shown in any of Embodiments 1 to 4. It can be used in the display unit 8002.

[0452] The display unit 8002 is a light-emitting device equipped with light-emitting elements such as liquid crystal display devices and organic EL elements in each pixel. Electrophoresis display device, DMD (Digital Micromirror Display) e) Semiconductor display devices such as PDPs (Plasma Display Panels) It can be used.

[0453] The television equipment 8000 may include a receiver, modem, etc. The Oki 8000 can receive general television broadcasts using a receiver, and also has a modem. By connecting to a wired or wireless communication network via this, one-way communication (from the sender to...) The recipient (or the two-way communication between the sender and receiver, or between receivers) communicates information. It is also possible.

[0454] Furthermore, the television equipment 8000 is equipped with a CPU and memory for information communication. The television device 8000 may have a memory as shown in any of embodiments 5 to 7 or It is possible to use the CPU.

[0455] In Figure 24(A), an air conditioner having an indoor unit 8200 and an outdoor unit 8204 - is an example of an electronic device using the CPU of Embodiment 7. Specifically, the indoor unit 8200 It has a housing 8201, an air outlet 8202, a CPU 8203, etc. In Figure 24(A) The example shows the case where CPU8203 is located in the indoor unit 8200, but CPU8 203 may be provided on the outdoor unit 8204. Alternatively, the indoor unit 8200 and the outdoor unit 82 A CPU 8203 may be provided in both of 04. The CPU shown in Embodiment 7 is Because it is a CPU that uses oxide semiconductors, it has excellent heat resistance and is a highly reliable air conditioner. It can be used as a conditioner.

[0456] In Figure 24(A), the electric refrigerator-freezer 8300 is equipped with a CPU using an oxide semiconductor. This is an example of an electronic device. Specifically, the electric refrigerator 8300 consists of a casing 8301 and a refrigerator compartment. It has a door 8302 for the main compartment, a door 8303 for the freezer compartment, a CPU 8304, etc. In Figure 24(A), C The PU8304 is located inside the chassis 8301. The CPU shown in Embodiment 7 By using it in the CPU 8304 of the electric refrigerator / freezer 8300, power savings can be achieved.

[0457] Figure 24(B) shows an example of an electronic device, specifically an electric vehicle. Electric vehicle 970 Unit 0 is equipped with a secondary battery 9701. The power of the secondary battery 9701 is supplied to the control circuit 97 The output is adjusted by 02 and supplied to the drive unit 9703. The control circuit 9702 is shown in Figure It is controlled by a processing unit 9704 having ROM, RAM, CPU, etc. (not shown). By using the CPU shown in form 7 as the CPU for the electric vehicle 9700, power saving can be achieved. It can be measured.

[0458] The drive unit 9703 consists of a DC motor or an AC motor alone, or a motor and an internal combustion engine. It is composed of a combination of components. The processing unit 9704 receives the driver's operation information of the electric vehicle 9700. (Acceleration, deceleration, stopping, etc.) and driving information (information such as uphill and downhill slopes, and the load on the drive wheels) Based on input information (such as cargo information), a control signal is output to the control circuit 9702. 702 receives an electrical signal from the secondary battery 9701 via a control signal from the processing unit 9704. The energy is adjusted to control the output of the drive unit 9703. (When an AC motor is installed) Although not shown in the diagram, it also incorporates an inverter that converts direct current to alternating current.

[0459] This embodiment can be implemented in appropriate combination with other embodiments. [Explanation of symbols]

[0460] 1 Gate layer 2 Gate insulating layer 3. Oxide semiconductor layer 4. Source electrode layer 5. Drain electrode layer 6. Etching stop layer 7 areas 8 areas 100 circuit boards 106 element isolation insulating layer 108 gate insulating film 110 Guard Station 116 Channel formation region 120 Impurity region 124 Intermetallic compound area 128 Insulating layer 130 Insulating layer 142a Electrode layer 142b Electrode layer 144 Oxide semiconductor layer 146 Gate insulating film 148a Token 148b Conductive layer 150 Insulating layer 152 Insulating layer 156 Wiring 160 transistors 162 transistors 164 Capacitive elements 185 circuit boards 400 circuit boards 401 Guard Layer 402 Gate Insulator 403 Oxide semiconductor film 404a Low resistance area 404b Low resistance region 405a Source electrode layer 405b Drain electrode layer 406 Insulating film 407 Insulating film 409 Channel formation region 410 transistors 413 Insulating film 414a Sidewall insulation layer 414b Sidewall insulation layer 415 Interlayer insulating film 417a insulating film 417b insulating film 420 transistors 436 Underlayment Insulation Layer 440a transistor 440b transistor 440c transistor 440d transistor 440e Transistor 440f transistor 440g transistor 442 Gate insulating film 445a Amorphous region 445b Amorphous region 448 insulating film 450 capacitance wiring 451 capacity 500 circuit boards 502 Gate Insulation Layer 504 Interlayer insulating layer 505 Color Filter Layer 506 Insulating layer 507 Bulkhead 510 transistors 511 Gate Layer 512 Oxide semiconductor layer 513a conductive layer 513b Conductive layer 520 Capacitive elements 521 Conductive layer 522 Oxide semiconductor layer 523 Conductive layer 530 Wiring layer intersection 533 Conductive layer 540 light-emitting elements 541 Electrode layer 542 Electroluminescent layer 543 Electrode layer 601 circuit board 602 Photodiode 606a Semiconductor film 606b Semiconductor film 606c semiconductor film 608 Adhesive layer 613 circuit board 622 light 631 Insulating layer 633 Interlayer insulating layer 634 Interlayer insulating layer 640 transistors 641a Electrode layer 641b Electrode layer 642 Electrode layer 643 Conductive layer 645 Conductive layer 656 transistors 658 Photodiode reset signal line 659 Gate signal line 671 Photosensor output signal line 672 Photosensor Reference Signal Line 1141 Switching element 1142 memory cells 1143 memory cell group 1189 ROM Interface 1190 circuit board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM 3000 circuit boards 3001 Transistor 3003a electrode 3003b electrode 3003c electrode 3004 Logic Circuits 3021 Main Unit 3022 Fixed part 3023 Display section 3024 Operation Buttons 3025 External memory slot 3100a wiring 3100b wiring 3100c wiring 3100d wiring 3106 Element isolation insulating layer 3140a insulating film 3140b insulating film 3141a Insulating film 3141b insulating film 3142a Insulating film 3142b insulating film 3170a memory cell 3170b memory cell 3171a Transistor 3171b Transistor 3200 transistors 3202 Transistor 3204 Capacitive element 3208 Electrode 3210a conductive layer 3210b conductive layer 3212 Electrode 3214 Electrode 3216 Wiring 3220 Insulating layer 3222 Insulating layer 3224 Insulating layer 3303 Electrode 3400a Memory Cell Array 3400b memory cell array 3400n memory cell array 3501a electrode 3501b electrode 3501c electrode 3502a electrode 3502b electrode 3502c electrode 3503a electrode 3503b electrode 3505 Electrode 4001 circuit board 4002 pixel section 4003 Signal Line Drive Circuit 4004 Scan Line Drive Circuit 4005 Sealant 4006 circuit board 4008 Liquid Crystal Layer 4010 Transistor 4011 Transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4018a FPC(Flexible printed circuit) 4018b FPC(Flexible printed circuit) 4019 Anisotropic conductive layer 4020 Insulating layer 4021 Insulating layer 4030 Electrode layer 4031 Electrode layer 4032 Insulating layer 4033 Insulating layer 4035 Spacer 4510 Bulkhead 4511 Electroluminescent layer 4513 Light-emitting element 4514 Filling material 8000 Television equipment 8001 enclosure 8002 Display section 8003 Speaker section 8200 indoor unit 8201 enclosure 8202 Air outlet 8203 CPU 8204 Outdoor unit 8300 Electric Refrigerator / Freezer 8301 enclosure 8302 Refrigerator door 8303 Freezer door 8304 CPU 9000 Table 9001 enclosure 9002 Legs 9003 Display section 9004 Display button 9005 Power Cord 9033 Fastener 9034 Switch 9035 Power switch 9036 Switch 9038 Operation switch 9201 Main Unit 9202 enclosure 9203 Display section 9204 Keyboard 9205 External connection port 9206 Pointing device 9630 cabinet 9631 Display section 9631a Display section 9631b Display section 9632a area 9632b area 9633 Solar Cell 9634 Charge / Discharge Control Circuit 9635 Battery 9636 DC-DC converter 9637 Converter 9638 Operation Keys 9639 button 9700 Electric Vehicles 9701 Secondary battery 9702 control circuit 9703 Drive unit 9704 Processing Unit

Claims

[Claim 1] Gate layer and A gate insulating layer provided on the gate layer, An oxide semiconductor layer provided on the gate insulating layer, A source electrode layer and a drain electrode layer are provided in a region on the oxide semiconductor layer that is isolated from each other, The region on the oxide semiconductor layer includes an etching stop layer provided in the region between the source electrode layer and the drain electrode layer, A transistor in which the proportion of crystalline regions in a first region overlapping the interface with the etching stop layer of the oxide semiconductor layer is higher than the proportion of crystalline regions in a second region overlapping the interface with the source electrode layer or the drain electrode layer.

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