Memory system, memory controller, and control method

Abstract

Perform error correction with higher accuracy. [Solution] The memory system comprises a non-volatile memory and a memory controller. The memory controller performs an iterative process that includes obtaining first likelihood information corresponding to a first read information using correspondence information between multiple read information and multiple likelihood information, and obtaining posterior likelihood information using the first likelihood information, until a first or second termination condition is met. If the first termination condition is met, the memory controller performs preprocessing for updating the correspondence information, and after performing the preprocessing or if the second termination condition is met, it performs the update process using the posterior likelihood information obtained in the iterative process. The first termination condition indicates that decoding has stalled since the previous soft-decision decoding and that the number of soft-decision decoding iterations is equal to or greater than a first threshold. The second termination condition indicates that the number of iterations has reached the maximum value.

Description

Technical Field

[0001] The following embodiments relate to a memory system, a memory controller, and a control method.

Background Art

[0002] In a memory system, in order to protect data stored in a memory such as a NAND-type flash memory, error-corrected encoded data is stored in the memory. Therefore, when reading the data stored in the memory, the error-corrected encoded data (also referred to as the received word) read from the memory is decoded to restore the data before error-corrected encoding.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] An embodiment of the present invention aims to provide a memory system, a memory controller, and a control method capable of performing error correction (decoding) with higher accuracy.

Means for Solving the Problems

[0005] The memory system of the embodiment comprises a non-volatile memory and a memory controller. The memory controller performs an iterative process that includes soft-decision decoding, which involves using correspondence information between multiple read information and multiple likelihood information to obtain first likelihood information corresponding to a first read information, and then using the first likelihood information to obtain posterior likelihood information, until a first or second termination condition is met. If the first termination condition is met, the memory controller performs preprocessing for updating the correspondence information, and after performing the preprocessing or if the second termination condition is met, it performs the update process using the posterior likelihood information obtained in the iterative process. The first termination condition indicates that decoding has stalled since the previous soft-decision decoding and that the number of soft-decision decoding iterations is equal to or greater than a first threshold. The second termination condition indicates that the number of iterations has reached the maximum value. [Brief explanation of the drawing]

[0006] [Figure 1] A block diagram of the memory system according to the first embodiment. [Figure 2] A diagram illustrating examples of external and internal codes. [Figure 3] A diagram illustrating an example of code construction. [Figure 4] Block diagram of the decoder according to the first embodiment. [Figure 5] A flowchart of the decoding process in the first embodiment. [Figure 6] A flowchart of the determination process in the first embodiment. [Figure 7] A diagram showing an example of the decoding process according to the first embodiment. [Figure 8] Flowchart of the determination process in the second embodiment. [Figure 9] A diagram showing an example of the decoding process according to the second embodiment. [Modes for carrying out the invention]

[0007] The memory system according to the embodiment will be described in detail below with reference to the attached drawings. However, the present invention is not limited to the following embodiments.

[0008] (First Embodiment) Figure 1 is a block diagram showing a schematic configuration example of a memory system according to the first embodiment. As shown in Figure 1, the memory system 1 comprises a memory controller 10 and a non-volatile memory 20. The memory system 1 is connectable to a host 30, and Figure 1 shows the system connected to the host 30. The host 30 may be, for example, an electronic device such as a personal computer or a mobile terminal.

[0009] The non-volatile memory 20 is a non-volatile memory that stores data in a non-volatile manner, such as NAND memory. In the following description, the case in which NAND memory is used as the non-volatile memory 20 is given as an example, but it is also possible to use storage devices other than NAND memory, such as 3D structured flash memory, ReRAM (Resistance Random Access Memory), and FeRAM (Ferroelectric Random Access Memory), as the non-volatile memory 20. Furthermore, it is not essential that the non-volatile memory 20 is a semiconductor memory, and this embodiment can also be applied to various storage media other than semiconductor memory.

[0010] The memory system 1 may be a memory card or the like, in which the memory controller 10 and non-volatile memory 20 are configured as a single package, or it may be an SSD (Solid State Drive) or the like.

[0011] The memory controller 10 controls writing to the non-volatile memory 20 in accordance with write requests from the host 30. The memory controller 10 also controls reading from the non-volatile memory 20 in accordance with read requests from the host 30. The memory controller 10 comprises a host interface (host I / F) 15, a memory interface (memory I / F) 13, a control unit 11, an encoding / decoding unit (codec) 14, and a data buffer 12. The host interface 15, memory interface 13, control unit 11, encoding / decoding unit 14, and data buffer 12 are interconnected by an internal bus 16. Some or all of the operation of each component of the memory controller 10 may be implemented by the CPU (Central Processing Unit) executing firmware, or by hardware.

[0012] The host I / F 15 is a circuit that performs processing according to the interface standard with the host 30 and outputs commands received from the host 30, user data to be written, etc., to the internal bus 16. The host I / F 15 also transmits user data read and restored from the non-volatile memory 20, responses from the control unit 11, etc., to the host 30.

[0013] The memory interface 13 is a circuit that performs write operations to the non-volatile memory 20 based on instructions from the control unit 11. The memory interface 13 also performs read operations from the non-volatile memory 20 based on instructions from the control unit 11.

[0014] The control unit 11 comprehensively controls each component of the memory system 1. When the control unit 11 receives an instruction from the host 30 via the host interface 15, it performs control according to that instruction. For example, the control unit 11 instructs the memory interface 13 to write user data and parity to the non-volatile memory 20 according to an instruction from the host 30. The control unit 11 also instructs the memory interface 13 to read user data and parity from the non-volatile memory 20 according to an instruction from the host 30.

[0015] Also, when the control unit 11 receives a write request for user data from the host 30, it accumulates the user data in the data buffer 12 and determines the storage area (memory area) in the non-volatile memory 20 for the user data. That is, the control unit 11 manages the write destination of the user data. The correspondence between the logical address of the user data received from the host 30 and the physical address indicating the storage area on the non-volatile memory 20 where the user data is stored is stored as an address translation table.

[0016] Also, when the control unit 11 receives a read request from the host 30, it converts the logical address specified by the read request into a physical address using the above address translation table, and instructs the memory I / F 13 to perform a read from the physical address.

[0017] In a NAND memory, generally, writing and reading are performed in a data unit called a page, and erasing is performed in a data unit called a block. In the present embodiment, a plurality of memory cells connected to the same word line are called a memory cell group. When the memory cell is a single-level cell (SLC), one memory cell group corresponds to one page. When the memory cell is a multi-level cell (MLC), one memory cell group corresponds to a plurality of pages. Also, each memory cell is connected to a word line and also to a bit line. Therefore, each memory cell can be identified by an address identifying the word line and an address identifying the bit line.

[0018] The data buffer 12 temporarily stores the user data received by the memory controller 10 from the host 30 until it is stored in the non-volatile memory 20. Also, the data buffer 12 temporarily stores the user data read from the non-volatile memory 20 until it is transmitted to the host 30. For the data buffer 12, for example, a general-purpose memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory) can be used.

[0019] User data transmitted from host 30 is transferred to internal bus 16 and temporarily stored in data buffer 12. The encoding / decoding unit 14 encodes the user data to generate codewords. The encoding / decoding unit 14 also decodes the received codewords, which are data read from non-volatile memory 20, to restore the user data. Therefore, the encoding / decoding unit 14 comprises an encoder 17 and a decoder 18. In addition to user data, the data encoded by the encoding / decoding unit 14 may also include control data used internally by the memory controller 10, etc.

[0020] Next, the writing process of this embodiment will be described. When writing user data to the non-volatile memory 20, the control unit 11 instructs the encoder 17 to encode the user data. At that time, the control unit 11 determines the storage location (storage address) of the codeword in the non-volatile memory 20 and also instructs the memory I / F 13 of the determined storage location.

[0021] The encoder 17 encodes user data on the data buffer 12 and generates a codeword based on instructions from the control unit 11. The encoding scheme can include, for example, algebraic coding schemes such as BCH (Bose-Chaudhuri-Hocquenghem) coding and RS (Reed-Solomon) coding, as well as coding schemes that use these codes as row and column component codes (such as product coding). The memory interface 13 controls the storage of the codeword in a storage location on the non-volatile memory 20 as instructed by the control unit 11.

[0022] Next, the process for reading from the non-volatile memory 20 in this embodiment will be described. When reading from the non-volatile memory 20, the control unit 11 specifies an address on the non-volatile memory 20 and instructs the memory interface 13 to read. The control unit 11 also instructs the decoder 18 to start decoding. The memory interface 13 reads data from the specified address on the non-volatile memory 20 according to the instructions of the control unit 11 and inputs the read data as a received word to the decoder 18. The decoder 18 decodes this received word, which is the data read from the non-volatile memory 20.

[0023] Next, the error correction code (codeword) used in this embodiment will be described. In this embodiment, the encoder 17 generates a concatenated code as the error correction code. The concatenated code is a code consisting of, for example, an error correction code C1 (first error correction code) generated using data (user data) stored in the non-volatile memory 20, and an error correction code C2 (second error correction code) generated using the error correction code C1. Hereinafter, the error correction code C1 will be referred to as the outer code, and the error correction code C2 will be referred to as the inner code.

[0024] The outer code is used to remove residual errors that could not be corrected by error correction using the inner code. The outer code can be, for example, a 4-bit correctable BCH code. Since erroneous correction may occur during decoding (residual error removal) using the outer code, a determination process may be performed to determine whether or not erroneous correction has occurred. The inner code can be, for example, a multidimensional error correction code.

[0025] Here, a multidimensional error correction code refers to one in which at least one of the constituent units of an error correction code, a symbol, is protected multiple times by several smaller component codes. Furthermore, one symbol consists of, for example, one bit (an element of a binary field) or an element of an alphabet, such as a finite field other than a binary field. For the sake of simplicity, the following explanation will use a binary error correction code in which one symbol consists of one bit as an example. In the explanation, there may be instances where symbols and bits appear interchangeably, but both represent the same meaning.

[0026] An example of a multidimensional error correction code is the product code. In a product code, for example, each information symbol, which is the constituent unit of user data, is protected by a BCH code containing a parity symbol of a predetermined parity length in both the row and column directions. That is, in a product code, all symbols are doubly protected by component codes in the row direction (referred to as dimension 1) and the column direction (referred to as dimension 2). Note that multidimensional error correction codes are not limited to this, and may also include, for example, a Generalized Low Density Parity Check Code (LDPC code). In general multidimensional error correction codes, including generalized LDPC codes, the degree of protection may differ for each symbol, and component codes cannot be grouped into dimensions 1 and 2, but this technology can also be applied to such code configurations.

[0027] For simplicity, the following example describes a two-dimensional error correction code (product code) in which each symbol is protected by two component codes that can be grouped into Dimension 1 and Dimension 2. Each component code in each dimension contains one or more component codes defined for that dimension. In the following, a group of component codes corresponding to each dimension that contains one or more component codes may be referred to as a component code group. For example, a component code group of Dimension 1 contains n1 component codes, and a component code group of Dimension 2 contains n2 component codes. The applicable error correction codes are not limited to these, and may also be N-dimensional error correction codes in which at least one symbol among the symbols that make up the code is protected by N component code groups (where N is an integer greater than or equal to 2). When expressed in terms of the number of component codes contained in each component code group, an N-dimensional error correction code is protected by M component codes (where M is the sum of ni (1 ≤ i ≤ N), N is an integer greater than or equal to 2, and ni is the number of component codes in the i-th dimension).

[0028] Examples of outer and inner codes will be explained using Figure 2. Figure 2 shows an example where a two-dimensional block product code containing five blocks in the row direction and six blocks in the column direction is used as the inner code. Each block contains multiple symbols that constitute the code. Each block corresponds to a set of symbols, which is a collection of multiple symbols that make up the code. The number of blocks in each direction is not limited to the example shown in Figure 2. For example, in the following figures, a two-dimensional block product code containing four blocks each in the row and column directions may be explained as the inner code.

[0029] As shown in Figure 2, the encoder 17 first encodes the user data 210 into an outer code 220. The outer code 220 includes the user data 210 and an outer code parity 221. Next, the encoder 17 encodes the outer code 220 into an inner code 230. The inner code 230 includes the outer code 220, a row-direction parity 231 of the inner code, and a column-direction parity 232 of the inner code.

[0030] The internal code is, for example, a two-dimensional block product code whose component codes are 3-bit correctable BCH codes. In the example in Figure 2, the five component codes in the row direction (dimension 1) and the six component codes in the column direction (dimension 2) are each 3-bit correctable BCH codes.

[0031] External codes can be interpreted as primarily serving the following roles: • Removal of errors that cannot be corrected by internal symbols (residual errors) • Check if there are any errors remaining in the user data: If no errors remain, the process will terminate, indicating that decryption was successful.

[0032] The concatenated code shown in Figure 2 can be decoded, for example, as follows. (A1) Decoding using an internal code (product code) is performed. In product code decoding, hard-decision decoding, which has low correction capability but is fast, is performed first. Hard-decision decoding is decoding using hard-decision value data, which is binary data of 0 or 1, read from the non-volatile memory 20. Hereafter, the hard-decision value data will be called hard bit data (HB data), and hard-decision decoding will sometimes be called HB decoding. (A2) If HB decoding fails, soft-decision decoding, which is slower but has higher correction capabilities than HB decoding, is performed. Soft-decision decoding is a decoding method that uses likelihood information (such as the log-likelihood ratio) that represents the probability of being 0 or 1. In the following, soft-decision decoding may be referred to as SB (soft bit) decoding. (A3) If decoding using the inner code fails, decoding using the outer code is performed.

[0033] Since the inner code is a product code, decoding of the component codes in the row direction (dimension 1) and the component codes in the column direction (dimension 2) may be performed repeatedly.

[0034] The concatenated codes, consisting of internal and external codes, may be further protected by other codes. Figure 3 shows an example of a configuration in which multiple concatenated codes are protected by RS codes.

[0035] RS frame 301 corresponds to a frame in which multiple symbols are encoded using RS coding. When multiple RS frames are arranged horizontally, a concatenated code frame (concatenated code frame) is obtained by encoding the symbols in the corresponding rows of each RS frame using concatenated coding. Concatenated code frame 302 is an example of such a frame. The number of concatenated code frames (number of rows) is not limited, but is typically around 70 to 140.

[0036] The code shown in Figure 3 can be decoded, for example, as follows. (B1) Each connected code frame is decoded. (B2) If decoding of a concatenated code frame fails, all concatenated code frames are decoded in order to decode them using RS coding. (B3) Using the information obtained from decoding multiple concatenated code frames and the RS code, the concatenated code frame that failed to decode is re-decoded. (B4) Re-decoding is repeatedly performed until the concatenated code frame that failed to decode is successfully decoded.

[0037] As explained in Figure 2, SB decoding may be performed repeatedly for a single concatenated code frame. Furthermore, in a configuration where re-decoding of multiple concatenated code frames is repeated, as shown in Figure 3, the number of SB decoding executions may increase even further. In other words, the overall latency of the decoding process may increase. Therefore, in order to reduce latency, it is desirable to have a function (hereinafter referred to as the termination function) that terminates processing midway without repeating SB decoding for frames that fail to decode.

[0038] On the other hand, the decryption process may be configured so that a function to improve the performance of SB decryption (hereinafter referred to as the performance improvement function) is executed each time SB decryption is repeated. For such configurations, it is desirable to incorporate a termination function so that the effects of the performance improvement function are not suppressed.

[0039] The memory system 1 of this embodiment can reduce latency while suppressing performance degradation of error correction (decoding). For example, the memory system 1 implements a truncation function so as not to truncate when the number of SB decoding iterations is small. Furthermore, when the memory system 1 does truncate, it performs the necessary preprocessing for the performance improvement function before truncating.

[0040] Next, an example of the configuration of the decoder 18 in this embodiment will be described. Figure 4 is a block diagram showing a schematic configuration example of the decoder 18 in the first embodiment. As shown in Figure 4, the decoder 18 includes a read information memory 121, an SB decoder 101, an HB decoder 102, a determination unit 103, and an update unit 104.

[0041] The read information memory 121 is implemented, for example, by SRAM. The SB decoder 101, HB decoder 102, determination unit 103, and update unit 104 are implemented by at least one of registers, adders, multipliers, and other arithmetic units. The registers are implemented, for example, by logic circuits such as flip-flops. The adders, multipliers, selectors, and other arithmetic units are implemented, for example, by logic circuits.

[0042] The read information memory 121 is a memory that stores read information, which is data read from the non-volatile memory 20.

[0043] Of the read information, the data corresponding to the hard decision value, which is binary information determining whether each bit is 0 or 1, corresponds to the hard bit data mentioned above. The data corresponding to the portion of the read information excluding the hard bit data is sometimes called soft bit data.

[0044] The decoding process may require data called channel values. Channel values ​​represent the log-likelihood ratio (LLR) corresponding to a pair of hard bit data and soft bit data. Channel values ​​are sometimes referred to as channel LLR data. Channel values ​​are determined, for example, by an LLR table that associates a pair of hard bit data and soft bit data with the channel value. A channel value is an example of a soft decision input value based on soft decision read information read from non-volatile memory 20. The LLR table corresponds to correspondence information that associates multiple read information (pairs of hard bit data and soft bit data) with multiple likelihood information (log-likelihood ratios).

[0045] For example, in a soft-bit read operation, one hard bit data and multiple soft bit data are obtained. The one hard bit data is obtained using the same read voltage (hereinafter referred to as VrH) as the read voltage used in a hard-bit read operation. The multiple soft bit data are obtained using multiple read voltages, including read voltages smaller than VrH and read voltages larger than VrH. The LLR table is a table that associates channel values ​​with each pair of one hard bit data and multiple soft bit data.

[0046] The SB decoder 101 performs SB decoding (soft-decision decoding) using the read information. For example, the SB decoder 101 uses an LLR table to determine the corresponding channel value from one hard bit data and multiple soft bit data included in the read information. The SB decoder 101 performs decoding with the channel value as input and outputs a soft-decision value (soft-decision output value) as a result. The soft-decision output value is, for example, a value that expresses the probability information of whether each bit is 0 or 1 in the form of LLR, and is sometimes called a posterior value (posterior value LLR).

[0047] Thus, SB decoding includes the process of determining the channel value (first likelihood information) corresponding to the read information (first read information) for each of the multiple bits contained in the read information (first read information) read from the non-volatile memory 20, using the LLR table (correspondence information), and then determining the posterior LLR (posterior likelihood information) using the channel value.

[0048] In this embodiment, SB decoding may be repeated as shown in the product code in Figure 2. That is, the SB decoder 101 repeatedly performs SB decoding until the termination condition is met. The process of repeating (iterating) SB decoding may be referred to as iterative processing below.

[0049] The HB decoder 102 performs HB decoding (hard-bit decoding) using the read information. For example, the HB decoder 102 takes hard bit data as input and performs decoding, and outputs a hard-bit value as a result.

[0050] The HB decoder 102 performs HB decoding as a decoding method to be executed before SB decoding of the product code, for example, as in (A1) above. The HB decoder 102 also performs HB decoding to determine whether SB decoding was successful.

[0051] The determination unit 103 determines whether or not the termination conditions for the iterative process are met. The termination conditions include, for example, the following termination conditions CA (first termination condition) and CB (second termination condition). • Termination condition CA: A condition indicating that, among the multiple SB decodings repeatedly performed within the iteration process, the value of the indicator showing the progress of decoding has stagnated compared to the previous SB decoding, and the number of SB decoding iterations is equal to or greater than the threshold THA (first threshold). • Termination condition CB: A condition indicating that the number of repetitions has reached the maximum value.

[0052] The indicator used in the termination condition CA is, for example, the total number of bits in which the post-value LLR is greater than or equal to the threshold THB (second threshold). This total number is sometimes called MaxLLRCount. MaxLLRCount is a value calculated, for example, as shown in equation (1) below. Note that #{} represents the number of elements within {}. MaxLLRCount= #{|Post-value LLR|≧Thresholding bit THB} ···(1)

[0053] As described above, the posterior value LLR represents the probability that the bit in question was originally either 0 or 1, and is an inferred value obtained through the decoding process. Therefore, a large absolute value of the posterior value LLR indicates a high level of confidence in the decoding result. Furthermore, the condition that the absolute value of the posterior value LLR is greater than or equal to the threshold THB indicates that decoding is progressing smoothly. Thus, MaxLLRCount can be interpreted as representing the total number of bits for which decoding is progressing smoothly. MaxLLRCount is expected to increase monotonically with decoding. On the other hand, a stagnation in the value of MaxLLRCount can be interpreted as meaning that the decoding of the frame being decoded is stalled (i.e., it is a frame that fails to decode).

[0054] Note that a stagnation in the MaxLLRCount value means, for example, that the increase in MaxLLRCount has stagnated. A stagnation in the increase of MaxLLRCount means, for example, that the amount of increase in MaxLLRCount is below the threshold THC (third threshold), or that MaxLLRCount is decreasing.

[0055] The termination condition CA can be interpreted as a condition for realizing the termination function described above. That is, the termination condition CA includes the fact that decoding is stalled as part of the termination conditions. In this embodiment, the termination condition CA further includes the fact that the number of SB decoding iterations is equal to or greater than the threshold THA (first threshold) as part of the termination conditions. This condition corresponds to a condition to prevent the effect of performance improvement by the performance improvement function from being suppressed.

[0056] The update unit 104 performs an update process to update the LLR table. The update process involves, for example, using the decoding results (posterior LLR values) obtained by the iterative SB decoding process to estimate an LLR table that better fits the channel, and updating the LLR table used in subsequent SB decoding with the estimated LLR table. The process of estimating the LLR table may be implemented using any conventional method.

[0057] The update process performed by the update unit 104 corresponds to the performance improvement function described above. Note that the performance improvement function is not limited to the LLR table update process; it may be any other function that improves the performance of SB decoding.

[0058] Suppose that when the LLR table update process is executed as a performance improvement function, the system is configured to simply terminate processing midway for frames that fail to decode under subframes. In such a configuration (comparative example), the estimation accuracy of the LLR table may decrease and decoding performance may not improve due to the following reasons. (C1) If censorship occurs when the number of iterations is small, the reliability of the data used to estimate the LLR table will be reduced. (C2) The following processes, which are performed in the later stages of the iteration to improve the estimation accuracy of the LLR table, are not executed due to termination. • Change the index in the log-prior probability ratio table. • Hard-determination decoding with better decoding performance

[0059] Therefore, this embodiment includes the following functions (D1) and (D2) to suppress the decrease in estimation accuracy of the LLR table that may occur due to the above-mentioned causes. (D1) If the number of iterations is too small, set a threshold for the number of iterations to prevent the termination function from being executed. If the number of iterations is less than the threshold, termination will not be performed. (D2) If termination is performed, the preprocessing necessary to improve the estimation accuracy of the LLR table, which is performed in the latter half of the iteration process, is completed before the iteration process is terminated.

[0060] For example, function (D1) is implemented by using the condition included in the termination condition CA above, which indicates that the number of iterations is greater than or equal to the threshold THA. In function (D2), the processing to be performed in the latter half of the iteration process, as described in (C2) above, is performed as preprocessing. For example, if the termination condition CA is met, preprocessing necessary to improve the accuracy of the update process is performed. Preprocessing is performed, for example, by at least one of the SB decoder 101 and the HB decoder 102.

[0061] If the iterative process is terminated by termination condition CA, the update unit 104 executes the update process after the preprocessing is performed. If the iterative process is terminated by termination condition CB, processing equivalent to preprocessing is performed in the latter half of the iterative process. Therefore, if termination condition CB is met, the update unit 104 executes the update process without performing preprocessing separately from the iterative process.

[0062] After the update process is performed, the decoder 18 performs further iteration using the updated LLR table. Using the updated LLR table increases the likelihood of successful decoding.

[0063] Next, the flow of the decoding process by the memory system 1 of this embodiment will be described. Figure 5 is a flowchart showing an example of the decoding process of the first embodiment.

[0064] Note that the decoding process in Figure 5 is an example of a decoding process that includes an iterative process of repeating SB decoding. As described above, the iterative process can be performed with a code configured as shown in Figure 2 or Figure 3. The code on which the iterative process is performed is not limited to Figure 2 or Figure 3, but may be any other code.

[0065] The control unit 11 reads the error correction code from the non-volatile memory 20 and obtains read information (step S101). The control unit 11 transfers the read information to the read information memory 121 and stores it.

[0066] Next, the HB decoder 102 of decoder 18 performs HB decoding (step S102). Decoder 18 determines whether or not the decoding (HB decoding) was successful (step S103). If decoding fails (step S103: No), the SB decoder 101 of decoder 18 performs SB decoding (step S104).

[0067] The HB decoder 102 of decoder 18 performs HB decoding to determine whether SB decoding is successful or not (step S105). Note that the determination of whether SB decoding is successful or not may be performed when predetermined conditions are met. The predetermined conditions are, for example, any of the following conditions. The number of repetitions is even. The number of repetitions is odd. The number of repetitions is a multiple of a predetermined integer.

[0068] The decoder 18 uses the result of HB decoding in step S105 to determine whether or not decoding was successful (step S106). If decoding fails (step S106: No), the determination unit 103 of the decoder 18 determines whether or not to terminate the iteration (step S107). Details of the determination process by the determination unit 103 will be described later.

[0069] If the determination process determines that the iteration should not be terminated (step S107: No), the process returns to step S104 and is repeated. If the determination process determines that the iteration should be terminated (step S107: Yes), the determination unit 103 determines whether the termination condition for the update process that updates the LLR table (hereinafter referred to as termination condition CC) is met (step S108). For example, the determination unit 103 determines that termination condition CC is met when the number of iterations of the update process reaches a predetermined upper limit.

[0070] If the termination condition CC is not met (step S108: No), the update unit 104 executes the update process for the LLR table (step S109). After the update process, the process returns to step S104 and is repeated.

[0071] If the termination condition CC is met (step S108: Yes), the decoder 18 notifies an external control unit or the like of the decryption failure (step S110) and terminates the decryption process.

[0072] If it is determined in step S103 or step S106 that decryption was successful (step S103: Yes, step S106: Yes), the decoder 18 notifies an external control unit or the like of the decrypted word along with the success of the decryption (step S111), and terminates the decryption process.

[0073] Next, the details of the determination process in step S107 will be described. Figure 6 is a flowchart showing an example of the determination process in the first embodiment.

[0074] The determination unit 103 determines whether the number of repetitions is equal to or greater than the threshold THA (step S201). If the number of repetitions is equal to or greater than the threshold THA (step S201: Yes), the determination unit 103 determines whether the number of repetitions has been skipped (step S202).

[0075] Skipping the number of iterations means skipping (increasing) the number of iterations to a predetermined value in step S204, which will be described later. Skipping the number of iterations is equivalent to terminating the iterative process midway. The predetermined value is, for example, the number of iterations at which the execution of preprocessing necessary to improve the estimation accuracy of the LLR table begins.

[0076] If the number of repetitions has not been skipped (step S202: No), the determination unit 103 determines whether or not MaxLLRCount has increased (step S203).

[0077] If MaxLLRCount is not increasing (step S203: No), the determination unit 103 skips the number of repetitions to a specified value (step S204). Note that the determination in step S203 that MaxLLRCount is not increasing corresponds to the above termination condition CA being satisfied.

[0078] In the example in Figure 6, by skipping the number of iterations up to a specified value, preprocessing necessary to improve the accuracy of the update process can be performed during the SB decoding (step S104) or HB decoding (step S105) included in the iterative processing for the number of iterations from the specified value to the maximum value.

[0079] Note that the procedure for performing preprocessing after terminating decryption is not limited to the procedure of skipping the number of iterations as shown in Figure 6. For example, instead of skipping the number of iterations, a procedure may be used in which preprocessing is performed after terminating decryption and ending the iterative process (step S107: Yes), and before performing the LLR table update process (step S109).

[0080] After the number of repetitions has been skipped (step S204), if the number of repetitions has already been skipped (step S202: Yes), and if MaxLLRCount has increased (step S203: Yes), the determination unit 103 determines whether the number of repetitions has reached the maximum value (step S205). Note that the determination in step S205 corresponds to determining whether the above termination condition CB is met.

[0081] If the number of repetitions reaches the maximum value (step S205: Yes), the determination unit 103 outputs a determination result indicating that the repetition should be terminated (step S206), and the determination process ends.

[0082] If it is determined in step S201 that the number of repetitions is not equal to or greater than the threshold THA (step S201: No), and if it is determined in step S205 that the number of repetitions has not reached the maximum value (step S205: No), the determination unit 103 outputs a determination result indicating that the repetition will not be terminated (step S206), and terminates the determination process.

[0083] Next, we will explain the details of the preprocessing. When the LLR table update process is performed as a performance improvement function, the following process described in (C2) above may be performed as preprocessing. • Change the index in the log-prior probability ratio table. • Hard-determination decoding with better decoding performance

[0084] First, let's explain how to change the index in the log-prior probability ratio table. The log-prior probability ratio is used to determine the decoding success rate. The decoding success rate is used, for example, to determine the maximum likelihood decoding word.

[0085] A log-prior probability ratio table is a table used to determine the log-prior probability ratio. For example, a log-prior probability ratio table is a predetermined table that associates an index with a log-prior probability ratio. The log-prior probability ratio tends to increase as the decoding process progresses. Therefore, the index is typically a value that uses the number of decoding iterations as the key.

[0086] On the other hand, if decoding is not progressing properly, the situation where the log-prior probability ratio increases as decoding progresses will no longer apply. Therefore, when the number of iterations approaches the maximum value, it is determined that decoding is not progressing properly, and the index is forcibly changed to a smaller value (to reduce the required log-prior probability ratio). This process is equivalent to changing the index in the log-prior probability ratio table. This makes it possible to perform decoding more accurately.

[0087] The modification of the log-prior probability ratio table is performed, for example, during SB decoding by the SB decoder 101. For example, when the number of iterations reaches a predetermined value, the SB decoder 101 modifies the log-prior probability ratio table and then performs SB decoding. The predetermined value can be set in any way, but for example, it is greater than half of the maximum number of iterations and less than or equal to the maximum number of iterations.

[0088] Next, we will discuss hard-decision decoding with higher decoding performance. Hard-decision decoding with higher decoding performance refers to hard-decision decoding that performs better than hard-decision decoding performed at other iteration counts (for example, hard-decision decoding performed when the number of iterations is less than the threshold THA). Examples of hard-decision decoding with higher decoding performance include decoding with a larger allowable latency and decoding with an increased number of correctable bits.

[0089] Hard-decision decoding, which offers superior decoding performance, is performed, for example, as HB decoding (step S105 in Figure 5) executed by the HB decoder 102 during iterative processing. For example, the HB decoder 102 performs hard-decision decoding, which offers superior decoding performance, when the number of iterations reaches a predetermined value.

[0090] Next, an example of the decoding process according to this embodiment will be described. Figure 7 is a diagram showing an example of the decoding process according to this embodiment. Figure 7 shows an example in which each parameter related to the iterative process is set as follows. • Maximum number of repetitions: 15 • Threshold THA: 4 • Default value: 13

[0091] In this embodiment, if the number of iterations of the loop is less than the threshold THA=4, the decoding process will not be terminated midway, even if the value of the indicator showing the progress of decoding (MaxLLRCount) is stagnant. Termination is performed when the number of iterations is greater than or equal to the threshold THA=4 and the value of the indicator showing the progress of decoding (MaxLLRCount) is stagnant (termination condition CA). In the example in Figure 7, the number of iterations is skipped to a specified value (=13) in order to execute the preprocessing that is performed in the latter half of the loop 701.

[0092] After the processing of step 701 in the latter half is executed, the LLR table update process (step S109 in Figure 6) is executed, followed by the next iteration process (step S104 in Figure 6).

[0093] In this embodiment, preprocessing is performed before the update process, which improves the accuracy of the LLR table update process. As a result, in the next iteration, the possibility of decoding proceeding without stagnation is increased by using the accurately updated LLR table.

[0094] (Second embodiment) If SB decoding fails, it is desirable to terminate the iteration midway to suppress the increase in latency. The first embodiment described above includes a termination function for this purpose. On the other hand, when SB decoding is successful, continuing to repeat SB decoding may increase the probability of successful decoding.

[0095] The second embodiment further includes a function that carries over the number of iterations reduced by the termination function to the number of iterations in the next iteration. This makes it possible to improve decoding performance while suppressing the increase in latency.

[0096] In the second embodiment, for example, if the decoder 18 terminates the SB decoding iteration due to termination condition CA, it increases the maximum number of iterations used in the termination condition CB of the next iteration. For example, the decoder 18 calculates the maximum number to be used in the termination condition CB of the next iteration by adding an integer of 1 or more, which is less than or equal to the reduction number (skip number) of the SB decoding iterations when the SB decoding iteration is terminated due to termination condition CA, to the maximum number. The reduction number can be calculated, for example, by "default value - number of iterations when terminated - 1". Since an integer less than or equal to the reduction number is added, the overall latency increase of the decoding process, which repeats multiple iterations, can be suppressed.

[0097] In this embodiment, the determination process by the determination unit 103 differs from that of the first embodiment. An example of the determination process in this embodiment will be described below. Figure 8 is a flowchart showing an example of the determination process in the second embodiment.

[0098] Steps S301 to S304 are the same as steps S201 to S204 in Figure 6, which shows the determination process of the first embodiment, so their explanation will be omitted.

[0099] In this embodiment, after skipping the number of iterations to a predetermined value (step S304), the determination unit 103 calculates the maximum value for the next iteration (step S305). For example, the determination unit 103 calculates the maximum value for the next iteration by adding the number of iterations skipped (reduction) to the maximum value used in the current iteration. The calculated maximum value may be stored in a storage unit such as a data buffer 12.

[0100] In the next step S306, the determination unit 103 uses the maximum value calculated for the current iteration. When the current iteration ends (step S107: Yes in Figure 6) and the process transitions to the next iteration, the determination unit 103 uses the maximum value calculated in step S305.

[0101] If decoding is not skipped, the determination unit 103 may set the maximum value for the next iteration to the default value (for example, 15 times). The determination unit 103 may also be configured to use the value obtained by adding the reduction number from the previous iteration to the default value as the maximum value to be used in the current iteration.

[0102] Steps S306 to S308 are the same as steps S205 to S207 in Figure 6, which shows the determination process of the first embodiment, so their explanation will be omitted.

[0103] Next, an example of the decoding process according to this embodiment will be described. Figure 9 is a diagram showing an example of the decoding process according to this embodiment. Similar to Figure 7, Figure 9 shows an example in which each parameter related to the iterative process is set as follows. • Maximum number of repetitions: 15 • Threshold THA: 4 • Default value: 13

[0104] Let's assume that the decoding process was terminated when the number of iterations reached 4. In this case, the determination unit 103 calculates a value 23, which is obtained by adding the reduction number 8 (default value 13 - number of iterations 4 - 1) to the maximum value 15, as the maximum value for the next iteration.

[0105] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0106] 1. Memory System 10 Memory Controllers 11 Control Unit 12 data buffers 13 Memory I / F 14. Encoding / Decoding Section 15 Host I / F 16 Internal bus 17 Encoder 18 Decoder 20 Non-volatile memory 30 hosts 101 SB decoder 102 HB decoder 103 Judgment section 104 Update section

Claims

1. A non-volatile memory that stores data and error correction codes generated using the data, The first read information is read from the non-volatile memory. Using correspondence information that associates multiple read information with multiple likelihood information, the first likelihood information, which corresponds to the read first read information, is determined from among the multiple likelihood information. For each of the multiple bits contained in the first read information, a soft decision decoding process is performed, which includes a process of obtaining posterior likelihood information using the first likelihood information, and this process is repeated until the first termination condition or the second termination condition is met. If the first termination condition is met, the preprocessing for the update process that updates the corresponding information is executed. After the preprocessing described above is performed, or if the second termination condition is met, the update process is performed using the apost-likelihood information obtained in the iterative process. After executing the update process, the iterative process is executed again. Memory controller and Equipped with, The first termination condition indicates that, among the multiple soft-decision decodings repeatedly performed within the iterative process, the value of the index indicating the progress of decoding has stagnated compared to the previous soft-decision decoding, and the number of iterations of the soft-decision decoding within the iterative process is equal to or greater than the first threshold. The second termination condition indicates that the number of repetitions has reached its maximum value. Memory system.

2. The aforementioned memory controller If the iteration of the soft-determination decoding is terminated by the first termination condition, the maximum value used in the second termination condition of the next iteration is increased. The memory system according to claim 1.

3. The aforementioned memory controller The maximum value to be used in the second termination condition of the next iteration is calculated by adding an integer of 1 or more, which is less than or equal to the reduction in the number of iterations of the soft-decision decoding when the soft-decision decoding is terminated according to the first termination condition, to the maximum value. The memory system according to claim 2.

4. The indicator showing the progress of the decoding is the total number of bits for which the aposterior likelihood information is equal to or greater than the second threshold. The first termination condition indicates that the increase in the total number for the previous soft-decision decoding has stagnated, and the number of repetitions is equal to or greater than the first threshold. The memory system according to claim 1.

5. The iterative process includes hard-deterministic decoding to determine whether the soft-deterministic decoding was successful. The preprocessing is a hard-decision decoding that has better decoding performance than the hard-decision decoding that is performed when the number of iterations is less than the first threshold. The memory system according to claim 1.

6. The first termination condition is, In the iterative process described above, among the multiple soft-decision decodings that are repeatedly performed, the increase in the total number of bits for which the posterior likelihood information is equal to or greater than the second threshold compared to the previous soft-decision decoding is less than or equal to the third threshold, or the total number is decreasing. and, This indicates that the number of repetitions is equal to or greater than the second threshold. The memory system according to claim 1.

7. The error correction code is an N-dimensional error correction code in which at least one symbol among the symbols constituting the code is protected by a group of N component codes (where N is an integer of 2 or more). The memory system according to claim 1.

8. First read information is read from a non-volatile memory that stores data and an error correction code generated using the said data. Using correspondence information that associates multiple read information with multiple likelihood information, the first likelihood information, which corresponds to the read first read information, is determined from among the multiple likelihood information. For each of the multiple bits contained in the first read information, a soft decision decoding process is performed, which includes a process of obtaining posterior likelihood information using the first likelihood information, and this process is repeated until the first termination condition or the second termination condition is met. If the first termination condition is met, the preprocessing for the update process that updates the corresponding information is executed. After the preprocessing described above is performed, or if the second termination condition is met, the update process is performed using the apost-likelihood information obtained in the iterative process. After executing the update process, the iterative process is executed again. The first termination condition indicates that, among the multiple soft-decision decodings repeatedly performed within the iterative process, the value of the index indicating the progress of decoding has stagnated compared to the previous soft-decision decoding, and the number of iterations of the soft-decision decoding within the iterative process is equal to or greater than the first threshold. The second termination condition indicates that the number of repetitions has reached its maximum value. Memory controller.

9. A control method by a memory controller for controlling a non-volatile memory that stores data and error correction codes generated using the data, The first read information is read from the non-volatile memory. Using correspondence information that associates multiple read information with multiple likelihood information, the first likelihood information, which corresponds to the read first read information, is determined from among the multiple likelihood information. For each of the multiple bits contained in the first read information, a soft decision decoding process is performed, which includes a process of obtaining posterior likelihood information using the first likelihood information, and this process is repeated until the first termination condition or the second termination condition is met. If the first termination condition is met, the preprocessing for the update process that updates the corresponding information is executed. After the preprocessing described above is performed, or if the second termination condition is met, the update process is performed using the apost-likelihood information obtained in the iterative process. After executing the update process, the iterative process is executed again. This includes, The first termination condition indicates that, among the multiple soft-decision decodings repeatedly performed within the iterative process, the value of the index indicating the progress of decoding has stagnated compared to the previous soft-decision decoding, and the number of iterations of the soft-decision decoding within the iterative process is equal to or greater than the first threshold. The second termination condition indicates that the number of repetitions has reached its maximum value. Control method.

Images