Wafers and semiconductor devices

Abstract

Provided are a wafer and a semiconductor device capable of improving characteristics. 【Solution】According to an embodiment, the wafer includes a substrate and a nitride member. The nitride member includes an intermediate nitride layer containing Al α1 Ga 1-α1 N (0 < α1 ≦ 1), a first nitride layer containing Al z1 Ga 1-z1 N (0 < z1 < α1), a second nitride layer containing Al z2 Ga 1-z2 N (0 < z2 < α1), and Al z3 Ga 1-z3 N (0 ≦ z3

Description

Technical Field

[0001] Embodiments of the present invention relate to a wafer and a semiconductor device.

Background Art

[0002] For example, in a semiconductor device based on a wafer containing a nitride, improvement in characteristics is desired.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments of the present invention provide a wafer and a semiconductor device capable of improving characteristics.

Means for Solving the Problems

[0005] According to an embodiment of the present invention, a wafer includes a substrate and a nitride member. The nitride member includes an intermediate nitride layer containing Al α1 Ga 1-α1 N (0 <α1 ≤ 1), a first nitride layer containing Al z1 Ga 1-z1 N (0 <z1 <α1), a second nitride layer containing Al z2 Ga 1-z2 N (0 <z2 <α1), and an Al z3 Ga 1-z3It includes a third nitride layer containing N(0≦z3<z2). The intermediate nitride layer is between the substrate and the third nitride layer in a first direction from the substrate to the nitride member. The first nitride layer is between the intermediate nitride layer and the third nitride layer. The second nitride layer is between the first nitride layer and the third nitride layer. The second carbon concentration in the second nitride layer is lower than the first carbon concentration in the first nitride layer and lower than the third carbon concentration in the third nitride layer.

Brief Description of the Drawings

[0006] [Figure 1] FIG. 1 is a schematic cross-sectional view illustrating a wafer according to the first embodiment. [Figure 2] FIG. 2 is a graph illustrating a wafer according to the first embodiment. [Figure 3] FIG. 3 is a graph illustrating the characteristics of a wafer. [Figure 4] FIG. 4 is a graph illustrating the characteristics of a wafer. [Figure 5] FIG. 5 is a schematic cross-sectional view illustrating a wafer according to the first embodiment. [Figure 6] FIG. 6 is a schematic cross-sectional view illustrating a wafer according to the first embodiment. [Figure 7] FIG. 7 is a schematic cross-sectional view illustrating a semiconductor device according to the second embodiment. [Figure 8] FIG. 8 is a schematic cross-sectional view illustrating a semiconductor device according to the second embodiment.

Embodiments for Carrying Out the Invention

[0007] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationships between the thickness and width of each part, the ratios of the sizes between parts, etc. are not necessarily the same as in reality. Even when representing the same part, there are cases where the dimensions and ratios are represented differently in the drawings. In this specification and each figure, elements that are the same as those described above with respect to the previously presented figures are denoted by the same reference numerals, and detailed descriptions thereof are omitted as appropriate.

[0008] (First Embodiment) FIG. 1 is a schematic cross-sectional view illustrating a wafer according to the first embodiment. As shown in FIG. 1, a wafer 210 according to the embodiment includes a substrate 18s and a nitride member 10M. As will be described later, the wafer 210 may further include other layers.

[0009] The nitride member 10M includes an intermediate nitride layer 11i containing Al α1 Ga 1-α1 N (0 < α1 ≤ 1), a first nitride layer 11 containing Al z1 Ga 1-z1 N (0 < z1 < α1), a second nitride layer 12 containing Al z2 Ga 1-z2 N (0 < z2 < α1), and a third nitride layer 13 containing Al z3 Ga 1-z3 N (0 ≤ z3 < z2).

[0010] The intermediate nitride layer 11i is between the substrate 18s and the third nitride layer 13 in a first direction D1 from the substrate 18s to the nitride member 10M.

[0011] Let the first direction D1 be the Z-axis direction. Let one direction perpendicular to the Z-axis direction be the X-axis direction. Let the direction perpendicular to both the Z-axis direction and the X-axis direction be the Y-axis direction, the substrate 18s extends along the X-Y plane. The nitride member 10M extends along the X-Y plane.

[0012] The first nitride layer 11 is between the intermediate nitride layer 11i and the third nitride layer 13. The second nitride layer 12 is between the first nitride layer 11 and the third nitride layer 13.

[0013] For example, the composition ratio α1 may be between 0.9 and 1. The intermediate nitride layer 11i may be, for example, an AlN layer. As will be described later, the composition ratio z1 may vary within the first nitride layer 11. The composition ratio z2 may be, for example, between 0.1 and 0.5. The second nitride layer 12 may be, for example, an AlGaN layer. The composition ratio z3 may be, for example, between 0 and 0.1. The third nitride layer 13 may be, for example, a GaN layer.

[0014] In this embodiment, the second carbon concentration C2 in the second nitride layer 12 is lower than the first carbon concentration C1 in the first nitride layer 11 and lower than the third carbon concentration C3 in the third nitride layer 13. The third nitride layer 13 is, for example, a GaN layer containing a high concentration of carbon. The second nitride layer 12 is an AlGaN layer with a low carbon concentration.

[0015] It was found that high pressure resistance can be obtained with the carbon concentration profile described above.

[0016] The following describes three samples with different secondary carbon concentrations (C2). In the first sample SP1, the second carbon concentration C2 is lower than the first carbon concentration C1 and lower than the third carbon concentration C3. The first sample SP1 corresponds to the configuration of the embodiment.

[0017] Figure 2 is a graph illustrating a wafer according to the first embodiment. Figure 2 illustrates the composition and impurity profiles of wafer 210. Figure 2 shows the SIMS (Secondary Ion Mass Spectrometry) analysis results of the first sample SP1. In Figure 2, the horizontal axis represents the position pZ in the Z-axis direction. The left vertical axis of Figure 2 represents the carbon concentration CC1. The right vertical axis of Figure 2 represents the Al count Al1. In Figure 2, the regions of the first nitride layer 11, the second nitride layer 12, and the third nitride layer 13 are shown.

[0018] As shown in Figure 2, in the first sample SP1, the second carbon concentration C2 in the second nitride layer 12 is lower than the first carbon concentration C1 in the first nitride layer 11. The second carbon concentration C2 is lower than the third carbon concentration C3 in the third nitride layer 13.

[0019] In the second sample SP2, corresponding to the first reference example, the second carbon concentration C2 is lower than the third carbon concentration C3, but substantially the same as the first carbon concentration C1. In the third sample SP3, corresponding to the second reference example, the second carbon concentration C2 is substantially the same as the third carbon concentration C3, and higher than the first carbon concentration C1.

[0020] The pressure resistance of the second sample SP2 is 1.13 times that of the third sample SP3. The pressure resistance of the first sample SP1 is 1.15 times that of the third sample SP3. Thus, it was found that a higher pressure resistance can be obtained when the second carbon concentration C2 is lower than the first carbon concentration C1 and lower than the third carbon concentration C3.

[0021] Figure 3 is a graph illustrating the characteristics of a wafer. The horizontal axis of Figure 3 represents the secondary carbon concentration (C2). The vertical axis of Figure 3 represents the helical dislocation density (SD1). Figure 3 shows the evaluation results for the first sample SP1, the second sample SP2, and the third sample SP3. As shown in Figure 3, the helical dislocation density SD1 decreases as the secondary carbon concentration (C2) decreases. A low helical dislocation density SD1 is obtained in the first sample SP1.

[0022] Figure 4 is a graph illustrating the characteristics of a wafer. The horizontal axis of Figure 4 represents the secondary carbon concentration C2. The vertical axis of Figure 4 represents the full width at half maximum (FWHM) w1 of the peak corresponding to the (002) plane of GaN in X-ray diffraction. A small FWHM w1 corresponds to small crystal fluctuations and good crystallinity. Figure 4 shows the evaluation results for the first sample SP1, the second sample SP2, and the third sample SP3. As shown in Figure 4, the FWHM w1 decreases as the secondary carbon concentration C2 decreases. A small FWHM is obtained in the first sample SP1.

[0023] Thus, it was found that a low screw dislocation density SD1 can be obtained due to the low second carbon concentration C2. It was found that a small full width at half maximum w1 can be obtained due to the low second carbon concentration C2. Accordingly, it is considered that a high breakdown voltage can be obtained. It is considered that the breakdown voltage is improved due to the high crystal quality.

[0024] The third nitride layer 13 is, for example, a GaN layer containing carbon. It is known that a high breakdown voltage can be obtained by providing such a third nitride layer 13. This is presumably based on the fact that injected carriers are trapped by levels based on carbon. On the other hand, according to the results of the inventor's experiments, it was found that a high breakdown voltage can be obtained as described above by lowering the second carbon concentration C2 in the second nitride layer 12 between the substrate 18s and the third nitride layer 13.

[0025] The embodiment is based on such new findings. By having the second carbon concentration C2 lower than the first carbon concentration C1 and lower than the third carbon concentration C3, a low screw dislocation density SD1 and a small full width at half maximum w1 can be obtained. Such a carbon concentration profile is considered to provide good crystallinity and a high breakdown voltage. According to the embodiment, a wafer capable of improving characteristics can be provided. Further, in the embodiment, due to the structure in which the region with a low carbon concentration is sandwiched between two regions with a high carbon concentration, carriers are considered to be confined in the region with a low carbon concentration. Accordingly, a high breakdown voltage is considered to be obtained.

[0026] The above sample has the configuration illustrated in FIG. 1. The wafer 210 according to the embodiment may have the configuration illustrated in FIG. 1.

[0027] As shown in FIG. 1, the first nitride layer 11 may include a nitride laminate 11S. The nitride laminate 11S includes a plurality of first films 11a containing Al y1 Ga 1-y1 N(0 < y1 ≦ 1), and Al y2 Ga 1-y2It includes a plurality of second films 11b including N (0≦y2<y1). One of the plurality of first films 11a is between one of the plurality of second films 11b and another one of the plurality of second films 11b in the first direction D1. One of the plurality of second films 11b is between one of the plurality of first films 11a and another one of the plurality of first films 11a in the first direction D1. For example, the first film 11a and the second film 11b may be provided alternately.

[0028] The nitride laminate 11S may be, for example, a superlattice layer. By providing the nitride laminate 11S, for example, the strain of the crystal is relaxed. For example, warping is suppressed. The composition ratio y1 may be, for example, 0.8 or more and 1 or less. The composition ratio y2 may be, for example, 0 or more and 0.15 or less.

[0029] The first nitride layer 11 may include an intermediate region 11A containing Al, Ga, and N. The intermediate region 11A is between the intermediate nitride layer 11i and the nitride laminate 11S. In one example, the Al composition ratio in the intermediate region 11A may decrease in the direction from the intermediate nitride layer 11i to the second nitride layer 12. For example, the strain of the crystal is relaxed. For example, warping is suppressed.

[0030] As will be described later, one of the nitride laminate 11S and the intermediate region 11A may be omitted.

[0031] The ratio of the absolute value of the difference between the maximum value and the minimum value of the carbon concentration in the nitride laminate 11S to the maximum value may be 0.1 or less. In the nitride laminate 11S, the carbon concentration may be substantially constant.

[0032] The ratio of the absolute value of the difference between the maximum value and the minimum value of the carbon concentration in the second nitride layer 12 to the maximum value may be 0.1 or less. In the second nitride layer 12, the carbon concentration may be substantially constant.

[0033] The ratio of the absolute value of the difference between the maximum value and the minimum value of the Al concentration in the second nitride layer 12 to the maximum value may be 0.1 or less. In the second nitride layer 12, the Al composition ratio may be substantially constant.

[0034] As shown in Figure 1, the thickness of the second nitride layer 12 along the first direction D1 is defined as the second thickness t2. The thickness of the third nitride layer 13 along the first direction D1 is defined as the third thickness t3. For example, the second thickness t2 may be thicker than the third thickness t3. For example, a higher breakdown voltage is easier to obtain. For example, a lower helical dislocation density SD1 is easier to obtain. For example, a smaller full width at half maximum is easier to obtain.

[0035] The first thickness t1 of the first nitride layer 11 is defined as the thickness along the first direction D1. For example, the second thickness t2 of the second nitride layer 12 may be thinner than the first thickness t1. A thicker first thickness t1 allows for more effective strain relief, for example.

[0036] If the first nitride layer 11 includes a nitride laminate 11S and an intermediate region 11A, the first thickness t1 may correspond to the sum of the thickness t11S of the nitride laminate 11S and the thickness t11A of the intermediate region 11A.

[0037] As shown in Figure 2, in this embodiment, the third carbon concentration C3 may be higher than the first carbon concentration C1. For example, rearrangements can be effectively reduced.

[0038] The secondary carbon concentration C2 is, for example, 1 × 10⁻⁶ 17 cm -3 The above is 1 x 10 19 cm -3 The following are preferable: High voltage resistance is easily obtained. For example, a low spiral dislocation density SD1 is easily obtained. A small half-width w1 is easily obtained.

[0039] The third carbon concentration (C3) is, for example, 1 × 10⁻⁶ 19 cm -3 Exceeding 1 x 10 20 cm -3 The following is sufficient. This makes it easier to suppress current collapse. The first carbon concentration C1 is, for example, 1 × 10⁻⁶. 19 cm -3 Exceeding 5 x 10 19 cm -3 The following is sufficient. This makes it easier to suppress carrier injection.

[0040] As shown in FIG. 1, the wafer 210 may further include a first semiconductor layer 10 containing Al x1 Ga 1-x1 N (0 ≦ x1 < 1). The nitride member 10M is between the substrate 18s and the first semiconductor layer 10. The composition ratio x1 may be, for example, 0 or more and 0.13 or less. The first semiconductor layer 10 may be, for example, a GaN layer. The carbon concentration in the first semiconductor layer 10 is lower than the third carbon concentration C3 in the third nitride layer 13. The carbon concentration in the first semiconductor layer 10 is, for example, 1 × 10 18 cm -3 less than.

[0041] As shown in FIG. 1, the wafer 210 may further include a second semiconductor layer 20 containing Al x2 Ga 1-x2 N (0 < x2 ≦ 1, x1 < x2). The first semiconductor layer 10 is between the nitride member 10M and the second semiconductor layer 20. The composition ratio x2 may be, for example, 0.15 or more and 3.5 or less. The second semiconductor layer 20 may be, for example, an AlGaN layer. The carbon concentration in the second semiconductor layer 20 is lower than the third carbon concentration C3 in the third nitride layer 13. The carbon concentration in the second semiconductor layer 20 is, for example, 1 × 10 19 cm -3 less than.

[0042] FIG. 5 is a schematic cross-sectional view illustrating a wafer according to the first embodiment. As shown in FIG. 5, in the wafer 211 according to the embodiment, the intermediate region 11A is omitted. The configuration of the wafer 211 except this may be the same as the configuration of the wafer 210. In the wafer 211, the nitride laminate 11S is in contact with the intermediate nitride layer 11i and the second nitride layer 12.

[0043] FIG. 6 is a schematic cross-sectional view illustrating a wafer according to the first embodiment. As shown in FIG. 6, in the wafer 212 according to the embodiment, the nitride laminate 11S is omitted. The configuration of the wafer 212 except this may be the same as the configuration of the wafer 210.

[0044] In the wafer 212, the first nitride layer 11 includes an intermediate region 11A containing Al, Ga, and N. Also in the wafer 212, the Al composition ratio in the intermediate region 11A may decrease in the direction from the intermediate nitride layer 11i to the second nitride layer 12. In the wafer 212, the intermediate region 11A is in contact with the intermediate nitride layer 11i and the second nitride layer 12.

[0045] (Second Embodiment) The second embodiment relates to a semiconductor device. The semiconductor device includes the wafer 210 described with respect to the first embodiment or a modification thereof.

[0046] FIG. 7 is a schematic cross-sectional view illustrating a semiconductor device according to the second embodiment. As shown in FIG. 7, a semiconductor device 110 according to the embodiment includes the wafer 210 according to the first embodiment, a first electrode 51, a second electrode 52, and a third electrode 53.

[0047] For example, when the wafer 210 does not include the first semiconductor layer 10 and the second semiconductor layer 20, the semiconductor device 110 includes the first semiconductor layer 10 and the second semiconductor layer 20. The first semiconductor layer 10 contains Al x1 Ga 1-x1 N (0 ≦ x1 < 1). The second semiconductor layer 20 contains Al x2 Ga 1-x2 N (0 < x2 ≦ 1, x1 < x2). The first semiconductor layer 10 is, for example, a GaN layer. The second semiconductor layer 20 is, for example, an AlGaN layer.

[0048] The nitride member 10M is between the substrate 18s and the second semiconductor layer 20. The first semiconductor layer 10 is between the nitride member 10M and the second semiconductor layer 20.

[0049] The second direction D2 from the first electrode 51 to the second electrode 52 intersects the first direction D1. The second direction D2 is, for example, the X-axis direction. The position of the third electrode 53 in the second direction D2 is between the position of the first electrode 51 in the second direction D2 and the position of the second electrode 52 in the second direction D2.

[0050] The second semiconductor layer 20 includes a first semiconductor portion 21 and a second semiconductor portion 22. The direction from the first semiconductor portion 21 to the second semiconductor portion 22 is along the second direction D2. The first electrode 51 is electrically connected to the first semiconductor portion 21. The second electrode 52 is electrically connected to the second semiconductor portion 22.

[0051] The current flowing between the first electrode 51 and the second electrode 52 is controlled by the potential of the third electrode 53. The potential of the third electrode 53 may be, for example, a potential relative to the potential of the first electrode 51. The first electrode 51 functions as, for example, a source electrode. The second electrode 52 functions as a drain electrode. The third electrode 53 functions as a gate electrode. The semiconductor device 110 is, for example, a transistor.

[0052] The first semiconductor layer 10 includes a region facing the second semiconductor layer 20. A carrier region is formed in this region. The carrier region is, for example, a two-dimensional electron gas. The semiconductor device 110 is, for example, a HEMT (High Electron Mobility Transistor).

[0053] In the semiconductor device 110 according to this embodiment, for example, high breakdown voltage can be obtained. Good crystallinity can be obtained. For example, low on-resistance can be obtained. According to this embodiment, a semiconductor device with improved characteristics can be provided.

[0054] As shown in Figure 7, in this example, at least a portion of the third electrode 53 may be provided between the first semiconductor portion 21 and the second semiconductor portion 22 in the second direction D2. The third electrode 53 is, for example, a recessed gate electrode. For example, a high threshold voltage can be obtained. For example, normally-off operation can be obtained. At least a portion of the third electrode 53 may be provided between a portion of the first semiconductor layer 10 and another portion of the first semiconductor layer 10 in the second direction D2.

[0055] For example, the first semiconductor layer 10 includes a first partial region 10a, a second partial region 10b, a third partial region 10c, a fourth partial region 10d, and a fifth partial region 10e. The direction from the first partial region 10a to the first electrode 51 is along the first direction D1. The direction from the second partial region 10b to the second electrode 52 is along the first direction D1. The direction from the third partial region 10c to the third electrode 53 is along the first direction D1.

[0056] The fourth position of the fourth subregion 10d in the second direction D2 lies between the first position of the first subregion 10a in the second direction D2 and the third position of the third subregion 10c in the second direction D2. The fifth position of the fifth subregion 10e in the second direction D2 lies between the third position of the third subregion 10c in the second direction D2 and the second position of the second subregion 10b in the second direction D2.

[0057] The direction from the fourth subregion 10d to the first semiconductor portion 21 is along the first direction D1. The direction from the fifth subregion 10e to the second semiconductor portion 22 is along the first direction D1. In this example, a portion of the third electrode 53 is located between the fourth subregion 10d and the fifth subregion 10e in the second direction D2. A high threshold voltage can be obtained. For example, normally-off operation can be obtained stably.

[0058] As shown in Figure 7, the semiconductor device 110 may further include a first insulating member 41. The first insulating member 41 includes a first insulating portion 41p. The first insulating portion 41p is provided between the third electrode 53 and the nitride member 10M. The first insulating portion 41p functions, for example, as a gate insulating film.

[0059] The electrodes described above may extend along a third direction D3. The third direction D3 intersects a plane containing the first direction D1 and the second direction D2.

[0060] Figure 8 is a schematic cross-sectional view illustrating a semiconductor device according to the second embodiment. As shown in FIG. 8, the semiconductor device 111 according to the embodiment includes the wafer 210 according to the first embodiment, the first electrode 51, the second electrode 52, and the third electrode 53. In the semiconductor device 111, the third electrode 53 does not overlap with the second semiconductor layer 20 in the second direction D2. The configuration of the semiconductor device 111 except this may be the same as that of the semiconductor device 110.

[0061] In the semiconductor device 111, for example, a normally-on operation can be obtained. In the semiconductor device 111, the first insulating member 41 may be omitted. The semiconductor device 111 can be used as, for example, a high-frequency switching element.

[0062] In the embodiment, information regarding the shape of the nitride layer and the like can be obtained by, for example, electron microscope observation. Information regarding the composition and element concentration in the nitride layer can be obtained by, for example, EDX (Energy Dispersive X-ray Spectroscopy), or SIMS (Secondary Ion Mass Spectrometry). Information regarding the composition in the nitride layer can be obtained by, for example, reciprocal lattice space mapping.

[0063] The embodiment may include the following technical solutions. (Technical solution 1) A substrate, A nitride member, Comprising, The nitride member is Al α1 Ga 1-α1 An intermediate nitride layer containing N (0 <α1 ≤ 1), Al z1 Ga 1-z1 A first nitride layer containing N (0 <z1 <α1), Al z2 Ga 1-z2 A second nitride layer containing N (0 <z2 <α1), Al z3 Ga 1-z3 A third nitride layer containing N (0 ≤ z3 <z2), Including, The intermediate nitride layer is located between the substrate and the third nitride layer in a first direction from the substrate to the nitride member. The first nitride layer is located between the intermediate nitride layer and the third nitride layer. The second nitride layer is located between the first nitride layer and the third nitride layer. The wafer, wherein a second carbon concentration in the second nitride layer is lower than a first carbon concentration in the first nitride layer and lower than a third carbon concentration in the third nitride layer.

[0064] (Technical solution 2) The first nitride layer includes a nitride laminate. The nitride laminate Al y1 Ga 1-y1 A plurality of first films containing N (0 < y1 ≤ 1), Al y2 Ga 1-y2 A plurality of second films containing N (0 ≤ y2 < y1), and includes One of the plurality of first films is located between one of the plurality of second films and another one of the plurality of second films in the first direction. The wafer according to Technical solution 1, wherein the one of the plurality of second films is located between the one of the plurality of first films and another one of the plurality of first films in the first direction.

[0065] (Technical solution 3) The first nitride layer includes an intermediate region containing Al, Ga, and N. The wafer according to Technical solution 2, wherein the intermediate region is located between the intermediate nitride layer and the nitride laminate.

[0066] (Technical solution 4) The wafer according to Technical solution 3, wherein an Al composition ratio in the intermediate region decreases in a direction from the intermediate nitride layer to the second nitride layer.

[0067] (Technical solution 5) The wafer according to Technical Proposal 1, wherein the first nitride layer includes an intermediate region containing Al, Ga, and N.

[0068] (Technical proposal 6) The wafer according to Technical Proposal 5, wherein the Al composition ratio in the intermediate region decreases in the direction from the intermediate nitride layer to the second nitride layer.

[0069] (Technical proposal 7) The wafer according to Technical Proposal 2, wherein the ratio of the absolute value of the difference between the highest and lowest carbon concentrations in the nitride laminate to the highest concentration is 0.1 or less.

[0070] (Technical proposal 8) A wafer according to any one of Technical Proposals 1 to 6, wherein the ratio of the absolute value of the difference between the highest and lowest carbon concentrations in the second nitride layer to the highest value is 0.1 or less.

[0071] (Technical proposal 9) The wafer according to any one of Technical Proposals 1 to 6, wherein the ratio of the absolute value of the difference between the highest and lowest values ​​of Al concentration in the second nitride layer to the highest value is 0.1 or less.

[0072] (Technical proposal 10) A wafer according to any one of Technical Proposals 1 to 9, wherein the second thickness of the second nitride layer is greater than the third thickness of the third nitride layer.

[0073] (Technical proposal 11) A wafer according to any one of Technical Proposals 1 to 9, wherein the second thickness of the second nitride layer is thinner than the first thickness of the first nitride layer.

[0074] (Technical proposal 12) The wafer described in any one of Technical Proposals 1 to 11, wherein the third carbon concentration is higher than the first carbon concentration.

[0075] (Technical proposal 13) The aforementioned second carbon concentration is 1 × 10⁻⁶ 17 cm -3 The above is 1 x 1019 cm -3 A wafer according to any one of Technical Solutions 1 to 12, as follows.

[0076] (Technical Solution 14) The third carbon concentration is greater than 1×10 19 cm -3 and less than or equal to 1×10 20 cm -3 A wafer according to any one of Technical Solutions 1 to 13, as follows.

[0077] (Technical Solution 15) The first carbon concentration is greater than 1×10 19 cm -3 and less than or equal to 5×10 19 cm -3 A wafer according to any one of Technical Solutions 1 to 14, as follows.

[0078] (Technical Solution 16) Al x1 Ga 1-x1 Further comprising a first semiconductor layer containing Alx1Ga1 - x1N (0≦x1<1), The nitride member is located between the substrate and the first semiconductor layer. A wafer according to any one of Technical Solutions 1 to 15, as follows.

[0079] (Technical Solution 17) Al x2 Ga 1-x2 Further comprising a second semiconductor layer containing Alx2Ga1 - x2N (0<x2≦1, x1<x2), The first semiconductor layer is located between the nitride member and the second semiconductor layer. A wafer according to Technical Solution 16, as follows.

[0080] (Technical Solution 18) A wafer according to any one of Technical Solutions 1 to 15, a first electrode, a second electrode, a third electrode, Al x1 Ga 1-x1 a first semiconductor layer containing Alx1Ga1 - x1N (0≦x1<1), Al x2 Ga 1-x2A second semiconductor layer including N(0 < x2 ≤ 1, x1 < x2), comprising, wherein the nitride member is between the substrate and the second semiconductor layer, the first semiconductor layer is between the nitride member and the second semiconductor layer, a second direction from the first electrode to the second electrode intersects the first direction, a position of the third electrode in the second direction is between a position of the first electrode in the second direction and a position of the second electrode in the second direction, the second semiconductor layer includes a first semiconductor portion and a second semiconductor portion, a direction from the first semiconductor portion to the second semiconductor portion is along the second direction, the first electrode is electrically connected to the first semiconductor portion, the second electrode is electrically connected to the second semiconductor portion, a semiconductor device.

[0081] (Technical proposal 19) At least a part of the third electrode is provided between the first semiconductor portion and the second semiconductor portion in the second direction, the semiconductor device according to Technical proposal 18.

[0082] (Technical proposal 20) At least a part of the third electrode is provided between a part of the first semiconductor layer and another part of the first semiconductor layer in the second direction, the semiconductor device according to Technical proposal 18.

[0083] According to an embodiment, a wafer and a semiconductor device capable of improving characteristics can be provided.

[0084] In this specification, the state of "being electrically connected" includes a state in which a plurality of conductors are physically in contact and an electric current flows between these plurality of conductors. The state of "being electrically connected" includes a state in which another conductor is inserted between a plurality of conductors and an electric current flows between these plurality of conductors. <00,00434> Embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, the specific configuration of each element, such as the substrate, nitride layer, and electrodes, included in the wafer and semiconductor device is included within the scope of the present invention as long as the present invention can be implemented in the same manner and similar effects can be obtained by appropriately selecting from the range known to those skilled in the art.

[0086] Furthermore, combinations of two or more elements from any of the specific examples, to the extent technically feasible, are also included within the scope of the present invention, insofar as they encompass the gist of the invention.

[0087] Furthermore, all wafers and semiconductor devices that a person skilled in the art can design and implement based on the wafers and semiconductor devices described above as embodiments of the present invention, insofar as they encompass the gist of the present invention, also fall within the scope of the present invention.

[0088] Furthermore, within the scope of the concept of the present invention, a person skilled in the art could conceive of various modifications and alterations, and these modifications and alterations are also understood to fall within the scope of the present invention.

[0089] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0090] 10, 20: First and second semiconductor layers, 10M: Nitride material, 10a~10e: First to fifth partial regions, 11~13: First to third nitride layers, 11A: Intermediate region, 11S: Nitride laminate, 11a, 11b: First and second films, 11i: Intermediate nitride layer, 18s: Substrate, 21, 22: First and second semiconductor portions, 41: First insulating material, 41p: First insulating portion, 51~53: First to third electrodes, 110, 111: Semiconductor device, 210~212: Wafer, Al1: Count, C1~C3: First to third carbon concentrations, CC1: Carbon concentration, D1~D3: First to third directions, SD1: Dislocation density, SP1~SP3: First to third samples, pZ: Position t1~t3: 1st to 3rd thickness, w1: width at half maximum

Claims

1. Substrate and, Nitride material member, Equipped with, The nitride member is Al α１ Ga １－α１ An intermediate nitride layer containing N (0 < α1 ≤ 1), Al ｚ１ Ga １－ｚ１ A first nitride layer containing N (0 < z1 < α1), Al ｚ２ Ga １－ｚ２ A second nitride layer containing N (0 < z2 < α1), Al ｚ３ Ga １－ｚ３ A third nitride layer containing N (0 ≤ z3 < z2), Includes, The intermediate nitride layer is located between the substrate and the third nitride layer in a first direction from the substrate to the nitride member. The first nitride layer is located between the intermediate nitride layer and the third nitride layer. The second nitride layer is located between the first nitride layer and the third nitride layer. A wafer in which the second carbon concentration in the second nitride layer is lower than the first carbon concentration in the first nitride layer and lower than the third carbon concentration in the third nitride layer.

2. The first nitride layer includes a nitride laminate, The nitride laminate is Al ｙ１ Ga １－ｙ１ A plurality of first films containing N(0 < y1 ≤ 1), Al ｙ２ Ga １－ｙ２ Multiple second membranes including N (0 ≤ y2 < y1), Includes, One of the plurality of first films is located between one of the plurality of second films and another of the plurality of second films in the first direction. The wafer according to claim 1, wherein one of the plurality of second films is located in the first direction between one of the plurality of first films and another of the plurality of first films.

3. The first nitride layer includes an intermediate region containing Al, Ga, and N. The wafer according to claim 2, wherein the intermediate region is located between the intermediate nitride layer and the nitride laminate.

4. The wafer according to claim 3, wherein the Al composition ratio in the intermediate region decreases in the direction from the intermediate nitride layer to the second nitride layer.

5. The wafer according to claim 1, wherein the first nitride layer includes an intermediate region containing Al, Ga, and N.

6. The wafer according to claim 5, wherein the Al composition ratio in the intermediate region decreases in the direction from the intermediate nitride layer to the second nitride layer.

7. The wafer according to claim 2, wherein the ratio of the absolute value of the difference between the highest and lowest carbon concentrations in the nitride laminate to the highest value is 0.1 or less.

8. The wafer according to any one of claims 1 to 6, wherein the ratio of the absolute value of the difference between the highest and lowest carbon concentrations in the second nitride layer to the highest value is 0.1 or less.

9. The wafer according to any one of claims 1 to 6, wherein the ratio of the absolute value of the difference between the highest and lowest values ​​of Al concentration in the second nitride layer to the highest value is 0.1 or less.

10. The wafer according to any one of claims 1 to 6, wherein the second thickness of the second nitride layer is greater than the third thickness of the third nitride layer.

11. The wafer according to any one of claims 1 to 6, wherein the second thickness of the second nitride layer is thinner than the first thickness of the first nitride layer.

12. The wafer according to any one of claims 1 to 6, wherein the third carbon concentration is higher than the first carbon concentration.

13. The second carbon concentration is 1 × 10 １７ cm －３ The above is 1 x 10 １９ cm －３ The wafer according to any one of claims 1 to 6, which is as follows:

14. The third carbon concentration is 1 × 10 １９ cm －３ Exceeding 1 x 10 ２０ cm －３ The wafer according to claim 13, which is as follows:

15. The first carbon concentration is 1 × 10 １９ cm －３ Exceeding 5 x 10 １９ cm －３ The wafer according to claim 14, which is as follows:

16. Al ｘ１ Ga １－ｘ１ Further comprising a first semiconductor layer containing N (0 ≤ x1 < 1), The nitride member is located between the substrate and the first semiconductor layer in the wafer according to any one of claims 1 to 6.

17. Al ｘ２ Ga １－ｘ２ Further comprising a second semiconductor layer containing N (0 < x² ≤ 1, x¹ < x²), The wafer according to claim 16, wherein the first semiconductor layer is located between the nitride member and the second semiconductor layer.

18. A wafer according to any one of claims 1 to 6, First electrode and, The second electrode and The third electrode and Al ｘ１ Ga １－ｘ１ A first semiconductor layer containing N (0 ≤ x1 < 1), Al ｘ２ Ga １－ｘ２ A second semiconductor layer containing N (0 < x² ≤ 1, x¹ < x²), Equipped with, The nitride member is located between the substrate and the second semiconductor layer. The first semiconductor layer is located between the nitride member and the second semiconductor layer. The second direction from the first electrode to the second electrode intersects with the first direction. The position of the third electrode in the second direction is between the position of the first electrode in the second direction and the position of the second electrode in the second direction. The aforementioned second semiconductor layer includes a first semiconductor portion and a second semiconductor portion. The direction from the first semiconductor portion to the second semiconductor portion is along the second direction, The first electrode is electrically connected to the first semiconductor portion. The aforementioned second electrode is electrically connected to the aforementioned second semiconductor portion, and is a semiconductor device.

19. The semiconductor device according to claim 18, wherein at least a portion of the third electrode is provided between the first semiconductor portion and the second semiconductor portion in the second direction.

20. The semiconductor device according to claim 18, wherein at least a portion of the third electrode is provided between a portion of the first semiconductor layer and another portion of the first semiconductor layer in the second direction.

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