Semiconductor equipment

Abstract

To provide a semiconductor device that significantly reduces power consumption and retains stored data over a long period of time. [Solution] The multi-level semiconductor device includes a memory cell 200 connected in series, a drive circuit 213 that selects a memory cell to drive a second signal line S2 and a word line WL, a drive circuit 212 that selects either a write potential and outputs it to a first signal line S1, a read circuit 211 that compares the potential of the bit line BL with a reference potential, and a potential generation circuit 214 that generates a write potential and a reference potential and supplies them to the drive circuit and the read circuit. Each memory cell has a first transistor connected to the bit line and the source line, a second transistor connected to the first and second signal lines, and a third transistor connected to the word line, the bit line and the source line. The second transistor includes an oxide semiconductor layer, and the gate electrode of the first transistor is connected to either the source electrode or the drain electrode of the second transistor.

Description

Technical Field

[0001] The disclosed invention relates to a semiconductor device using semiconductor elements and a method for manufacturing the same.

Background Art

[0002] Memory devices using semiconductor elements are roughly classified into volatile memory devices in which stored contents are lost when power supply is cut off, and non-volatile memory devices in which stored contents are retained even when power supply is cut off.

[0003] A typical example of a volatile memory device is DRAM (Dynamic Random Access Memory). DRAM stores information by selecting transistors constituting memory elements and accumulating electric charges in capacitors.

[0004] Based on the above principle, in DRAM, when information is read, the electric charges in the capacitors are lost. Therefore, every time data is read, a rewrite operation is required again. In addition, there is a leakage current in the transistors constituting the memory elements, and electric charges flow out or in even when the transistors are not selected. Therefore, the data retention period is short. For this reason, a rewrite operation (refresh operation) is required at a predetermined cycle, and it is difficult to sufficiently reduce power consumption. Also, since stored contents are lost when power supply is cut off, another memory device using magnetic materials or optical materials is required for long-term memory retention.

[0005] Another example of a volatile memory device is SRAM (Static Random Access Memory). SRAM stores stored contents using circuits such as flip-flops. ​​​​​​​​​​​​Because it retains data, a refresh operation is unnecessary, which is an advantage over DRAM in this respect. However, because it uses circuits such as flip-flops, the cost per unit of memory capacity is high. There is a problem that it will become less effective. Also, there is the issue that if the power supply is cut off, the memory contents will be lost. Therefore, it is no different from DRAM.

[0006] A typical example of a non-volatile memory device is flash memory. Flash memory is a type of non-volatile memory device. The transistor has a floating gate between its gate electrode and channel formation region, Because memory is stored by holding an electric charge in a floating gate, the data retention period is extremely short. It has the advantage of being extremely long-lasting (semi-permanent) and not requiring the refresh operations necessary for volatile memory devices. It has points (see, for example, Patent Document 1).

[0007] However, the gate insulating layer that makes up the memory element is affected by the tunnel current generated during writing. Because it deteriorates, the memory element will stop functioning if it is repeatedly written to. A problem arises. To avoid this problem, for example, the number of write cycles for each memory element can be made uniform. This method is employed, but achieving it requires complex peripheral circuits. Furthermore, even if such methods are adopted, the fundamental problem of lifespan will not be resolved. In other words, flash memory is unsuitable for applications where information needs to be rewritten frequently.

[0008] Furthermore, in order to inject or remove charge from a floating gate, high A certain voltage is required. Furthermore, a relatively long time is required for charge injection or removal. However, there is also the problem that it is not easy to speed up writing and erasing. [Prior art documents] [Patent Documents]

[0009] [Patent Document 1] Japanese Patent Application Publication No. 57-105889 [Overview of the project] [Problems that the invention aims to solve]

[0010] In view of the above-mentioned problems, in one aspect of the disclosed invention, the stored contents are stored even when power is not supplied. To provide a new semiconductor device structure that allows for data retention and has no limit on the number of write cycles. One of the objectives is to provide a semiconductor device with a configuration that facilitates the multi-level conversion of data that can be stored. One of its purposes is to provide it. [Means for solving the problem]

[0011] One aspect of the present invention relates to a transistor formed using an oxide semiconductor and other materials This is a semiconductor device relating to a stacked structure with transistors formed using the following: A configuration can be adopted.

[0012] One aspect of the present invention comprises a source line, a bit line, a first signal line, a plurality of second signal lines, and a plurality Between the word line, source line, and bit line, there are multiple memory cells connected in series, An address signal is input, and among multiple memory cells, the memory cell specified by the address signal is selected. The second signal drives multiple second signal lines and multiple word lines to select a recell. The drive circuits for the line and word line, and the selection of one of several write potentials to the first signal line. The first signal line is output, and the potential of the bit line and multiple reference potentials are input to it. A readout circuit that reads data by comparing the potential of a wire with multiple reference potentials, and multiple Generates write potential and multiple reference potentials for the drive circuit and read circuit of the first signal line. It has a potential generation circuit that supplies power to a plurality of memory cells, and one of the memory cells has a first gate electrode, the A first transistor having one source electrode and a first drain electrode, and a second gate A second transistor having a source electrode, a second source electrode, and a second drain electrode, A third transistor having a third gate electrode, a third source electrode, and a third drain electrode. A transistor and a second transistor are provided on a substrate containing a semiconductor material. The lampistor is composed of an oxide semiconductor layer, a first gate electrode, and a second source electrode. Alternatively, one of the second drain electrodes is electrically connected to the source wire and the first source wire. The pole and the third source electrode are electrically connected, and the bit line and the first drain electrode are connected. The third drain electrode is electrically connected to the first signal line and the second source electrode or the The other of the two drain electrodes is electrically connected to one of several second signal lines and the second gate The gate electrode is electrically connected to one of several ward wires, and the third gate electrode is electrically connected to it. It is a connected semiconductor device.

[0013] In the above, the first gate electrode and the second source electrode or the second drain electrode It is preferable to have a capacitive element electrically connected to one of the two.

[0014] Another aspect of the present invention includes a source line, a bit line, a first signal line, and a plurality of second signals Multiple memos connected in series between the line, multiple word lines, source line, and bit line. A recell, an address signal, and multiple reference potentials are input, and among the multiple memory cells, the address Multiple second signal lines and multiple Drives a word line and outputs one of several reference potentials selected for a single word line. This involves a drive circuit for the second signal line and word line, and selecting one of several write potentials. A drive circuit for the first signal line, which outputs to the first signal line, and a specified bit line connected to it. A read circuit reads data by reading the conductance of the memory cell, and Generates multiple write potentials and multiple reference potentials to drive the first signal line and read out. The circuit has a potential generation circuit that supplies power to the circuit, and one of the plurality of memory cells is a first gate electrode A first transistor having a first source electrode and a first drain electrode, and a second A second transistor having a gate electrode, a second source electrode, and a second drain electrode. The transistor has a capacitive element and a first transistor provided on a substrate containing a semiconductor material, and The transistor 2 is composed of an oxide semiconductor layer and consists of a first gate electrode and a second thaw One of the drain electrodes or the second drain electrode and one of the electrodes of the capacitive element are electrically connected. The source line and the first source electrode are electrically connected, and the bit line and the first drain electrode are electrically connected. This refers to an electrically connected first signal line and a second source electrode or second drain electrode. The other side is electrically connected to one of the multiple second signal lines and the second gate electrode, electrically A semiconductor is connected to one of several word lines, and the other electrode of the capacitive element is electrically connected to the other electrode. It is a body device.

[0015] In the above, the semiconductor device has a first selection line, a second selection line, and a gate A fourth transistor electrically connected at the electrodes, and a second select line and a gate electrode The second wiring has a fifth transistor that is electrically connected to the fourth transistor. The first drain electrode is electrically connected via a terminal, and the first wiring is connected to the fifth transistor. It is preferable that the first source electrode is electrically connected via a zista.

[0016] Furthermore, it is preferable that the potential generated by the potential generation circuit is supplied with a potential boosted by the boost circuit.

[0017] Furthermore, in the above, the first transistor is provided on a substrate containing semiconductor material. A channel-forming region and an impurity region provided to sandwich the channel-forming region, and the channel-forming region A first gate insulating layer on the region, a first gate electrode on the first gate insulating layer, and an impurity region It has a first source electrode and a first drain electrode that are electrically connected to it.

[0018] Furthermore, in the above, the second transistor is a second gate electrode on a substrate containing semiconductor material. The electrode, the second gate insulating layer on the second gate electrode, and the oxide semiconductor on the second gate insulating layer. A body layer and a second source electrode and a second drain electrode electrically connected to the oxide semiconductor layer. It has, and

[0019] Furthermore, in the above, the substrate containing the semiconductor material may be a single-crystal semiconductor substrate or an SOI substrate. It is preferable to use a plate. In particular, silicon is preferred as the semiconductor material.

[0020] Furthermore, in the above, the oxide semiconductor layer is an In-Ga-Zn-O based oxide semiconductor material. It is preferable to include it. In particular, the oxide semiconductor layer contains crystals of In2Ga2ZnO7. The following is preferable. Furthermore, the hydrogen concentration of the oxide semiconductor layer is 5 × 10 19 atoms / cm 3 The following is preferable. Also, the off-current of the second transistor is 1 × 10⁻⁶. -13 A The following is preferable:

[0021] Furthermore, in the above, the second transistor is provided in a region that overlaps with the first transistor. It can be configured in this way.

[0022] In this specification, the terms "above" and "below" refer to the relative position of the constituent elements, not just "directly above". This does not limit the location to "directly below". For example, "the first gate on the gate insulating layer If the expression is "gate electrode," it means that there are no other components between the gate insulating layer and the first gate electrode. We will not exclude anything that is included. Also, the terms "upper" and "lower" are expressions used for the sake of explanation. This does not include merely the inverted form, and unless otherwise specified, it also includes the reversed form.

[0023] Furthermore, in this specification, the terms "electrode" and "wiring" refer to these components functionally. It is not limited to this. For example, "electrode" can be used as part of "wiring". And the reverse is also true. Furthermore, the terms "electrode" and "wiring" refer to multiple "electrodes". This also includes cases where the "wiring" is formed as an integrated part.

[0024] Furthermore, the "source" and "drain" functions are used when employing transistors with different polarities. However, this can change when the direction of current changes during circuit operation. In this specification, the terms "source" and "drain" are interchangeable. It is assumed that this is possible.

[0025] In this specification, "electrically connected" means "having some kind of electrical effect." This includes cases where the connection is made via a means of "something that has some electrical effect." This means that there are no particular restrictions as long as it enables the exchange of electrical signals between connected objects.

[0026] For example, "something that has some kind of electrical effect" includes not only electrodes and wiring, but also... Switching elements such as inverters, resistive elements, inductors, capacitors, and various other components. This includes elements that possess certain capabilities.

[0027] Furthermore, generally speaking, an "SOI substrate" is a substrate in which a silicon semiconductor layer is provided on an insulating surface. However, in this specification, a semiconductor layer made of a material other than silicon is provided on the insulating surface. It is used as a concept that also includes substrates with the constructed configuration. In other words, the semiconductor layer that the "SOI substrate" has This is not limited to silicon semiconductor layers. Also, the substrate in the "SOI substrate" is silicon This applies not only to semiconductor substrates such as wafers, but also to glass substrates, quartz substrates, sapphire substrates, and metal substrates. This includes any non-semiconductor substrate. In other words, a semiconductor on a conductive substrate or an insulating substrate having an insulating surface. The term "SOI substrate" broadly includes those having layers made of materials. Furthermore, in this specification... Furthermore, the term "semiconductor substrate" refers not only to a substrate made solely of semiconductor materials, but also to a substrate made of semiconductor materials. This refers to all substrates, including those containing SOI substrates. In other words, in this specification, "SOI substrate" is also broadly referred to as " It is listed under "semiconductor substrate".

[0028] Furthermore, in this specification, "materials other than oxide semiconductors" means any material other than an oxide semiconductor. Any material is acceptable. For example, silicon, germanium, silicon germanium. Examples include um, silicon carbide, gallium arsenide, etc. Other methods include using organic semiconductor materials. It is also possible. Furthermore, unless otherwise specified, materials constituting semiconductor devices, etc., are oxides. Either semiconductor materials or materials other than oxide semiconductors may be used. [Effects of the Invention]

[0029] In one aspect of the present invention, the lower part has a transistor made of a material other than an oxide semiconductor, and the upper A semiconductor device having a transistor made of an oxide semiconductor is provided.

[0030] Transistors using oxide semiconductors have extremely low off-currents, so we decided to use them. It is possible to retain memory content for an extremely long period of time. In other words, refresh function This eliminates the need for manual operation, or makes it possible to significantly reduce the frequency of refresh operations. Therefore, power consumption can be significantly reduced. Also, even if there is no power supply... It is possible to retain memory content over a long period of time.

[0031] Furthermore, it does not require high voltage for writing information, and there are no problems with element degradation. This involves injecting and extracting charge into a floating gate, similar to non-volatile memory. Since it is not necessary, no deterioration of the gate insulating layer occurs at all. In other words, according to the present invention The semiconductor device does not have the limitations on the number of rewrite cycles that are a problem with conventional non-volatile memory. This dramatically improves reliability. Furthermore, it enables switching between the on and off states of transistors. Therefore, since information is written, high-speed operation can be easily achieved. Also, flash The advantage is that it eliminates the need to erase information required in memory, etc. There's also a to.

[0032] Furthermore, transistors using materials other than oxide semiconductors are different from transistors using oxide semiconductors. Compared to standard, it allows for even faster operation, and by using this, the stored contents can be processed It is possible to perform reading at high speed.

[0033] Furthermore, by providing a boost circuit, it becomes easier to multi-level data that can be stored, thus increasing storage capacity. It is possible to improve this.

[0034] Thus, transistors using materials other than oxide semiconductors and transistors using oxide semiconductors By integrating a transistor, a semiconductor device with unprecedented features can be realized. It is possible. [Brief explanation of the drawing]

[0035] [Figure 1] A circuit diagram used to explain a semiconductor device. [Figure 2] Cross-sectional and plan views illustrating a semiconductor device. [Figure 3] A cross-sectional diagram illustrating the manufacturing process of semiconductor devices. [Figure 4] A cross-sectional diagram illustrating the manufacturing process of semiconductor devices. [Figure 5] A cross-sectional diagram illustrating the manufacturing process of semiconductor devices. [Figure 6] Cross-sectional view of a transistor using an oxide semiconductor. [Figure 7] The energy band diagram (schematic diagram) in the A-A' section of Figure 6. [Figure 8] (A) shows the state where a positive voltage (VG>0) is applied to the gate (GE1), and (B) shows the state where a negative voltage (VG<0) is applied to the gate (GE1). [Figure 9] This diagram shows the relationship between the vacuum level, the work function (φM) of metals, and the electron affinity (χ) of oxide semiconductors. [Figure 10] A diagram showing the CV characteristics. [Figure 11] A diagram showing the relationship between Vg and (1 / C)². [Figure 12] A cross-sectional diagram illustrating a semiconductor device. [Figure 13] A cross-sectional diagram illustrating a semiconductor device. [Figure 14] A cross-sectional diagram illustrating a semiconductor device. [Figure 15] A cross-sectional diagram illustrating a semiconductor device. [Figure 16] A circuit diagram used to explain a semiconductor device. [Figure 17] A block circuit diagram used to explain a semiconductor device. [Figure 18] A circuit diagram used to explain a semiconductor device. [Figure 19] A circuit diagram used to explain a semiconductor device. [Figure 20] A circuit diagram used to explain a semiconductor device. [Figure 21] A circuit diagram used to explain a semiconductor device. [Figure 22] A circuit diagram used to explain a semiconductor device. [Figure 23] A circuit diagram used to explain a semiconductor device. [Figure 24] A circuit diagram used to explain a semiconductor device. [Figure 25] A timing chart illustrating the write and read operations of a semiconductor device. [Figure 26] A circuit diagram used to explain a semiconductor device. [Figure 27] A block circuit diagram used to explain a semiconductor device. [Figure 28] A circuit diagram used to explain a semiconductor device. [Figure 29] A circuit diagram used to explain a semiconductor device. [Figure 30] A graph showing the relationship between the potential of the word line WL and node A. [Figure 31] A timing chart diagram illustrating the readout operation for a semiconductor device. [Figure 32] A diagram illustrating electronic devices using semiconductor devices. [Modes for carrying out the invention]

[0036] An example of an embodiment of the present invention will be described below with reference to the drawings. However, the present invention is as follows The description is not limited to the present invention, and without departing from the spirit and scope of the present invention, its form and Those skilled in the art will readily understand that the details can be modified in various ways. Therefore, the present invention is as follows: The description of the embodiment shown is not to be limited to the content described therein.

[0037] Furthermore, the position, size, and scope of each component shown in the drawings are, for the sake of easier understanding, The actual location, size, and range may not be represented. Therefore, the drawings may not always show the actual location, size, or range. It is not limited to the indicated location, size, or range.

[0038] Furthermore, the ordinal numbers such as "1st," "2nd," and "3rd" used in this specification are intended to avoid confusion of constituent elements. It should be noted that this is added to avoid the issue and does not limit the number of occurrences.

[0039] (Embodiment 1) In this embodiment, the configuration and manufacturing method of a semiconductor device according to one aspect of the disclosed invention are described below. This will be explained with reference to Figures 1 to 15.

[0040] <Circuit configuration of semiconductor device> Figure 1 shows an example of the circuit configuration of a semiconductor device. This semiconductor device is made of materials other than oxide semiconductors. It consists of a transistor 160 made of material and a transistor 162 made of oxide semiconductor. This is achieved. In Figure 1, transistor 162 is an oxide semiconductor (Oxide S To clearly indicate that an emiconductor was used, the OS code was added. The same applies to the following embodiments.

[0041] Here, the gate electrode of transistor 160 and the source electrode or dot of transistor 162 It is electrically connected to one of the rain electrodes. Also, the first line The source wire (also called SL) and the source electrode of transistor 160 are electrically connected. The second line (also called the bit line BL) and the dray of transistor 160 The electrodes are electrically connected. And the third wire (3rd Line: 1st signal) The other side of the source electrode or drain electrode of transistor 162 (also called line S1) Electrically connected, the fourth wire (4th Line: also called the second signal line S2), and the transistor It is electrically connected to the gate electrode of the inverter 162.

[0042] Transistor 160, which uses materials other than oxide semiconductors, is a transistor that uses oxide semiconductors. Compared to standard, it allows for even faster operation, and by using this, the stored contents can be processed It is possible to perform readouts and other operations at high speed. Furthermore, it uses an oxide semiconductor transistor. Transistor 162 has the characteristic of having an extremely low off-current. Therefore, transistor 1 By turning off 62, the potential of the gate electrode of transistor 160 can be kept at that level for an extremely long time. It is possible to hold it over time. Also, with the oxide semiconductor transistor 162 This also has the advantage of making short-channel effects less likely to occur.

[0043] By taking advantage of the characteristic that the potential of the gate electrode can be maintained for a long period of time, Information can be written, stored, and read as follows:

[0044] First, we will explain how to write and retain information. First, the potential of the fourth wire is... The potential at which transistor 162 turns on is set to the ON state, and transistor 162 is turned ON. As a result, the potential of the third wire is applied to the gate electrode of transistor 160 (write (Including). Then, the potential of the fourth wire is set as the potential at which transistor 162 is in the off state. By turning off transistor 162, the gate electrode of transistor 160 The electric potential is maintained (held).

[0045] Since the off-current of transistor 162 is extremely small, the gate electrode of transistor 160 The potential is maintained for a long time. For example, the potential of the gate electrode of transistor 160 is If the potential is such that transistor 160 is turned on, then the on state of transistor 160 will last for a long time. This will be maintained over time. Also, the potential of the gate electrode of transistor 160 If the potential is such that transistor 160 is in the off state, then transistor 160 will remain in the off state for a long time. It is retained over time.

[0046] Next, we will explain how to read the information. As mentioned above, the ON state of transistor 160 Alternatively, when the OFF state is maintained, a predetermined potential (low potential) is applied to the first wiring. When this happens, the potential of the second wiring differs depending on whether transistor 160 is on or off. It takes the value of . For example, when transistor 160 is ON, the potential of the first wiring is As a result, the potential of the second wiring decreases. Conversely, transistor 160 is In the "F" state, the potential of the second wiring does not change.

[0047] In this way, while the information is retained, the potential of the second wiring is compared with a predetermined potential. This allows us to extract the information.

[0048] Next, we will explain how to rewrite information. Rewriting information involves writing the information as described above and This is done in the same way as holding. In other words, the potential of the fourth wire is set when transistor 162 is ON. To achieve this potential, transistor 162 is turned ON. This results in the potential of the third wiring. (A potential related to new information) is applied to the gate electrode of transistor 160. Then, The potential of the fourth wire is set to the potential at which transistor 162 is in the OFF state, By turning off 62, the new information is retained.

[0049] Thus, the semiconductor device relating to the disclosed invention directly generates information through subsequent writing. It is possible to rewrite the information. Therefore, it is necessary in flash memory and other applications. This eliminates the need for an erase operation, thus suppressing the decrease in operating speed caused by the erase operation. In other words, high-speed operation of semiconductor devices will be achieved.

[0050] Note that the above explanation refers to an n-type transistor (n-channel transistor) that uses electrons as carriers. This concerns the case where ) is used, but instead of an n-type transistor, holes are used as carriers. It goes without saying that a p-type transistor can be used.

[0051] Furthermore, in order to facilitate the maintenance of the potential of the gate electrode of transistor 160, It goes without saying that capacitive elements or the like can be added to the gate electrode of the 160.

[0052] <Planar and cross-sectional configurations of semiconductor devices> Figure 2 shows an example of the configuration of the semiconductor device described above. Figure 2(A) shows a cross-section of the semiconductor device. Figure 2(B) shows the planes of the semiconductor device. Here, Figure 2(A) is the same as Figure 2(B). This corresponds to the cross-section along lines A1-A2 and B1-B2. Figures 2(A) and 2(B) The semiconductor device shown in ) has a transistor 160 at the bottom that uses a material other than an oxide semiconductor. It has a transistor 162 made of oxide semiconductor on its upper part. Transistor 160 and transistor 162 are both described as n-type transistors. However, a p-type transistor may also be used. In particular, transistor 160 should be a p-type transistor. This is possible.

[0053] The transistor 160 is located in a channel formation region 11 provided on a substrate 100 containing semiconductor material. 6 and the impurity region 114 and high concentration impurity region provided so as to sandwich the channel formation region 116. The pure material region 120 (these are also simply called the impurity region) and the channel-forming region 11 A gate insulating layer 108 provided on 6, and a gate electrode provided on the gate insulating layer 108 Source electrode or drain electrode 130a that is electrically connected to 110 and the impurity region 114. It has a source electrode or a drain electrode 130b.

[0054] Here, a sidewall insulating layer 118 is provided on the side surface of the gate electrode 110. Furthermore, as shown in the cross-sectional view of the substrate 100, there is a region that does not overlap with the sidewall insulating layer 118. It has a high-concentration impurity region 120, and on the high-concentration impurity region 120 there is a metal compound region 1 24 exists. Also, on the substrate 100, element isolation and insulation surround the transistor 160. A layer 106 is provided, and an interlayer insulating layer 126 and cover the transistor 160. An interlayer insulating layer 128 is provided. Source electrode or drain electrode 130a, source electrode The electrode or drain electrode 130b is formed in the interlayer insulating layer 126 and the interlayer insulating layer 128. It is electrically connected to the metal compound region 124 through the opening. In other words, the source electrode. Alternatively, the drain electrode 130a, source electrode, or drain electrode 130b is a metal compound region. Electrically connected to the high-concentration impurity region 120 and the impurity region 114 via region 124. It is. Also, the gate electrode 110 has a source electrode or drain electrode 130a and a source electrode Electrode 130c, which is provided similarly to electrode or drain electrode 130b, is electrically connected. ru.

[0055] The transistor 162 has a gate electrode 136d provided on the interlayer insulating layer 128, and a gate A gate insulating layer 138 provided on electrode 136d, and a gate insulating layer 138 provided on An oxide semiconductor layer 140, and provided on the oxide semiconductor layer 140, and The electrically connected source electrode or drain electrode 142a, source electrode or drain It has an in electrode 142b.

[0056] Here, the gate electrode 136d is embedded in the insulating layer 132 formed on the interlayer insulating layer 128. It is provided so as to be inserted. Also, similar to the gate electrode 136d, the source electrode or Electrode 136a is in contact with drain electrode 130a, and is connected to source electrode or drain electrode 130b Electrode 136b is formed in contact with electrode 130c, and electrode 136c is formed in contact with electrode 130c. ru.

[0057] Furthermore, a protective layer is placed on top of the transistor 162 so as to be in contact with a portion of the oxide semiconductor layer 140. An insulating layer 144 is provided, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, openings reaching the source electrode or drain electrode 142a and the source electrode or drain electrode 142b are provided in the protective insulating layer 144 and the interlayer insulating layer 146. Through the openings, electrodes 150d and 150e are formed in contact with the source electrode or drain electrode 142a and the source electrode or drain electrode 142b. Also, similar to the electrodes 150d and 150e, electrodes 150a, 150b, and 150c are formed in contact with the electrodes 136a, 136b, and 136c through the openings provided in the gate insulating layer 138, the protective insulating layer 144, and the interlayer insulating layer 146.

[0058] Here, it is desirable that the oxide semiconductor layer 140 is sufficiently purified by removing impurities such as hydrogen. Specifically, the hydrogen concentration in the oxide semiconductor layer 140 is 5×10 19 atoms / cm 3 or less, preferably 5×10 18 atoms / cm 3 or less, more preferably 5×10 atoms / cm 17 or less. 3 Also, in the oxide semiconductor layer 140 with a sufficiently reduced hydrogen concentration and high purity, the carrier concentration is sufficiently small compared to that in a general silicon wafer (a silicon wafer doped with trace amounts of impurity elements such as phosphorus and boron) (about 1×10 1 4 / cm 3 ). 3 That is, the carrier concentration of the oxide semiconductor layer 140 is 1×10 / cm 12 or less, preferably 1×10 3 / 11 / cm ​​​​cm 3 The following applies. In this way, the hydrogen concentration is sufficiently reduced and the purity is increased, and the i-type (true By using a (modified) or substantially i-type oxide semiconductor, extremely good off-current is achieved. A transistor 162 with the desired characteristics can be obtained. For example, if the drain voltage Vd is +1V or This is for +10V, and when the gate voltage Vg is in the range of -5V to -20V, the off-current is 1 x 10 -13 It is A or less. Thus, the hydrogen concentration is sufficiently reduced, and intrinsic or A substantially intrinsically activated oxide semiconductor layer 140 is applied, and the off-current of transistor 162 is By reducing the acid, it is possible to realize semiconductor devices with new configurations. The hydrogen concentration in the hydrogenated semiconductor layer 140 was determined by secondary ion mass spectrometry (SIMS). This was measured using ion mass spectrometry (ION).

[0059] Furthermore, an insulating layer 152 is provided on the interlayer insulating layer 146, and embedded in the insulating layer 152. Electrodes 154a, 154b, 154c, and 154d are provided so as to be inserted. Here, electrode 154a is in contact with electrode 150a, and electrode 154b is in contact with electrode 150 It is in contact with b, and electrode 154c is in contact with electrode 150c and electrode 150d, and electrode 1 Electrode 54d is in contact with electrode 150e.

[0060] In other words, in the semiconductor device shown in Figure 2, the gate electrode 110 of transistor 160 and The source electrode or drain electrode 142a of the lampistor 162 is connected to electrode 130c, electrode 1 36c, electrode 150c, electrode 154c and electrode 150d are electrically connected. ru.

[0061] <Method for fabricating semiconductor devices> Next, we will describe an example of a method for manufacturing the above semiconductor device. Below, we will first explain the lower part The method for fabricating the transistor 160 will be explained with reference to Figure 3, and then the upper transistor The method for manufacturing Ta162 will be explained with reference to Figures 4 and 5.

[0062] <Method for fabricating the lower transistor> First, prepare a substrate 100 containing semiconductor material (see Figure 3(A)). The plate 100 can be a single-crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor substrate. Compound semiconductor substrates such as silicon germanium, SOI substrates, etc. can be applied. Here, we will use a single-crystal silicon substrate as the substrate 100 containing semiconductor material. One example will be provided.

[0063] A protective layer 102 is formed on the substrate 100, which serves as a mask for forming an element isolation insulating layer. (See Figure 3(A)). The protective layer 102 can be, for example, silicon oxide or silicon nitride. An insulating layer made of silicon nitride or similar material can be used. In order to control the threshold voltage of the transistor, an impurity is imparted to impart n-type conductivity. Monochemical elements or impurity elements that impart p-type conductivity may be added to the substrate 100. In the case of ricon, impurities that impart n-type conductivity include, for example, phosphorus and arsenic. This can be achieved. Furthermore, examples of impurities that impart p-type conductivity include boron and aluminum. Materials such as nium and gallium can be used.

[0064] Next, etching is performed using the protective layer 102 as a mask, and the material covered by the protective layer 102 is then... A portion of the substrate 100 in the area that is not present (exposed area) is removed. This separates the half A conductive region 104 is formed (see Figure 3(B)). Dry etching is used for this etching process. It is preferable to use an etching gas, but wet etching may also be used. The etching solution can be appropriately selected depending on the material to be etched.

[0065] Next, an insulating layer is formed to cover the semiconductor region 104, and the region superimposed on the semiconductor region 104 By selectively removing the insulating layer, an element isolation insulating layer 106 is formed (see Figure 3(B)). The insulating layer is formed using silicon oxide, silicon nitride, silicon nitride oxide, etc. Methods for removing the insulating layer include polishing treatments such as CMP and etching treatments. Either of these may be used. Note that after the formation of the semiconductor region 104, or after device isolation and insulation After the formation of layer 106, the protective layer 102 is removed.

[0066] Next, an insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer. ru.

[0067] The insulating layer will later become the gate insulating layer, and can be obtained using methods such as CVD or sputtering. Silicon oxide, silicon nitride, silicon nitride, hafnium oxide, aluminum oxide A single-layer or multi-layer structure of a film containing aluminum, tantalum oxide, etc. is preferable. By oxidizing and nitriding the surface of the semiconductor region 104 through lazma treatment or thermal oxidation treatment, The above insulating layer may be formed. High-density plasma treatment may be performed using, for example, He, Ar, Kr, Using noble gases such as Xe and mixed gases such as oxygen, nitrogen oxides, ammonia, nitrogen, and hydrogen This can be done. Furthermore, the thickness of the insulating layer is not particularly limited, but for example, 1 nm or more. It can be reduced to 0 nm or less.

[0068] The layer containing conductive material is made of metallic materials such as aluminum, copper, titanium, tantalum, and tungsten. It can be formed using semiconductor materials such as polycrystalline silicon containing conductive materials. A layer containing a conductive material may be formed using [a specific method]. The formation method is not particularly limited and may include vapor deposition, C [another specific method]. Various film deposition methods such as the VD method, sputtering method, and spin coating method can be used. In this embodiment, an example of forming a layer containing a conductive material using a metal material is described below. This shall be shown.

[0069] Subsequently, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 108 , forming the gate electrode 110 (see Figure 3(C)).

[0070] Next, an insulating layer 112 is formed to cover the gate electrode 110 (see Figure 3(C)). Then, half By adding phosphorus (P) or arsenic (As) to the conductive region 104, a shallow bonding depth with the substrate 100 is achieved. This forms an impurity region 114 (see Figure 3(C)). Note that this is an n-type transistor. Phosphorus or arsenic is added to form the transistor, but when forming a p-type transistor, You can add impurity elements such as boron (B) or aluminum (Al). The formation of region 114 results in the formation of a channel beneath the gate insulating layer 108 of the semiconductor region 104. Region 116 is formed (see Figure 3(C)). Here, the concentration of the added impurities is set as appropriate. However, when semiconductor devices are miniaturized to a high degree, it is possible to increase the concentration. This is desirable. Also, here, the impurity region 114 is formed after the insulating layer 112 is formed. The process employs a method of forming an insulating layer 112 after forming an impurity region 114. That's also acceptable.

[0071] Next, the sidewall insulating layer 118 is formed (see Figure 3(D)). Layer 118 is formed to cover the insulating layer 112, and then an insulating layer is formed to provide high anisotropy to the insulating layer. By applying an etching process, it can be formed in a self-aligned manner. Then, the insulating layer 112 is partially etched, and the upper surface of the gate electrode 110 and the impurity region 1 It's best to expose the top surface of part 14.

[0072] Next, to cover the gate electrode 110, impurity region 114, sidewall insulating layer 118, etc. Then, an insulating layer is formed. And in the region where the insulating layer is in contact with the impurity region 114, phosphorus ( By adding P or arsenic (As), a high-concentration impurity region 120 is formed (see Figure 3(E)). (Illuminate). After that, remove the above insulating layer, gate electrode 110, sidewall insulating layer 118, A metal layer 122 is formed to cover the high-concentration impurity region 120, etc. (See Figure 3(E)). The metal layer 122 is formed by various thin-film deposition methods such as vacuum deposition, sputtering, and spin coating. It can be formed using the semiconductor material that constitutes the semiconductor region 104. It is desirable to form this using a metallic material that reacts with the material to form a low-resistance metallic compound. Examples of such metallic materials include titanium, tantalum, tungsten, nickel, and cobalt. Examples include platinum, etc.

[0073] Next, heat treatment is performed to react the metal layer 122 with the semiconductor material. This results in high A metal compound region 124 is formed adjacent to the concentration impurity region 120 (see Figure 3(F)). Furthermore, when using polycrystalline silicon or the like as the gate electrode 110, A metal compound region will also be formed in the area that comes into contact with the metal layer 122.

[0074] As for the above heat treatment, for example, heat treatment by irradiation with a flash lamp can be used. Of course, other heat treatment methods may be used, but the chemical reaction involved in the formation of metal compounds is important. To improve controllability, it is desirable to use a method that enables very short heat treatment times. It appears that the above-mentioned metallic compound region is formed by the reaction between a metallic material and a semiconductor material. This is a region in which conductivity is sufficiently enhanced. This allows for a significant reduction in electrical resistance and improvement of the device characteristics. After forming region 124, the metal layer 122 is removed.

[0075] Next, an interlayer insulating layer 126 and an interlayer insulating layer are formed to cover each of the components formed by the above process. Forms 128 (see Figure 3(G)). Interlayer insulating layers 126 and 128 are formed of oxides Silicon nitride, silicon nitride, hafnium oxide, aluminum oxide, tahnix oxide It can be formed using materials containing inorganic insulating materials such as tar. Also, polyimide, It is also possible to form it using organic insulating materials such as acrylic. The structure consists of two layers: an edge layer 126 and an interlayer insulating layer 128. However, the configuration of the interlayer insulating layer is not limited to this. No. After the formation of the interlayer insulating layer 128, its surface is subjected to CMP or etching treatment, etc. Therefore, it is desirable to flatten it.

[0076] Subsequently, an opening is formed in the interlayer insulating layer that extends to the metal compound region 124, and the opening The source electrode or drain electrode 130a and the source electrode or drain electrode 130b are connected to the source electrode or drain electrode 130a. Form (see Figure 3(H)). Source electrode or drain electrode 130a or source electrode or The drain electrode 130b is, for example, subjected to PVD or CVD methods in the region including the opening. After forming the conductive layer, a part of the conductive layer is removed using methods such as etching or CMP. It can be formed by removing [something].

[0077] Furthermore, a portion of the above conductive layer can be removed to form the source electrode or drain electrode 130a or source electrode. Alternatively, when forming the drain electrode 130b, the surface is processed to be flat. This is desirable. For example, after forming a thin titanium film or titanium nitride film in the region including the opening, When forming a tungsten film to fill an opening, subsequent CMP (Chemical Polishing) can cause problems. The necessary tungsten film, titanium film, titanium nitride film, etc., are removed, and the flatness of the surface is improved. This can improve the source electrode or drain electrode 130a, By planarizing the surface including the drain electrode 130b, in subsequent processes This makes it possible to form good electrodes, wiring, insulating layers, semiconductor layers, etc.

[0078] In this case, the source electrode or drain electrode 130 that comes into contact with the metal compound region 124 Although only a and the source electrode or drain electrode 130b are shown, in this process, The electrode that comes into contact with the electrode 110 (for example, electrode 130c in Figure 2) is then combined to form This can be achieved. Source electrode or drain electrode 130a, source electrode or drain There are no particular limitations on the material that can be used as electrode 130b; various conductive materials can be used. It can be used. For example, molybdenum, titanium, chromium, tantalum, tungsten, Conductive materials such as aluminum, copper, neodymium, and scandium can be used.

[0079] As a result, a transistor 160 is formed using a substrate 100 containing semiconductor material. After the above process, electrodes, wiring, insulating layers, etc. may be formed. Furthermore, by adopting a multilayer wiring structure consisting of a laminated structure of interlayer insulating layers and conductive layers, high We can provide a semiconductor device with integrated components.

[0080] <Method for fabricating the upper transistor> Next, using Figures 4 and 5, the process of fabricating the transistor 162 on the interlayer insulating layer 128 is described. The process will be explained. Figures 4 and 5 show various electrodes on the interlayer insulating layer 128 and the trap. This shows the manufacturing process for transistor 162, and is therefore located at the bottom of transistor 162. Details regarding transistor 160 and other components have been omitted.

[0081] First, the interlayer insulating layer 128, the source electrode or drain electrode 130a, the source electrode or drain An insulating layer 132 is formed on the rain electrode 130b and electrode 130c (see Figure 4(A)). The marginal layer 132 can be formed using methods such as PVD or CVD. Silicon nitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide It can be formed using materials containing inorganic insulating materials such as ru.

[0082] Next, the source electrode or drain electrode 130a, source electrode or An opening is formed that extends to the drain electrode 130b and electrode 130c. An opening is also formed in the region where the gate electrode 136d is formed. A conductive layer 134 is formed to embed it (see Figure 4(B)). The above opening is made using a mask. It can be formed by methods such as etching. The mask is a photomask. It can be formed by methods such as exposure. Etching can be done using wet etching. Either etching or dry etching can be used, but from the perspective of microfabrication, dry etching is preferable. It is preferable to use a ching. The conductive layer 134 is formed by methods such as PVD or CVD. This can be done using a film method. Materials that can be used to form the conductive layer 134 include Molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium Examples include conductive materials such as scandium, as well as alloys and compounds of these materials (e.g., nitrides). It is possible.

[0083] More specifically, for example, a thin titanium film is formed in the region including the opening by the PVD method, and CV After forming a thin titanium nitride film using method D, a tungsten film was formed to embed it in the opening. A method can be applied to achieve this. Here, the titanium film formed by the PVD method is below Partial electrode (here, source electrode or drain electrode 130a, source electrode or drain electrode The oxide film on the surface of electrodes (such as electrode 130b and electrode 130c) is reduced, thereby lowering the contact resistance with the lower electrode. It has the function of causing [something]. Furthermore, the titanium nitride film that is formed afterward suppresses the diffusion of the conductive material. It has a barrier function that controls it. In addition, a barrier film made of titanium or titanium nitride is formed. Later, a copper film may be formed by a plating method.

[0084] After forming the conductive layer 134, the conductive layer 1 is formed using methods such as etching and CMP. Remove a portion of 34 to expose the insulating layer 132, and then remove electrode 136a, electrode 136b, electrode 1 36c, forming the gate electrode 136d (see Figure 4(C)). Note that the conductive layer 134 By removing a portion, electrodes 136a, 136b, 136c, and gate electrode 136d are formed. When doing so, it is desirable to process the surface so that it becomes flat. In this way, insulating layer 13 2. Planarize the surfaces of electrode 136a, electrode 136b, electrode 136c, and gate electrode 136d. This allows for the formation of good electrodes, wiring, insulating layers, semiconductor layers, etc., in subsequent processes. This becomes possible.

[0085] Next, insulating layer 132, electrode 136a, electrode 136b, electrode 136c, gate electrode 136d A gate insulating layer 138 is formed to cover it (see Figure 4(D)). Gate insulating layer 138 This can be formed using methods such as CVD or sputtering. Also, the gate insulating layer 138 is silicon oxide, silicon nitride, silicon oxide nitride, silicon oxide nitride, aluminum oxide, oxide It is preferable to form the gate insulation to include hafnium, tantalum oxide, etc. Layer 138 may be a single-layer structure or a multi-layer structure. For example, as a raw material gas By plasma CVD using silane (SiH4), oxygen, and nitrogen, silicon oxide nitride is produced. A gate insulating layer 138 can be formed. The thickness of the gate insulating layer 138 is not particularly limited. However, it is not possible to set it to, for example, 10 nm to 500 nm. For example, a first gate insulating layer with a film thickness of 50 nm or more and 200 nm or less, and the first gate insulating It is preferable to laminate a second gate insulating layer with a thickness of 5 nm to 300 nm on the layer.

[0086] Furthermore, by removing impurities, the oxide semiconductor can be made i-type or substantially i-type (high Purified oxide semiconductors are extremely sensitive to interface states and interface charges, therefore When using oxide semiconductors like the one shown in the image for the oxide semiconductor layer, the interface with the gate insulating layer is important. Therefore, the gate insulating layer 138 in contact with the highly purified oxide semiconductor layer is made of high-grade material. This will require a change in quality.

[0087] For example, high-density plasma CVD using μ-wave (2.45 GHz) is a method that produces dense materials with high dielectric strength. It is suitable in that it can form a high-quality gate insulating layer 138. The contact between the conductor layer and the high-quality gate insulating layer reduces the interface state and improves the interface properties. Because it can be made into something like that.

[0088] Of course, if it can form a good insulating layer as a gate insulating layer, then high-purity material Even when using an oxide semiconductor layer, other methods such as sputtering and plasma CVD are used. The method can be applied. Furthermore, by heat treatment after formation, the film quality and oxide semiconductor layer can be modified. An insulating layer that modifies the interface properties may be applied. In any case, the gate insulating layer 138 The film quality is good, and the interface level density with the oxide semiconductor layer is reduced, resulting in a good interface. You just need to create something that can form a surface.

[0089] When impurities are present in an oxide semiconductor, stress such as a strong electric field or high temperature can cause them to... The bond between the impurity and the main component of the oxide semiconductor is broken, and the resulting unbonded bonds reach the threshold voltage. This induces a shift in (Vth).

[0090] In contrast, impurities in oxide semiconductors, especially hydrogen and water, are removed as much as possible, as described above. By improving the interface characteristics with the gate insulating layer, stress such as strong electric fields and high temperatures can be reduced. It is possible to obtain a stable transistor even under these conditions.

[0091] Next, an oxide semiconductor layer is formed on the gate insulating layer 138, and etching is performed using a mask. The oxide semiconductor layer is processed by methods such as those described above to form island-shaped oxide semiconductor layers 140. (See Figure 4(E)).

[0092] Examples of oxide semiconductor layers include the quaternary metal oxide In-Sn-Ga-Zn-O system and the three-layer system. The original metal oxide systems are In-Ga-Zn-O, In-Sn-Zn-O, and In-Al- Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn-O Systems such as the In-Zn-O system, Sn-Zn-O system, and Al-Zn-O system, which are binary metal oxides. Zn-Mg-O system, Sn-Mg-O system, In-Mg-O system, In-O system, Sn-O system Furthermore, oxide semiconductor layers such as Zn-O can be applied. The material may contain SiO2.

[0093] Furthermore, the oxide semiconductor layer is InMO3(ZnO) m We use thin films denoted as (m>0). This is possible. Here, M is one or more golds selected from Ga, Al, Mn, and Co. This indicates the group element. For example, M could be Ga, Ga and Al, Ga and Mn, or Ga and C. Examples include o. InMO3(ZnO) m Among oxide semiconductor films denoted as (m>0), Oxide semiconductors with a composition containing Ga as M are called In-Ga-Zn-O oxide semiconductors. , the thin film is an In-Ga-Zn-O based oxide semiconductor film (In-Ga-Zn-O based amorphous film We will refer to it as such.

[0094] In this embodiment, the oxide semiconductor layer is an In-Ga-Zn-O based oxide semiconductor film deposition material. Using a target, an amorphous oxide semiconductor layer is formed by sputtering. Furthermore, by adding silicon to the amorphous oxide semiconductor layer, its crystallization is suppressed. Therefore, for example, a target containing 2% to 10% by weight of SiO2. An oxide semiconductor layer may be formed using [a specific method / tool].

[0095] For example, an oxide semiconductor layer can be fabricated using the sputtering method. A zinc-based oxide semiconductor film deposition target can be used. As a target for depositing Ga-Zn-O based oxide semiconductor films, In2O3:Ga2O3:Z Targets with a composition ratio of nO = 1:1:1 [mol ratio] can also be used. Furthermore, as a target for In-Ga-Zn-O based oxide semiconductor film deposition, In2O3:G a2O3:ZnO=1:1:2 [mol ratio], or In2O3:Ga2O3:ZnO= A target with a composition ratio of 1:1:4 [mol ratio] may also be used. Oxide semiconductor The filling rate of the film deposition target is 90% or more and 100% or less, preferably 95% or more (for example, 9 It is 9.9%. By using an oxide semiconductor film deposition target with a high packing density, A dense oxide semiconductor layer is formed.

[0096] The formation atmosphere for oxide semiconductor layers can be a noble gas atmosphere (typically argon), an oxygen atmosphere, or... Alternatively, a mixed atmosphere of a noble gas (typically argon) and oxygen is preferable. In terms of, for example, impurities such as hydrogen, water, compounds having a hydroxyl group or hydrides, it is preferable to use high-purity gas in which the concentration of impurities is reduced to about several ppm (preferably about several ppb). is preferable.

[0097] When forming the oxide semiconductor layer, the substrate is held in a processing chamber maintained in a reduced-pressure state, and the substrate temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor layer while heating the substrate, the impurity concentration contained in the oxide semiconductor layer can be reduced. Further, damage to the oxide semiconductor layer due to sputtering is reduced. And, while removing residual moisture in the processing chamber, a sputtering gas from which hydrogen and water have been removed is introduced, and an oxide semiconductor layer is formed using a metal oxide as a target. To remove residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. Also, as an exhaust stage, a turbo pump with a cold trap added thereto may be used. A film formation chamber evacuated using a cryopump exhausts compounds containing hydrogen atoms such as hydrogen atoms, water (H2O), etc., and compounds containing carbon atoms, etc. Therefore, the concentration of impurities contained in the oxide semiconductor layer formed in the film formation chamber can be reduced. [[ID=二十]] As forming conditions, for example, conditions such as the distance between the substrate and the target being 10mm, the pressure being 0.6 Pa, the direct current (DC) power being 0.5 kW, and the atmosphere being an oxygen (oxygen flow rate ratio 100%) atmosphere can be applied. When using a pulsed direct current (DC) power supply, powdery substances (also referred to as particles or dust) generated during film formation can be reduced, and the film thickness distribution can also be made smaller.

[0098] ​​​​​​​​​​​​​​ Therefore, it is preferable. The thickness of the oxide semiconductor layer is 2 nm or more and 200 nm or less, preferably 5 nm or more and 30 nm or less. Note that the appropriate thickness varies depending on the oxide semiconductor material to be applied, so the thickness may be appropriately selected according to the material used.

[0099] Note that before forming the oxide semiconductor layer by sputtering, it is preferable to perform reverse sputtering in which argon gas is introduced to generate plasma and remove dust adhering to the surface of the gate insulating layer 138. Here, reverse sputtering means that in the normal sputtering method, ions are collided with the sputter target, whereas, conversely, the surface is modified by colliding ions with the processing surface. The method of colliding ions with the processing surface includes a method of applying a high-frequency voltage to the processing surface side in an argon atmosphere to generate plasma near the substrate. Note that instead of an argon atmosphere, a nitrogen atmosphere, a helium atmosphere, an oxygen atmosphere, or the like may be used. The above-mentioned etching of the oxide semiconductor layer may use either dry etching or wet etching. Of course, both may be used in combination. The etching conditions (etching gas, etching solution, etching time, temperature, etc.) are appropriately set according to the material so that etching can be performed into a desired shape. Examples of the etching gas used for dry etching include gases containing chlorine (chlorine-based gases, for example, chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrachloride (CCl4), etc.). Also, gases containing fluorine (fluorine-based gases, for example, tetrafluoride For the method of colliding ions with the processing surface, a high-frequency voltage is applied to the processing surface side in an argon atmosphere to generate plasma near the substrate. There are methods such as this. Note that instead of an argon atmosphere, a nitrogen atmosphere, a helium atmosphere, an oxygen atmosphere, etc. may be used. substrate. Examples of the method of colliding ions with the processing surface include applying a high-frequency voltage to the processing surface side in an argon atmosphere to generate plasma near the substrate. Note that instead of an argon atmosphere, a nitrogen atmosphere, a helium atmosphere, an oxygen atmosphere, etc. may be used. For the etching of the above-mentioned oxide semiconductor layer, either dry etching or wet etching may be used. Of course, both can be used in combination. The etching conditions (etching gas, etching solution, etching time, temperature, etc.) are appropriately set according to the material so that etching can be performed into a desired shape.

[0100] For the etching of the above oxide semiconductor layer, either dry etching or wet etching may be used. Of course, both can be used in combination. The etching conditions (etching gas, etching solution, etching time, temperature, etc.) are appropriately set according to the material so that etching can be performed into a desired shape. For dry etching, the etching gas used may include, for example, a gas containing chlorine (chlorine-based gas, for example, chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrachloride (CCl4), etc.). Also, a gas containing fluorine (fluorine-based gas, for example, tetrafluoride etching time, temperature, etc.) are appropriately set according to the material so that etching can be performed into a desired shape.

[0101] Examples of the etching gas used for dry etching include gases containing chlorine (chlorine-based gases, for example, chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrachloride (CCl4), etc.). Also, gases containing fluorine (fluorine-based gases, for example, tetrafluoride (CCl4), etc.). Also, gases containing fluorine (fluorine-based gases, for example, tetrafluoride Carbon (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoromethane ( CHF3, etc., hydrogen bromide (HBr), oxygen (O2), and helium (He) in these gases. Gases to which noble gases such as argon (Ar) have been added may also be used.

[0102] As for dry etching methods, parallel plate type RIE (Reactive Ion Etching) Methods such as the ing method and ICP (Inductively Coupled Plasma: induction) A coupled plasma etching method can be used. It can etch into the desired shape. Etching conditions (amount of power applied to the coil-type electrode, amount of power applied to the electrode on the substrate side) The power consumption, electrode temperature on the substrate, etc., should be set as appropriate.

[0103] Etching solutions used in wet etching include a solution of phosphoric acid, acetic acid, and nitric acid. You can use this. Alternatively, you may use ITO07N (manufactured by Kanto Chemical Co., Ltd.).

[0104] Next, it is desirable to perform a first heat treatment on the oxide semiconductor layer. This first heat treatment This allows for the dehydration or dehydrogenation of the oxide semiconductor layer. The temperature of the first heat treatment is The temperature should be between 300°C and 750°C, preferably above 400°C and below the substrate's strain point. For example, The substrate is introduced into an electric furnace using a resistance heating element, and the oxide semiconductor layer 140 is exposed to a nitrogen atmosphere. A heat treatment is performed at 450°C under atmospheric pressure for 1 hour. During this time, the oxide semiconductor layer 140 is exposed to the atmosphere. Avoid contact and prevent the re-introduction of water or hydrogen.

[0105] Furthermore, heat treatment equipment is not limited to electric furnaces; it also includes heat conduction from a heated medium such as gas, or It may also be a device that heats the object to be processed by thermal radiation. For example, RTA (Rapid Thermal Anneal) devices such as GRTA (Gas Rapid Thermal Anneal) devices and LRTA (Lamp Rapid Thermal Anneal) devices can be used. An LRTA device is a device that heats the object to be processed by the radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure mercury lamps. A GRTA device is a device that performs heat treatment using high-temperature gas. As the gas, noble gases such as argon, or inert gases such as nitrogen that do not react with the object to be processed by heat treatment are used. For example, as the first heat treatment, a GRTA treatment may be performed in which the substrate is introduced into an inert gas heated to a high temperature of 650°C to 700°C, heated for several minutes, and then the substrate is taken out from the inert gas. Using GRTA treatment enables high-temperature heat treatment in a short time. Also, because it is a short-time heat treatment, it can be applied even under temperature conditions exceeding the distortion point of the substrate.

[0106] Note that the first heat treatment is preferably performed in an atmosphere mainly composed of nitrogen or noble gases (helium, neon, argon, etc.) and containing no water, hydrogen, etc. For example the purity of the nitrogen or noble gases such as helium, neon, and argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0107]

[0108] ​​​​​Depending on the conditions of the first heat treatment, or the material of the oxide semiconductor layer, the oxide semiconductor layer may crystallize. Furthermore, it may be microcrystalline or polycrystalline. For example, the crystallinity rate may be 90% or more, or 80%. In some cases, a microcrystalline oxide semiconductor layer of % or more may be formed. Also, depending on the conditions of the first heat treatment, Depending on the material of the oxide semiconductor layer, it may become an amorphous oxide semiconductor layer that does not contain crystalline components. There are also combinations.

[0109] Furthermore, crystals (particle size 1 nm or larger) can form on amorphous oxide semiconductors (for example, on the surface of an oxide semiconductor layer). In the case of an oxide semiconductor layer containing a mixture of elements smaller than 20 nm (typically between 2 nm and 4 nm) There are also combinations.

[0110] Furthermore, by providing a crystalline layer on the surface of the amorphous region, the electrical properties of the oxide semiconductor layer can be changed. It is also possible to do so. For example, In-Ga-Zn-O based oxide semiconductor film deposition target When forming an oxide semiconductor layer using [a specific material], electrically anisotropic In2Ga2Zn By forming oriented crystalline regions of O7 crystal grains, the electrical properties of the oxide semiconductor layer are altered. It can be done.

[0111] More specifically, for example, if the c-axis of In2Ga2ZnO7 is perpendicular to the surface of the oxide semiconductor layer By orienting the material in a specific direction, the conductivity in the direction parallel to the surface of the oxide semiconductor layer is improved. This allows for improved insulation in the direction perpendicular to the surface of the oxide semiconductor layer. Crystalline regions like these have the function of suppressing the intrusion of impurities such as water and hydrogen into the oxide semiconductor layer. To possess.

[0112] Furthermore, the oxide semiconductor layer having the crystalline portion described above is processed by GRTA treatment. It can be formed by heat. Also, the Zn content is less than the In or Ga content. By using a sputtering target, it is possible to form the material more favorably.

[0113] The first heat treatment of the oxide semiconductor layer 140 involves processing it into island-shaped oxide semiconductor layers 140. This can also be done on the previous oxide semiconductor layer. In that case, after the first heat treatment, a heating device or The substrate is then removed and subjected to the photolithography process.

[0114] Furthermore, the first heat treatment described above has the effect of dehydrating and dehydrogenating the oxide semiconductor layer. This can also be called dehydration treatment, dehydrogenation treatment, etc. The process involves forming an oxide semiconductor layer, and then placing a source electrode or drain on the oxide semiconductor layer 140. After stacking the electrodes, a protective insulating layer is formed on the source electrode or drain electrode, etc. This can be done at the appropriate timing. The principle can be applied not just once, but multiple times.

[0115] Next, the source electrode or drain electrode 142a is brought into contact with the oxide semiconductor layer 140. A source electrode or drain electrode 142b is formed (see Figure 4(F)). The drain electrode 142a, the source electrode or drain electrode 142b are oxide semiconductor layer 1 After forming a conductive layer to cover 40, selectively etch the conductive layer by It can be formed.

[0116] The conductive layer is created using PVD methods such as sputtering, and CVD methods such as plasma CVD. It can be formed using the method. Furthermore, aluminum and chromium can be used as materials for the conductive layer. Elements selected from copper, tantalum, titanium, molybdenum, and tungsten, or the elements mentioned above. Alloys containing the following components can be used: manganese, magnesium, zirconium, bellflower. One or more materials selected from lylium and thorium may be used. Aluminum, titanium, tantalum, tungsten, molybdenum, chromium, neodymium, Materials consisting of one or more elements selected from candium may also be used.

[0117] Furthermore, the conductive layer may be formed from a conductive metal oxide. Examples of conductive metal oxides include acid Indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), indium oxide Indiene tin oxide alloy (In2O3-SnO2, sometimes abbreviated as ITO), indiene oxide Zinc oxide alloy (In2O3-ZnO) or silicon oxide in these metal oxide materials Alternatively, a material containing silicon oxide can be used.

[0118] The conductive layer may be a single layer or a laminated structure of two or more layers. For example, sil A single-layer structure of an aluminum film containing condensate, and a two-layer structure in which a titanium film is laminated on top of an aluminum film. Examples include a three-layer structure in which a titanium film, an aluminum film, and another titanium film are stacked.

[0119] Here, the exposure used during mask formation for etching includes ultraviolet light, KrF laser light, and ArF Using laser light is preferable.

[0120] The channel length (L) of the transistor is the length between the lower end of the source electrode or drain electrode 142a and the lower end of the source electrode or drain electrode 142a. This is determined by the distance between the source electrode or the lower end of the drain electrode 142b. When exposure is performed with a channel length (L) of less than 25 nm, the range is from a few nanometers to several tens of nanometers. For the first time, using extremely short wavelength ultraviolet light, a mask shape Perform exposure. Ultra-ultraviolet exposure provides high resolution and a large depth of field. Therefore, later The channel length (L) of the formed transistor shall be between 10 nm and 1000 nm. This is also possible, and the operating speed of the circuit can be increased. Furthermore, because the off-current value is extremely small, This prevents increased power consumption.

[0121] Furthermore, when etching the conductive layer, care is taken to ensure that the oxide semiconductor layer 140 is not removed. Adjust the materials and etching conditions as appropriate. In this process, a portion of the oxide semiconductor layer 140 is etched, and grooves (recesses) are formed. ) can also form an oxide semiconductor layer having ).

[0122] Furthermore, between the oxide semiconductor layer 140 and the source electrode or drain electrode 142a, and the oxide semiconductor An oxide conductive layer is formed between the conductive layer 140 and the source electrode or drain electrode 142b. It may also be an oxide conductive layer and a source electrode or drain electrode 142a or source electrode or The conductive layer for forming the drain electrode 142b is formed continuously (continuous deposition). It is possible. The oxide conductive layer can function as either a source region or a drain region. By providing a conductive oxide layer, the resistance of the source region or drain region can be reduced. This enables high-speed operation of transistors.

[0123] Furthermore, in order to reduce the number of masks used and the number of processes, exposure is performed in which transmitted light has multiple intensities. A resist mask is formed using a multi-gradation mask, and this is used for etching. The process may be carried out. A resist mask formed using a multi-gradation mask has multiple thicknesses. It takes on a stepped shape, and the shape can be further deformed by ashing, It can be used in multiple etching processes to process different patterns. In other words, one sheet A multi-gradation mask allows for registration masks that correspond to at least two different patterns. A cavity can be formed. Therefore, the number of exposure masks can be reduced, and the corresponding cavity can be formed. Since the trisography process can also be reduced, the process can be simplified.

[0124] Furthermore, after the above-mentioned process, plasma treatment is performed using gases such as N2O, N2, or Ar. It is preferable to perform the following: The plasma treatment will cause the surface of the exposed oxide semiconductor layer to Adhered water and other substances are removed. Also, oxygen-containing gases such as a mixture of oxygen and argon are removed. Plasma treatment using a plasma can also be performed. This supplies oxygen to the oxide semiconductor layer. It is possible to reduce defects caused by oxygen deficiency.

[0125] Next, a protective insulating layer 14 that is in contact with a portion of the oxide semiconductor layer 140 without being exposed to the atmosphere. Form 4 (see Figure 4(G)).

[0126] The protective insulating layer 144 is treated by methods such as sputtering to remove impurities such as water and hydrogen from the protective insulating layer 144. It can be formed using appropriate methods to prevent contamination. Furthermore, its thickness is 1 nm or more. Materials that can be used for the protective insulating layer 144 include silicon oxide, silicon nitride, and oxide. Examples include silicon nitride and silicon oxide nitride. Furthermore, the structure can be a single layer or a multilayer structure. The structure is also good. The substrate temperature when forming the protective insulating layer 144 is between room temperature and 300°C. It is preferable to do so, and the atmosphere can be a noble gas atmosphere (typically argon), an oxygen atmosphere, or Alternatively, a mixed atmosphere of a noble gas (typically argon) and oxygen is preferable.

[0127] If hydrogen is present in the protective insulating layer 144, the hydrogen may penetrate into the oxide semiconductor layer, and the hydrogen may... This can lead to oxygen abstraction in the oxide semiconductor layer, and the back channel side of the oxide semiconductor layer This can lead to a decrease in resistance and the formation of parasitic channels. Therefore, protective insulating layer 1 It is important to avoid using hydrogen in the formation process of 44, as it contains as little hydrogen as possible. That is the case.

[0128] Furthermore, it is preferable to form the protective insulating layer 144 while removing residual moisture in the processing chamber. The ion semiconductor layer 140 and the protective insulating layer 144 are designed to not contain hydrogen, hydroxyl groups, or water. That is the reason.

[0129] To remove residual moisture from the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. It is preferable. Furthermore, as an exhaust method, a turbo pump with a cold trap is used. It is also acceptable. The deposition chamber, which has been evacuated using a cryopump, contains, for example, hydrogen atoms and water (H2 Because compounds containing hydrogen atoms, such as O), are removed, the protective insulation formed in the deposition chamber is The concentration of impurities in layer 144 can be reduced.

[0130] The sputtering gas used to form the protective insulating layer 144 contains hydrogen, water, and hydroxyl groups. The concentration of impurities such as compounds or hydrides is around a few ppm (preferably around a few ppb). It is preferable to use a high-purity gas from which impurities have been removed.

[0131] Next, a second heat treatment (preferably 20) is performed under an inert gas atmosphere or an oxygen gas atmosphere. It is desirable to perform the procedure at temperatures between 0°C and 400°C (for example, between 250°C and 350°C). Next, a second heat treatment is performed at 250°C for 1 hour under a nitrogen atmosphere. After the second heat treatment, This can reduce variations in the electrical characteristics of the inverter. Furthermore, the second heat treatment Furthermore, during the second heat treatment, the above You may switch gases. Following the second heat treatment, use an oxygen atmosphere, or plenty of hydrogen or water. By undergoing a cooling process in the removed atmosphere, oxygen can also be supplied to the oxide semiconductor. It is possible.

[0132] Furthermore, even if heat treatment is performed in air at temperatures between 100°C and 200°C for 1 hour to 30 hours Good. This heat treatment may be performed by heating while maintaining a constant heating temperature, or from room temperature to 100°C or higher. The process involves repeatedly raising the temperature to a heating temperature of 200°C or lower, and then lowering it from the heating temperature back to room temperature. This may be done. Alternatively, this heat treatment may be performed under reduced pressure before the formation of the protective insulating layer. Performing heat treatment under reduced pressure can shorten the heating time. Note that this heat treatment is as described above. This can be performed in place of the second heat treatment, or before or after the second heat treatment.

[0133] Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see Figure 5(A)). The marginal layer 146 can be formed using methods such as PVD or CVD. Silicon nitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide Formation of interlayer insulating layer 146 is possible using materials containing inorganic insulating materials such as ru. Afterward, it is desirable to planarize the surface using methods such as CMP or etching. It's nice.

[0134] Next, the interlayer insulating layer 146, the protective insulating layer 144, and the gate insulating layer 138 are treated with electrode 1 36a, electrode 136b, electrode 136c, source electrode or drain electrode 142a, source An opening is formed that reaches the electrode or drain electrode 142b, and the electrode is embedded in the opening. A conductive layer 148 is formed (see Figure 5(B)). The above opening is made by etching using a mask, etc. It can be formed by the following method. The mask can be formed by methods such as exposure using a photomask. Therefore, it is possible to form it. Etching methods include wet etching and dry etching. Either etching method can be used, but from the perspective of microfabrication, dry etching is recommended. The following is preferable. The conductive layer 148 is formed using a film deposition method such as PVD or CVD. This is possible. Materials that can be used to form the conductive layer 148 include molybdenum, cyanoacrylate, and cyanoacrylate. Tan, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium Examples include conductive materials, their alloys, and compounds (such as nitrides).

[0135] Specifically, for example, a thin titanium film is formed in the region including the opening by the PVD method, and then the CVD method is applied. After forming a thin titanium nitride film, a tungsten film is formed to fill the opening. The following method can be applied. Here, the titanium film formed by the PVD method is the lower electric Electrodes (here, electrode 136a, electrode 136b, electrode 136c, source electrode or drain) The oxide film on the surface of electrode 142a, source electrode or drain electrode 142b, etc. is reduced. It has the function of reducing contact resistance with the lower electrode. Furthermore, the titanium nitride formed thereafter... The film has a barrier function that suppresses the diffusion of conductive materials. It also contains titanium and titanium nitride. After forming a barrier film using a method such as [mentioning a specific method], a copper film may be formed by a plating method.

[0136] After forming the conductive layer 148, the conductive layer 148 is formed using methods such as etching and CMP. By removing a portion of it and exposing the interlayer insulating layer 146, electrodes 150a, 150b, and 1 50c, electrode 150d, and electrode 150e are formed (see Figure 5(C)). Note that the above conductive layer Remove a portion of 148 to obtain electrodes 150a, 150b, 150c, 150d, and When forming the 150e pole, it is desirable to process the surface so that it is flat. Sea urchin, interlayer insulating layer 146, electrode 150a, electrode 150b, electrode 150c, electrode 150d, By flattening the surface of electrode 150e, a good electrode, wiring, and insulation can be achieved in subsequent processes. This makes it possible to form marginal layers and other structures.

[0137] Furthermore, an insulating layer 152 is formed, and electrodes 150a, 150b, and 1 An opening is formed that extends to electrode 50c, electrode 150d, and electrode 150e, and the material is embedded in the opening. After forming a conductive layer, a portion of the conductive layer is removed using methods such as etching or CMP. , exposing the insulating layer 152, electrode 154a, electrode 154b, electrode 154c, electrode 154 Form d (see Figure 5(D)). This step is the same as when forming electrode 150a, etc. Since there is some information available, I will omit the details.

[0138] When transistor 162 is fabricated using the method described above, the hydrogen concentration of the oxide semiconductor layer 140 The degree is 5x10 19 atoms / cm 3 The following applies, and also the off-current of transistor 162. This is the detection limit of 1 × 10⁻⁶ -13 It becomes less than or equal to A. Furthermore, the off-current of transistor 162 (Here, the value per unit channel width (1 μm) is 100 zA / μm or less.) Such as, the hydrogen concentration is sufficiently reduced to achieve high purity, and defects caused by oxygen deficiency are reduced. By applying the oxide semiconductor layer 140, a transistor 162 with excellent characteristics can be obtained. This is possible. Furthermore, it has a transistor 160 at the bottom made of a material other than an oxide semiconductor. A semiconductor device with excellent properties was fabricated, having a transistor 162 made of oxide semiconductor material on the upper part. It is possible.

[0139] Furthermore, although much research has been done on the physical properties of oxide semiconductors, the energy gap is It does not include the idea of ​​sufficiently reducing the localized energy level itself. In one aspect of the disclosed invention, By removing water and hydrogen, which can cause the presence of energy levels, from the oxide semiconductor, a highly purified oxide is achieved. To fabricate a semiconductor, the localized energy levels within the energy gap are significantly reduced. This is based on the idea that, through this, the manufacture of extremely superior industrial products can be achieved. It makes it possible.

[0140] Furthermore, when removing hydrogen or water, oxygen may also be removed at the same time. Therefore, oxygen is supplied to the unbonded metals that occur due to oxygen deficiency, and localization due to oxygen vacancies. It is preferable to further increase the purity (to type i) of oxide semiconductors by reducing the number of existing energy levels. For example, an oxygen-rich oxide film is formed in contact with the channel-forming region, and at 200°C~4 By performing heat treatment at temperatures of 0°C, typically around 250°C, the oxide film can be removed from the acid It is possible to reduce localized energy levels caused by oxygen vacancies by supplying oxygen to the ionized semiconductor. .

[0141] Factors that degrade the properties of oxide semiconductors include excess hydrogen causing a conduction band of 0.1-0.2 eV. These are thought to be shallow energy levels or deep energy levels due to oxygen deficiency. To achieve this, hydrogen is thoroughly removed and sufficient oxygen is supplied.

[0142] In the disclosed invention, the oxide semiconductor is made highly pure, therefore the carrier density in the oxide semiconductor is It's small enough.

[0143] Furthermore, using the Fermi-Dirac distribution law at room temperature, the energy gap is 3.0 The intrinsic carrier density of oxide semiconductors, which is 5-3.15 eV, is 1 × 10⁻¹⁶. -7 / cm 3 next The true carrier density is 1.45 × 10⁻⁶ 10 / cm 3 It is much smaller than silicon. stomach.

[0144] Therefore, the number of holes, which are minority carriers, is extremely small, and IGFET (Insulated In the off state of a Gate Field Effect Transistor The leakage current is 100 aA / μm or less at room temperature, preferably 10 aA / μm or less, and Preferably, a value of 1 aA / μm or less can be expected. The notation is 1 aA per 1 μm of transistor channel width (1 × 10⁻¹⁶). -18 The current in A) It indicates that something is flowing.

[0145] However, 4H-SiC is a wide-bandgap semiconductor with an energy gap of 3 eV or more. (3.26eV), GaN (3.42eV), etc. are known, and similar transistor characteristics It is expected that properties will be obtained. However, these semiconductor materials are processed at temperatures above 1500°C. Because it involves passing through a certain temperature, thinning is practically impossible. Also, on top of a silicon integrated circuit... Even if one attempts to create a three-dimensional stack, it is impossible due to the process temperature being too high. On the other hand, acid Dioxide semiconductors can be formed into thin films by heated sputtering at room temperature to 400°C, and dehydration is possible. Dehydrogenation (removal of hydrogen and water) and oxidation (supply of oxygen) at 450°C Because it can be achieved at ~700℃, a three-dimensional stacked structure can be built on top of a silicon integrated circuit. It can be formed.

[0146] Although oxide semiconductors are generally considered to be n-type, in one aspect of the disclosed invention, water and hydrogen By removing impurities such as these, and by supplying oxygen, which is a constituent element of oxide semiconductors, i To achieve mold formation. In this respect, unlike mold formation by adding impurities as with silicon, It can be said that it includes technological concepts that have not been seen before.

[0147] <Conductivity mechanism of transistors using oxide semiconductors> Here, the conductivity mechanism of an oxide semiconductor transistor will be explained using Figures 6 to 9. It should be noted that the following explanation is merely one consideration, and the validity of the invention should not be denied based on it. I would like to add that it is not a thing.

[0148] Figure 6 is a cross-sectional view of a transistor (thin-film transistor) using an oxide semiconductor. An oxide semiconductor layer (OS) is provided on the gate electrode (GE1) via a gate insulating layer (GI). A source electrode (S) and a drain electrode (D) are provided on top of it, and the source electrode (S) An insulating layer is provided so as to cover the drain electrode (D).

[0149] Figure 7 shows the energy band diagram (schematic diagram) in the A-A' section of Figure 6. In diagram 7, the black circles (●) represent electrons, and the white circles (○) represent holes, with their respective charges (-q, +q). ) has a positive voltage (V) across the drain electrode. D After applying >0), the dashed line represents the gate voltage. When no voltage is applied to the pole (V G (=0), the solid line represents a positive voltage (V) across the gate electrode. G Mark >0) This shows the case where voltage is applied. When no voltage is applied to the gate electrode, the high potential barrier is due to This indicates an off state where no carriers (electrons) are injected from the electrode to the oxide semiconductor, resulting in no current flow. On the other hand, applying a positive voltage to the gate lowers the potential barrier, allowing current to flow. To show a certain state.

[0150] Figure 8 shows a schematic diagram of the energy bands in the cross-section B-B' in Figure 6. Figure 8(A) shows a positive voltage (V) applied to the gate electrode (GE1). G The given state is >0. This indicates the ON state, where carriers (electrons) flow between the source electrode and the drain electrode. Furthermore, Figure 8(B) shows a negative voltage (V) applied to the gate electrode (GE1). G With <0) applied This indicates the off state (where minority carriers are not flowing).

[0151] Figure 9 shows the vacuum level and the work function of the metal (φM ), the relationship of electron affinity (χ) of oxide semiconductors show.

[0152] At room temperature, electrons in metals are degenerate, and the Fermi level is located within the conduction band. On the other hand, Conventional oxide semiconductors are n-type, and their Fermi level (E F ) is at the center of the band gap The intrinsic Fermi level (E) is located there. i It is located away from the conduction band and closer to it. In semiconductor materials, it is known that some hydrogen acts as a donor, which is one of the factors that causes n-type semiconductors. Yes, they are.

[0153] In contrast, the oxide semiconductor according to one aspect of the disclosed invention uses hydrogen, which is a factor in n-type formation, as an acid By removing elements from oxide semiconductors, the oxide semiconductor contains as few elements other than the main components (impurity elements) as possible. By increasing the purity in such a way, it is made to be true (type i), or substantially true. In other words, instead of adding impurity elements to make it i-type, impurities such as hydrogen and water are removed as much as possible. The characteristic feature is that by removing certain components, a highly purified type i (intrinsic semiconductor) or something close to it is produced. This is the result. F ) is the true Fermi level (E i ) to the same extent as It is possible.

[0154] Band gap (E) of oxide semiconductors g The voltage is 3.15 eV, and the electron affinity (χ) is 4.3 V It is said that the work function of titanium (Ti) that makes up the source electrode and drain electrode is , is approximately equal to the electron affinity (χ) of the oxide semiconductor. In this case, at the metal-oxide semiconductor interface In this case, no Schottky-type barrier is formed for electrons.

[0155] At this time, as shown in Figure 8(A), electrons are in the gate insulating layer and the highly purified oxide semiconductor. It moves near the interface (the lowest, most energetically stable part of the oxide semiconductor).

[0156] Furthermore, as shown in Figure 8(B), when a negative potential is applied to the gate electrode (GE1), a decimal Since the number of holes, which act as carriers, is virtually zero, the current will be extremely close to zero.

[0157] In this way, high purity is achieved by minimizing the presence of elements other than the main components of oxide semiconductors (impurity elements). By degree conversion, it becomes intrinsic (type i) or substantially intrinsic, thus the gate insulating layer The interfacial properties with the semiconductor become apparent. Therefore, the gate insulating layer has a good interface with the oxide semiconductor. The ability to form such a thing is required. Specifically, for example, power supply frequencies in the VHF band to microwave band. Insulating layers fabricated by CVD using high-density plasma generated in large quantities, and sputtering It is preferable to use an insulating layer manufactured by law.

[0158] To improve the purity of the oxide semiconductor while ensuring a good interface between the oxide semiconductor and the gate insulating layer. By doing so, for example, the channel width (W) of the transistor becomes 1 × 10 4 μm, channel length If (L) is 3 μm, then 10 -13 Off-current of less than A, sub-voltage of 0.1V / dec. A threshold swing value (S value) (gate insulating layer thickness: 100 nm) can be achieved.

[0159] In this way, the oxide semiconductor is processed to minimize the presence of elements other than its main component (impurity elements). Purification can improve the operation of transistors.

[0160] <Career density> The technical concept of the disclosed invention is to sufficiently reduce the carrier concentration in the oxide semiconductor layer. The aim is to make it as close to true (type i) as possible. Below is how to calculate the carrier concentration. The carrier concentrations measured will be explained with reference to Figures 10 and 11. .

[0161] First, let's briefly explain how to determine the carrier concentration. The carrier concentration is calculated using MOS capacity. This can be determined by fabricating a capacitor and evaluating the results of the CV measurement (CV characteristics) of the MOS capacitor. It is possible to do so.

[0162] More specifically, the relationship between the gate voltage Vg and capacitance C of a MOS capacitor is plotted as C. -Create a graph representing the V characteristic, and from the CV characteristic, the gate voltage Vg and (1 / C) 2 to Create a graph to represent the relationship, and in that graph, (1 / C) in the weak inversion region. 2 The derivative of By calculating and substituting the derivative value into equation (1), the carrier concentration N d The size is required. In equation (1), e is the elementary charge, ε0 is the permittivity of vacuum, and ε is the dielectric constant of the oxide semiconductor. This is the relative permittivity.

[0163]

number

[0164] Next, we will explain the carrier concentration that was actually measured using the method described above. A titanium film is formed on a lath substrate to a thickness of 300 nm, and a titanium nitride film is formed on the titanium film. Formed with a thickness of nm, an In-Ga-Zn-O based oxide semiconductor is used on the titanium nitride film. An oxide semiconductor layer is formed with a thickness of 2 μm, and a silver film is applied on the oxide semiconductor layer with a thickness of 300 nm. A sample (MOS capacitor) formed using the following method was used. The oxide semiconductor layer was In-Ga- Target for Zn-O based oxide semiconductor film deposition (In2O3:Ga2O3:ZnO=1:1 The oxide semiconductor layer was formed by sputtering using a 1 [mol ratio] method. The formation atmosphere is a mixed atmosphere of argon and oxygen (flow ratio: Ar:O2 = 30 (sccm)). I set it to :15(sccm).

[0165] Figure 10 shows the CV characteristics, and Figure 11 shows Vg and (1 / C). 2 The relationship between each is shown in the figure. (1 / C) in the weak inversion region shown in graph 11 2 From the derivative of , we can obtain using equation (1). The carrier concentration was 6.0 × 10⁻⁶ 10 / cm 3 That was the case.

[0166] Thus, an i-type or substantially i-type oxide semiconductor (for example, with a carrier concentration of 1 x 10 12 / cm 3 The following is preferable: 1 × 10 11 / cm 3 By using the following, It is possible to obtain transistors with extremely excellent off-current characteristics.

[0167] <Variation> Figures 12 to 15 show modified configurations of semiconductor devices. In the following description, these are modified configurations. Next, we will explain a configuration of transistor 162 that differs from the above. The configuration of the Zista 160 is the same as described above.

[0168] Figure 12 shows a gate electrode 136d located beneath an oxide semiconductor layer 140, and a source electrode or The drain electrode 142a and the source electrode or drain electrode 142b are made of an oxide semiconductor layer The transistor 162 has a configuration in which it is in contact with the oxide semiconductor layer 140 on the lower surface of 140. An example is shown. Note that the planar structure can be modified as appropriate to correspond to the cross-section, so here... Only the cross-section will be shown.

[0169] A major difference between the configuration shown in Figure 12 and the configuration shown in Figure 2 is the source electrode or drain electrode. Contact between electrode 142a and source electrode or drain electrode 142b and oxide semiconductor layer 140 There is a continuation position. In other words, in the configuration shown in Figure 2, on the upper surface of the oxide semiconductor layer 140 The source electrode or drain electrode 142a and the source electrode or drain electrode 142 In contrast to contact with b, in the configuration shown in Figure 12, the lower surface of the oxide semiconductor layer 140 The source electrode or drain electrode 142a and the source electrode or drain electrode 142 It comes into contact with b. And, due to this difference in contact, the arrangement of other electrodes, insulating layers, etc. is different. This is how it is. The details of each component are the same as in Figure 2.

[0170] Specifically, the transistor 162, as shown in Figure 12, is provided on the interlayer insulating layer 128. The gate electrode 136d, the gate insulating layer 138 provided on the gate electrode 136d, and Source electrode or drain electrode 142a, source electrode provided on the insulating layer 138 Alternatively, the drain electrode 142b and the source electrode or drain electrode 142a, source electrode The device also includes an oxide semiconductor layer 140 in contact with the upper surface of the drain electrode 142b.

[0171] Here, the gate electrode 136d is embedded in the insulating layer 132 formed on the interlayer insulating layer 128. It is provided so as to be inserted. Also, similar to the gate electrode 136d, the source electrode or Electrode 136a is in contact with drain electrode 130a, and is connected to source electrode or drain electrode 130b Electrode 136b is formed in contact with electrode 130c, and electrode 136c is formed in contact with electrode 130c. ru.

[0172] Furthermore, a protective layer is placed on top of the transistor 162 so as to be in contact with a portion of the oxide semiconductor layer 140. An insulating layer 144 is provided, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, the protective insulating layer 144 and the interlayer insulating layer 146 have a source electrode or drain. An opening is provided that reaches the source electrode 142a, or the drain electrode 142b. Through the opening, electrodes 150d and 150e are connected to the source electrode or drain electrode. It is formed in contact with electrode 142a, source electrode or drain electrode 142b. Similar to pole 150d and electrode 150e, the gate insulating layer 138, protective insulating layer 144, and interlayer insulating layer Through the opening provided in layer 146, electrodes 136a, 136b, and 136c are in contact. Electrodes 150a, 150b, and 150c are formed.

[0173] Furthermore, an insulating layer 152 is provided on the interlayer insulating layer 146, and embedded in the insulating layer 152. Electrodes 154a, 154b, 154c, and 154d are provided so as to be inserted. Here, electrode 154a is in contact with electrode 150a, and electrode 154b is in contact with electrode 150 It is in contact with b, and electrode 154c is in contact with electrode 150c and electrode 150d, and electrode 1 Electrode 54d is in contact with electrode 150e.

[0174] Figure 13 shows an example of a configuration having a gate electrode 136d on an oxide semiconductor layer 140. Here, Figure 13(A) shows the source electrode or drain electrode 142a, or the source electrode or drain The rain electrode 142b is located on the lower surface of the oxide semiconductor layer 140. This is an example of a configuration in which the source electrode or drain electrode 142a is in contact with the following: Figure 13(B) shows the source electrode or drain electrode 142a, The source electrode or drain electrode 142b is acid on the upper surface of the oxide semiconductor layer 140. This is an example of a configuration in which the ionized semiconductor layer 140 is in contact with the semiconductor layer.

[0175] The main difference between the configurations shown in Figures 2 and 12 and the configuration shown in Figure 13 is the oxide semiconductor layer 140. The point is that it has a gate electrode 136d on top. Also, the configuration shown in Figure 13(A) and Figure 13(B) The major difference in the configuration shown is the source electrode or drain electrode 142a, or the source electrode Alternatively, the drain electrode 142b is either on the lower or upper surface of the oxide semiconductor layer 140. The point is whether or not contact occurs in that situation. And due to these differences, other electricity The arrangement of electrodes, insulating layers, etc., differs. Details of each component are the same as in Figure 2, etc. That is the case.

[0176] Specifically, in Figure 13(A), the source electrode or drain is provided on the interlayer insulating layer 128. In electrode 142a, source electrode or drain electrode 142b, and source electrode or drain Oxide semiconductor contacting the upper surface of the source electrode 142a or the drain electrode 142b Body layer 140, gate insulating layer 138 provided on oxide semiconductor layer 140, gate insulating It has a gate electrode 136d in a region that overlaps with the oxide semiconductor layer 140 on layer 138.

[0177] Furthermore, in Figure 13(B), the oxide semiconductor layer 140 provided on the interlayer insulating layer 128 and acid Source electrode or drain electrode provided so as to be in contact with the upper surface of the ionized semiconductor layer 140 142a, source electrode or drain electrode 142b, oxide semiconductor layer 140, source electrode On the electrode or drain electrode 142a and the source electrode or drain electrode 142b The gate insulating layer 138 is superimposed on the oxide semiconductor layer 140 on the gate insulating layer 138. It has a gate electrode 136d in the region.

[0178] In addition, in the configuration shown in Figure 13, compared to the configuration shown in Figure 2, etc., some components can be omitted. There are combinations (for example, electrode 150a and electrode 154a). In this case, the manufacturing process is simplified. This also provides the secondary effect of... It goes without saying that some components can be omitted.

[0179] Figure 14 shows the case where the device size is relatively large, with a gauge below the oxide semiconductor layer 140. This is an example of a configuration having an electrode 136d. In this case, the flatness of the surface and coverage Since the requirements are relatively lenient, the wiring and electrodes are formed to be embedded within the insulating layer. It is not necessary. For example, by performing patterning after the formation of the conductive layer, the gate electrode 13 It is possible to form 6d, etc. Although not shown in the diagram here, transistor 16 The value 0 can also be created in the same way.

[0180] The main difference between the configuration shown in Figure 14(A) and the configuration shown in Figure 14(B) is the source electrode or The drain electrode 142a, or the source electrode or drain electrode 142b, is located in the oxide semiconductor layer 1 The point is whether contact occurs on the lower or upper surface of 40. These differences result in variations in the arrangement of other electrodes, insulating layers, and other components. The details of each component are the same as in Figure 2, etc.

[0181] Specifically, in Figure 14(A), the gate electrode 136d provided on the interlayer insulating layer 128 and , a gate insulating layer 138 provided on the gate electrode 136d, and provided on the gate insulating layer 138 The source electrode or drain electrode 142a, source electrode or drain electrode 14 2b, source electrode or drain electrode 142a, source electrode or drain electrode 142 It has an oxide semiconductor layer 140 in contact with the upper surface of b.

[0182] Furthermore, in Figure 14(B), the gate electrode 136d provided on the interlayer insulating layer 128 and the gate A gate insulating layer 138 provided on the electrode 136d, and the gate electrode on the gate insulating layer 138 An oxide semiconductor layer 140 is provided in the region overlapping with pole 136d, and the oxide semiconductor layer 140 Source electrode or drain electrode 142a provided so as to be in contact with the upper surface, source electrode It has an electrode or drain electrode 142b.

[0183] Furthermore, in the configuration shown in Figure 14, compared to the configuration shown in Figure 2, etc., some components can be omitted. In some cases, this is possible. In this case as well, the benefit of simplifying the manufacturing process can be obtained.

[0184] Figure 15 shows the case where the device size is relatively large, with a gauge on the oxide semiconductor layer 140. This is an example of a configuration having an electrode 136d. In this case as well, surface flatness and coverage The requirements are relatively lenient, so wiring and electrodes can be embedded in the insulating layer. It is not necessary to form it. For example, by patterning after the formation of the conductive layer, the gate electrode It is possible to form 136d and the like. Note that, although not shown in the diagram, transistors The same process can be used to manufacture the 160.

[0185] The main difference between the configuration shown in Figure 15(A) and the configuration shown in Figure 15(B) is the source electrode or The drain electrode 142a, or the source electrode or drain electrode 142b, is located in the oxide semiconductor layer 1 The point is whether contact occurs on the lower or upper surface of 40. These differences result in variations in the arrangement of other electrodes, insulating layers, and other components. The details of each component are the same as in Figure 2, etc.

[0186] Specifically, in Figure 15(A), the source electrode or drain is provided on the interlayer insulating layer 128. In electrode 142a, source electrode or drain electrode 142b, and source electrode or drain Oxide semiconductor contacting the upper surface of the source electrode 142a or the drain electrode 142b Body layer 140, source electrode or drain electrode 142a, source electrode or drain electrode 142b, a gate insulating layer 138 provided on the oxide semiconductor layer 140, and gate insulating layer 1 A gate electrode 136d is provided in a region that overlaps with the oxide semiconductor layer 140 on 38, and do.

[0187] Furthermore, in Figure 15(B), the oxide semiconductor layer 140 provided on the interlayer insulating layer 128 and acid Source electrode or drain electrode provided so as to be in contact with the upper surface of the ionized semiconductor layer 140 142a, source electrode or drain electrode 142b, and source electrode or drain electrode 1 42a, source electrode or drain electrode 142b, provided on the oxide semiconductor layer 140 In the region where the gate insulating layer 138 and the oxide semiconductor layer 140 on the gate insulating layer 138 overlap It has a gate electrode 136d provided.

[0188] Furthermore, in the configuration shown in Figure 15, compared to the configuration shown in Figure 2, etc., some components can be omitted. In some cases, this is possible. In this case as well, the benefit of simplifying the manufacturing process can be obtained.

[0189] As described above, one aspect of the disclosed invention realizes a semiconductor device with a new configuration. In this embodiment, transistors 160 and 162 are stacked to form the transistor. Although an example has been given, the configuration of the semiconductor device is not limited to this. In this configuration, the channel length directions of transistors 160 and 162 are perpendicular to each other. I have explained an example, but the positional relationship between transistor 160 and transistor 162 is not the same. It is not limited. Furthermore, by superimposing transistor 160 and transistor 162 It is permissible to set one up.

[0190] Furthermore, in this embodiment, for the sake of ease of understanding, the semiconductor device is the smallest memory unit (1 bit). As explained above, the configuration of semiconductor devices is not limited to this. Multiple semiconductor devices can be used. By connecting them appropriately, it is also possible to configure more advanced semiconductor devices. For example, the above semiconductor device By using multiple units, it is possible to configure NAND and NOR type semiconductor devices. The configuration is not limited to Figure 1 and can be changed as appropriate.

[0191] The semiconductor device according to this embodiment is extremely efficient due to the low off-current characteristics of the transistor 162. It is possible to retain information for a long period of time. In other words, it is required for DRAM, etc. Refresh operations are unnecessary, and power consumption can be reduced. Furthermore, it is virtually non-volatile. It can be used as a self-sustaining memory device.

[0192] Furthermore, information is written through the switching operation of transistor 162, It does not require high voltage and there are no issues with component degradation. Furthermore, the on / off switching of the transistor... Therefore, since information is written to and erased, high-speed operation can be easily achieved. By controlling the potential input to the transistor, it is possible to directly rewrite the information. Therefore, the erase operation required for flash memory and the like is unnecessary, and the erase operation is This can suppress the resulting decrease in operating speed.

[0193] Furthermore, transistors using materials other than oxide semiconductors are different from transistors using oxide semiconductors. Compared to standard, it allows for even faster operation, and by using this, the stored contents can be processed It is possible to perform reading at high speed.

[0194] The configurations and methods shown in this embodiment may be combined with the configurations and methods shown in other embodiments as appropriate. They can be used together.

[0195] (Embodiment 2) In this embodiment, the circuit configuration and operation method of a semiconductor device according to one aspect of the present invention are described. explain.

[0196] Figure 16 shows an example of a circuit diagram for a memory element (hereinafter also referred to as a memory cell) in a semiconductor device. As shown in Figure 16, the memory cell 200 is of the multi-level type, and the first signal line S1 (third wiring) ) and the second signal line S2 (fourth wiring), and the word line WL (fifth wiring), and the transistor It consists of transistor 201, transistor 202, transistor 203, and capacitive element 205. Transistors 201 and 203 are made of materials other than oxide semiconductors. It is formed using an oxide semiconductor, and transistor 202 is formed using an oxide semiconductor. Here, transistors 201 and 203 are transistors shown in Embodiment 1. It is preferable to have a configuration similar to that of 160. Also, transistor 202 is in the same configuration as in Embodiment 1. It is preferable to have a configuration similar to that of the transistor 162 shown. Furthermore, the memory cell 200 is It is electrically connected to the source line SL (first wiring) and the bit line BL (second wiring). via transistors (including those that constitute other memory cells), the source line SL and It is preferable that it be electrically connected to the bit line BL.

[0197] Here, the gate electrode of transistor 201 and the source electrode or dot of transistor 202 It is electrically connected to one of the rain electrodes. Also, the source wire SL and the transistor The source electrode of transistor 201 and the source electrode of transistor 203 are electrically connected, and The T-wire BL, the drain electrode of transistor 201, and the drain electrode of transistor 203. These are electrically connected. And the first signal line S1 and the saw of transistor 202 The other electrode, either the drain electrode or the other electrode, is electrically connected to the second signal line S2 and the transient The gate electrode of transistor 202 is electrically connected to the word line WL and transistor 203. It is electrically connected to the gate electrode of the capacitor element 205. The gate electrode of transistor 201 and the source electrode or drain electrode of transistor 202 One side is electrically connected, and a predetermined potential is applied to the other electrode of the capacitive element 205. is. The predetermined potential is, for example, GND or the like. Note that the source line SL and the source electrodes of the transistor 201 and the source electrode of the transistor 203 may be connected via a transistor (including those constituting other memory cells). Also, the bit line BL and the drain electrodes of the transistor 201 and the transistor 203 may be connected via a transistor (including those constituting other memory cells).

[0198] Here, the operation of the memory cell 200 will be briefly described. For example, in the case of a 4 - valued type, the four states of the memory cell 200 are set as data "00b", "01b", "10b", "11b", and the potential of the node (hereinafter, node A) connected to the gate electrode of the transistor 201 is set as V00, V01, V10, V11 (V00 < V01 < V10 < V11) respectively. The read operation is performed by charging the bit line BL from the source line SL side through the selected memory cell. When charging is performed from the source line SL side, the bit line BL reflects the state of the memory cell 200 and is charged to the potential represented by (the potential of node A) - (the threshold voltage Vth of the transistor 201). As a result, the potential of the bit line BL becomes V00 - Vth, V01 - Vth, V10 - Vt h, V11 - Vth for the data "00b", "01 b", "10b", "11b", and from the differences in these potentials, the data "00b", "01b", "10b", "11b" can be read.

[0199] FIG. 17 shows a block circuit diagram of a semiconductor device according to an aspect of the present invention having a storage capacity of m × n bits. Here, as an example, a NAND - type semiconductor device in which the memory cells 200 are connected in series is shown. ​

[0200] A semiconductor device according to one aspect of the present invention comprises m word lines WL(1) to WL(m) and a second signal line. Lines S2(1) to S2(m), n bit lines BL(1) to BL(n), and the first signal line S1(1) to S1(n), two selection lines SEL(1) and SEL(2), and multiple memory locations. Cells 200(1,1) to 200(m,n) are arranged in m rows and n columns (m and n are natural values). A memory cell array 210 arranged in a matrix of (number) and along the selection line SEL(1) Then, the bit lines BL(1)~BL(n) and memory cells 200(1,1)~200(1,n) The transistors 215(1,1)~215(1,n) are positioned between them, and the selection line SEL( 2) Along the source line SL(1)~SL(n) and memory cell 200(m,1)~200 The transistors 215(2,1)~215(2,n) are positioned between (m,n), and The drive circuit 217 for the signal line, the readout circuit 211, the drive circuit 212 for the first signal line, and the second The signal line and word line drive circuit 213, the potential generation circuit 214, and the selection line drive circuit 21 It is composed of peripheral circuits such as 6(1) and 216(2). Other peripheral circuits include A refresh circuit or the like may be provided.

[0201] Consider each of the 200 memory cells, for example, memory cell 200(i,j) (where i is 1 or less). The upper integer is less than or equal to m, and j is an integer between 1 and n (inclusive). Memory cell 200(i,j) is The first signal line S1(j), the second signal line S2(i), and the word line WL(i) are connected respectively. It is also said that the memory cell 200(i1,j) (where i1 is an integer between 2 and m) has The drain electrodes of transistors 201 and 203 are connected to memory cell 200 (i1 -1,j) is connected to the source electrodes of transistors 201 and 203. The transistors in memory cell 200(i2,j) (where i2 is an integer between 1 and m-1) The source electrodes of transistors 201 and 203 are connected to memory cell 200(i2+1,j) It is connected to the drain electrodes of transistors 201 and 203. The drain current of transistors 201 and 203 in cell 200(1,j) The pole is connected to the source electrode of transistor 215(1,j), and memory cell 200(m, The source electrodes of transistors 201 and 203 in j) are, It is connected to the drain electrode of transistor 215(2,j). The electrode is connected to the bit line BL(j), and the source electrode of transistor 215(2,j) is It is connected to the source line SL(j). Also, the gate electrode of transistor 215(1,j) The gate electrode of transistor 215(2,j) is connected to the selection line SEL(1), and the selection line SEL(1) is connected to the selection line SEL(1). It is connected to line SEL(2).

[0202] Also, source lines SL(1) to SL(n) are connected to the source line drive circuit 217, and bit line BL( 1) BL(n) is connected to the readout circuit 211, and the first signal lines S1(1) to S1(n) are connected to the first signal The drive circuit 212 of line number has the second signal line S2(1)~S2(m) and word line WL(1)~ WL(m) is connected to the drive circuit 213 for the second signal line and word line, and the selection line SEL(1), SEL (2) is connected to the drive circuits 216(1) and 216(2) of the selection line, respectively.

[0203] Figure 18 shows an example of the drive circuit 213 for the second signal line and word line. The drive circuit 213 of the D line includes a decoder, etc. The second signal line S2 is a light enable signal. Switches controlled by the WE signal, and controls by the decoder output signal. The wires V_S20, V_S21, and V_S2S are connected via the switch. The word line WL is a switch controlled by the read enable signal (RE signal). Wiring V_WL0, wiring V_ WL1 is connected to wiring V_WLS. The decoder receives an address signal from an external source. It will be done.

[0204] When an address signal is input to the drive circuit 213 for the second signal line and word line, the address is The selected row (hereinafter also referred to as the selected row) is asserted (activated), and the other rows (hereinafter referred to as the non-selected row) are asserted (activated). The selected line (also referred to as the selected line) is deasserted (deactivated). Additionally, the RE signal is deasserted. Then, the potential V_WLS is applied to the word line WL, and when the RE signal is asserted, selection The word line WL of a row has a potential V_WL1, and the word line WL of an unselected row has a potential V_WL0. Each is applied. Also, when the WE signal is deasserted, the second signal line S2 has a potential When V_S2S is applied and the WE signal is asserted, a potential exists in the second signal line S2 of the selected row. The potential V_S21 is applied to the second signal line S2 of the unselected row, and the potential V_S20 is applied to that line.

[0205] Furthermore, transistor 203, which is connected to the word line WL to which the potential V_WL0 is applied, is turned ON. This should be done. Also, the transistor connected to the word line WL to which the potential V_WL1 is applied. The zista 203 is turned off. Also, potentials V_S2S and V_S20 are applied. The transistor 202 connected to the second signal line S2 is turned off. Transistor 202 connected to the second signal line S2 to which potential V_S21 is applied turns ON. Make it so.

[0206] The drive circuits 216(1) and 216(2) for the selection line activate the selection line S when the RE signal is asserted. Let EL(1) and SEL(2) be at potential V_SEL1, and transistor 215(1,1)~( Turn on transistors 1,n) and 215(2,1)~(2,n). Also, RE signal When the signal is deasserted, V_SEL0[V] is set to transistor 215(1,1)~(1 Turn off transistors 215(2,1)~(2,n) and (2,n).

[0207] Figure 19 shows an example of the drive circuit 212 for the first signal line. The drive circuit 212 for the first signal line is: It has a multiplexer (MUX1). The multiplexer (MUX1) has a signal DI, and The write potentials V00, V01, V10, and V11 are input. Multiplexer (MUX1) The output terminal of ) is connected to the first signal line S1 via a switch. Also, the first signal line S1 is connected to GND via a switch. The above switch enables the light. It is controlled by a signal.

[0208] When the signal DI is input to the drive circuit 212 of the first signal line, the multiplexer (MUX1) Depending on the value of signal DI, the write potential Vw is set to one of V00, V01, V10, or V11. Select. The behavior of the multiplexer (MUX1) is shown in Table 1. Light enable signal When asserted, the selected write potential Vw is applied to the first signal line S1, When the enable signal is deasserted, the first signal line S1 is connected to GND.

[0209]

Table 1

[0210] The drive circuit 217 of the source line applies a voltage Vs_read to the source line SL during the read period after precharge. In other periods, 0V is applied. Here, the voltage Vs_read is set higher than V11 - Vth. The drive circuit 217 of the source line applies a voltage Vs_read to the source line SL during the read period after precharge. In other periods, 0V is applied. Here, the voltage Vs_read is set higher than V11 - Vth. The drive circuit 217 of the source line applies a voltage Vs_read to the source line SL during the read period after precharge. In other periods, 0V is applied. Here, the voltage Vs_read is set higher than V11 - Vth.

[0211] Fig. 20 shows an example of the read circuit 211. The read circuit 211 includes a sense amplifier circuit and a logic circuit. One input terminal of the sense amplifier circuit is connected to the bit line BL or the wiring Vpc via a switch. One of the reference potentials Vref0, Vref1, Vref2 is input to the other input terminal of the sense amplifier circuit. Each output terminal of the sense amplifier circuit is connected to an input terminal of the logic circuit. The switch is controlled by the row enable signal and the signal Φpc. Fig. 20 shows an example of the read circuit 211. The read circuit 211 includes a sense amplifier circuit and a logic circuit. One input terminal of the sense amplifier circuit is connected to the bit line BL or the wiring Vpc via a switch. One of the reference potentials Vref0, Vref1, Vref2 is input to the other input terminal of the sense amplifier circuit. Each output terminal of the sense amplifier circuit is connected to an input terminal of the logic circuit. The switch is controlled by the row enable signal and the signal Φpc. Fig. 20 shows an example of the read circuit 211. The read circuit 211 includes a sense amplifier circuit and a logic circuit. One input terminal of the sense amplifier circuit is connected to the bit line BL or the wiring Vpc via a switch. One of the reference potentials Vref0, Vref1, Vref2 is input to the other input terminal of the sense amplifier circuit. Each output terminal of the sense amplifier circuit is connected to an input terminal of the logic circuit. The switch is controlled by the row enable signal and the signal Φpc. Fig. 20 shows an example of the read circuit 211. The read circuit 211 includes a sense amplifier circuit and a logic circuit. One input terminal of the sense amplifier circuit is connected to the bit line BL or the wiring Vpc via a switch. One of the reference potentials Vref0, Vref1, Vref2 is input to the other input terminal of the sense amplifier circuit. Each output terminal of the sense amplifier circuit is connected to an input terminal of the logic circuit. The switch is controlled by the row enable signal and the signal Φpc. Fig. 20 shows an example of the read circuit 211. The read circuit 211 includes a sense amplifier circuit and a logic circuit. One input terminal of the sense amplifier circuit is connected to the bit line BL or the wiring Vpc via a switch. One of the reference potentials Vref0, Vref1, Vref2 is input to the other input terminal of the sense amplifier circuit. Each output terminal of the sense amplifier circuit is connected to an input terminal of the logic circuit. The switch is controlled by the row enable signal and the signal Φpc. Fig. 20 shows an example of the read circuit 211. The read circuit 211 includes a sense amplifier circuit and a logic circuit. One input terminal of the sense amplifier circuit is connected to the bit line BL or the wiring Vpc via a switch. One of the reference potentials Vref0, Vref1, Vref2 is input to the other input terminal of the sense amplifier circuit. Each output terminal of the sense amplifier circuit is connected to an input terminal of the logic circuit. The switch is controlled by the row enable signal and the signal Φpc.

[0212] By setting the values of the reference potentials Vref0, Vref1, Vref2 to satisfy V00 - Vth < Vref0 < V01 - Vth < Vref1 < V10 - Vth < Vref2 < V11 - Vth, the state of the memory cell can be read as a 3-bit digital signal. For example, in the case of the data "00b", the voltage of the bit line BL is V00 - Vth. This value is smaller than any of the reference potentials Vref0, Vref1, Vref2. Therefore, the outputs SA_OUT0, SA_OUT1, SA_OUT2 of the sense amplifier circuit are all "0", "0", "0". Similarly, in the case of the data "01b", By setting the values of the reference potentials Vref0, Vref1, Vref2 to satisfy V00 - Vth < Vref0 < V01 - Vth < Vref1 < V10 - Vth < Vref2 < V11 - Vth, the state of the memory cell can be read as a 3-bit digital signal. For example, in the case of the data "00b", the voltage of the bit line BL is V00 - Vth. This value is smaller than any of the reference potentials Vref0, Vref1, Vref2. Therefore, the outputs SA_OUT0, SA_OUT1, SA_OUT2 of the sense amplifier circuit are all "0", "0", "0". Similarly, in the case of the data "01b", By setting the values of the reference potentials Vref0, Vref1, Vref2 to satisfy V00 - Vth < Vref0 < V01 - Vth < Vref1 < V10 - Vth < Vref2 < V11 - Vth, the state of the memory cell can be read as a 3-bit digital signal. For example, in the case of the data "00b", the voltage of the bit line BL is V00 - Vth. This value is smaller than any of the reference potentials Vref0, Vref1, Vref2. Therefore, the outputs SA_OUT0, SA_OUT1, SA_OUT2 of the sense amplifier circuit are all "0", "0", "0". Similarly, in the case of the data "01b", By setting the values of the reference potentials Vref0, Vref1, Vref2 to satisfy V00 - Vth < Vref0 < V01 - Vth < Vref1 < V10 - Vth < Vref2 < V11 - Vth, the state of the memory cell can be read as a 3-bit digital signal. For example, in the case of the data "00b", the voltage of the bit line BL is V00 - Vth. This value is smaller than any of the reference potentials Vref0, Vref1, Vref2. Therefore, the outputs SA_OUT0, SA_OUT1, SA_OUT2 of the sense amplifier circuit are all "0", "0", "0". Similarly, in the case of the data "01b", By setting the values of the reference potentials Vref0, Vref1, Vref2 to satisfy V00 - Vth < Vref0 < V01 - Vth < Vref1 < V10 - Vth < Vref2 < V11 - Vth, the state of the memory cell can be read as a 3-bit digital signal. For example, in the case of the data "00b", the voltage of the bit line BL is V00 - Vth. This value is smaller than any of the reference potentials Vref0, Vref1, Vref2. Therefore, the outputs SA_OUT0, SA_OUT1, SA_OUT2 of the sense amplifier circuit are all "0", "0", "0". Similarly, in the case of the data "01b", By setting the values of the reference potentials Vref0, Vref1, Vref2 to satisfy V00 - Vth < Vref0 < V01 - Vth < Vref1 < V10 - Vth < Vref2 < V11 - Vth, the state of the memory cell can be read as a 3-bit digital signal. For example, in the case of the data "00b", the voltage of the bit line BL is V00 - Vth. This value is smaller than any of the reference potentials Vref0, Vref1, Vref2. Therefore, the outputs SA_OUT0, SA_OUT1, SA_OUT2 of the sense amplifier circuit are all "0", "0", "0". Similarly, in the case of the data "01b", By setting the values of the reference potentials Vref0, Vref1, Vref2 to satisfy V00 - Vth < Vref0 < V01 - Vth < Vref1 < V10 - Vth < Vref2 < V11 - Vth, the state of the memory cell can be read as a 3-bit digital signal. For example, in the case of the data "00b", the voltage of the bit line BL is V00 - Vth. This value is smaller than any of the reference potentials Vref0, Vref1, Vref2. Therefore, the outputs SA_OUT0, SA_OUT1, SA_OUT2 of the sense amplifier circuit are all "0", "0", "0". Similarly, in the case of the data "01b", The outputs SA_OUT0, SA_OUT1, and SA_OUT2 of the sense amplifier circuit are each If the data is "1", "0", "0", then the output of the sense amplifier circuit S A_OUT0, SA_OUT1, and SA_OUT2 are set to "1", "1", and "0" respectively. In the case of data "11b", the output of the sense amplifier circuit is SA_OUT0, SA_OUT 1. SA_OUT2 will be "1", "1", and "1" respectively. Then, the argument shown in Table 2 Using a logic circuit represented by a logical value table, 2 bits of data DO are generated and read by the read circuit 2 Output from 11.

[0213] [Table 2]

[0214] In the illustrated readout circuit 211, when the signal φpc is asserted, the bit line BL And the input terminal of the sense amplifier connected to the bit line BL is charged to potential Vpc. Precharging can be performed by the signal φpc. Note that the potential Vpc is V00-V Lower than th. When the RE signal is asserted, the source line of the source line drive circuit 217 The potential Vs_read was applied to SL, and as a result, the bit line BL reflected the data. The potential is charged. Then, the readout described above is performed in the readout circuit 211.

[0215] Note that the "potential of bit line BL" used for comparison during reading is determined via a switch. The potential of the node at the input terminal of the sense amplifier connected to line BL is included. Therefore, the potentials compared in the readout circuit must be exactly the same as the potential of the bit line BL. It's not necessary.

[0216] Figure 21 shows an example of a potential generation circuit 214. In the potential generation circuit 214, the desired potential is generated. It can be generated by dividing the resistance between the power supply potential Vdd and GND. The potential is output via an analog buffer. In this way, the write potential V00,V 01, V10, V11, and reference potentials Vref0, Vref1, Vref2 are generated. Note that in Figure 21, V00 <Vref0<V01<Vref1<V10<Vref2< The configuration shown results in V11, but the relationship between potentials is not limited to this. Resistors and reference elements are also used. By adjusting the code, the necessary potential can be generated as needed. Also, V00, V 01, V10, V11 and Vref0, Vref1, Vref2 are generated using a separate potential generation circuit. You can generate it this way.

[0217] The potential generation circuit 214 is supplied with a potential boosted by the boost circuit instead of the power supply potential Vdd. This is also good. By supplying the output of the boost circuit to the potential generation circuit, the absolute value of the potential difference can be increased. This will enable the supply of higher potential.

[0218] Even when the power supply potential Vdd is supplied directly to the potential generation circuit, the potential is divided into many potentials. It is possible to divide it. However, in this case, it becomes difficult to distinguish between adjacent potentials. There is a risk of increased write and read errors. In this regard, the output of the boost circuit is potential-generating By supplying it to the circuit, the absolute value of the potential difference can be increased, so Even when increasing the ratio, a sufficient difference in potential between adjacent points can be maintained.

[0219] This allows for the storage of a single memory cell without increasing write or read errors. It is possible to increase the capacity.

[0220] Figure 22(A) shows a boost circuit 219 as an example of a boost circuit that performs a four-stage boost. In (A), the power supply potential Vdd is supplied to the input terminal of the first diode 402. The output terminal of the first diode 402 is connected to the input terminal of the second diode 404 and the first capacitor One terminal of the element 412 is connected. Similarly, the output terminal of the second diode 404 is connected. The input terminal of the third diode 406 and one terminal of the second capacitive element 414 are connected to the child. It is done. The same applies below, so a detailed explanation will be omitted, but the output terminal of the nth diode It can also be said that one terminal of the nth capacitive element is connected to the child (n: a natural number). Furthermore, the output of the fifth diode 410 becomes the output Vout of the boost circuit 219.

[0221] Furthermore, the other terminal of the first capacitive element 412 and the diode 40 of the third capacitive element 416 The clock signal CLK is input to the terminal that is not connected to the output terminal of 6. The other terminal of the second capacitance element 414 and the other terminal of the fourth capacitance element 418 are inverted The clock signal CLKB is input. That is, the other terminal of the 2k-1 capacitance element is When the clock signal CLK is input, the other terminal of the 2k capacitance element receives the inverting clock signal C. It can be said that LKB is input (k: natural number). However, the final stage capacitive element (in this embodiment) Then, the other terminal of the fifth capacitive element (420) is input to the ground potential (GND).

[0222] When the clock signal CLK is High, that is, when the inverted clock signal CLKB is Low In some cases, the first capacitive element 412 and the third capacitive element 416 are charged, and the clock The potentials of nodes N1 and N3, which are capacitively coupled to the signal CLK, are lowered by a predetermined voltage. It can be raised. Meanwhile, node N2 and node are capacitively coupled with the inverted clock signal CLKB. The potential of N4 is lowered by a predetermined voltage.

[0223] As a result, the first diode 402, the third diode 406, and the fifth diode 41 Charge moves through 0, raising the potentials of nodes N2 and N4 to predetermined values. It is possible.

[0224] Next, the clock pulse CLK goes low, and the inverted clock signal CLKB goes high. Then, the potentials of nodes N2 and N4 are further increased. Meanwhile, nodes N1, The potentials of node N3 and node N5 are lowered by a predetermined voltage.

[0225] As a result, charge moves through the second diode 404 and the fourth diode 408. As a result, the potentials of nodes N3 and N5 will be raised to a predetermined level. Thus, the relationship of potential at each node is V N5 >V N4(CLKB=Hi gh) >V N3(CLK=High) >V N2(CLKB=High) >V N1(CLK =High) When the voltage reaches >Vdd, the voltage is boosted. Note the configuration of the boost circuit 219. This is not limited to systems that perform a four-stage boost. The number of boost stages can be changed as appropriate.

[0226] Note that the output Vout of the boost circuit 219 is greatly affected by the variations in the diodes. For example, a diode is realized by connecting the source electrode and gate electrode of a transistor. However, in this case, it will be affected by variations in the transistor threshold.

[0227] To precisely control the output Vout, a configuration that feeds back the output Vout is adopted. You can use it. Figure 22(B) shows the circuit configuration when the output Vout is fed back. Here is an example. The boost circuit 219 in Figure 22(B) is the same as the boost circuit 219 shown in Figure 22(A). It is equivalent to that.

[0228] The output terminal of the boost circuit 219 is connected to one of the input terminals of the sense amplifier circuit via resistor R1. They are connected. Also, one input terminal of the sense amplifier circuit is connected to ground via resistor R2. In other words, one input terminal of the sense amplifier circuit corresponds to the output Vout. A potential V1 will be input. Here, V1 = Vout·R2 / (R1+R2) ru.

[0229] Furthermore, the reference potential Vref is input to the other input terminal of the sense amplifier circuit. In the sense amplifier circuit, V1 and Vref will be compared. The output terminal is connected to the control circuit. The control circuit also receives the clock signal CLK0. The control circuit, in response to the output from the sense amplifier circuit, sends a clock signal to the boost circuit 219. It outputs clock signal CLK and the inverted clock signal CLKB.

[0230] If V1 > Vref, the output sig_1 of the sense amplifier circuit is asserted, and the control circuit The supply of the clock signal CLK and the inverted clock signal CLKB to the boost circuit 219 is stopped. This will stop the voltage boosting operation, and therefore the rise in potential Vout will stop. Then, as the circuit connected to the output terminal of the boost circuit 219 consumes power, the potential Vo ut gradually decreases.

[0231] When V1 < Vref, the output sig_1 of the sense amplifier circuit is deasserted, and the control circuit starts supplying the clock signal CLK and the inverted clock signal CLKB to the boost circuit 219. As a result, a boosting operation is performed, and the potential Vout gradually rises.

[0232] In this way, by feeding back the output potential Vout of the boost circuit 219, it is possible to keep the output potential Vout of the boost circuit 219 at a constant value. This configuration is particularly effective when there are variations in the diodes. It is also effective when it is desired to generate a predetermined potential based on the reference potential Vref. Note that in the boost circuit 219, it is also possible to generate a plurality of potentials by using a plurality of different reference potentials. By supplying the output of the boost circuit to the potential generation circuit in this way, the absolute value of the potential difference can be increased. Therefore, it is possible to generate a higher potential without changing the minimum unit of the potential difference. That is, it is possible to increase the storage capacity of one memory cell.

[0233]

[0234] FIG. 23 shows a differential sense amplifier as an example of the sense amplifier circuit. The differential sense amplifier has input terminals Vin(+) and Vin(-) and an output terminal Vout, and amplifies the potential difference between Vin(+) and Vin(-). If the potential of Vin(+) is higher than the potential of Vin(-), Vout outputs a High signal, and if the potential of Vin(+) is lower than the potential of Vin(-), also lower, Vout outputs a Low signal.​​If the value is lower than this, Vout outputs a Low signal.

[0235] Figure 24 shows a latch-type sense amplifier as an example of a sense amplifier circuit. The control amplifier has input and output terminals V1 and V2, and input terminals for control signals Sp and Sn. First, set signal Sp to High and signal Sn to Low, and cut off the power supply potential (Vdd). Then, the potentials to be compared are applied to V1 and V2 respectively. After that, the signal Sp is set to Low. When the signal Sn is set to High and the power supply potential (Vdd) is supplied, the potential of V1 becomes the potential of V2. If it is higher than V2, the output of V1 will be High and the output of V2 will be Low, and the potential of V1 will be V2 If the potential is lower than that, the output of V1 will be Low and the output of V2 will be High. Then, the potential difference between V1 and V2 is amplified.

[0236] Here is an example of a specific operating potential (voltage). For example, the threshold voltage of transistor 201 is Approximately 0.3V, with power supply potential Vdd=2V, V11=1.6V, V10=1.2V, V0 1=0.8V, V00=0V and Vref0=0.3V, Vref1=0.7V, Vre f2 can be set to 1.1V. Also, Vs_read can be set to 2V. V_WL0=2V, V_WL1=0V, V_WLS=0V, V_S20=0V, V_S2 It is best to set 1=2V, V_S2S=0V, V_SEL0=0V, and V_SEL1=2V. The potential Vpc can be set to, for example, 0V.

[0237] Next, the operation of the semiconductor device shown in Figure 17 will be explained. For example, in the case of a quaternary type, memo The four states of the Recell 200 are designated as data "00b", "01b", "10b", and "11b". , let the potentials of node A at that time be V00, V01, V10, and V11 (V00 < V0 1 < V10 < V11) respectively. In this configuration, writing and reading are performed row by row.

[0238] First, the writing operation of the semiconductor device will be described. The writing operation is performed during the period when the write enable signal is asserted. Also, during the writing operation, the read enable signal is deasserted. When writing to the memory cells 200(i,1) to 200(i,n) in the i-th row, the second signal line S2(i) is set to the potential V_S21, and the transistor 202 of the selected memory cell is turned on. On the other hand, the second signal lines S2 other than the i-th row are set to the potential V_S20, and the transistors 202 of the non-selected memory cells are turned off. The potentials of the first signal lines S1(1) to S1(n) are set to V00 for the column where the data "00b" is written, V01 for the column where the data "01b" is written, V10 for the column where the data "10b" is written, and V11 for the column where the data "11b" is written, according to the signal DI input to the driving circuit 212 of the first signal line. That is, they are set as follows: At the end of writing, before the potentials of the first signal lines S1(1) to S1(n) change, the second signal line S2(i) is set to the potential V_S20 to turn off the transistor 202 of the selected memory cell. For other wirings, for example, the bit lines BL(1) to BL(n) are set to 0V, the word lines WL(1) to WL(m) are set to the potential V_WLS, the selection lines SEL(1), SEL "(2) are set to the potential V_SEL0, and the potentials of the source lines SL(1) to SL(n) are set to 0V. An example of the timing chart of the above writing operation is shown in Fig. 25(A). Note that Fig. 25( A) shows the timing chart when writing the data "10b" to the memory cell. ​​​​​​​

[0239] As a result, the potential of node A of the memory cell where data "00b" was written is approximately V00 [V], the potential of node A of the memory cell on which data "01b" was written is approximately V01[ [V], the potential of node A of the memory cell where data "10b" was written is approximately V10[V The potential of node A of the memory cell where data "11b" was written is approximately V11[V]. This is the result. Also, the potential of node A of the unselected memory cell remains unchanged. Here, node A has A charge corresponding to the potential of the first signal line S1 is accumulated, but the off-current of transistor 202 is Because it is extremely small, or practically zero, the gate electrode of transistor 201 ( The potential at node A) is maintained for a long period of time.

[0240] Next, we will explain the read operation of the semiconductor device. The read operation is read-enabled. This is done during the period when the signal is asserted. Also, during the read operation, the write enable signal is The data is inserted. The memory cells 200(i,1) to 200(i,n) of the i-th row are read. In this case, the potentials of the selection lines SEL(1) and SEL(2) are set to V_SEL1, and the transistor 215(1,1)~(1,n) and transistor 215(2,1)~(2,n) Set the state to n. Also, set the potential of word line WL(i) to V_WL1, and the word lines other than the i-th row W Let the potential of L be V_WL0. At this time, transistor 203 of the i-th row memory cell is O The state becomes "F". Transistor 203 of memory cells other than row i turns ON. Second signal Let the potential V_S2S be set at the line S2(1)~S2(m), and transistor 2 of all memory cells Set 02 to the OFF state. Set the potential of the first signal lines S1(1) to S1(n) to 0V.

[0241] During the read operation, the signal Φpc is asserted for the initial period. As a result, bit line B L is precharged to potential Vpc [V]. Next, source lines SL(1)~SL(n) Let Vs be the potential Vs of the memory cell. Depending on the state of station 201, current flows from the source line SL to the bit line BL, and the bit line BL The potential is represented by (potential at node A) - (threshold voltage Vth of transistor 201). It is charged by the bit line BL. As a result, the potential of the data "00b", "01b", "1 For 0b'' and 11b'', V00-Vth, V01-Vth, V10-Vth, V11 -Vth. The readout circuit reads the data "00b", "01" from these potential differences. It is possible to read "b", "10b", and "11b". Note that V11-Vth is V_ Ensure that SEL1-Vth_SEL and V_WL0-Vth_203 are less than or equal to the specified range. Here, Vth_SEL represents the threshold voltage of transistor 215, and Vth_203 is This represents the threshold voltage of transistor 203.

[0242] An example of a timing chart for the above read operation is shown in Figure 25(B). The figure shows, This is a timing chart for reading data "10b" from a memory cell. The potential of the word line WL becomes V_WL0, and the potential of the source line SL becomes Vs_read. The bit line BL corresponds to the memory cell data "10b" and charges the potential V10-Vth. It is powered. As a result, SA_OUT0, SA_OUT1, and SA_OUT2 are each " The results are 1", "1", and "0".

[0243] Furthermore, when writing, if a thin-film transistor is formed on the SOI substrate, the semiconductor... If the device does not have a substrate potential, the potential of the word lines WL(i+1) to WL(m) is set to V It is preferable to set the potential of _WL0 and the selected line SEL(2) to V_SEL1. at least the source electrode or drain electrode of transistor 201 of the i-th row memory cell The other potential can be set to approximately 0V. Alternatively, the potential of the selection line SEL(1) can be set to V_S. The potential of EL1, the word lines WL(1) to WL(i-1) may be defined as V_WL0. On the other hand, When a transistor is formed on a single-crystal semiconductor substrate, the semiconductor device has a substrate potential. In that case, the substrate potential can be set to 0V.

[0244] Note that the potential of the bit lines BL(1) to BL(n) during writing was set to 0V, but the selection line SE When the potential of L(1) is V_SEL0[V], it is either floating or greater than 0V. It is acceptable if the voltage is charged. The voltage of the first signal lines S1(1) to S1(n) during reading. The voltage is set to 0V, but it is acceptable for the battery to be in a floating state or charged to a potential above 0V.

[0245] Furthermore, in this embodiment, the first signal line S1 is arranged in the direction of the bit line BL (column direction), and the second The signal line S2 is positioned in the direction of the word line WL (row direction), but this configuration is not necessarily limited to this. It is not that it can be done. For example, if the first signal line S1 is placed in the word line WL direction (row direction), The two signal lines S2 may be arranged in the direction of the bit line BL (column direction). In that case, the The drive circuit to which the first signal line S1 is connected and the drive circuit to which the second signal line S2 is connected are as appropriate. Just place them.

[0246] In this embodiment, a quad-value memory cell operates, that is, one memory cell contains four different We have explained how to write and read either state, but the circuit configuration can be changed as needed. By changing it, an n-value memory cell is created, that is, any n different state (where n is 2 or less). The integers above can be written to and read from.

[0247] For example, an 8-level memory cell has three times the memory capacity compared to a 2-level memory cell. In this approach, eight different write potentials are prepared to determine the potential of node A, thereby generating eight different states. For reading, seven different reference potentials are prepared, which are capable of distinguishing between eight states. In the heading, one sense amplifier is installed, and it is possible to read the data after performing seven comparisons. Furthermore, by providing feedback on the comparison results, it is possible to reduce the number of comparisons to three. In the readout method that drives the source line SL, seven sense amplifiers are provided, It is also possible to read the results after multiple comparisons. Furthermore, multiple sense amplifiers can be used to perform multiple comparisons. It is also possible to configure it in this way.

[0248] Generally, 2 k In memory cells with a value (where k is an integer greater than or equal to 1), compared to the case of a binary value, The capacity will be k times greater. For writing, the write potential that determines the potential of node A is set to 2 k Prepare different types And, 2 k It generates a number of states. In reading, 2 k Two states that can distinguish between individual states k -It is good to prepare one type of reference potential. 2. Provide one sense amplifier. k -1 comparison It is possible to go and read the data. Also, by providing feedback on the comparison results, the comparison process can be repeated. It is also possible to reduce the number to k times. In the readout method that drives the source line SL, sense Two amplifiers k - You can also set up one and read it in a single comparison. Also, multiple senses are possible. It is also possible to configure the system to include an amplifier and perform multiple comparisons.

[0249] The semiconductor device according to this embodiment is extremely efficient due to the low off-current characteristics of the transistor 202. It is possible to retain information for a long period of time. In other words, it is required for DRAM, etc. Refresh operations are unnecessary, and power consumption can be reduced. Furthermore, it is virtually non-volatile. It can be used as a self-sustaining memory device.

[0250] Furthermore, information is written through the switching operation of transistor 202, It does not require high voltage and there are no issues with component degradation. Furthermore, the on / off switching of the transistor... Therefore, since information is written to and erased, high-speed operation can be easily achieved. By controlling the potential input to the transistor, it is possible to directly rewrite the information. Therefore, the erase operation required for flash memory and the like is unnecessary, and the erase operation This can suppress the decrease in operating speed caused by this.

[0251] Furthermore, transistors using materials other than oxide semiconductors are different from transistors using oxide semiconductors. Compared to standard, it allows for even faster operation, and by using this, the stored contents can be processed It is possible to perform reading at high speed.

[0252] Furthermore, since the semiconductor device according to this embodiment is a multi-level type, the number of units per area is greater than that of a binary type. The capacity can be increased. Therefore, it is possible to miniaturize and highly integrate semiconductor devices. Yes, it is possible. Furthermore, during the write operation, the potential of the floating node can be directly controlled. This allows for easy and precise threshold voltage control required for multi-level memory. This allows for the verification of the state after writing to multi-value memory. It can be omitted, which in turn reduces the time required for writing.

[0253] Furthermore, in the semiconductor device according to this embodiment, the output of the boost circuit is supplied to the potential generation circuit. By doing so, the absolute value of the potential difference can be made larger. Therefore, the smallest unit of the potential difference can be changed. It is possible to generate a higher potential without modification. In other words, one memory cell It is possible to increase the memory capacity.

[0254] The configurations and methods shown in this embodiment may be combined with the configurations and methods shown in other embodiments as appropriate. They can be used together.

[0255] (Embodiment 3) In this embodiment, an example of a semiconductor device circuit configuration and operation different from that of Embodiment 2 is described below. I will explain.

[0256] Figure 26 shows an example of a circuit diagram for a memory cell in a semiconductor device. The memory cell shown in Figure 26. 240 is a multi-level type, and has a first signal line S1, a second signal line S2, a word line WL, and a transit It consists of a transistor 201, a transistor 202, and a capacitive element 204. Transistor 201 is formed using a material other than an oxide semiconductor, and transistor 20 2 is formed using an oxide semiconductor. Here, transistor 201 is, in this embodiment It is preferable to have a configuration similar to that of transistor 160 shown in 1. Also, transistor 20 It is preferable that component 2 has the same configuration as transistor 162 shown in Embodiment 1. Memory cell 240 is electrically connected to source line SL and bit line BL, Source line SL and bit line B via the zista (including those that constitute other memory cells) It is preferable to electrically connect it to L.

[0257] Here, the gate electrode of transistor 201 and the source electrode or dot of transistor 202 One of the rain electrodes and one of the electrodes of the capacitive element 204 are electrically connected. The source wire SL and the source electrode of transistor 201 are electrically connected, and the transistor The drain electrode of sta201 and the bit line BL are electrically connected. The source electrode or drain electrode of the transistor 202 and the first signal line S1 are electrically connected. The second signal line S2 and the gate electrode of transistor 202 are electrically connected. The word line WL and the other electrode of the capacitive element 204 are electrically connected. Oh, the source wire SL and the source electrode of transistor 201 are transistors (other memory They may also be connected via bit lines BL and The drain electrode of Ranjista 201 is a transistor (and also a component of other memory cells). It may be connected via (including).

[0258] Here, we will briefly explain the operation of memory cell 240. For example, in the case of a quaternary type, The four states of the Recell 240 are designated as data "00b", "01b", "10b", and "11b". The potentials of node A of transistor 201 are V00, V01, V10, and V11 respectively. Let V00 < V01 < V10 < V11). The potential of node A of the memory cell 240 depends on the potential of the word line WL, and the higher the potential of the word line WL, the higher the potential of node A of the memory cell 240. For example, when the potential of the word line WL is changed from a low potential to a high potential for different 4-state memory cells, the transistor 201 of the memory cell with data "11b" first becomes in the on state, and subsequently, the memory cells with data "10b", "01b", and "00b" become in the on state in sequence. This means that by appropriately selecting the potential of the word line WL, the state of the memory cell (i.e., the data of the memory cell) can be identified. When the potential of the word line WL is appropriately selected, the memory cell with the transistor 201 in the on state becomes in a low-resistance state, and the memory cell with the transistor 201 in the off state becomes in a high-resistance state. Therefore, by distinguishing these resistance states by the read circuit, the data "00b", "01b", "10b", and "11b" can be read. By appropriately selecting the potential of the word line WL, the state of the memory cell (that is, the data of the memory cell) can be identified. This means that by appropriately selecting the potential of the word line WL, the memory cell with the transistor 201 in the on state becomes in a low-resistance state, and the memory cell with the transistor 201 in the off state becomes in a high-resistance state. Therefore, by distinguishing these resistance states by the read circuit, the data "00b", "01b", "10b", and "11b" can be read. When the potential of the word line WL is appropriately selected, the memory cell with the transistor 201 in the on state becomes in a low-resistance state, and the memory cell with the transistor 201 in the off state becomes in a high-resistance state. Therefore, by distinguishing these resistance states by the read circuit, the data "00b", "01b", "10b", and "11b" can be read. "10b", "11b" can be read.

[0259] Fig. 27 shows a block circuit diagram of a semiconductor device according to an aspect of the present invention having a storage capacity of m × n bits. Here, as an example, a NAND-type semiconductor device in which memory cells 240 are connected in series is shown.

[0260] The semiconductor device shown in Fig. 27 includes m word lines WL and a second signal line S2, n bit lines BL and a first signal line S1, two selection lines SEL(1) and SEL(2), and a plurality of memory cells 240(1,1) to 240(m,n) arranged in a matrix of m (rows) × n (columns) (m and n are natural numbers), a memory cell array 250, along the selection line SEL(1), bit lines BL(1) to BL(n) and memory cells 240(1,1) to 240(1,n) ​ The transistors 255(1,1)~255(1,n) are positioned between them, and the selection line SEL( 2) Along the source line SL(1)~SL(n) and memory cell 240(m,1)~240 The transistors 255(2,1) to 255(2,n) are positioned between (m,n), and the reading Output circuit 251, drive circuit 252 for the first signal line, and drive circuit for the second signal line and word line. 253, the potential generation circuit 254, and the selection line drive circuits 256(1) and 256(2) It is composed of peripheral circuits. Other peripheral circuits include a refresh circuit, etc. It's okay.

[0261] Consider each of the 240 memory cells, for example, memory cell 240(i,j) (where i is 1 or less). The upper integer is less than or equal to m, and j is an integer between 1 and n (inclusive). Memory cell 240(i,j) is The first signal line S1(j), the second signal line S2(i), and the word line WL(i) are connected respectively. It is also said that the memory cell 240(i1,j) (where i1 is an integer between 2 and m) has The drain electrode of transistor 201 is connected to the transistor of memory cell 240 (i1-1,j). Connected to the source electrode of the converter 201, memory cell 240(i2,j) (i2 is 1 or greater) The source electrode of transistor 201 (an integer less than or equal to m-1) is located in memory cell 240 (i It is connected to the drain electrode of transistor 201, which has 2+1,j). Memory cell 24 The drain electrode of transistor 201, which is located at 0(1,j), is located at transistor 255(1, The source electrode of j) is connected to the transistor 201 of the memory cell 240(m,j) The source electrode is connected to the drain electrode of transistor 255(2,j). The drain electrode of transistor 255(1,j) is connected to the bit line BL(j), and transistor 2 The source electrode at 55(2,j) is connected to the source wire SL(j).

[0262] Furthermore, the bit lines BL(1) to BL(n) are connected to the readout circuit 251, and the first signal line S1(1) ~S1(n) is connected to the drive circuit 252 of the first signal line, and the second signal lines S2(1)~S2(m) and Word lines WL(1) to WL(m) are connected to the second signal line and word line drive circuit 253, and the selected line SEL(1) and SEL(2) are connected to the drive circuits 256(1) and 256(2) of the selected lines, respectively. They are connected. A potential Vs is applied to source lines SL(1) to SL(n). Source lines SL(1) to SL(n) do not necessarily need to be separated, and they do not need to be electrically separated from each other. It's also acceptable to configure it so that it's connected in a way that allows for this.

[0263] Furthermore, the configurations of the first signal line drive circuit 252 and the potential generation circuit 254 are as follows: In state 2, the configurations shown in Figures 19 and 21 should be applied. Furthermore, the potential generation circuit 254 is... Instead of the power supply potential Vdd, the potential boosted by the boost circuit shown in Figure 22 in Embodiment 2 is supplied. It may also be supplied. Furthermore, the drive circuits 256(1) and 256(2) for the selection lines are also shown in Embodiment 2. You can apply the configuration described above.

[0264] Figure 28 shows an example of the readout circuit 251. The readout circuit consists of a sense amplifier circuit and a flip It has a push-flop circuit, a bias circuit 257, etc. The bias circuit 257 is a switch It is connected to the bit line BL via it. Also, the bias circuit 257 is the input of the sense amplifier circuit It is connected to the power terminal. The other input terminal of the sense amplifier circuit receives the reference potential Vref. Furthermore, the output terminal of the sense amplifier circuit is connected to the input terminal of the flip-flop circuit. The above switch is controlled by a read enable signal.

[0265] The readout circuit 251 shown in Figure 28 has one sense amplifier circuit and four different states Two comparisons will be performed for identification. The two comparisons will be based on signals RE0 and RE1. It is controlled by signals RE0 and RE1 respectively. It is controlled in this way, and the value of the output signal of the sense amplifier circuit is stored. Flip-flop circuit FF The output of 0 is the signal DOb[1], and the output of the flip-flop circuit FF1 is the signal DOb[ It is output from the readout circuit as [0].

[0266] In the illustrated readout circuit 251, when the RE signal is deasserted, the bit line BL Connect this to the wiring Vpc and perform precharging. When the RE signal is asserted, the bit line BL The bias circuit 257 then conducts. Note that precharging is not necessary.

[0267] Figure 29 shows an example of a drive circuit 253 for the second signal line and word line. The drive circuit 253 of the D line includes a decoder, multiplexer (MUX2), etc. (Second signal) Line S2 is a switch controlled by a light enable signal (WE signal), and Deco Wiring V_S20, wiring V_S21, via a switch controlled by the output signal. The wiring is connected to V_S2S. The word wire WL is connected to the read enable signal (RE signal). Therefore, via the switches controlled by the decoder output signal, It is connected to wiring V_WL0, wiring V_WL1, and wiring V_WLS. Also, multi The Plexor (MUX2) has signals RE0, RE1, DOb[1], and reference potentials Vref0, V ref1, Vref2, and GND are input, and the potential V_WL is output. The address signal is input from an external source.

[0268] When an address signal is input to the drive circuit 253 for the second signal line and word line, the address is The selected rows are asserted, and the other rows are deasserted. Furthermore, when the RE signal is deasserted, a potential V_WLS is applied to the word line WL, and RE When the signal is asserted, the word line WL of the selected row has a potential V_WL1, and the word line WL of the unselected row has a potential V_WL1. The potential V_WL0 is applied to each of the do-wires WL. Additionally, the WE signal is deasserted. Then, a potential V_S2S is applied to the second signal line S2, and when the WE signal is asserted, selection The second signal line S2 of the row has a potential V_S21, and the second signal line S2 of the unselected row has a potential V_S2 Each is assigned a value of 0. V_WL1 is selected by the multiplexer (MUX2). It is the electric potential. The multiplexer has three types depending on the values ​​of the signals RE0, RE1, and DOb[1]. Select one of the following reference potentials: Vref0, Vref1, Vref2, and GND. Table 3 shows the behavior of ticplexa (MUX2).

[0269] [Table 3]

[0270] Note that transistor 201, which is connected to the word line WL to which the potential V_WL0 is applied, is turned ON. This should be done. Also, the second signal line S to which potentials V_S2S and V_S20 are applied. The transistor 202 connected to 2 should be turned off. Also, the potential V_S21 is marked The transistor 202 connected to the added second signal line S2 is turned on.

[0271] Three types of reference potentials Vref0, Vref1, Vref2 (Vref0 <Vref1<Vr ef2) and the transient of the memory cell when that potential is selected as the potential of the word line WL Let's explain the state of station 201. Vref2 is selected as the potential of the word line WL. If selected, the transistor 201 of the memory cell with data "00b" is turned off. Select the potential that turns on transistor 201 of the memory cell with data "01b". Furthermore, if Vref1 is selected as the potential of the word line WL, then data "01 Turn off transistor 201 of memory cell "b", and turn off the memory cell "10b" Select the potential that turns on transistor 201. Also, Vref0 is set to When selected as the potential of the code line WL, the transient of the memory cell for data "10b" Turn off transistor 201 and turn on transistor 201 of the memory cell for data "11b". Select the potential to be the state.

[0272] In this case, the readout circuit 251 performs the readout by making two comparisons. The first comparison is The comparison is performed using Vref1. The second time, the comparison result DOb[1] using Vref1 is If the value is "0", compare using Vref0; if the value is "1", compare using Vref2. This is done. In this way, it becomes possible to read the four states through two comparisons. Yes.

[0273] In this embodiment, the number of comparisons in the read operation was set to two, but this configuration is not limited to this. It is not necessary. For example, it is also possible to configure to perform the comparison three times without feeding back the value after the comparison. Okay.

[0274] An example of a specific action potential (voltage) is shown. For example, the power supply potential is set to Vdd = 2V, and the threshold voltage Vth of the transistor 201 is set to 1.8V. The potential of node A depends on the capacitance C1 between the word line WL and node A and the gate capacitance C2 of the transistor 202. Here, as an example, it is assumed that C1 / C2 >> 1 when the transistor 202 is in the off state and C1 / C2 = 1 when the transistor 202 is in the on state. FIG. 30 shows the relationship between the potential of node A and the potential of the word line WL when the potential of the source line SL is 0V. From FIG. 30, for example, when the potential of node A for the data "00b" at the time of writing is 0V, the potential of node A for the data "01b" is 0.8V, the potential of node A for the data "10b" is 1.2V, and the potential of node A for the data "11b" is 1.6V, it can be seen that the reference potentials are Vref0 = 0.4V, Vref1 = 0.8V, and Vref2 = 1.2V. The potential of the word line WL and the potential of node A depend on the capacitance C1 between the word line WL and node A and the gate capacitance C2 of the transistor 202. Here, as an example, it is assumed that C1 / C2 >> 1 when the transistor 202 is in the off state and C1 / C2 = 1 when the transistor 202 is in the on state. FIG. 30 shows the relationship between the potential of node A and the potential of the word line WL when the potential of the source line SL is 0V. From FIG. 30, for example, when the potential of node A for the data "00b" at the time of writing is 0V, the potential of node A for the data "01b" is 0.8V, the potential of node A for the data "10b" is 1.2V, and the potential of node A for the data "11b" is 1.6V, it can be seen that the reference potentials are Vref0 = 0.4V, Vref1 = 0.8V, and Vref2 = 1.2V. The potential of node A depends on the capacitance C1 between the word line WL and node A and the gate capacitance C2 of the transistor 202. Here, as an example, it is assumed that C1 / C2 >> 1 when the transistor 202 is in the off state and C1 / C2 = 1 when the transistor 202 is in the on state. FIG. 30 shows the relationship between the potential of node A and the potential of the word line WL when the potential of the source line SL is 0V. From FIG. 30, for example, when the potential of node A for the data "00b" at the time of writing is 0V, the potential of node A for the data "01b" is 0.8V, the potential of node A for the data "10b" is 1.2V, and the potential of node A for the data "11b" is 1.6V, it can be seen that the reference potentials are Vref0 = 0.4V, Vref1 = 0.8V, and Vref2 = 1.2V. As an example, it is assumed that C1 / C2 >> 1 when the transistor 202 is in the off state and C1 / C2 = 1 when the transistor 202 is in the on state. FIG. 30 shows the relationship between the potential of node A and the potential of the word line WL when the potential of the source line SL is 0V. From FIG. 30, for example, when the potential of node A for the data "00b" at the time of writing is 0V, the potential of node A for the data "01b" is 0.8V, the potential of node A for the data "10b" is 1.2V, and the potential of node A for the data "11b" is 1.6V, it can be seen that the reference potentials are Vref0 = 0.4V, Vref1 = 0.8V, and Vref2 = 1.2V. FIG. 30 shows the relationship between the potential of node A and the potential of the word line WL when the potential of the source line SL is 0V. From FIG. 30, for example, when the potential of node A for the data "00b" at the time of writing is 0V, the potential of node A for the data "01b" is 0.8V, the potential of node A for the data "10b" is 1.2V, and the potential of node A for the data "11b" is 1.6V, it can be seen that the reference potentials are Vref0 = 0.4V, Vref1 = 0.8V, and Vref2 = 1.2V. From FIG. 30, for example, when the potential of node A for the data "00b" at the time of writing is 0V, the potential of node A for the data "01b" is 0.8V, the potential of node A for the data "10b" is 1.2V, and the potential of node A for the data "11b" is 1.6V, it can be seen that the reference potentials are Vref0 = 0.4V, Vref1 = 0.8V, and Vref2 = 1.2V. The potential of node A for the data "00b" at the time of writing is 0V, the potential of node A for the data "01b" is 0.8V, the potential of node A for the data "10b" is 1.2V, and the potential of node A for the data "11b" is 1.6V. When the potential of node A for the data "10b" is 1.2V and the potential of node A for the data "11b" is 1.6V, it can be seen that the reference potentials are Vref0 = 0.4V, Vref1 = 0.8V, and Vref2 = 1.2V. It can be seen that it is good to set the reference potentials to Vref0 = 0.4V, Vref1 = 0.8V, and Vref2 = 1.2V. It can be seen that it is good to set the reference potentials to Vref0 = 0.4V, Vref1 = 0.8V, and Vref2 = 1.2V.

[0275] The operation of the semiconductor device shown in FIG. 27 will be described. Here, the case of the 4-value type will be described. The four states of the memory cell 240 are set to the data "00b", "01b", "10b", and "11b", and the potential of node A at that time is set to V00, V01, V10, and V11 (V00 < V01 < V10 < V11), respectively. In this configuration, writing and reading are performed for each row. The four states of the memory cell 240 are set to the data "00b", "01b", "10b", and "11b", and the potential of node A at that time is set to V00, V01, V10, and V11 (V00 < V01 < V10 < V11), respectively. In this configuration, writing and reading are performed for each row. The four states of the memory cell 240 are set to the data "00b", "01b", "10b", and "11b", and the potential of node A at that time is set to V00, V01, V10, and V11 (V00 < V01 < V10 < V11), respectively. In this configuration, writing and reading are performed for each row.

[0276] First, the writing operation of the semiconductor device will be described. The writing operation is performed during the period when the write enable signal is asserted. Also, during the writing operation, the read enable signal is deasserted. The writing operation is performed during the period when the write enable signal is asserted. Also, during the writing operation, the read enable signal is deasserted. The data is inserted. Writing is performed to memory cells 240(i,1) to 240(i,n) of the i-th row. In this case, the second signal line S2(i) is set to potential V_S21, and the transient of the selected memory cell Turn on station 202. Meanwhile, set the potential of the second signal line S2 other than the i-th row to V_S20. , the transistor 202 of the unselected memory cell is turned off. First signal line S1(1)~ The potential of S1(n) depends on the signal DI input to the drive circuit 212 of the first signal line. In the column where "00b" is written, it is V00, in the column where "01b" is written, it is V01, The column where "10b" is written will be V10, and the column where "11b" is written will be V11. Furthermore, upon completion of the writing process, the potential of the first signal lines S1(1) to S1(n) will change. Before that, the second signal line S2(i) is set to potential V_S20, and the transient of the selected memory cell Turn off the STA202. Other wiring, for example, bit lines BL(1) to BL(n) The potential is 0V, the potential of the word lines WL(1) to WL(m) is V_WLS[V], and the selection line SEL (1) The potential of SEL(2) is V_SEL0[V], and the source lines SL(1)~SL(n) The potential Vs is set to 0V. The timing chart for the above writing operation is the same as in Figure 25(A). It appears that... Figure 25(A) shows the process of writing data "10b" to the memory cell. This is a timing chart for the combination.

[0277] As a result, the potential of node A, where data "00b" was written, was approximately V00[V]. The potential of node A of the memory cell that wrote "01b" is approximately V01[V], data The potential of node A of the memory cell that wrote "10b" is approximately V10[V], data The potential of node A of the memory cell that has been written with 11b" is approximately V11[V]. Therefore, the potential of node A of the unselected memory cell remains unchanged. Here, node A has the first signal line Charge is accumulated according to the potential of S1, but the off-current of transistor 202 is extremely small. Or, since it is practically zero, the gate electrode (node ​​A) of transistor 201 The electrical potential is maintained for an extended period.

[0278] Next, we will explain the read operation of the semiconductor device. The read operation is read-enabled. This is done during the period when the signal is asserted. Also, during the read operation, the write enable signal is The memory cells 240(i,1) to 240(i,n) of the i-th row are read. In this case, the potentials of the selection lines SEL(1) and SEL(2) are set to V_SEL1, and the transistor Turn on 255(1,1) to 255(2,n). Source lines SL(1) to SL(n Let the potential Vs of ) be 0V. Let the potential V_S2S be the second signal line S2(1)~S2(m), Turn off transistor 202 in all memory cells. First signal lines S1(1)~S1 Let the potential of (n) be 0V.

[0279] Then, the word line WL(i) is set to potential V_WL1, and the word lines WL other than the i-th row are set to potential V_W Let L0. Transistor 201 of memory cells other than the i-th row will be turned ON. As a result, The resistance state (conductance) between the bit line BL and the source line SL is the transient of the selected row. When TA201 is ON, it results in a low resistance state; when it is OFF, it results in a high resistance state. In the selection process, the potential of the word line WL is appropriately selected, and data transitions between different memory cells. The on / off states of TA201 are made different. As a result, the readout circuit is bit Distinguish between the resistance state (conductance) between line BL and source line SL, and use data "00b". It is possible to read "01b", "10b", and "11b". In other words, the specified memory space The data can be read by reading the resistance state (conductance) of the resistor. Reading the resistance state (conductance) of a memory cell means reading the tensile strength of the memory cell. This refers to reading the ON or OFF state of the inverter 201. An example of a timing chart is shown in Figure 31. Figure 31 shows the data from the memory cell. This is the timing chart for reading "01b". RE0 and RE1 are asserted. During the specified period, reference potentials Vref1 and Vref2 are input to the selected word line WL. The comparison results in the sense amplifier circuit were as follows for the flip-flop circuits FF0 and FF1, respectively It is stored. If the data of the memory cell is "01b", the flip-flop circuit FF0 The values ​​of FF1 will be "1" and "0". The potentials of the first signal line S1 and the second signal line S2 are It is 0V.

[0280] Note that the potential of node A of transistor 201 after writing (the potential of the word line WL is 0V) The value is preferably less than or equal to the threshold voltage of transistor 201. Also, V_WL 0=2V, V_WLS=0V, V_S20=0V, V_S21=2V, V_S2S=0V It can be done this way.

[0281] Note that during writing, the bit lines BL(1) to BL(n) were set to 0V, but the selection line SEL(1 If the potential of ) is V_SEL0, it is in a floating state or charged to a potential greater than 0V. It is acceptable if it is set to 0V. The first signal lines S1(1) to S1(n) during reading were set to 0V, It is acceptable for the battery to be in a floating state or charged to a potential greater than 0V.

[0282] Furthermore, in this embodiment, the first signal line S1 is arranged in the direction of the bit line BL (column direction), and the second The signal line S2 is positioned in the direction of the word line WL (row direction), but this configuration is not necessarily limited to this. It is not that it can be done. For example, if the first signal line S1 is placed in the word line WL direction (row direction), The two signal lines S2 may be arranged in the direction of the bit line BL (column direction). In that case, the The drive circuit to which the first signal line S1 is connected and the drive circuit to which the second signal line S2 is connected are as appropriate. Just place them.

[0283] In this embodiment, a quad-value memory cell operates, that is, one memory cell contains four different We have explained how to write and read either state, but the circuit configuration can be changed as needed. By changing it, an n-value memory cell is created, that is, any n different state (where n is 2 or less). The integers above can be written to and read from.

[0284] For example, an 8-level memory cell has three times the memory capacity compared to a 2-level memory cell. In this approach, eight different write potentials are prepared to determine the potential of node A, thereby generating eight different states. For reading, seven different reference potentials are prepared, which are capable of distinguishing between eight states. In the heading, one sense amplifier is installed, and it is possible to read the data after performing seven comparisons. Furthermore, by providing feedback on the comparison results, it is possible to reduce the number of comparisons to three. In the readout method that drives the source line SL, seven sense amplifiers are provided, It is also possible to read the results after multiple comparisons. Furthermore, multiple sense amplifiers can be used to perform multiple comparisons. It is also possible to configure it in this way.

[0285] Generally, 2 k In memory cells with a value (where k is an integer greater than or equal to 1), compared to the case of a binary value, The capacity will be k times greater. For writing, the write potential that determines the potential of node A is set to 2 k Prepare different types And, 2 k It generates a number of states. In reading, 2 k Two states that can distinguish between individual states k -It is good to prepare one type of reference potential. 2. Provide one sense amplifier. k -1 comparison It is possible to go and read the data. Also, by providing feedback on the comparison results, the comparison process can be repeated. It is also possible to reduce the number to k times. In the readout method that drives the source line SL, sense Two amplifiers k - You can also set up one and read it in a single comparison. Also, multiple senses are possible. It is also possible to configure the system to include an amplifier and perform multiple comparisons.

[0286] The semiconductor device according to this embodiment is extremely efficient due to the low off-current characteristics of the transistor 202. It is possible to retain information for a long period of time. In other words, it is required for DRAM, etc. Refresh operations are unnecessary, and power consumption can be reduced. Furthermore, it is virtually non-volatile. It can be used as a self-sustaining memory device.

[0287] Furthermore, information is written through the switching operation of transistor 202, It does not require high voltage and there are no issues with component degradation. Furthermore, the on / off switching of the transistor... Therefore, since information is written to and erased, high-speed operation can be easily achieved. By controlling the potential input to the transistor, it is possible to directly rewrite the information. Therefore, the erase operation required for flash memory and the like is unnecessary, and the erase operation is This can suppress the resulting decrease in operating speed.

[0288] Furthermore, transistors using materials other than oxide semiconductors are different from transistors using oxide semiconductors. Compared to standard, it allows for even faster operation, and by using this, the stored contents can be processed It is possible to perform reading at high speed.

[0289] Furthermore, since the semiconductor device according to this embodiment is a multi-level type, the number of units per area is greater than that of a binary type. The capacity can be increased. Therefore, it is possible to miniaturize and highly integrate semiconductor devices. Yes, it is possible. Furthermore, during the write operation, the potential of the floating node can be directly controlled. This allows for easy and precise threshold voltage control required for multi-level memory. This allows for the verification of the state after writing to multi-value memory. It can be omitted, which in turn reduces the time required for writing.

[0290] Furthermore, in the semiconductor device according to this embodiment, the output of the boost circuit is supplied to the potential generation circuit. By doing so, the absolute value of the potential difference can be made larger. Therefore, the smallest unit of the potential difference can be changed. It is possible to generate a higher potential without modification. In other words, one memory cell It is possible to increase the memory capacity.

[0291] The configurations and methods shown in this embodiment may be combined with the configurations and methods shown in other embodiments as appropriate. They can be used together.

[0292] (Embodiment 4) In this embodiment, an example of an electronic device equipped with the semiconductor device obtained in the previous embodiment is described below. This will be explained using Figure 32. The semiconductor device obtained in the above embodiment does not have a power supply. Even in such cases, it is possible to retain information. Furthermore, no degradation occurs due to writing and erasing. Furthermore, its operation is also high-speed. For this reason, a new configuration of electric device can be created using this semiconductor device. It is possible to provide sub-devices. Furthermore, the semiconductor device according to the above embodiment is integrated These components are then mounted on circuit boards and installed inside various electronic devices.

[0293] Figure 32(A) shows a notebook-type personal computer including a semiconductor device according to the above embodiment. It is a data system consisting of the main unit 301, the casing 302, the display unit 303, the keyboard 304, etc. This has been done. A semiconductor device according to one aspect of the present invention is used in a notebook-type personal computer. By applying this technology, it becomes possible to retain information even when there is no power supply. Also, There is no degradation associated with writing and erasing. Furthermore, the operation is also fast. For this reason, It is preferable to apply a semiconductor device according to one embodiment of the invention to a notebook-type personal computer. That is the case.

[0294] Figure 32(B) shows a personal digital assistant (PDA) including a semiconductor device according to the previous embodiment. The main unit 311 includes a display unit 313, an external interface 315, and operation buttons 314, etc. A stylus 312 is provided as an accessory for operation. By applying the semiconductor device mentioned above to a PDA, information can be retained even when there is no power supply. It is possible to do so. Furthermore, no degradation occurs due to writing and erasing. Moreover, its operation is It is high-speed. For this reason, it is preferable to apply a semiconductor device according to one aspect of the present invention to a PDA. That is the case.

[0295] Figure 32(C) shows an example of electronic paper including a semiconductor device according to the above embodiment, This shows the e-book 320. The e-book 320 is housed in two enclosures, enclosure 321 and enclosure 323. It is constructed such that the housing 321 and housing 323 are integrated by the shaft portion 337. The shaft portion 337 can be used as an axis for opening and closing operations. With this configuration, electronic books The 320 can be used like a paper book. A semiconductor device according to one aspect of the present invention By applying this technology to e-paper, information can be retained even when there is no power supply. It is possible. Furthermore, no degradation occurs during writing and erasing. Moreover, the operation is also high-speed. Therefore, it is preferable to apply a semiconductor device according to one aspect of the present invention to electronic paper. be.

[0296] The display unit 325 is incorporated into the housing 321, and the display unit 327 is incorporated into the housing 323. The display units 325 and 327 may be configured to display a continuation screen, or differently. It is also possible to configure the system to display a different screen. By configuring the system to display different screens, for example, Text is displayed on the right-hand display unit (display unit 325 in Figure 32(C)), and on the left-hand display unit (Figure 32 (C) allows an image to be displayed on the display unit 327).

[0297] Furthermore, Figure 32(C) shows an example in which the housing 321 is equipped with an operating section, etc. The body 321 is equipped with a power supply 331, operation keys 333, speaker 335, etc. Pages can be turned using -333. Note that the keyboard and port are located on the same surface as the display unit. The configuration may also include input devices, etc. Connection terminals (earphone jack, USB terminal, or AC adapter and USB cable, etc.) The configuration may also include terminals that can be connected to various cables, a recording medium insertion section, and so on. Furthermore, eBook 320 may be configured to also function as an electronic dictionary.

[0298] Furthermore, the e-book 320 may be configured to transmit and receive information wirelessly. It is also possible to configure the system to allow users to purchase and download desired book data from a sub-book server. It is possible.

[0299] Furthermore, electronic paper can be applied to any field that displays information. For example, in addition to ebooks, there are posters, advertisements on trains and other vehicles, and credit cards. This can be applied to displays on various types of cards, such as TCG cards.

[0300] Figure 32(D) shows a mobile phone including a semiconductor device according to the previous embodiment. The telephone consists of two housings, housing 340 and housing 341. Housing 341 is front Display panel 342, speaker 343, microphone 344, pointing device 3 It is equipped with 46, a camera lens 347, an external connection terminal 348, etc. Also, the housing 340 This includes a solar cell 349 for charging the mobile phone, an external memory slot 350, etc. It is equipped with. Furthermore, the antenna is built into the housing 341. This is according to one aspect of the present invention. By applying semiconductor devices to mobile phones, information can be retained even when there is no power supply. This is possible. Furthermore, no degradation occurs during writing and erasing. Moreover, its operation is also high-performance. It is fast. For this reason, applying a semiconductor device according to one aspect of the present invention to a mobile phone is preferable. It is suitable.

[0301] The display panel 342 has a touch panel function, and the image displayed in Figure 32(D) is Multiple operation keys 345 are shown with dotted lines. Note that the mobile phone has a solar cell 34 A boost circuit is implemented to increase the voltage output from 9 to the voltage required for each circuit. Furthermore, in addition to the above configuration, the configuration will incorporate a contactless IC chip, a small recording device, etc. It's also possible.

[0302] The display panel 342 changes its orientation as appropriate depending on the usage mode. Since the camera lens 347 is located on the same plane as 42, video calls are possible. Speaker 343 and microphone 344 are not limited to voice calls, but also video calls, recording, and playback. Raw materials can be used. Furthermore, the housing 340 and housing 341 slide together, as shown in Figure 32(D). It can be transformed from an unfolded state to an overlapping state, and can be made smaller for portability. It is Noh.

[0303] External connection terminal 348 can be connected to various cables such as AC adapters and USB cables. It also enables charging and data communication. In addition, the external memory slot 350 can be used for recording media. By inserting this, it can handle the storage and movement of larger amounts of data. In addition to the above functions, It may also be equipped with infrared communication capabilities, television reception capabilities, etc.

[0304] Figure 32(E) shows a digital camera including a semiconductor device according to the previous embodiment. The digital camera consists of the main unit 361, the display unit (A) 367, the eyepiece 363, and the operation switch 364. It consists of a display unit (B) 365, a battery 366, and the like. One aspect of the present invention By applying the semiconductor device to a digital camera, information can be transmitted even when there is no power supply. It is possible to retain it. Furthermore, no degradation occurs due to writing or erasing. Its operation is also fast. For this reason, a semiconductor device according to one aspect of the present invention is suitable for a digital camera. It is preferable to use it.

[0305] Figure 32(F) shows a television apparatus including a semiconductor device according to the previous embodiment. In the vision device 370, the display unit 373 is incorporated into the housing 371. This makes it possible to display video. Note that here, the enclosure is connected by stand 375. This shows the configuration that supported 371.

[0306] The television device 370 can be operated using the control switches on the housing 371 or a separate remote control. This can be done using the control unit 380. The operation keys 379 on the remote control unit 380 This allows you to control the channel and volume, and manipulate the image displayed on the display unit 373. It is possible to output from the remote control unit 380 to the remote control unit 380. A configuration may also be provided that includes a display unit 377 for displaying the information. Semiconductor according to one aspect of the present invention By applying this device to a television system, information can be retained even when there is no power supply. It is possible to do so. Furthermore, no degradation occurs due to writing and erasing. Moreover, its operation is It is high-speed. For this reason, a semiconductor device according to one aspect of the present invention is applied to a television apparatus. This is preferable.

[0307] Furthermore, it is preferable that the television equipment 370 be configured to include a receiver, modem, etc. The receiver can receive regular television broadcasts. It can also receive broadcasts via a modem. By connecting to a wired or wireless communication network, one-way communication (from sender to receiver) is possible. (Sender) or two-way information communication (between sender and receiver, or between receivers, etc.) This is possible.

[0308] The configurations and methods shown in this embodiment may be combined with the configurations and methods shown in other embodiments as appropriate. They can be used together. [Explanation of symbols]

[0309] 100 circuit boards 102 Protective layer 104 Semiconductor field 106 Element isolation insulating layer 108 Gate Insulation Layer 110 Guard Station 112 Insulating layer 114 Impurity region 116 Channel formation region 118 Sidewall insulation layer 120 High concentration impurity region 122 Metal layer 124 Metal compound area 126 Interlayer insulating layer 128 Interlayer insulating layer 130a Source electrode or drain electrode 130b Source electrode or drain electrode 130c electrode 132 Insulating layer 134 Conductive layer 136a electrode 136b Electrode 136c electrode 136d Gate 138 Gate Insulation Layer 140 Oxide semiconductor layer 142a Source electrode or drain electrode 142b Source electrode or drain electrode 144 Protective insulating layer 146 Interlayer insulating layer 148 Conductive layer 150a electrode 150b electrode 150c electrode 150d electrode 150e electrode 152 Insulating layer 154a electrode 154b electrode 154c electrode 154d electrode 160 transistors 162 transistors 200 memory cells 201 Transistors 202 transistors 203 Transistors 204 Capacitive element 205 Capacitive element 210 memory cell array 211 Readout Circuit 212 First signal line drive circuit 213 Drive circuit for the second signal line and word line 214 Potential generation circuit 215 transistors 216 Selected Line Drive Circuit 217 Source wire drive circuit 219 Boost Circuit 240 memory cells 250 memory cell array 251 Readout Circuit 252 First signal line drive circuit 253 Drive circuit for the second signal line and word line 254 Potential generation circuit 255 transistors 256 Selected Line Drive Circuit 257 Bias Circuit 301 Main Unit 302 enclosures 303 Display section 304 Keyboard 311 Main Unit 312 Stylus 313 Display section 314 Operation Buttons 315 External Interface 320 eBooks 321 cabinet 323 enclosures 325 Display section 327 Display section 331 Power supply 333 Operation Keys 335 speakers 337 Shaft 340 cabinets 341 cabinets 342 Display Panel 343 speakers 344 Microphone 345 Operation Keys 346 Pointing devices 347 Camera Lenses 348 External connection terminals 349 solar cells 350 external memory slots 361 Main Unit 363 Eyepiece 364 Operation Switches 365 Display section (B) 366 Battery 367 Display section (A) 370 Television equipment 371 cabinets 373 Display section 375 Stand 377 Display section 379 Operation Keys 380 Remote Control Unit 402 First diode 404 Second diode 406 Third diode 408 Fourth diode 410 Fifth diode 412 First capacitive element 414 Second capacitive element 416 Third capacitive element 418 Fourth capacitive element 420 Fifth capacitive element

Claims

[Claim 1] Source line and, Bit lines and, First signal line and, Multiple second signal lines, Multiple word lines, A plurality of memory cells are connected in series between the source line and the bit line, A drive circuit for second signal lines and word lines, which receives an address signal and drives the plurality of second signal lines and the plurality of word lines to select a memory cell specified by the address signal from among the plurality of memory cells, A drive circuit for the first signal line that selects one of several write potentials and outputs it to the first signal line, A readout circuit receives the potential of the bit line and a plurality of reference potentials as inputs, and reads out data by comparing the potential of the bit line with the plurality of reference potentials. The system includes a potential generation circuit that generates the plurality of write potentials and the plurality of reference potentials and supplies them to the drive circuit and the read circuit of the first signal line, One of the aforementioned plurality of memory cells is A first transistor having a first gate electrode, a first source electrode, and a first drain electrode, A second transistor having a second gate electrode, a second source electrode, and a second drain electrode, The third transistor has a third gate electrode, a third source electrode, and a third drain electrode, The first transistor is provided on a substrate containing a semiconductor material, The second transistor described above is composed of an oxide semiconductor layer, The first gate electrode and either the second source electrode or the second drain electrode are electrically connected. The source wire, the first source electrode, and the third source electrode are electrically connected. The bit line, the first drain electrode, and the third drain electrode are electrically connected. The first signal line and the other of the second source electrode or the second drain electrode are electrically connected. One of the plurality of second signal lines and the second gate electrode are electrically connected. A semiconductor device in which one of the plurality of word lines is electrically connected to the third gate electrode.

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