Verification and read control technologies for memory devices

Abstract

This invention provides a method for operating a memory device that includes multiple memory holes of various diameters. [Solution] In a memory device, word lines are grouped into a first group and a second group based on the memory hole diameter. The circuit determines whether a selected word line is in the first group or the second group. In response that the selected word line is in the first zone, the circuit performs a memory operation using a first set of reference voltages. In response that the selected word line is in the second group, the circuit performs a memory operation using a second set of reference voltages. The first and second sets of reference voltages differ for multiple data states and are similar for at least one data state in the highest threshold voltage range.

Description

Technical Field

[0001] (Field of the Invention) The subject disclosure generally relates to memory devices, and more specifically to improved read verification techniques for improving reliability.

[0002] (Related Applications) Semiconductor memories are widely used in various electronic devices such as mobile phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, servers, solid state drives, non-mobile computing devices, etc. Semiconductor memories can include non-volatile memories or volatile memories. In non-volatile memories, the non-volatile memory can store and retain information even when not connected to a power source, such as a battery.

[0003] A NAND memory device includes a chip having a plurality of memory blocks, and each memory block includes an array of memory cells arranged as a plurality of word lines. The memory cells can be programmed to have a threshold voltage associated with a data state. During a sense operation, a reference voltage is applied to the selected word line, and the threshold voltage of the memory cell is compared to the reference voltage. By repeating this process with a set of reference voltages, it is possible to determine in which data state the memory cells of the selected word line are.

Summary of the Invention

[0004] One aspect of the present disclosure relates to a method for operating a memory device. The method includes the step of preparing a memory block having an array of memory cells arranged as a plurality of word lines. The memory block further includes a plurality of memory holes having varying diameters and through which the plurality of word lines pass. The word lines are grouped into a first group and a second group based on the diameter of the memory holes. The method follows the step of determining whether a selected word line of the plurality of word lines is in the first group or the second group. In response that the selected word line is in the first group, the method follows the step of performing a memory operation using a first set of reference voltages. In response that the selected word line is in the second group, the method follows the step of performing a memory operation using a second set of reference voltages. The first and second sets of reference voltages are different for a plurality of data states and similar for at least one data state in the highest threshold voltage range.

[0005] According to another aspect of the present disclosure, the memory operation is a 3-bit memory operation per memory cell, and each of the first and second sets of reference voltages comprises seven reference voltages associated with seven programmed data states in various threshold voltage ranges.

[0006] According to yet another aspect of this disclosure, the memory operation is a programming operation, and the reference voltages of the first set and the second set of reference voltages are verify voltages.

[0007] According to yet another aspect of the present disclosure, the reference voltages of the second set of reference voltages are greater than the reference voltages of the first set of reference voltages, such that programming the memory cells of the word lines in the second zone for a first six programmed data state increases the margin between erased data states and the first programmed data states compared to programming the memory cells of the word lines in the first zone.

[0008] According to yet another aspect of this disclosure, for each programmed data state except the final data state, the reference voltage of the second set of reference voltages is greater than the reference voltage of the first set of reference voltages by a first offset.

[0009] According to yet another aspect of this disclosure, the memory holes have a larger diameter in the word lines of the first zone and a smaller diameter in the word lines of the second zone.

[0010] According to yet another aspect of this disclosure, the memory operation is a read operation.

[0011] According to another aspect of this disclosure, for each of the data states of a plurality of data states, excluding the final data state, the reference voltage is equal to the verify voltage of that data state plus a first offset and a second offset. In the case of the final data state, the reference voltage is equal to the verify voltage of the final data state plus a first offset.

[0012] Another aspect of the present disclosure relates to a memory device. The memory device includes a memory block comprising an array of memory cells arranged as a plurality of word lines. The memory block further includes a plurality of memory holes having varying diameters and passing through the plurality of word lines. The word lines are grouped into a first group and a second group based on the memory hole diameter. The memory device further includes a circuit for performing a memory operation on a selected word line of the plurality of word lines. The circuit is configured to determine whether the selected word line is in the first group or the second group. In response that the selected word line is in the first zone, the circuit is configured to perform a memory operation using a first set of reference voltages. In response that the selected word line is in the second group, the circuit is configured to perform a memory operation using a second set of reference voltages. The first and second sets of reference voltages are different for a plurality of data states and similar for at least one data state in the highest threshold voltage range.

[0013] According to another aspect of the present disclosure, the memory operation is a 3-bit memory operation per memory cell, and each of the first and second sets of reference voltages comprises seven reference voltages associated with seven programmed data states in various threshold voltage ranges.

[0014] According to yet another aspect of this disclosure, the memory operation is a programming operation, and the reference voltages of the first set and the second set of reference voltages are verify voltages.

[0015] According to yet another aspect of the present disclosure, the reference voltage of the second set of reference voltages is greater than the reference voltage of the first set of reference voltages, such that programming the memory cells of the word lines in the second zone for the first six programmed data states increases the margin between the erased data states and the first programmed data states compared to programming the memory cells of the word lines in the first group.

[0016] According to yet another aspect of this disclosure, for each programmed data state except the final data state, the reference voltage of the second set of reference voltages is greater than the reference voltage of the first set of reference voltages by a first offset.

[0017] According to yet another aspect of this disclosure, the memory holes have a larger diameter in the word lines of the first zone and a smaller diameter in the word lines of the second zone.

[0018] According to yet another aspect of this disclosure, the memory operation is a read operation.

[0019] According to another aspect of this disclosure, for each of the data states of a plurality of data states, excluding the final data state, the reference voltage is equal to the verify voltage of that data state plus a first offset and a second offset. In the case of the final data state, the reference voltage is equal to the verify voltage of the final data state plus a first offset.

[0020] A further aspect of the present disclosure relates to an apparatus comprising a memory block having an array of memory cells arranged as a plurality of word lines. The memory block further comprises a plurality of memory holes having varying diameters and passing through the plurality of word lines. The plurality of word lines comprises a bottom-level word line and other word lines. The apparatus further comprises a sensing means configured to perform a sensing operation on a selected word line of the plurality of word lines. The sensing means is configured to determine whether the selected word line is one of the bottom-level word lines or one of the other word lines. In response that the selected word line is one of the other word lines, the sensing means is configured to perform a sensing operation using a first set of reference voltages. In response that the selected word line is one of the bottom-level word lines, the sensing means is configured to perform a sensing operation using a second set of reference voltages. The first and second sets of reference voltages are different for a plurality of data states and similar for at least one data state in the highest threshold voltage range.

[0021] According to another aspect of this disclosure, the detection operation is a verify operation, and the reference voltages of the first set and the second set of reference voltages are verify voltages.

[0022] According to yet another aspect of this disclosure, the detection operation is a reading operation.

[0023] According to another aspect of the present disclosure, the sensing operation is a 3-bit sensing operation per memory cell, and each of the first and second sets of reference voltages comprises seven reference voltages associated with seven programmed data states in various threshold voltage ranges. [Brief explanation of the drawing]

[0024] A more detailed description will be given below with reference to the exemplary embodiments depicted in the accompanying drawings. It should be understood that these figures are merely illustrative of the exemplary embodiments of the present disclosure and thus do not limit the scope thereof. The following accompanying drawings are used to describe and explain the present disclosure in conjunction with additional specificity and details. [Figure 1A] It is a block diagram of an exemplary memory device. [Figure 1B] It is a block diagram of an exemplary control circuit. [Figure 1C] It is a block diagram of an exemplary circuit of the memory device of FIG. 1A. [Figure 2] It is a diagram showing a block of memory cells in an exemplary two-dimensional configuration of the memory array of FIG. 1A. [Figure 3A] It is a cross-sectional view of an exemplary floating-gate memory cell within a NAND string. [Figure 3B] It is a cross-sectional view of an exemplary floating-gate memory cell within a NAND string. [Figure 4A] It is a cross-sectional view of an exemplary charge-trapping memory cell within a NAND string. [Figure 4B] It is a cross-sectional view of an exemplary charge-trapping memory cell within a NAND string. [Figure 5] It is a block diagram of an exemplary sense block SB1 of FIG. 1. [Figure 6A] It is a perspective view of a set of blocks in an exemplary three-dimensional configuration of the memory array of FIG. 1. [Figure 6B] It is a cross-sectional view of a part of one of the blocks of FIG. 6A. [Figure 6C] It is a diagram showing a plot of the memory hole diameter in the stack of FIG. 6B. [Figure 6D] It is an enlarged view of the region 622 of the stack of FIG. 6B. [Figure 7A] It is a top view of an exemplary word line layer WL0 of the stack of FIG. 6B. [Figure 7B] It is a top view of an exemplary top dielectric layer DL116 of the stack of FIG. 6B. [Figure 8] This is a cross-sectional view through a portion of a memory block and a pair of memory holes. [Figure 9] This figure shows the threshold voltage distribution for pages of a memory cell programmed with 3 bits per memory cell (TLC). [Figure 10] This is a schematic diagram of an example NAND string during detection operation. [Figure 11] This figure shows the threshold voltage distribution of memory cell pages after they have been programmed into TLC but have undergone true temperature data retention (TTDR). [Figure 12] This figure shows the threshold voltage distribution of memory cell pages after they have been programmed into a TLC but have undergone a read disturb (RD). [Figure 13] This is a plot of voltages applied to word lines in a memory block, showing the verification voltages applied during programming of various word lines. [Figure 14] This figure shows a threshold voltage distribution plot for two pages of a memory cell, including a first page programmed using a first set of verify voltages and a second page programmed using a different second set of verify voltages. [Figure 15] This is a flowchart illustrating the steps for programming a selected word line memory cell according to an exemplary embodiment of the present disclosure. [Figure 16] This is a flowchart illustrating the step of reading a memory cell of a selected word line according to an exemplary embodiment of the present disclosure. [Modes for carrying out the invention]

[0025] This disclosure relates to an operating technique for memory devices that improves true temperature data retention (TTDR) without compromising read disturb (RD). This is achieved by introducing a verification voltage and read voltage for the lowest layer of at least one data state, separate from the verification voltages and read voltages for other data states. By improving TTDR and RD, reliability is improved.

[0026] Figure 1A is a block diagram of an exemplary memory device 100 configured to sense (read and verify) memory cells of a memory block according to the read-verify technique of the subject disclosure. The memory die 108 includes a memory structure 126 consisting of memory cells such as an array of memory cells, a control circuit 110, and a read / write circuit 128. The memory structure 126 is addressable by word lines via a row decoder 124 and by bit lines via a column decoder 132. The read / write circuit 128 includes a plurality of sense blocks SB1, SB2, ... SBp (sense circuits) that can read or program one page of memory cells in parallel. Typically, a controller 122 is included in the same memory device 100 (e.g., a removable storage card) as one or more memory dies 108. Commands and data are transferred between the host 140 and the controller 122 via a data bus 120, and further transferred between the controller and one or more memory dies 108 via a line 118.

[0027] The memory structure 126 may be two-dimensional or three-dimensional. The memory structure 126 may include one or more arrays of memory cells, including a three-dimensional array. The memory structure 126 may include a monolithic three-dimensional memory structure in which multiple memory levels are formed on (but not in) a single substrate, such as a wafer, without the interposition of a substrate. The memory structure 126 may include any type of non-volatile memory, monolithically formed within one or more physical levels of an array of memory cells having active regions located on a silicon substrate. The memory structure 126 may be in a non-volatile memory device having circuits associated with the operation of memory cells, whether the associated circuits are on or inside the substrate.

[0028] The control circuit 110 works in cooperation with the read / write circuit 128 to perform memory operations on the memory structure 126 and includes a state machine 112, an on-chip address decoder 114, and a power control module 116. The state machine 112 provides chip-level control of the memory operations.

[0029] The storage area 113 may be provided, for example, for programming parameters. Programming parameters may include a program voltage, a program voltage bias, a location parameter indicating the location of a memory cell, a contact line connector thickness parameter, a verify voltage, and / or the like. The location parameter may indicate the location of a memory cell within an entire array of NAND strings, the location of a memory cell as existing within a particular group of NAND strings, the location of a memory cell on a particular plane, and / or the like. The contact line connector thickness parameter may indicate the thickness of a contact line connector, a substrate or material on which the contact line connector is formed, and / or the like.

[0030] The on-chip address decoder 114 provides an address interface between the address used by the host or memory controller and the hardware address used by decoders 124 and 132. The power control module 116 controls the power and voltage supplied to the word and bit lines during memory operation. This may include drivers for the word line, SGS, and SGD transistors, as well as the source line. In one approach, the sense block may include the bit line driver. The SGS transistor is a selection gate transistor at the source end of the NAND string, and the SGD transistor is a selection gate transistor at the drain end of the NAND string.

[0031] In some embodiments, some of the components can be combined. In various designs, one or more components other than the memory structure 126 (either individually or in combination) can be considered as at least one control circuit configured to perform the operations described herein. For example, the control circuit may include any one or a combination of the control circuit 110, state machine 112, decoders 114 / 132, power control module 116, sense blocks SBb, SB2,...SBp, read / write circuit 128, controller 122, etc.

[0032] The control circuit 150 may include a programming circuit 151 configured to perform a program verify operation on a set of memory cells, the set of memory cells including a memory cell assigned to represent one data state of a plurality of data states and a memory cell assigned to represent another data state of a plurality of data states. This program verify operation includes a plurality of program verify iterations, in which the programming circuit performs programming on a selected word line and then applies a verify signal to the selected word line. The control circuit 150 may further include a counting circuit 152 configured to obtain a count of memory cells that have passed a verify test for a given data state. The control circuit 150 may further include a determination circuit 153 configured to determine whether the programming operation is complete based on the amount by which this count exceeds a threshold.

[0033] For example, Figure 1B is a block diagram of an exemplary control circuit 150, which includes a programming circuit 151, a counting circuit 152, and a determination circuit 153.

[0034] The off-chip controller 122 may include a processor 122c, storage devices (memory) such as ROM 122a and RAM 122b, an error correction code (ECC) engine 245, and a reference voltage engine 246. The ECC engine can correct a large number of read errors that occur when the upper tail of the Vt distribution is too high. However, there may be errors that cannot be corrected. The techniques provided herein reduce the likelihood of errors that cannot be corrected.

[0035] Storage devices 122a and 122b contain code, such as instruction sets, and the processor 122c is operable to execute the instruction sets to provide the functions described herein. Alternatively, or additionally, the processor 122c may access the code from the storage device 126a of the memory structure 126, such as reserved areas of memory cells in one or more word lines. For example, the controller 122 may use the code to access the memory structure 126 for programming, reading, and erasing operations. The code may include boot code and control code (e.g., a set of instructions). The boot code is software that initializes the controller 122 during the boot, or startup process, and enables the controller 122 to access the memory structure 126. The code can be used by the controller 122 to control one or more memory structures 126. When power is applied, the processor 122c fetches and executes the boot code from ROM 122a or storage device 126a, the boot code initializes system components, and the control code loads into RAM 122b. Once loaded into RAM 122b, the control code is executed by processor 122c. The control code includes drivers that perform basic tasks such as controlling and allocating memory, prioritizing instruction processing, and controlling input and output ports.

[0036] In general, control codes may include instructions that perform the functions described herein and provide voltage waveforms, including those described below, including steps in the flowchart which will be further discussed later. For example, as illustrated in Figure 1C, control circuits 110, controller 122, control circuit 150, and / or any other circuits are configured / programmed to determine in step 160 during memory operation whether the selected word line WLn is the lowest-level word line in the memory block or one of the other word lines in the memory block. In step 161, in response that the selected word line WLn is one of the other word lines, a set of reference voltages to be used in a subsequent sensing operation is set to a first set of reference voltages, and in response that the selected word line WLn is the lowest-level word line, it is set to a second set of reference voltages. In step 162, a sensing operation is performed. In some embodiments, the sensing operation is a verify operation. In some other embodiments, the sensing operation is a read operation. These techniques will be further described below.

[0037] In one embodiment, the host is a computing device (e.g., a laptop, desktop, smartphone, tablet, or digital camera) that includes one or more processors and one or more processor-readable storage devices (RAM, ROM, flash memory, hard disk drive, solid-state memory) that store processor-readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host may further include additional system memory, one or more input / output interfaces, and / or one or more input / output devices that communicate with the one or more processors.

[0038] In addition to NAND flash memory, other types of non-volatile memory can also be used.

[0039] Semiconductor memory devices include volatile memory devices such as dynamic random access memory ("DRAM") or static random access memory ("SRAM") devices, non-volatile memory devices such as resistive random access memory ("ReRAM"), electrically erasable programmable read-only memory ("EEPROM"), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory ("FRAM"), and magnetoresistive random access memory ("MRAM"), as well as other semiconductor elements capable of storing information. Each type of memory device may have a different configuration. For example, flash memory devices may be configured in a NAND or NOR configuration.

[0040] Memory devices can be formed from passive and / or active elements in any combination. In non-limiting embodiments, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity switching storage elements such as antifuses or phase change materials, and steering elements such as diodes or transistors as appropriate. In even more non-limiting embodiments, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements that house charge storage regions, such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0041] Multiple memory elements can be configured so that they are connected in series, or so that each element is individually accessible. As a non-limiting example, flash memory devices with a NAND configuration (NAND memory) typically include memory elements connected in series. A NAND string is an example of a set of transistors connected in series, including memory cells and SG transistors.

[0042] A NAND memory array may be configured such that the array consists of multiple memory strings, where each string consists of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, the memory elements may be configured such that each element is individually accessible (e.g., a NOR memory array). NAND and NOR memory configurations are examples, and memory elements may be configured in other ways. Semiconductor memory elements located in and / or on a substrate may be arranged in two or three dimensions, such as a two-dimensional memory structure or a three-dimensional memory structure.

[0043] In a two-dimensional memory structure, semiconductor memory elements are arranged in a single plane or at the single memory device level. Typically, in a two-dimensional memory structure, memory elements are arranged in a plane (e.g., an xy-direction plane) that extends substantially parallel to the main surface of the substrate supporting the memory elements. The substrate may be a wafer on which layers of memory elements are formed, or a carrier substrate to which the memory elements are attached after they have been formed. In non-limiting embodiments, the substrate may include a semiconductor such as silicon.

[0044] Memory elements may be arranged in an ordered array, such as multiple rows and / or columns, at the level of a single memory device. However, memory elements may be arranged in an irregular or non-orthogonal configuration. Each memory element may have two or more electrodes or contact lines, such as bit lines and word lines.

[0045] A three-dimensional memory array is arranged such that memory elements occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional structure (i.e., in the x, y, and z directions, where the z direction is substantially perpendicular to the main plane of the substrate, and the x and y directions are substantially parallel to the main plane of the substrate).

[0046] In a non-limiting embodiment, a three-dimensional memory structure may be arranged vertically as a stack of multiple two-dimensional memory devices. In another non-limiting embodiment, a three-dimensional memory array may be arranged as multiple vertical columns (e.g., columns substantially perpendicular to the main plane of the substrate, i.e., extending in the y-direction), with each column having multiple memory elements. The columns may be arranged in a two-dimensional configuration, e.g., in the xy-plane, which results in a three-dimensional arrangement of memory elements having elements on multiple vertically stacked memory planes. Other configurations of three-dimensional memory elements can also constitute a three-dimensional memory array.

[0047] As a non-limiting embodiment, in a three-dimensional array of NAND strings, memory elements may be coupled together to form a NAND string within a single horizontal (e.g., xy) memory device level. Alternatively, memory elements may be coupled together to form a vertical NAND string traversing multiple horizontal memory device levels. Other three-dimensional configurations can be envisioned in which some NAND strings contain memory elements within a single memory level, and other strings contain memory elements spanning multiple memory levels. Three-dimensional memory arrays can further be designed in NOR and ReRAM configurations.

[0048] Typically, in a monolithic three-dimensional memory array, one or more memory device levels are formed on a single substrate. If necessary, the monolithic three-dimensional memory array may further have one or more memory layers, at least partially, within a single substrate. In non-limiting embodiments, the substrate may include a semiconductor such as silicon. In a monolithic three-dimensional array, the layers constituting each memory device level of the array are typically formed on layers of memory device levels beneath the array. However, adjacent memory device level layers in a monolithic three-dimensional memory array may be shared, or there may be intervening layers between the memory device levels.

[0049] In this case as well, the two-dimensional arrays may be formed separately and then packaged together to form a non-monolithic memory device having multiple memory layers. For example, a non-monolithic stacked memory can be constructed by forming memory levels on separate substrates and then stacking the memory levels on top of each other. The substrates may be thinned or removed from the memory device levels before stacking, but since the memory device levels are initially formed on separate substrates, the resulting memory array is not a monolithic three-dimensional memory array. Furthermore, multiple two-dimensional or three-dimensional memory arrays (monolithic or non-monolithic) may be formed on separate chips and then packaged together to form a stacked chip memory device.

[0050] Figure 2 illustrates memory cell blocks 200, 210 in an example two-dimensional configuration of the memory array 126 of Figure 1. The memory array 126 can include many such blocks 200, 210. Each example block 200, 210 includes a number of NAND strings and their respective bit lines, e.g., BL0, BL1, ..., shared between the blocks. Each NAND string is connected at one end to a drain-side selection gate (SGD), and the control gate of the drain-side selection gate is connected via a common SGD line. The other end of the NAND strings is connected to a source-side selection gate (SGS), which is connected to a common source line 220. Between the SGS and the SGD are 112 word lines, e.g., WL0 to WL111. In some embodiments, a memory block may include more or fewer word lines than 112. For example, in some embodiments, a memory block may include 164 word lines. In some cases, dummy word lines that do not store user data may be used in the memory array adjacent to the selection gate transistor, or between certain data word lines. Such dummy word lines can shield the edge data word lines from certain edge effects.

[0051] One type of non-volatile memory that can be provided in a memory array is a floating-gate memory, as seen in Figures 3A and 3B. However, other types of non-volatile memory can also be used. As will be discussed in more detail below, in another embodiment shown in Figures 4A and 4B, a charge-trap memory cell non-volatilely stores charge using a non-conducting dielectric material instead of a conduction-floating gate. A three-layer dielectric, formed from silicon oxide, silicon nitride, and silicon oxide ("ONO"), is sandwiched between a conduction-controlled gate and the surface of a semiconducting substrate above the memory cell channel. The cell is programmed by injecting electrons into the nitride from the cell channel, in which case the electrons are trapped and stored in a restricted region. This stored charge then changes the threshold voltage of a portion of the cell's channel in a detectable manner. The cell is erased by injecting hot holes into the nitride. A similar cell can be provided in a split-gate configuration, where a doped polycrystalline silicon gate extends across a portion of the memory cell channel to form a separate select transistor.

[0052] Another approach uses NROM cells. For example, two bits are stored in each NROM cell, with an ONO dielectric layer extending across the channel between the source and drain diffusion regions. The charge of one data bit is localized in the dielectric layer adjacent to the drain, and the charge of the other data bit is localized in the dielectric layer adjacent to the source. Multi-state data storage is obtained by separately reading the binary states of spatially separated charge storage regions within the dielectric. Other types of non-volatile memory are also known.

[0053] Figure 3A illustrates cross-sectional views of exemplary floating-gate memory cells 300, 310, and 320 within a NAND string. In this figure, the bit line, or NAND string direction, is on the page, and the word line direction proceeds from left to right. In one embodiment, the word line 324 extends at both ends of the NAND string, including the respective channel regions 306, 316, and 326. Memory cell 300 includes a control gate 302, a floating gate 304, a tunnel oxide layer 305, and a channel region 306. Memory cell 310 includes a control gate 312, a floating gate 314, a tunnel oxide layer 315, and a channel region 316. Memory cell 320 includes a control gate 322, a floating gate 321, a tunnel oxide layer 325, and a channel region 326. Each memory cell 300, 310, and 320 is located within a different NAND string. An interpolydielectric (IPD) layer 328 is also illustrated. Control gates 302, 312, and 322 are part of the word line. A cross-sectional view along the contact line connector 329 is provided in Figure 3B.

[0054] The control gates 302, 312, and 322 enclose the floating gates 304, 314, and 321, increasing the surface contact area between the control gates 302, 312, and 322 and the floating gates 304, 314, and 321. This increases the IPD capacity and the coupling ratio, making programming and erasing easier. However, as NAND memory devices shrink, the spacing between adjacent cells 300, 310, and 320 narrows, leaving almost no space for the control gates 302, 312, and 322 and the IPD layer 328 between two adjacent floating gates 302, 312, and 322.

[0055] As an alternative, flat or planar memory cells 400, 410, and 420 have been developed, where the control gates 402, 412, and 422 are flat or planar, as seen in Figures 4A and 4B. That is, this does not enclose a floating gate, and the only contact with the charge storage layer 428 is from above. In this case, there is no advantage to having a high floating gate. Instead, the floating gate can be made very thin. Furthermore, the floating gate can be used to store charge, or a thin charge trap layer can be used to trap charge. This technique avoids the problem of ballistic electron transport, where electrons tunnel through the tunnel oxide film during programming and then pass through the floating gate.

[0056] Figure 4A shows a cross-sectional view of exemplary charge trap memory cells 400, 410, and 420 within a NAND string. This figure shows memory cells 400, 410, and 420 viewed in the word line direction, including flat control gates and charge trap regions, as an embodiment of the memory cells 400, 410, and 420 shown in two dimensions in the memory cell array 126 of Figure 1. Charge trap memory can be used in NOR and NAND flash memory devices. This technique uses an insulator such as a SiN film to store electrons, in contrast to floating-gate MOSFET technology, which uses a conductor such as doped polycrystalline silicon to store electrons. In one embodiment, a word line 424 extends at both ends of the NAND string, including the respective channel regions 406, 416, and 426. A portion of the word line provides control gates 402, 412, and 422. Below the word line are the IPD layer 428, charge trap layers 404, 414, 421, polycrystalline silicon layers 405, 415, 425, and tunnel layers 409, 407, 408. Each charge trap layer 404, 414, 421 extends continuously in its respective NAND string. The planar shape of the control gate can be made thinner than that of the floating gate. In addition, the memory cells can be placed closer to each other.

[0057] Figure 4B illustrates a cross-sectional view of the structure of Figure 4A along a contact wire connector 429. The NAND string 430 includes an SGS transistor 431, exemplary memory cells 400, 433, ..., 435, and an SGD transistor 436. The control gate layer 402 and the floating gate layer can communicate through the passages in the IPD layer 428 of the SGS and SGD transistors 431, 436. For example, the control gate 402 and the floating gate layer may be polycrystalline silicon, and the tunnel oxide layer may be silicon oxide. The IPD layer 428 may be a laminate of nitride (N) and oxide (O), such as a non-non-on configuration.

[0058] A NAND string can be formed on a substrate including a p-type substrate region 455, an n-type well 456, and a p-type well 457. The p-type wells have n-type source / drain diffusion regions sd1, sd2, sd3, sd4, sd5, sd6, and sd7 formed within them. A channel voltage Vch can be applied directly to the channel region of the substrate.

[0059] Figure 5 illustrates an exemplary block diagram of sense block SB1 of Figure 1. In one approach, the sense block comprises multiple sense circuits. Each sense circuit is associated with a data latch. For example, exemplary sense circuits 550a, 551a, 552a, and 553a are associated with data latches 550b, 551b, 552b, and 553b, respectively. In one approach, different subsets of bit lines may be detected using different sense blocks. This allows for the division of the processing load associated with the sense circuits, which can be processed by the respective processors within each sense block. For example, a sense circuit controller 560 in SB1 can communicate with a set of sense circuits and latches. The sense circuit controller 560 may include a precharge circuit 561 that supplies voltage to each sense circuit to set the precharge voltage. In one assumed approach, the voltage is supplied independently to each sense circuit, for example, via a data bus and a local bus. In another assumed approach, a common voltage is supplied to each sense circuit simultaneously. The sense circuit controller 560 may further include a precharge circuit 561, a memory 562, and a processor 563. The memory 562 may store code executable by the processor to perform the functions described herein. These functions may include reading latches 550b, 551b, 552b, and 553b associated with the sense circuits 550a, 551a, 552a, and 553a, setting bit values ​​in the latches, and further providing voltages to set the precharge levels in the sense nodes of the sense circuits 550a, 551a, 552a, and 553a. Further exemplary details relating to the sense circuit controller 560 and the sense circuits 550a, 551a, 552a, and 553a are provided below.

[0060] In some embodiments, a memory cell may include a flag register containing a set of latches that store flag bits. In some embodiments, the number of flag registers may correspond to the number of data states. In some embodiments, one or more flag registers may be used to control the type of verification technique used when verifying a memory cell. In some embodiments, the output of the flag bits may modify the associated logic of the device, such as an address decoding circuit, so that a designated block of the cell is selected. Bulk operations (such as an erase operation) may be performed using the flags set in the flag registers, or using a combination of the flag register and the address register, as in the case of implicit addressing, or alternatively by direct addressing using only the address register.

[0061] Figure 6A is a perspective view of a set of blocks 600 in a three-dimensional configuration illustrating an example of the memory array 126 of Figure 1. On the substrate are exemplary blocks BLK0, BLK1, BLK2, and BLK3 of memory cells (storage elements), and a peripheral region 604 having circuits used by blocks BLK0, BLK1, BLK2, and BLK3. For example, the circuits may include voltage drivers 605 that can be connected to the control gate layers of blocks BLK0, BLK1, BLK2, and BLK3. In one method, the control gate layers at a common height within blocks BLK0, BLK1, BLK2, and BLK3 are driven in common. The substrate 601 can further support the circuits beneath blocks BLK0, BLK1, BLK2, and BLK3, along with one or more lower metal layers patterned as conduction paths for carrying the signals of the circuits. Blocks BLK0, BLK1, BLK2, and BLK3 are formed within an intermediate region 602 of the memory device. In the upper region 603 of the memory device, one or more upper metal layers are patterned as conduction paths for carrying circuit signals. Each block BLK0, BLK1, BLK2, BLK3 contains a stack region of memory cells, and the alternating levels of the stack represent word lines. In one assumed method, each block BLK0, BLK1, BLK2, BLK3 has opposing hierarchical sides from which vertical contacts extend to the upper metal layer, forming connections to the conduction paths. Although four blocks BLK0, BLK1, BLK2, BLK3 are illustrated as an example, two or more blocks extending in the x and / or y directions can be used.

[0062] In one assumed method, the x-length of the plane represents the direction in which the signal path to the word line extends within one or more upper metal layers (word line, or SGD line direction), and the y-width of the plane represents the direction in which the signal path to the bit line extends within one or more upper metal layers (bit line direction). The z-direction represents the height of the memory device.

[0063] Figure 6B illustrates an illustrative cross-sectional view of one part of blocks BLK0, BLK1, BLK2, and BLK3 of Figure 6A. The block includes a laminate 610 in which conductive layers and dielectric layers are arranged alternately. In this embodiment, the conductive layers include data word line layers (word lines) WL0 to WL111, as well as two SGD layers, two SGS layers, and four dummy word line layers DWLD0, DWLD1, DWLS0, and DWLS1. The dielectric layers are labeled DL0 to DL116. Furthermore, a region of the laminate 610 including NAND strings NS1 and NS2 is illustrated. Each NAND string contains memory holes 618, 619 which are filled with material that forms memory cells adjacent to the word lines. A region 622 of the laminate 610 is illustrated in more detail in Figure 6D and will be discussed in further detail below. The dielectric layer can have a variable thickness, allowing some conductive layers to move closer to or further away from adjacent conductive layers. The thickness of the dielectric layer affects the "on-pitch," a factor in memory density. Specifically, reducing the on-pitch allows more memory cells to be used in a given area, but this may compromise reliability.

[0064] The laminate 610 includes a substrate 611, an insulating film 612 on the substrate 611, and a portion of the source line SL. NS1 has a source end 613 at the bottom 614 of the laminate and a drain end 615 at the top 616 of the laminate 610. Contact line connectors (e.g., slits such as metal-filled slits) 617, 620 may be periodically provided throughout the laminate 610 as interconnections that penetrate the laminate 610, such as connecting the source line to specific contact lines above the laminate 610. The contact line connectors 617, 620 are used during the formation of the word line and may then be filled with metal. A portion of the bit line BL0 is also shown. Conducted via 621 connects the drain end 615 to BL0.

[0065] Figure 6C shows a plot of memory hole diameters within the stack in Figure 6B. The vertical axis is aligned with the stack in Figure 6B and illustrates the width (wMH), e.g., diameter, of memory holes 618 and 619. The word line layers WL0 to WL111 in Figure 6A are repeated as an example, at their respective heights z0 to z111 within the stack. In such memory devices, the memory holes etched through the stack have a very high aspect ratio. For example, a depth-to-diameter ratio of about 25 to 30 is common. The memory holes may have a circular cross-section. Due to the etching process, the memory hole width may vary along the length of the hole. Typically, the diameter gradually decreases from the top to the bottom of the memory hole; that is, the memory hole is tapered and narrows at the bottom of the stack. In some cases, it is slightly narrower at the top of the hole near the selection gate, the diameter is slightly wider, and then gradually decreases from the top to the bottom of the memory hole.

[0066] Figure 6D shows an enlarged view of region 622 of the stack 610 in Figure 6B. Memory cells are formed at different heights of the stack at the intersections of the word line layers and memory holes. In this embodiment, SGD transistors 680, 681 are located above the dummy memory cells 682, 683 and the data memory cell MC. For example, atomic layer deposition can be used to deposit several layers along the sidewalls (SW) of the memory holes 630 and / or within each word line layer. For example, each row (e.g., pillars formed by the material within the memory holes 630) may include a charge trap layer such as SiN or other nitride, or a film 663, tunnel layer 664, polycrystalline silicon, or channel 665, and dielectric core 666. The word line layers may include a blocking oxide / blocking high dielectric material 660, a metal barrier 661, and a conductive metal such as tungsten as a control gate. For example, control gates 690, 691, 692, 693, 694 are provided. In this embodiment, all layers except the metal are provided in the memory hole 630. In other methods, some of the layers may be within the control gate layer. Additional pillars are similarly formed in different memory holes. The pillars can form columnar active regions (AAs) of the NAND string.

[0067] When a memory cell is programmed, electrons accumulate in a portion of the charge trap layer associated with the memory cell. These electrons are drawn from the channel through the tunnel layer into the charge trap layer. The threshold voltage Vt of the memory cell increases proportionally to the amount of accumulated charge. During a sensing operation, the threshold voltage Vt is detected or measured. During an erase operation, the electrons return to the channel.

[0068] Each of the memory holes 630 may be filled with a plurality of annular layers, including a blocking oxide layer, a charge trap layer 663, a tunnel layer 664, and a channel layer. The core region of each memory hole 630 is filled with body material, and the plurality of layers are located between the core region and the word line layer in each of the memory holes 630. In some cases, the charge trap layer 663 and the tunnel layer 664 are annular in shape. In other cases, these layers are semicircular, as will be further detailed below.

[0069] Since the channel length is not formed on the substrate, the NAND string can be considered to have a floating body channel. Furthermore, the NAND string is provided by multiple word line layers that overlap each other in a laminate, separated from each other by dielectric layers.

[0070] Figure 7A illustrates a top view of the word line layer WL0 in an example of the laminate 610 shown in Figure 6B. As described above, a three-dimensional memory device may include a laminate in which conductive layers and dielectric layers are arranged alternately. The conductive layers provide SG transistors and control gates for memory cells. The layer used for the SG transistors is the SG layer, and the layer used for memory cells is the word line layer. Furthermore, memory holes are formed within the laminate and filled with charge trapping material and channel material. This forms a vertical NAND string. Source lines are connected to the NAND string below the laminate, and bit lines are connected to the NAND string above the laminate.

[0071] A block BLK in a three-dimensional memory device can be divided into subblocks, each subblock containing a NAND string group with common SGD control lines. For example, refer to the SGD lines / control gates SGD0, SGD1, SGD2, and SGD3 of subblocks SBa, SBb, SBc, and SBd, respectively. Furthermore, the word line layers within a block can be divided into regions. Each region is located within its own subblock and can extend between periodically formed contact line connectors (e.g., slits) within the laminate to process the word line layers during the manufacturing process of the memory device. This process may include replacing the sacrificial material of the word line layers with metal. Generally, the distance between contact line connectors should be relatively short, taking into account the limits of the distance the etching solution can move laterally to remove the sacrificial material and the distance the metal can move to fill the gaps created by the removal of the sacrificial material. For example, the distance between contact line connectors can be such that several rows of memory holes are provided between adjacent contact line connectors. Furthermore, the layout of the memory holes and contact line connectors must take into account the limitations on the number of bit lines that can extend across the entire region, while each bit line connects to a different memory cell. After processing the word line layer, the contact line connectors are filed with metal as needed to obtain interconnects through the stack.

[0072] In this embodiment, there are four rows of memory holes between adjacent contact line connectors. Here, a row refers to a group of memory holes aligned in the X direction. Furthermore, to increase the density of memory holes, the rows of memory holes are arranged in a staggered pattern. The word line layer, or word line, is divided into regions WL0a, WL0b, WL0c, and WL0d, each region connected by contact lines 713. In one method, the final region of the word line layer in one block can be connected to the first region of the word line layer in the next block. Then, the contact lines 713 are connected to a voltage driver for the word line layer. Region WL0a has exemplary memory holes 710, 711 along contact lines 712. Region WL0b has exemplary memory holes 714, 715. Region WL0c has exemplary memory holes 716, 717. Region WL0d has exemplary memory holes 718, 719. The memory holes are also shown in Figure 7B. Each memory hole can be part of its respective NAND string. For example, memory holes 710, 714, 716, and 718 may be part of the NAND strings NS0_SBa, NS1_SBb, NS2_SBc, NS3_SBd, and NS4_sBE, respectively.

[0073] Each circle represents a cross-section of a memory hole in a word line layer or SG layer. The example circles shown with dashed lines represent memory cells provided by the material within the memory hole and the adjacent word line layers. For example, memory cells 720 and 721 are in WL0a, memory cells 724 and 725 are in WL0b, memory cells 726 and 727 are in WL0c, and memory cells 728 and 729 are in WL0d. These memory cells are at a common height in the stack.

[0074] Contact wire connectors (e.g., slits such as metal-filled slits) 701, 702, 703, and 704 may be positioned between and adjacent to the edges of regions WL0a to WL0d. The contact wire connectors 701, 702, 703, and 704 provide conduction paths from the bottom of the stack to the top of the stack. For example, source wires at the bottom of the stack may be connected to conduction wires at the top of the stack, which in turn are connected to voltage drivers in the peripheral regions of the memory device.

[0075] Figure 7B illustrates a top view of the top dielectric layer DL116 of an example of the stack shown in Figure 6B. The dielectric layer is divided into regions DL116a, DL116b, DL116c, and DL116d. Each region can be connected to its respective voltage driver. This allows a set of memory cells in one region of the word line layer to be programmed simultaneously, with each memory cell located in its respective NAND string connected to its respective bit line. During programming, detection, or erase operations, a voltage can be set on each bit line.

[0076] Region DL116a has exemplary memory holes 710, 711 along contact line 712, which coincides with bit line BL0. Numerous bit lines extend above the memory holes and connect to them, as indicated by the "X" symbol. BL0 connects to a set of memory holes, including memory holes 711, 715, 717, and 719. Another exemplary bit line BL1 connects to a set of memory holes, including memory holes 710, 714, 716, and 718. Furthermore, contact line connectors (slits such as metal-filled slits, for example) 701, 702, 703, and 704 from Figure 7A are also illustrated, penetrating the lamination vertically. The bit lines may be numbered in the order BL0 to BL23 across the entire DL116 layer in the x-direction.

[0077] Different subsets of bit lines connect to memory cells in different rows. For example, BL0, BL4, BL8, BL12, BL16, and BL20 connect to memory cells in the first row of the cell at the right edge of each region. BL2, BL6, BL10, BL14, BL18, and BL22 connect to memory cells in adjacent rows of the cell, adjacent to the first row at the right edge. BL3, BL7, BL11, BL15, BL19, and BL23 connect to memory cells in the first row of the cell at the left edge of each region. BL1, BL5, BL9, BL13, BL17, and BL21 connect to memory cells in adjacent rows of the memory cells, adjacent to the first row at the left edge.

[0078] Referring now to Figure 8, in one exemplary embodiment, the memory holes of the memory block each include an upper memory hole 800 (upper layer) and a lower memory hole 802 (lower layer). The upper memory hole 800 and the lower memory hole 802 are each frustoconical in shape, having a larger diameter at their upper end and a smaller diameter at their lower end. Thus, for each of the upper and lower memory holes, there is an upper word line where the memory hole has a relatively larger diameter and a lower word line where the memory hole has a relatively smaller diameter.

[0079] According to an exemplary embodiment of the present disclosure, word lines are divided into pairs, groups, or sets of zones based on the diameter of the memory holes, and the word lines in each zone or group can be discontinuous. More specifically, the bottom word lines of both the upper and lower memory holes are hereafter referred to as "bottom-level word lines 804". In the exemplary embodiment, for each of the upper memory hole 800 and the lower memory hole 802, the 10 word lines having the smallest memory holes are the bottom-level word lines 804, e.g., WL0-WL9 and WL81-90. In some other embodiments, the bottom-level word lines 804 may include more than 10 or fewer word lines. In some further embodiments, the number of bottom-level word lines in the upper memory hole may differ from the number in the lower memory hole. Also in further embodiments, the number of layers in a memory block may be more than or less than two (e.g., three or more layers including one or more intermediate layers).

[0080] In the exemplary embodiment, both the bottommost word line 804 itself and the dielectric layer DL between the bottommost word lines 804 are thicker than the other word lines 806 and the dielectric layer DL between the other word lines 806 (hereinafter referred to as "other word lines"). Therefore, the on-pitch between adjacent bottommost word lines is greater than that of other parts of the memory block.

[0081] Memory cells in a memory block can be programmed to store one or more bits of data in multiple data states, each data state associated with a range of threshold voltages Vt and each bit or set of bits. For example, Figure 9 shows the threshold voltage Vt distribution of a group of memory cells programmed according to a 3-bit per memory cell (TLC) storage scheme. In the TLC storage scheme, there are a total of eight data states: an erase state (Er) and seven programmed data states (S1, S2, S3, S4, S5, S6, and S7). Each programmed data state (S1-S7) is associated with a respective verify voltage used during the verify portion of the programming operation. Other storage schemes are also available, such as 1 bit per memory cell with two data states (SLC), 2 bits per cell with four data states (MLC), 4 bits per cell with 16 data states (QLC), and 5 bits per cell with 32 data states (PLC). However, the following description will primarily focus on the TLC storage scheme.

[0082] Programming of memory cells is performed word line by word, from one side of the memory block to the other. Typically, programming memory cells in selected word lines to hold multiple bits per memory cell (e.g., MLC, TLC, or QLC) begins with the memory cell in the erase data state Er and involves multiple program loops, each program loop further including both a programming pulse and a verify operation. During the programming pulse, the threshold voltage Vt of the memory cell being programmed rises, while memory cells already in the final data state are prohibited, i.e., their threshold voltage Vt does not rise. During the verify operation, the threshold voltage Vt of the memory cell being programmed is compared to the verify voltage Vv associated with their final data state in the sensing operation.

[0083] Referring to Figure 10, the sensing operation (verify or read) begins when the sense node SEN on the drain side of the memory block is charged to a predetermined charging voltage. Simultaneously, all memory cells in the selected NAND string that store the selected memory cell of the selected word line WLn, except for the selected memory cell, are turned on by the path voltage VREAD. A reference voltage VCG (for example, one of Vv1 to Vv7 as depicted in Figure 9, depending on which data state is being verified) is applied to the control gate of the selected word line WLn.

[0084] Subsequently, the sense node SEN is discharged through the NAND string. Since all memory cells except the selected memory cell are turned on by the elevated path voltage VREAD, the discharge current Icell flowing through the NAND string is largely dependent on whether the reference voltage VCG turns on the selected memory cell, that is, whether the threshold voltage Vt of the memory cell is below or above the reference voltage VCG.

[0085] During the discharge time T_sense, the voltage on the SEN node is sensed by the sensing circuit and compared to V_sense, which is the threshold voltage Vt of the ΔVPGM sensing transistor. If the threshold voltage Vt of the selected memory cell is higher than the reference voltage VCG, the selected memory cell is not turned on by the reference voltage VCG and conducts only a very small / negligible current, resulting in a small discharge of the SEN node voltage. Therefore, the SEN node voltage remains higher than V_sense. On the other hand, if the threshold voltage Vt of the selected memory cell is lower than the reference voltage VCG, the reference voltage VCG turns on the selected memory cell, and a larger discharge current lowers the SEN node voltage below V_sense. By performing this process for each memory cell on the selected word line WLn, the data stored in the memory cells on the selected word line WLn is read out.

[0086] Returning to Figure 9, generally, a larger voltage gap, or margin, between two adjacent data states improves reliability. More specifically, a larger margin makes it easier for the memory device to distinguish between data states. However, two issues that can affect the margin between data states and compromise reliability are true temperature data retention (TTDR) and read disturb (RD).

[0087] TTDR occurs when electrons in a memory cell leak out of the charge trap layer, thereby lowering the threshold voltage Vt of the affected memory cell. Memory cells in the highest data state S7, which is associated with the highest threshold voltage range, are particularly vulnerable to TTDR. Figure 11 shows the threshold voltage Vt distribution of multiple memory cells where significant TTDR occurred. As shown, the lower tail of the S7 data state is shifted downward, reducing the margin between the S6 and S7 data states. Furthermore, some memory cells in the S7 data state have threshold voltages Vt below the reference voltage Vr7 associated with the S7 data state. These memory cells are misread as being in the S6 data state, which leads to bad bits.

[0088] On the other hand, a bad bit (RD) occurs when a memory cell is unintentionally programmed by an elevated path voltage VREAD applied to an unselected word line during a detection operation (read or verify). Memory cells in the erased data state Er are particularly vulnerable to RD because they have the lowest threshold voltage Vt. Figure 12 shows the threshold voltage Vt distribution for several memory cells where a significant RD occurred. As illustrated, the upper tail of the erased data state Er is shifted upward, and the margin between Er and the S1 data state is reduced. Furthermore, some memory cells in the erased data state Er now have a threshold voltage Vt that exceeds the reference voltage Vr1 associated with the S1 data state. These memory cells can be misread as the S1 data state, leading to bad bits.

[0089] One technique to mitigate the effects of TTDR is to increase the margin between the S6 data state and the S7 data state, and one technique to mitigate the effects of RD is to increase the margin between the erased data state Er and the S1 data state. However, the margins available for these adjustments without significantly impairing programming performance are limited. Therefore, these techniques lead to a trade-off between mitigating TTDR and RD.

[0090] One aspect of this disclosure relates to techniques for operating a memory device that mitigates both TTDR and RD while maintaining high programming performance. As will be discussed in more detail below, these techniques specifically optimize the verify voltage Vv applied to word lines during programming across the entire memory block, based on whether the memory cells in those word lines are vulnerable to TTDR or RD.

[0091] Moving to Figure 13, during programming of the memory cells of the "other word lines" (excluding the bottom layer lines), a first set of verify voltages Vv1 to Vv7 is adopted. Conversely, during programming of the memory cells of the bottom layer word lines, a second, different set of verify voltages Vv1_Bottom-Vv7_Bottom is adopted. The verify voltages Vv7 and Vv7_Bottom related to the S7 data state are the same in both sets. However, for the other data states S1 to S6, the verify voltages of the second set are greater than those of the first set. That is, Vv1_Bottom>Vv1, Vv2_Bottom>Vv2, Vv3_Bottom>Vv3, Vv4_Bottom>Vv4, Vv5_Bottom>Vv5, and Vv6_Bottom>Vv6. More specifically, for data states S1 to S6, the verify voltage of the second set is greater than the verify voltage of the first set by the data state-specific bottom layer offset, i.e., Vvn_Bottom = Vvn + Sn_Bottom_Offset. For example, Vv1_Bottom = Vv1 + S1_Bottom_Offset, Vv2_Bottom = Vv2 + S2_Bottom_Offset, and so on.

[0092] Figure 14 illustrates the threshold voltage Vt distribution for multiple memory cells programmed using a first set of verify voltages (solid line) and multiple memory cells programmed using a second set of verify voltages (dashed line). The second set of verify voltages, Vv1_Bottom-Vv7_Bottom, increases the margin between the erase data state Er and the S1 data state of the bottom-layer word line memory cells compared to other word lines. That is, margin M1_Bottom is larger than margin M1. It has been found that the bottom-layer word line memory cells are more vulnerable to RD and less vulnerable to TTDR compared to other word lines. Therefore, the larger margin M1_Bottom provides the bottom-layer word line memory cells with enhanced protection from bad bits caused by RD.

[0093] This indicates that memory cells in other word lines are more vulnerable to TTDR and less vulnerable to RD compared to the bottom-level word line. Since the first and second sets of verify voltages have the same verify voltage for the S7 data state (Vv7=Vv7_Bottom), the margin between the S6 and S7 data states in other word lines (M7) is larger than the same margin in the bottom-level word line (M7_Bottom). The increased margin between the S6 and S7 data states enhances the protection of memory cells in other word lines from bad bits due to TTDR.

[0094] Therefore, the technology of this aspect of the disclosure optimizes protection from bad bits in memory cells of both the lowest-layer word line and other word lines. Thus, reliability is improved and performance loss is absent or minimized. Furthermore, if the optimal setting may differ in the lowest-layer word line, we may also consider using a different S7 verify (Vv7).

[0095] According to some techniques, the reference voltage Vrn used during read operations is greater than the reference voltage Vvn used during verify operations by the amount of the data state-specific read offset, i.e., Vrn = Vvn + Sn_Read_Offset.

[0096] According to another aspect of this disclosure, the reference voltage Vrn used during reading of a memory cell in the bottom layer word line is offset by both a read offset from the verify voltage and a state-specific bottom layer offset. Thus, during one read of data states S1-S7 in one of the bottom layer word lines, the reference voltage VCG applied to the selected word line is equal to Vrn = Vvn + Sn_Bottom_Offset + Sn_Read_Offset. For example, in the case of reading data state S1, the reference voltage Vr1 is set to Vv1 + S1_Bottom_Offset + S1_Read_Offset. By offsetting the read voltage Vr from the verify voltage Vv by both the data state-specific bottom layer offset and the data state-specific read offset, bad bits during the read operation can be further reduced. In some embodiments, the read offset S7_Read_Offset for data state S7 can be any suitable value, including 0V.

[0097] Another aspect of the present disclosure relates to a method for programming memory cells in a selected word line of a memory device. Figure 15 is a flowchart 1500 illustrating the steps for performing this operation according to an exemplary embodiment of the present disclosure. These steps may be performed by a controller, a processor or processing device that executes instructions stored in memory, or any other circuitry, and / or other circuitry described herein that is specifically configured / programmed to perform the following steps.

[0098] In step 1502, programming begins for the memory cell of the selected word line WLn. In step 1504, the memory device determines whether the selected word line WLn is the lowest layer word line or one of the other word lines. In determination step 1506, it is determined whether the selected word line WLn is the lowest layer word line. If the answer in determination step 1506 is "no", in step 1508, the set of verify voltages to be used in the next programming operation is the first set of verify voltages Vv1 to Vv7. If the answer in determination step 1506 is "yes", in step 1510, the set of verify voltages to be used in the next programming operation is the second set of verify voltages Vv1_Bottom to Vv7_Bottom. Following either step 1508 or 1510, in step 1512, the memory cell of the selected word line WLn is programmed in multiple program loops using either a first set of verify voltages Vv1-Vv7 or a second set of verify voltages Vv1_Bottom-Vv7_Bottom. In either case, the same verify voltage is used during the verification of the S7 data state, i.e., Vv7 = Vv7_Bottom.

[0099] Another aspect of this disclosure relates to a method for reading memory cells of a selected word line in a memory device. Figure 16 is a flowchart 1600 illustrating the steps for performing this operation according to an exemplary embodiment of this disclosure. These steps may be performed by a controller, a processor or processing device that executes instructions stored in memory, or any other circuitry, and / or other circuitry described herein that is specifically configured / programmed to perform the following steps.

[0100] In step 1602, a read command is received for the selected word line WLn. In step 1604, the memory device determines what type of word line the selected word line WLn is, i.e., whether it is the lowest layer word line or any other word line. In determination step 1606, it is determined whether the selected word line WLn is the lowest layer word line. If the answer in determination step 1606 is "no", then in step 1608, for each of the data states S1 to S7, the read voltage Vrn is set to the value obtained by adding the read offset Sn_Read_Offset to the verify voltage Vvn, i.e., Vrn = Vvn + Sn_Read_Offset. If the answer in decision step 1606 is "yes", then in step 1610, for data states S1 to S7, the read voltage Vrn is set to the verify voltage Vvn plus the read offset Sn_Read_Offset and the bottom offset Sn_Bottom_Offset, i.e., Vrn = Vvn + Sn_Read_Offset + Sn_Bottom_Offset. In some embodiments, S7_Read_Offset may be set to 0 volts (0V). In step 1612, the read operation is performed on the selected word line WLn using the read voltages Vr1 to Vr7.

[0101] This specification uses various terms to refer to specific system components. Different companies may use different names for the same or similar components, but this description does not intend to distinguish between components that have different names but the same function. To the extent that the various functional units described in the following disclosure are referred to as “modules,” such features are not intended to unduly limit the range of potential implementation mechanisms. For example, a “module” may be implemented as a hardware circuit, including a customized very large-scale integrated circuit (VLSI) circuit, or a gate array, or a ready-made semiconductor including logic chips, transistors, or other individual components. In further embodiments, a module may be implemented as a programmable hardware device, such as a field-programmable gate array (FPGA), programmable array logic, or programmable logic device. Furthermore, a module may also be implemented, at least in part, by software executed by various types of processors. For example, a module may include segments of executable code that constitute a block of one or more physical or logical computer instructions that translate into an object, process, or function. Furthermore, the executable parts of such modules do not need to be physically located together; rather, they may be stored in different locations and, when executed together, may include different instructions that include the specified module and achieve the explicit purpose of that module. Executable code may include a single instruction or a set of instructions, or it may be distributed across various code segments, different programs, or several memory devices. In software, or implementations of partial software modules, parts of the software may be stored on one or more computer-readable and / or executable storage media, including, but not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor-based systems, apparatus, or devices, or any appropriate combination thereof.Generally speaking, for the purposes of this disclosure, computer-readable storage media and / or executable storage media may consist of any tangible and / or non-temporary media capable of storing and / or storing programs for use by or in connection with instruction execution systems, apparatus, processors, or devices.

[0102] Similarly, for the purposes of this disclosure, the term “component” may consist of any tangible, physical, and non-transient devices. For example, a component may be a hardware logic circuit consisting of a customized VLSI circuit, gate array, or other integrated circuit, or a commercially available semiconductor or other suitable mechanical and / or electronic device including a logic chip, transistor, or other individual component. In addition, a component may be implemented as a programmable hardware device, such as a field-programmable gate array (FPGA), programmable array logic, or programmable logic device. Furthermore, a component may consist of one or more silicon-based integrated circuit devices, such as chips, dies, die planes, or packages, or other individual electrical devices, in a configuration that electrically communicates with one or more other components via an electrical conductor, such as a printed circuit board (PCB). Thus, a module as defined above may, in a particular embodiment, be embodied by a component or implemented as a component, and in some cases, the terms module and component may be used interchangeably.

[0103] Where used herein, the term “circuit” includes one or more electrical and / or electronic components that constitute one or more conduction paths that allow electric current to flow. A circuit can be in the form of a closed-loop configuration or an open-loop configuration. In a closed-loop configuration, circuit components may provide a feedback path for current. In contrast, in an open-loop configuration, internal circuit components may not include a feedback path for current, but may still be considered to form a circuit. For example, an integrated circuit is called a circuit whether or not it is grounded (as a feedback path for current). In certain exemplary embodiments, a circuit may include a set of integrated circuits, a single integrated circuit, or a part of an integrated circuit. For example, a circuit may include customized VLSI circuits, gate arrays, logic circuits, and / or other forms of integrated circuits, as well as off-the-shelf semiconductors such as logic chips, transistors, or other discrete devices. In further embodiments, the circuit may include one or more silicon-based integrated circuit devices, such as chips, dies, die planes, or packages, or other discrete electrical devices, in a configuration that electrically communicates with one or more other components, for example, via electrical conductors on a printed circuit board (PCB). The circuit may also be implemented as a composite circuit with respect to programmable hardware devices such as field-programmable gate arrays (FPGAs), programmable array logic, and / or programmable logic devices. In other exemplary embodiments, the circuit may consist of a network of non-integrated electrical and / or electronic components (with or without integrated circuit devices). Thus, in certain embodiments, the modules defined above may be embodied by a circuit or implemented as a circuit.

[0104] It will be understood that the exemplary embodiments disclosed herein may consist of one or more microprocessors, certain non-processor circuits, and certain stored computer program instructions that control one or more microprocessors to implement some, most, or all of the functions disclosed herein. Alternatively, some or all of the functions may be implemented by a state machine without stored program instructions, or in one or more application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs) where each function, or a combination of some of the functions, is implemented as custom logic. Combinations of these methods may also be used. Furthermore, the following references to “controller” shall be defined as comprising individual circuit components, application-specific integrated circuits (ASICs), microcontrollers with control software, digital signal processors (DSPs), field-programmable gate arrays (FPGAs), and / or processors with control software, or a combination thereof.

[0105] In addition, the terms “couple,” “coupled,” and “couples” as used herein are intended to mean either a direct or indirect connection. Therefore, when a first device is coupled to or is coupled to a second device, the connection may be by direct connection or by indirect connection through other devices (or components) and connections.

[0106] With regard to the use of expressions such as “an embodiment,” “one embodiment,” “exemplary embodiment,” “particular embodiment,” or other similar terms in this specification, these expressions are intended to indicate that a particular feature, structure, function, operation, or characteristic described in relation to an embodiment is found in at least one embodiment of this disclosure. Therefore, where phrases such as “in one embodiment,” “in a particular embodiment,” or “in an exemplary embodiment” appear, they do not necessarily all refer to the same embodiment, and unless explicitly otherwise specified, they mean “one or more embodiments, but not all embodiments.” Furthermore, the terms “comprising,” “having,” and “including,” and their variations, are used non-exclusively and shall be interpreted as “including, but not limited to…,” unless explicitly otherwise specified. Also, an element preceded by “comprises…a” does not exclude the existence of additional identical elements in the process, method, system, article, or apparatus of interest that include that element, unless more constraints are imposed.

[0107] Furthermore, unless explicitly otherwise specified, the terms “a,” “an,” and “the” refer to “one or more.” For example, a “processor” programmed to perform various functions refers to a single processor programmed to perform all functions, or to multiple processors collectively programmed to perform each of various functions. In addition, the phrase “at least one of A and B,” as used herein and / or in the following claims, where A and B are variables indicating a particular object or attribute, indicates a choice between A or B, or both A and B, similar to the phrase “and / or.” Where present in a phrase involving more than two variables, this phrase is defined herein to include one variable, any one of the variables, any combination (or subcombination) of the variables, and all of the variables.

[0108] Furthermore, as used herein, the terms “about” or “approximately” apply to all numerical values, whether explicitly indicated or not. These terms generally refer to a range of numerical values ​​that a person skilled in the art would consider equivalent to (e.g., having the same function or result as) the value mentioned. In certain cases, these terms may include numerical values ​​rounded to the nearest significant figure.

[0109] In addition, unless explicitly otherwise specified, any enumeration of items described herein does not imply that any or all of the enumerated items are mutually exclusive and / or mutually inclusive. Furthermore, as used herein, the term “set” means “one or more,” and in the case of “set,” unless explicitly otherwise specified, it shall be interpreted according to set theory as meaning “one or more,” “ones or more,” and / or multiples of “ones or mores.”

[0110] The detailed description above is presented for illustrative and explanatory purposes only. It is not intended to be exhaustive or to limit the disclosure to the exact form. Many modifications and variations are possible in light of the above description. The embodiments described have been selected to best illustrate the principles of the Art and its practical applications, so that those skilled in the art can make the most effective use of the Art by making various modifications to various embodiments suitable for a particular intended use. The scope of the Art is defined by the claims appended herein.

Claims

1. A method for operating a memory device, A step of preparing a memory block, which includes an array of memory cells arranged as multiple word lines, and which includes multiple memory holes having various diameters that penetrate the multiple word lines, wherein the word lines are grouped into a first group and a second group based on the memory hole diameters. The step of determining whether the selected word lines of the plurality of word lines belong to the first group or the second group, The steps include: performing a memory operation using a first set of reference voltages in response to the selected word line being in the first group; The steps include: performing the memory operation using a second set of reference voltages in response that the selected word line is in the second group; A method wherein the first set and the second set of reference voltages are different for a plurality of data states and similar for at least one data state in the highest threshold voltage range.

2. The method according to claim 1, wherein the memory operation is a 3-bit memory operation per memory cell, and each of the first set and the second set of reference voltages comprises seven reference voltages associated with seven programmed data states in various threshold voltage ranges.

3. The method according to claim 2, wherein the memory operation is a programming operation, and the reference voltages of the first set and the second set of reference voltages are verify voltages.

4. The method according to claim 3, wherein, by programming the memory cells of the second group of word lines for the first six programmed data states, the reference voltage of the second set of reference voltages is greater than the reference voltage of the first set of reference voltages, such that the margin between erased data states and first programmed data states is increased compared to programming the memory cells of the first group of word lines.

5. The method according to claim 4, wherein for each of the programmed data states except the final data state, the reference voltage of the second set of reference voltages is greater than the reference voltage of the first set of reference voltages by a first offset.

6. The method according to claim 4, wherein the memory holes have a larger diameter in the first group of word lines and a smaller diameter in the second group of word lines.

7. The method according to claim 2, wherein the memory operation is a read operation.

8. For each of the data states of the plurality of data states, excluding the final data state, the reference voltage is equal to the verify voltage of the data state plus a first offset and a second offset. The method according to claim 6, wherein, in the case of the final data state, the reference voltage is equal to the verify voltage of the final data state plus the first offset.

9. A memory device, A memory block comprising an array of memory cells arranged as multiple word lines, and a plurality of memory holes having various diameters that penetrate the multiple word lines, wherein the word lines are grouped into a first group and a second group based on the memory hole diameter, The circuit includes a circuit that performs memory operations on selected word lines of the plurality of word lines, and the circuit is Determining whether the selected word line is in the first group or the second group, In response to the selected word line being in the first group, a memory operation is performed using a first set of reference voltages, The system is configured to perform the memory operation using a second set of reference voltages in response to the selected word line being within the second group, A memory device in which the first and second sets of reference voltages differ for a plurality of data states and are similar for at least one data state in the highest threshold voltage range.

10. The memory device according to claim 9, wherein the memory operation is a 3-bit memory operation per memory cell, and each of the first set and the second set of reference voltages comprises seven reference voltages associated with seven programmed data states in various threshold voltage ranges.

11. The memory device according to claim 10, wherein the memory operation is a programming operation, and the reference voltages of the first set and the second set of reference voltages are verify voltages.

12. The memory device according to claim 11, wherein the reference voltage of the second set of reference voltages is greater than the reference voltage of the first set of reference voltages, such that programming the memory cells of the second group of word lines for the first six programmed data states increases the margin between erased data states and first programmed data states compared to programming the memory cells of the first group of word lines.

13. The memory device according to claim 12, wherein for each of the programmed data states, excluding the final data state, the reference voltage of the second set of reference voltages is greater than the reference voltage of the first set of reference voltages by a first offset.

14. The memory device according to claim 12, wherein the memory holes have a larger diameter in the first group of word lines and a smaller diameter in the second group of word lines.

15. The memory device according to claim 10, wherein the memory operation is a read operation.

16. For each of the data states of the plurality of data states, excluding the final data state, the reference voltage is equal to the verify voltage of the data state plus a first offset and a second offset. The memory device according to claim 15, wherein, in the case of the final data state, the reference voltage is equal to the verify voltage of the final data state plus the first offset.

17. It is a device, A memory block comprising an array of memory cells arranged as multiple word lines, and comprising multiple memory holes having various diameters that penetrate the multiple word lines, wherein the multiple word lines include the lowest layer word line and other word lines, The detection means is configured to perform a detection operation on selected word lines of the plurality of word lines, and the detection means is configured to perform a detection operation on selected word lines of the plurality of word lines. Determine whether the selected word line is one of the bottommost word lines or one of the other word lines, In response to the selected word line being one of the other word lines, a detection operation is performed using a first set of reference voltages. The system is configured to perform the detection operation using a second set of reference voltages in response to the selected word line being one of the bottommost word lines, The apparatus wherein the first set and the second set of reference voltages differ for a plurality of data states and are similar for at least one data state in the highest threshold voltage range.

18. The apparatus according to claim 17, wherein the detection operation is a verify operation, and the reference voltages of the first set and the second set of reference voltages are verify voltages.

19. The apparatus according to claim 17, wherein the detection operation is a reading operation.

20. The apparatus according to claim 17, wherein the detection operation is a 3-bit detection operation per memory cell, and each of the first set and the second set of reference voltages comprises seven reference voltages associated with seven programmed data states in various threshold voltage ranges.

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