Packet processing device, packet processing circuit, and packet processing method

Abstract

We provide packet processing equipment and other devices that can adjust delay and jitter. [Solution] The packet processing device includes a packet processing unit that processes received packets and a buffering unit that stores the received packets. The buffering unit includes a plurality of buffers for storing each of the received packets, a selector for selecting the buffer to which to output the packets, and a switching control unit that controls the selector to sequentially switch the buffer from which to read the packets. When the packet processing unit receives a packet, it includes a distribution control unit that determines the destination buffer based on the insertion delay amount for each flow to which the packet belongs.

Description

Technical Field

[0001] The present invention relates to a packet processing apparatus, a packet processing circuit, and a packet processing method.

Background Art

[0002] As major requirements of 5G (5th Generation Mobile Communication System), concepts such as high capacity, low latency, and multi-connection, for example, have newly emerged, and the importance of these concepts continues to increase in B5G (Beyond 5G) and 6G. Particularly, "low latency" is a concept that has not been considered much conventionally, and there are many existing networks that cannot guarantee "low latency". th Moreover, even for low-latency applications, the required requirements are various. In particular, with the emergence of a new service called URLLC (Ultra-Reliable and Low Latency Communications), new requirements such as jitter removal and delay insertion may be demanded. Therefore, in order to support such URLLC services, a method that can more actively adjust the delay is required.

[0003] In conventional QoS control, priority control such as mediation of the packet reading order in units of priority classes / flows and rate control such as output rate adjustment are performed.

[0004]

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

[0006] However, conventional QoS control cannot intentionally alter the packet reading time, such as by adding a 5ms delay guarantee or delay insertion, and therefore cannot adjust delays or jitter.

[0007] One aspect of this is the aim to provide packet processing equipment that can adjust delay and jitter. [Means for solving the problem]

[0008] One embodiment of a packet processing device includes a packet processing unit for processing received packets and a buffering unit for storing received packets. The buffering unit includes a plurality of buffers for storing each of the received packets, a selector for selecting the buffer to output the packets to, and a switching control unit for controlling the selector to sequentially switch the buffer from which to read the packets. When the packet processing unit receives a packet, it includes a distribution control unit that determines the destination buffer based on the insertion delay amount for each flow to which the packet belongs. [Effects of the Invention]

[0009] In one configuration, delay and jitter can be adjusted. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 is an explanatory diagram showing an example of a packet communication system in Example 1. [Figure 2] Figure 2 is an explanatory diagram showing an example of a packet processing device. [Figure 3] Figure 3 is an explanatory diagram showing an example of the table structure of a TS information table. [Figure 4] Figure 4 is an explanatory diagram showing an example of the current table structure of the TS Management Department. [Figure 5]FIG. 5 is an explanatory diagram showing an example of the table configuration of the delay information table. [Figure 6] FIG. 6 is an explanatory diagram showing an example of the table configuration of the buffer management table. [Figure 7] FIG. 7 is an explanatory diagram showing an example of the buffering operation of the packet processing device. [Figure 8] FIG. 8 is a flowchart showing an example of the processing operation of the packet processing device related to the first reception processing. [Figure 9] FIG. 9 is an explanatory diagram showing an example of the packet communication system of Example 2. [Figure 10] FIG. 10 is an explanatory diagram showing an example of the transmission-side packet processing device. [Figure 11] FIG. 11 is an explanatory diagram showing an example of the reception-side packet processing device. [Figure 12] FIG. 12 is a flowchart showing an example of the processing operation of the reception-side packet processing device related to the second reception processing. [Figure 13] FIG. 13 is an explanatory diagram showing an example of the reception-side packet processing device of Example 3. [Figure 14] FIG. 14 is an explanatory diagram showing an example of the FIFO range. [Figure 15] FIG. 15 is a flowchart showing an example of the processing operation of the reception-side packet processing device related to the third reception processing. [Figure 16] FIG. 16 is an explanatory diagram showing an example of the packet communication system of Example 4. [Figure 17] FIG. 17 is an explanatory diagram showing an example of the transmission-side packet processing device. [Figure 18] FIG. 18 is an explanatory diagram showing an example of the reception-side packet processing device. [Figure 19] FIG. 19 is a sequence diagram showing an example of the TS synchronization processing. [Figure 20] FIG. 20 is a flowchart showing an example of the processing operation of the reception-side packet processing device related to the reception-side synchronization processing. [Figure 21]FIG. 21 is a flowchart showing an example of the processing operation of a transmission-side packet processing device related to transmission-side synchronization processing. [Figure 22] FIG. 22 is an explanatory diagram showing an example of the packet communication system of Example 5. [Figure 23] FIG. 23 is an explanatory diagram showing an example of a transmission-side packet processing device. [Figure 24] FIG. 24 is an explanatory diagram showing an example of the table configuration of an SN counter. [Figure 25] FIG. 25 is an explanatory diagram showing an example of a reception-side packet processing device. [Figure 26] FIG. 26 is an explanatory diagram showing an example of the table configuration of an SN management table. [Figure 27] FIG. 27 is an explanatory diagram showing an example of the buffering operation of a reception-side packet processing device. [Figure 28] FIG. 28 is a flowchart showing an example of the processing operation of a reception-side packet processing device related to the fourth reception processing. [Figure 29] FIG. 29 is a flowchart showing an example of the processing operation of a reception-side packet processing device related to expected SN update processing. [Figure 30] FIG. 30 is an explanatory diagram showing an example of the packet communication system of Comparative Example 1. [Figure 31A] FIG. 31A is an explanatory diagram showing an example of the buffering state of Comparative Example 1. [Figure 31B] FIG. 31B is an explanatory diagram showing an example of the buffering state of Comparative Example 1. [Figure 31C] FIG. 31C is an explanatory diagram showing an example of the buffering state of Comparative Example 1. [Figure 32] FIG. 32 is an explanatory diagram showing an example of the packet communication system of Comparative Example 2. [Figure 33A] FIG. 33A is an explanatory diagram showing an example of the buffering state of Comparative Example 2. [Figure 33B] FIG. 33B is an explanatory diagram showing an example of the buffering state of Comparative Example 2. [Figure 33C]Figure 33C is an explanatory diagram showing an example of the buffering state in Comparative Example 2. [Modes for carrying out the invention]

[0011] The following describes in detail embodiments of the packet processing device and the like disclosed in this application, based on the drawings. Note that the disclosed technology is not limited by each embodiment. Furthermore, the embodiments shown below may be combined as appropriate, provided they do not contradict each other. [Examples]

[0012] Figure 1 is an explanatory diagram showing an example of a packet communication system 1 of Embodiment 1. The packet communication system 1 shown in Figure 1 includes a transmitting device 2, a receiving device 3, a network 4, and a packet processing device 5. The transmitting device 2 is a communication device that transmits packets, such as a personal computer. The receiving device 3 is a communication device that receives packets, such as a server. The network 4 is a communication network that transmits packets between the transmitting device 2 and the receiving device 3. The packet processing device 5 is a processing device that performs packet processing on packets from the transmitting device 2 and transmits the processed packets to the receiving device 3.

[0013] Figure 2 is an explanatory diagram showing an example of a packet processing device 5. The packet processing device 5 shown in Figure 2 has a packet processing unit 10 and a buffering unit 20. The packet processing unit 10 is a packet processing circuit that can be attached to and detached from the packet processing device 5 and processes packets received from the transmitting device 2. The buffering unit 20 is a buffering circuit that can be attached to and detached from the packet processing device 5 and stores the received packets and reads and outputs the stored packets.

[0014] The buffering unit 20 includes a FIFO (Fast In Fast Out) group 21, a distribution unit 22, a selector 23, and a switching control unit 24. The FIFO group 21 has multiple FIFOs 21A, one for each TS (Time Slot) number. TS is the timing for reading packets. The FIFO group 21 is not provided for each flow to which a packet belongs, but is a buffer group shared among all flows. Each FIFO 21A stores the received packet and is a buffer that reads and outputs the stored packet according to the TS. Each FIFO 21A in the FIFO group 21 is assigned a TS number. The TS number is a number that identifies the TS. The TS number is information about the time corresponding to the timing. For example, if there are 1024 TS numbers from TS1 to TS1024, the FIFO group 21 will have 1024 FIFOs 21A. The FIFO group 21 comprises 1024 FIFOs, such as FIFO21A for TS number "1", FIFO21A for TS number "2", FIFO21A for TS number "1024", and so on.

[0015] The distribution unit 22 is positioned before the FIFO group 21 and distributes packets to be stored from the FIFO group 21 to the destination FIFO 21A. The selector 23 is positioned after the FIFO group 21 and selects one of the FIFO 21A from the FIFO group 21. During the selection period, packets accumulated in the selected FIFO 21A are output. The selector 23 selects the FIFO 21A from which packets are output.

[0016] The switching control unit 24 controls the selector 23 to sequentially switch the FIFO 21A to be read in TS units in order of TS number. The switching control unit 24 controls the selector 23 at a fixed period to sequentially switch the FIFO 21A. For example, if 1 TS is 0.1 m seconds, the switching control unit 24 controls the selector 23 to sequentially switch the FIFO 21A to be read in order of TS number every 0.1 m seconds. In other words, the selector 23 sequentially switches the FIFO 21A in order of TS number, such as "TS1" → "TS2" → "TS3" → ... → "TS1024" → "TS1" → "TS2" → ... For the sake of explanation, the TS numbers are set to 1 to 1024, but are not limited to these and can be changed as appropriate. The FIFO number used to identify FIFO 21A is the same as the TS number.

[0017] The packet processing unit 10 includes a receiving unit 11, a distribution control unit 13, a current TS management unit 14, a current TS counter 15, a TS information table 31, a delay information table 32, and a buffer management table 33. The receiving unit 11 is connected to the network 4 and receives packets from the transmitting device 2. The receiving unit 11 obtains a flow ID from the received packet. The flow ID is an ID that identifies the flow to which the packet belongs.

[0018] The distribution control unit 13 determines the destination FIFO 21A to which the received packet will be distributed, based on the insertion delay, which is the insertion delay amount for each flow ID in the delay information table 32. The distribution control unit 13 determines the destination FIFO 21A based on a fixed period of the selector 23. In other words, the distribution control unit 13 calculates the destination TS number corresponding to the read timing according to the insertion delay, which is the insertion delay amount for each flow to which the packet belongs, and determines the FIFO 21A of the calculated destination TS number (FIFO number) as the destination FIFO 21A. The distribution control unit 13 controls the distribution unit 22 in order to distribute the received packet to the determined destination FIFO 21A. The distribution control unit 13 then adjusts the delay between packets by distributing the packets of the relevant flow to the destination FIFO 21A. In other words, when the current TS number is "TS1", the distribution control unit 13 can distribute the received packet to the FIFO21A of "TS6", for example, enabling a delay of approximately 5 milliseconds.

[0019] The distribution control unit 13, for example, if the destination FIFO21A to which a received packet is to be distributed is in conflict with another received packet, will distribute the received packet from the destination FIFO21A to the nearest available FIFO21A. For example, consider the case where the destination FIFO21A for "TS6" to which a received packet is to be distributed is in conflict with another received packet. In this case, the system searches for an available FIFO21A as the destination FIFO21A for "TS6" from among the nearest FIFO21A, in the order of "TS7" FIFO21A → "TS8" FIFO21A → "TS9" FIFO21A → ... Note that, since the input rate basically equals the output rate, it is a rare case for different received packets to conflict with a single FIFO21A, and even if that were to happen, only a few FIFO21A would be shifted, and the impact on the entire packet communication system 1 would be minor.

[0020] Currently, the TS management unit 14 manages the current TS counter 15 while referring to the TS information table 31. The current TS counter 15 counts the TS number in units of TS using its own clock source and counts the current TS number.

[0021] Figure 3 is an explanatory diagram showing an example of the table structure of the TS information table 31. The TS information table 31 shown in Figure 3 manages the TS unit and the maximum TS number. The TS unit is the time equivalent to 1 TS, for example, 1 millisecond. The maximum TS number is the TS number of the maximum TS. For example, in the case of 1024 TS, the minimum TS number is "TS1" and the maximum TS number is "TS1024". The current TS counter 15 counts the current TS number while referring to the TS information table 31.

[0022] Figure 4 is an explanatory diagram showing an example of the table configuration of the current TS management unit 14. The current TS management unit 14 shown in Figure 4 manages the TS numbers of the current TS by counting them with the current TS counter 15.

[0023] Figure 5 is an explanatory diagram showing an example of the table structure of the delay information table 32. The delay information table 32 shown in Figure 5 manages the insertion delay 32B and the latest FIFO number 32C for each flow ID 32A. The flow ID 32A is the VLAN ID that identifies the flow. The insertion delay 32B is the amount of insertion delay imposed on each packet of the flow. The latest FIFO number 32C is the FIFO number that identifies the FIFO 21A that distributes and stores the latest received packets of the flow. The distribution control unit 13 refers to the delay information table 32 and can recognize, for example, that for flow ID #1, the insertion delay is 5TS and the latest FIFO number is "TS4", and for flow ID #2, the insertion delay is 3TS and the latest FIFO number is "TS18".

[0024] Figure 6 is an explanatory diagram showing an example of the table configuration of the buffer management table 33. The buffer management table 33 shown in Figure 6 manages the buffer limit value 33B and the queue length 33C for each FIFO number 33A. FIFO number 33A is the number that identifies FIFO 21A. Buffer limit value 33B is the upper limit of the buffering amount for FIFO 21A. Queue length 33C is the packet length of the packets stored in FIFO 21A. The distribution control unit 13 refers to the buffer management table 33 and can recognize, for example, that the buffer limit value 33B for FIFO 21A with FIFO number #1 is 125,000 bytes and the queue length 33C is 110,400 bytes. Note that FIFO number #1 is TS number "TS1", and FIFO number #2 is TS number "TS2". Furthermore, the distribution control unit 13 can refer to the queue length 33C in the buffer management table 33 and recognize an available FIFO 21A from the FIFO group 21.

[0025] Figure 7 is an explanatory diagram showing an example of the buffering operation of the packet processing unit 5. When the receiving unit 11 in the packet processing unit 5 receives a packet from the transmitting device 2, it obtains the flow ID within the packet. The distribution control unit 13 in the packet processing unit 5 obtains the insertion delay (5TS) corresponding to the obtained flow ID from the delay information table 32.

[0026] The distribution control unit 13 calculates "TS6" by adding the insertion delay "5TS" to the current TS number "TS1" which is currently counted by the TS counter 15. Then, the distribution control unit 13 determines that the FIFO 21A of "TS6" is the destination FIFO 21A and stores the received packet in the FIFO 21A of "TS6".

[0027] The switching control unit 24 then controls the selector 23 to sequentially switch the output of the FIFO 21A in order of TS number every 1 millisecond. The selector 23 then reads and outputs the packet from the FIFO 21A of "TS6" at the timing of "TS6".

[0028] Figure 8 is a flowchart showing an example of the processing operation of the packet processing device 5 involved in the first receiving process. In Figure 8, the receiving unit 11 within the packet processing device 5 determines whether or not it has received a received packet from the transmitting device 2 (step S11). If the receiving unit 11 has received a received packet (step S11: Yes), it obtains a flow ID from the received packet (step S12).

[0029] Furthermore, the distribution control unit 13 obtains the current TS from the current TS counter 15 (step S13). The distribution control unit 13 refers to the delay information table 32 and obtains the insertion delay 32B and the latest FIFO number 32C corresponding to the flow ID 32A (step S14). The distribution control unit 13 calculates the FIFO number corresponding to the TS number equivalent to (current TS number + insertion delay) (step S15). The current TS number is obtained from the current TS counter 15.

[0030] The distribution control unit 13 uses the calculated FIFO number as a candidate FIFO number and determines whether the candidate FIFO number is greater than or equal to the latest FIFO number (step S16). If the candidate FIFO number is greater than or equal to the latest FIFO number (step S16: Yes), the distribution control unit 13 refers to the buffer management table 33 and determines the FIFO number of the nearest available FIFO 21A after the FIFO number corresponding to the TS number equivalent to (current TS number + insertion delay) (step S17).

[0031] The distribution control unit 13 stores the received packet in the available FIFO 21A corresponding to the determined FIFO number (step S18). Furthermore, the distribution control unit 13 adds the packet length of the received packet to the queue length 33C of the FIFO 21A where the received packet is stored and updates the contents of the buffer management table 33 (step S19). Finally, the distribution control unit 13 updates the contents of the delay information table 32 with the FIFO number of the FIFO 21A where the received packet is stored as the latest FIFO number 32C (step S20), and terminates the processing operation shown in Figure 8.

[0032] If the candidate FIFO number is not equal to or greater than the latest FIFO number (step S16: No), the distribution control unit 13 refers to the buffer management table 33 and determines the FIFO number of the nearest available FIFO 21A after the latest FIFO number (step S21). The distribution control unit 13 then proceeds to the process in step S18 to store the received packet in the available FIFO 21A of the determined FIFO number.

[0033] If the distribution control unit 13 has not received a received packet (step S11: No), it terminates the processing operation shown in Figure 8.

[0034] The distribution control unit 13 obtains the insertion delay and the latest FIFO number corresponding to the flow ID of the received packet. The distribution control unit 13 calculates a candidate FIFO number using (current TS number + insertion delay). If the calculated candidate FIFO is greater than or equal to the latest FIFO number, the distribution control unit 13 determines the nearest FIFO number from the candidate FIFO number. As a result, the destination FIFO 21A for the received packet can be determined.

[0035] If the calculated candidate FIFO is not equal to or greater than the latest FIFO number, the distribution control unit 13 determines the nearest FIFO number from the latest FIFO number onward. As a result, it can determine the destination FIFO 21A for the received packet.

[0036] The packet processing device 5 of Embodiment 1 has a FIFO group 21 having multiple FIFOs 21A, one for each TS number, which store packets that can be read for each TS. When the distribution control unit 13 in the packet processing device 5 receives a packet from the transmitting device 2, it calculates the destination TS number (FIFO number) according to the insertion delay, which is the delay amount for each flow to which the packet belongs, in TS terms. Furthermore, the distribution control unit 13 determines the FIFO 21A of the calculated destination FIFO number from the FIFO group 21 as the destination FIFO. The distribution unit 22 distributes the received packet to the determined destination FIFO 21A. As a result, delay and jitter can be adjusted.

[0037] The switching control unit 24 within the packet processing unit 5 controls the selector 23 to switch the output of one FIFO 21A from the FIFO group 21, which is read out, in the order of TS number for each TS. As a result, packets stored in the FIFO group 21 can be output sequentially in the order of TS number.

[0038] The distribution control unit 13 calculates the destination TS number (FIFO number) based on the insertion delay in TS conversion and the current TS number. The distribution control unit 13 then determines the destination FIFO 21A for the calculated destination FIFO number. As a result, the destination FIFO 21A for the received packet can be determined using the current TS number of the current TS counter 15.

[0039] In Example 1, the packet processing device 5 currently counts the current TS from the TS counter 15 and uses the current TS number and insertion delay to obtain the FIFO number of the destination FIFO 21A. However, the current TS number may be synchronized between the transmitting packet processing device 6A and the receiving packet processing device 5A, and such an embodiment will be described below as Example 2. In addition, the same reference numerals are used for components identical to those in the packet communication system 1 of Example 1, and the explanation of the redundant components and operations will be omitted. [Examples]

[0040] Figure 9 is an explanatory diagram showing an example of the packet communication system 1A of Embodiment 2. The packet communication system 1A shown in Figure 9 includes a transmitting device 2, a receiving device 3, a network 4, a transmitting packet processing device 6A, and a receiving packet processing device 5A.

[0041] The transmitting packet processing unit 6A connects the transmitting device 2 and the network 4 and is a packet processing unit that processes transmitted packets. The receiving packet processing unit 5A connects the receiving device 3 and the network 4 and is a packet processing unit that processes received packets.

[0042] The transmitting packet processing unit 6A and the receiving packet processing unit 5A synchronize the current TS in advance using an external synchronization means such as PTP (Precision Time Protocol) or NTP (Network Time Protocol).

[0043] Figure 10 is an explanatory diagram showing an example of a transmitting packet processing device 6A. The transmitting packet processing device 6A shown in Figure 10 includes a current TS management unit 51, a current TS counter 52, a TS assignment unit 53, and a TS information table 54.

[0044] Currently, the TS management unit 51 manages the current TS number counted by the current TS counter 52 while referring to the TS information table 54. The current TS counter 52 counts the TS number in units of TS using its own clock source and counts the current TS number. The TS information table 54 manages the TS units and the maximum TS number. The contents of the TS information table 54 are the same as the contents of the TS information table 31.

[0045] When the TS assignment unit 53 transmits a transmission packet to the receiving device 3, it assigns a flow ID and the transmitting side TS number, which is the current TS number, to the transmission packet, for example, by using a VLAN tag. The transmitting side TS number is the first read number. The TS assignment unit 53 then transmits the transmission packet to the network 4. When the transmitting side packet processing device 6A transmits a packet to the receiving side packet processing device 5A, it transmits a packet that includes the transmitting side TS number, which is the current first TS number.

[0046] Figure 11 is an explanatory diagram showing an example of a receiving packet processing device 5A. The packet processing unit 10 in the receiving packet processing device 5A shown in Figure 11 includes a receiving unit 11, a distribution control unit 13, a current TS management unit 14, and a current TS counter 15. The packet processing unit 10 includes a TS information table 31, a delay information table 32, and a buffer management table 33. The buffering unit 20 in the receiving packet processing device 5A includes a FIFO group 21, a distribution unit 22, a selector 23, and a switching control unit 24. When the receiving unit 11 receives a received packet, it refers to the flow ID and the current TS number (transmitter TS number) in the received packet.

[0047] When the receiving packet processing unit 5A receives a packet from the transmitting packet processing unit 6A, it corrects the second TS number, which is the current TS number, based on the transmitting TS number in the packet. As a result, TS synchronization between the transmitting packet processing unit 6A and the receiving packet processing unit 5A can be ensured.

[0048] Figure 12 is a flowchart illustrating an example of the processing operation of the receiving packet processing device 5A involved in the second receiving process. The receiving packet processing device 5A synchronizes the current TS with the transmitting packet processing device 6 in advance using an external synchronization means. In Figure 12, the receiving unit 11 within the receiving packet processing device 5A determines whether or not it has received a received packet (step S31). If the receiving unit 11 has received a received packet (step S31: Yes), it obtains the flow ID and the transmitting TS number from the received packet (step S32).

[0049] Furthermore, the distribution control unit 13 obtains the current TS number from the current TS counter 15 (step S33). The distribution control unit 13 refers to the delay information table 32 and obtains the insertion delay 32B and the latest FIFO number 32C corresponding to the flow ID 32A (step S34). The distribution control unit 13 calculates a candidate FIFO number corresponding to the TS number equivalent to (transmitter TS number + insertion delay) (step S35).

[0050] The distribution control unit 13 determines whether the calculated candidate FIFO number is greater than or equal to the current TS number (step S36). If the candidate FIFO number is greater than or equal to the current TS number (step S36: Yes), the distribution control unit 13 determines whether the calculated candidate FIFO number is greater than or equal to the latest FIFO number (step S38). If the candidate FIFO number is greater than or equal to the latest FIFO number (step S38: Yes), the distribution control unit 13 refers to the buffer management table 33 and determines the FIFO number of the most recent available FIFO 21A from the candidate FIFO number (step S39).

[0051] The distribution control unit 13 stores the received packet in the available FIFO 21A corresponding to the determined FIFO number (step S40). Furthermore, the distribution control unit 13 adds the packet length of the received packet to the queue length 33C of the FIFO 21A where the received packet is stored and updates the contents of the buffer management table 33 (step S41). Finally, the distribution control unit 13 updates the contents of the delay information table 32 with the FIFO number of the FIFO 21A where the received packet is stored as the latest FIFO number (step S42), and terminates the processing operation shown in Figure 12.

[0052] If the candidate FIFO number is not equal to or greater than the latest FIFO number (step S38: No), the distribution control unit 13 refers to the buffer management table 33 and determines the FIFO number of the nearest available FIFO 21A from the latest FIFO number onward (step S43). Then, the distribution control unit 13 proceeds to the process in step S40.

[0053] If the candidate FIFO number is not equal to or greater than the current TS number (step S36: No), the distribution control unit 13 refers to the buffer management table 33 and determines the FIFO number of the nearest available FIFO 21A from the current TS number onward (step S44). Then, the distribution control unit 13 proceeds to the process in step S40.

[0054] If the distribution control unit 13 has not received a received packet (step S31: No), it terminates the processing operation shown in Figure 12.

[0055] The distribution control unit 13 calculates a candidate FIFO number using (the transmitting TS number of the received packet + insertion delay). The distribution control unit 13 determines whether the candidate FIFO number is greater than or equal to the current TS number. If the candidate FIFO number is greater than or equal to the current TS number, the distribution control unit 13 determines whether the candidate FIFO number is greater than or equal to the latest FIFO number. If the candidate FIFO number is greater than or equal to the latest FIFO number, the distribution control unit 13 determines the nearest available FIFO number from the candidate FIFO number. As a result, the destination FIFO 21A for the received packet can be determined.

[0056] If the distribution control unit 13 is not equal to or greater than the current TS number, it determines the nearest available FIFO number from the current TS number onward. As a result, it can determine the destination FIFO 21A for the received packet.

[0057] If the distribution control unit 13 is not equal to or greater than the latest FIFO number, it determines the nearest available FIFO number from the latest FIFO number onward. As a result, it can determine the destination FIFO 21A for the received packet.

[0058] In Embodiment 2, the distribution control unit 13 within the receiving packet processing device 5A calculates the destination FIFO number based on the TS-converted insertion delay and the transmitting TS number of the received packet, and determines the destination FIFO 21A for the calculated destination FIFO number. As a result, not only can delay and jitter be adjusted, but the destination FIFO 21A for the received packet can also be determined using the TS number within the received packet.

[0059] When the transmitting packet processing unit 6A sends a packet to the receiving packet processing unit 5A, it sends a packet that includes the transmitting TS number, which is the current first TS number. When the receiving packet processing unit 5A receives a packet from the transmitting packet processing unit 6A, it corrects the second TS number, which is the current TS number, based on the first TS number in the packet. As a result, TS synchronization between the transmitting packet processing unit 6A and the receiving packet processing unit 5A can be ensured.

[0060] In the receiving - side packet processing device 5A of Embodiment 2, when the delay amount of the transmission path between the receiving - side packet processing device 5A and the transmitting - side packet processing device 6A is large, the FIFO group 21 requires a FIFO 21A with a FIFO amount capable of absorbing the delay amount. For example, when the delay amount between Japan and the United States is 100 milliseconds and the delay fluctuation width on the transmission path is 10 milliseconds, a FIFO 21A with a FIFO amount for 110 milliseconds is required. That is, in the receiving - side packet processing device 5A, in order to satisfy the relationship between the insertion delay < FIFO amount, it is necessary to increase the FIFO 21A according to the insertion delay. Therefore, in order to deal with such a situation, an embodiment capable of realizing delay control while reducing the FIFO amount will be described below as Embodiment 3. The same components as those of the packet communication system 1A of Embodiment 2 are denoted by the same reference numerals, and the description of their overlapping configurations and operations will be omitted.

Embodiment

[0061] FIG. 13 is an explanatory diagram showing an example of the receiving - side packet processing device 5D of Embodiment 3. The receiving - side packet processing device 5D shown in FIG. 13 includes a packet processing unit 10 and a buffering unit 20. The packet processing unit 10 includes a receiving unit 11, a distribution control unit 13D, a current TS management unit 14, a current TS counter 15, a TS information table 31, a delay information table 32, and a buffer management table 33. The buffering unit 20 includes a FIFO group 21X, a distribution unit 22, a selector 23, and a switching control unit 24D.

[0062] The FIFO group 21X has a FIFO 21A with a FIFO amount capable of absorbing the delay amount corresponding to the delay fluctuation width. It is assumed that the receiving - side packet processing device 5D has previously observed and grasped the delay fluctuation width on the transmission path. The FIFO group 21 of Embodiment 2 requires a FIFO 21A with a FIFO amount corresponding to (delay amount + delay fluctuation width), while the FIFO group 21X of Embodiment 3 only requires a FIFO 21A with a FIFO amount corresponding to the delay fluctuation width. Therefore, the number m of FIFOs required for delay control can be significantly reduced.

[0063] FIG. 14 is an explanatory diagram showing an example of the FIFO range. In FIG. 14, the horizontal axis represents the differential time (TS) of the receiving-side packet processing device 5D, and the vertical axis represents the number of packets. The receiving-side packet processing device 5D prepares FIFOs 21A with the number m of FIFOs in the FIFO group 21X so as to cover the FIFO range in which the received packet can be output at the timing of (transmission-side TS number + insertion delay amount) after passing through the delay fluctuation from the current TS number of the received packet arriving after the transmission delay of the transmission path. The FIFO range is within the range from the current TS number to (current TS number + FIFO number m).

[0064] That is, the FIFO group 21X only needs to have the number m of FIFOs 21A with a delay fluctuation width < FIFO amount. Even when the insertion delay ≧ FIFO amount, the receiving-side packet processing device 5D can, of course, adjust the delay and jitter, and can determine the destination FIFO 21A of the received packet by using the TS number in the received packet.

[0065] When receiving a received packet, the distribution control unit 13D acquires the transmission-side TS number in the received packet and acquires the insertion delay corresponding to the flow ID in the received packet from the delay information table 32. The distribution control unit 13D determines the FIFO number of the TS number corresponding to the remainder obtained by dividing (transmission-side TS number + insertion delay) by the FIFO number (m), that is, (transmission-side TS number + insertion delay) mod FIFO number (m), as the destination FIFO 21A.

[0066] The switching control unit 24D controls the selector 23 so as to switch the FIFO number of the TS number corresponding to the remainder obtained by dividing the current TS number by the FIFO number (m), that is, the current TS number mod FIFO number (m), as the FIFO 21A to be read out.

[0067] Figure 15 is a flowchart showing an example of the processing operation of the receiving packet processing device 5D involved in the third receiving process. The receiving packet processing device 5D synchronizes the current TS with the transmitting packet processing device 6 in advance using an external synchronization means. In Figure 15, the receiving unit 11 within the receiving packet processing device 5D determines in step S31 whether or not it has received a received packet. If the receiving unit 11 has received a received packet, it executes the process in step S32 to obtain the flow ID and transmitting TS number from the received packet.

[0068] Furthermore, in step S33, the distribution control unit 13D obtains the current TS number from the current TS counter 15. The distribution control unit 13D refers to the delay information table 32 and obtains the insertion delay 32B and the latest FIFO number 32C corresponding to the flow ID 32A in step S34. The distribution control unit 13D executes the process in step S35 to calculate a candidate FIFO number corresponding to the TS number equivalent to (transmitter TS number + insertion delay).

[0069] The distribution control unit 13D determines whether the candidate FIFO number is equal to (current TS number + number of FIFOs) > candidate FIFO number ≥ current TS number (step S36A). If the distribution control unit 13D determines that the candidate FIFO number is equal to (current TS number + number of FIFOs) > candidate FIFO number ≥ current TS number (step S36A: Yes), it executes the process in step S38 to determine whether the calculated candidate FIFO number is equal to or greater than the latest FIFO number.

[0070] The distribution control unit 13D calculates the candidate FIFO number mod FIFO number if the candidate FIFO number is greater than or equal to the latest FIFO number. The distribution control unit 13D refers to the buffer management table 33 and determines the FIFO number of the most recent available FIFO 21A from the calculated (candidate FIFO number mod FIFO number) (step S39A).

[0071] The distribution control unit 13D executes the process in step S40 to store the received packet in the available FIFO 21A corresponding to the determined FIFO number.

[0072] If the candidate FIFO number in step S38 is not equal to or greater than the latest FIFO number, the distribution control unit 13D calculates (latest FIFO number mod FIFO count). The distribution control unit 13D refers to the buffer management table 33 and determines the FIFO number of the nearest available FIFO 21A from after the calculated (latest FIFO number mod FIFO count) (step S43A). Then, the distribution control unit 13D proceeds to the processing in step S40.

[0073] If the candidate FIFO number is not (current TS number + number of FIFOs) > candidate FIFO number ≥ current TS number (step S36A: No), the distribution control unit 13D calculates (current TS number mod number of FIFOs). Then, the distribution control unit 13D refers to the buffer management table 33 and determines the FIFO number of the nearest available FIFO 21A from after the calculated (current TS number mod number of FIFOs) (step S44A). Then, the distribution control unit 13D proceeds to the process in step S40.

[0074] In the following third receiving process, steps S39A, S43A, and S44A are performed to determine the FIFO number of the available FIFO21A that stores the received packet. The cases in which each of these processes is executed will now be explained.

[0075] First, let's explain the processing case for step S39A, which determines the FIFO number of the most recent available FIFO 21A from the calculated (candidate FIFO number mod FIFO count). As a premise, we assume that the receiving packet's sending TS number is "1", the insertion delay is "108", the current TS number is "104", the latest FIFO position is "107", the number of FIFOs is "8", and the expected delay is "103" to "106".

[0076] The distribution control unit 13D calculates a candidate FIFO number corresponding to TS number "109" which corresponds to (transmitter TS number "1" + insertion delay "108"). Furthermore, the distribution control unit 13D determines whether the calculated candidate FIFO number "109" is equal to (current TS number "104" + number of FIFOs "8") > candidate FIFO number "109" ≥ current TS number "104". Since the calculated candidate FIFO number "109" is equal to (current TS number + number of FIFOs) > candidate FIFO number ≥ current TS number, the distribution control unit 13D determines whether candidate FIFO number "109" is equal to or greater than the latest FIFO number "107".

[0077] The distribution control unit 13D calculates "5" using candidate FIFO number "109" mod FIFO number "8" because candidate FIFO number "109" is greater than or equal to the latest FIFO number "107". The distribution control unit 13D refers to the buffer management table 33 and determines the FIFO number of the nearest available FIFO 21A from the calculated "5". The distribution control unit 13D stores the received packet in the available FIFO 21A corresponding to the determined FIFO number.

[0078] Then, the switching control unit 24D will output packets from FIFO 21A with FIFO number "0" at the current TS number "104" and mod FIFO count "8".

[0079] Next, we will explain the processing case of step S44A, which determines the FIFO number of the nearest available FIFO 21A from the calculated current TS number modFIFO number onwards. As a premise, we assume that the transmitting TS number of the received packet is "1", the insertion delay is "108", the current TS number is "112", the latest FIFO position is "107", the number of FIFOs is "8", and the expected delay is "103" to "106".

[0080] The distribution control unit 13D calculates a candidate FIFO number corresponding to TS number "109" which is equivalent to (transmitter TS number "1" + insertion delay "108"). Furthermore, the distribution control unit 13D determines whether the calculated candidate FIFO number "109" is equal to (current TS number "112" + number of FIFOs "8") > candidate FIFO number "109" ≥ current TS number "112". Since the calculated candidate FIFO number "109" is not equal to (current TS number + number of FIFOs) > candidate FIFO number ≥ current TS number, the distribution control unit 13D calculates "0" using current TS number "112" mod number of FIFOs "8". The distribution control unit 13D refers to the buffer management table 33 and determines the FIFO number of the nearest available FIFO 21A from the calculated "0". The distribution control unit 13D stores the received packet in the available FIFO 21A corresponding to the determined FIFO number.

[0081] Then, the switching control unit 24D will output the packet in FIFO 21A with FIFO number "0" at the current TS number "112" mod FIFO count "8". As a result, if the arrival of the received packet is later than expected or arrives too early, the receiving packet processing unit 5D will immediately output it by placing it in the current TS's FIFO 21A.

[0082] This section describes the processing case for step S43A, which determines the FIFO number of the nearest available FIFO 21A from the calculated latest FIFO number modFIFO number onwards. As a premise, we assume that the receiving packet's sending TS number is "1", the insertion delay is "108", the current TS number is "104", the latest FIFO position is "110", the number of FIFOs is "8", and the expected delay is "103" to "106".

[0083] The distribution control unit 13D calculates a candidate FIFO number corresponding to TS number "109" which corresponds to (transmitter TS number "1" + insertion delay "108"). Furthermore, the distribution control unit 13D determines whether the calculated candidate FIFO number "109" is greater than or equal to (current TS number "104" + number of FIFOs "8") > candidate FIFO number "109" ≥ current TS number "104". Then, since the calculated candidate FIFO number "109" is greater than or equal to (current TS number "104" + number of FIFOs "8") > candidate FIFO number "109" ≥ current TS number "104", the distribution control unit 13D determines whether candidate FIFO number "109" is greater than or equal to the latest FIFO number "110".

[0084] The distribution control unit 13D determines that an order reversal occurs because candidate FIFO number "109" is not equal to or greater than the latest FIFO number "110". Therefore, the distribution control unit 13D calculates "6" using the latest FIFO number "110" mod FIFO number "8". The distribution control unit 13D refers to the buffer management table 33 and determines the FIFO number "7" of the nearest available FIFO 21A from the calculated "6" onwards. The distribution control unit 13D stores the received packet in the available FIFO 21A corresponding to the determined FIFO number.

[0085] Furthermore, the switching control unit 24D outputs packets from FIFO 21A with FIFO number "0" at the current TS number "104" mod FIFO count "8". As a result, if the insertion delay is slightly reduced due to a setting change (109 → 108), a situation of reversed order may occur where the calculated result is inserted before the latest FIFO position. However, the receiving packet processing unit 5D can avoid this reversed order situation.

[0086] In Embodiment 3, the distribution control unit 13D within the receiving packet processing unit 5D only needs to have a FIFO 21A equivalent to the delay fluctuation of the FIFO group 21X. It calculates the destination FIFO number according to the TS-converted insertion delay, the transmitting TS number of the received packet, and the number of FIFOs, and determines the destination FIFO 21A for the calculated destination FIFO number. As a result, the receiving packet processing unit 5D can adjust the delay and jitter while reducing the number of FIFOs in the FIFO group 21X.

[0087] The distribution control unit 13D calculates a candidate FIFO number using (the transmitting TS number of the received packet + insertion delay). The distribution control unit 13D determines whether the calculated candidate FIFO number satisfies (current TS number + number of FIFOs) > candidate FIFO number ≥ current TS number. If the calculated candidate FIFO number satisfies (current TS number + number of FIFOs) > candidate FIFO number ≥ current TS number, the distribution control unit 13D determines whether the candidate FIFO number is greater than or equal to the latest FIFO number. If the candidate FIFO number is greater than or equal to the latest FIFO number, the distribution control unit 13D determines the nearest available FIFO number from (candidate FIFO number mod number of FIFOs). As a result, the destination FIFO 21A for the received packet can be determined.

[0088] If the calculated candidate FIFO number is not (current TS number + number of FIFOs) > candidate FIFO number ≥ current TS number, the distribution control unit 13D determines the nearest available FIFO number from (current TS number mod number of FIFOs) onwards. As a result, even if the arrival of the received packet is later or earlier than expected, the destination FIFO 21A for the received packet can be determined.

[0089] If the distribution control unit 13D does not have a candidate FIFO number equal to or greater than the latest FIFO number, it determines the nearest available FIFO number from (latest FIFO number mod FIFO number) onwards. As a result, it can determine the destination FIFO 21A for the received packet while avoiding reversal of the order.

[0090] In Example 2, the current TS is synchronized between the transmitting packet processing unit 6A and the receiving packet processing unit 5A using an external synchronization means such as PTP or NTP. However, synchronization may also be performed using the TS attached to the control packet without using an external synchronization means, and such an embodiment will be described below as Example 4. [Examples]

[0091] Figure 16 is an explanatory diagram showing an example of the packet communication system 1B of Embodiment 4. Components identical to those of the packet communication system 1A of Embodiment 2 are denoted by the same reference numerals, and the explanation of their overlapping components and operations is omitted. The packet communication system 1B shown in Figure 16 includes a transmitting device 2, a receiving device 3, a network 4, a transmitting packet processing device 6B, and a receiving packet processing device 5B.

[0092] Figure 17 is an explanatory diagram showing an example of a transmitting packet processing unit 6B. The transmitting packet processing unit 6B shown in Figure 17 includes a current TS management unit 51, a current TS counter 52, a TS information table 54, a TS assignment unit 53, and a time synchronization unit 55. The time synchronization unit 55 synchronizes the current TS with the receiving packet processing unit 5B using the TS number of the control packet from the receiving packet processing unit 5B.

[0093] Figure 18 is an explanatory diagram showing an example of a receiving packet processing device 5B. The packet processing unit 10 in the receiving packet processing device 5B shown in Figure 18 includes a receiving unit 11, a distribution control unit 13, a current TS management unit 14, and a current TS counter 15. The packet processing unit 10 includes a TS information table 31, a delay information table 32, and a buffer management table 33. The receiving unit 11 includes a time synchronization unit 11A. The time synchronization unit 11A synchronizes the current TS with the transmitting packet processing device 6B using the transmitting TS number of the packets from the transmitting packet processing device 6B. The buffering unit 20 in the receiving packet processing device 5B includes a FIFO group 21, a distribution unit 22, a selector 23, and a switching control unit 24.

[0094] The time synchronization unit 11A stores the transmitting TS number in the received packet and the receiving TS number, which is the current TS number of the current TS counter 15, in a control packet and transmits the control packet to the transmitting packet processing unit. The time synchronization unit 55 in the transmitting packet processing unit 6B calculates the TS difference based on the transmitting TS number and the receiving TS number in the control packet and corrects the current TS based on the TS difference.

[0095] Figure 19 is a sequence diagram showing an example of TS synchronization processing. If the current TS number obtained by the TS counter 52 is "3", the transmitting packet processing unit 6B transmits a packet with the transmitting TS number "3" assigned to it to the receiving packet processing unit 5B.

[0096] If the current TS number obtained by the TS counter 15 is "9", the receiving packet processing unit 5B transmits a control packet containing the receiving TS number "3" and the receiving TS number "9" to the transmitting packet processing unit 6B.

[0097] When the transmitting packet processor 6B receives a control packet, it assumes that the current TS counter 52 has acquired the current TS number "7". In this case, the round-trip delay is (7-3)=4TS. Therefore, the one-way delay is (4TS÷2)=2TS. In other words, the one-way delay between the transmitting packet processor 6B and the receiving packet processor 5B is 2TS.

[0098] If the TS number of the transmitting packet processor 6B is "3", then 3 + 2 = 5, and the TS number of the receiving packet processor 5B can be inferred to be "9". In this case, the transmitting packet processor 6B can determine that the current TS of the transmitting side is 4 TS behind the current TS of the receiving side.

[0099] The time synchronization unit 55 in the transmitting packet processing unit 6B can synchronize the current TS with the receiving packet processing unit 5B by adding 4 TS to the current TS number. However, since errors due to delays and other factors may occur if this synchronization process is performed only once, it may be performed multiple times, and the above calculation may be performed from the minimum value (the value with the least impact of delay), and this can be modified as appropriate.

[0100] Figure 20 is a flowchart showing an example of the processing operation of the receiving packet processing device 5B involved in the receiving side synchronization process. In Figure 20, the time synchronization unit 11A within the receiving packet processing device 5B determines whether or not it has received a received packet from the transmitting packet processing device 6B (step S51). If the time synchronization unit 11A has received a received packet (step S51: Yes), it determines whether or not the current number of attempts is less than or equal to the upper limit (step S52).

[0101] If the current number of attempts is less than or equal to the upper limit (step S52: Yes), the time synchronization unit 11A increments the current number of attempts by +1 (step S53). The time synchronization unit 11A obtains the transmitting TS number from the received packet and also obtains the current TS number from the current TS counter 15 (step S54).

[0102] The time synchronization unit 11A obtains the transmitting TS number and the current TS number, inserts the transmitting TS number and the current TS number into the control packet (step S55), and transmits the control packet to the transmitting packet processing unit 6B (step S56). After transmitting the control packet, the time synchronization unit 11A starts a predetermined interval timer (step S57) and determines whether the predetermined interval timer has timed up or not (step S58). If the predetermined interval timer has timed up (step S58: Yes), the time synchronization unit 11A proceeds to step S52, which determines whether the current number of attempts is less than or equal to the upper limit.

[0103] If the time synchronization unit 11A has not received a received packet (step S51: No), it terminates the processing operation shown in Figure 20. If the current number of attempts is not less than or equal to the upper limit (step S52: No), the time synchronization unit 11A terminates the processing operation shown in Figure 20. Also, if the predetermined interval timer has not timed up (step S58: No), the time synchronization unit 11A proceeds to the processing in step S58 to determine whether or not the predetermined interval timer has timed up.

[0104] Figure 21 is a flowchart showing an example of the processing operation of the transmitting packet processing device 6B involved in the transmitting synchronization process. In Figure 21, the time synchronization unit 55 in the transmitting packet processing device 6B determines whether or not it has received a control packet from the receiving packet processing device 5B (step S61).

[0105] When the time synchronization unit 55 receives a control packet (step S61: Yes), it obtains the transmitting TS number and the receiving TS number from the control packet (step S62). In the example in Figure 19, the transmitting TS number is "3" and the receiving TS number is "9". The time synchronization unit 55 obtains the current TS number from the current TS counter 52 (step S63). In the example in Figure 19, the current TS number is "7".

[0106] The time synchronization unit 55 calculates the one-way delay based on ((current TS number - transmitting TS number) ÷ 2) (step S64). In other words, the time synchronization unit 55 calculates the one-way delay of 2 TS based on ((7 - 3) ÷ 2). The time synchronization unit 55 calculates the transmitting delay based on (receiving TS number - (one-way delay + transmitting TS number)) (step S65). In other words, the time synchronization unit 55 calculates the transmitting delay of 4 TS based on (9 - (2 + 3)).

[0107] The time synchronization unit 55 adds the transmitting delay to the next current TS number to synchronize the time (step S66), and then terminates the processing operation shown in Figure 21. Then, the time synchronization unit 55 adds the transmitting delay of 4TS to the current TS number to synchronize with the current TS of the receiving packet processing unit 5B.

[0108] If the time synchronization unit 55 does not receive a control packet (step S61: No), it terminates the processing operation shown in Figure 21.

[0109] In Embodiment 4, when the transmitting packet processor 6B transmits a packet to the receiving packet processor 5B, it transmits a packet containing the transmitting TS number, which is the current TS number, to the receiving packet processor 5B. When the receiving packet processor 5B receives a packet from the transmitting packet processor 6B, it extracts the transmitting TS number from the packet and obtains the receiving TS number as the current TS number. The receiving packet processor 5B transmits a control packet containing the transmitting TS number and the receiving TS number to the transmitting packet processor 6B. When the transmitting packet processor 6B receives the control packet, it extracts the current TS number and extracts the transmitting TS number and the receiving TS number from the control packet. Based on the transmitting TS number, the receiving TS number, and the current TS number, the transmitting packet processor 6B corrects the current TS number that it counts. As a result, TS synchronization between the transmitting packet processor 6B and the receiving packet processor 5B can be ensured without using an external synchronization means.

[0110] In the packet communication system 1A of Example 2, the example shown was the case where packets are transmitted between the transmitting packet processing unit 6A and the receiving packet processing unit 5A via network 4. However, an embodiment of a redundant configuration in which packets are transmitted between the transmitting packet processing unit 6A and the receiving packet processing unit 5A via the 0-system path of the first network 4A and the 1-system path of the second network 4B is described below as Example 5. In this example, components identical to those in the packet communication system 1A of Example 2 are denoted by the same reference numerals, and the explanation of their overlapping components and operations is omitted. [Examples]

[0111] Figure 22 is an explanatory diagram showing an example of the packet communication system 1C of Embodiment 5. The packet communication system 1C shown in Figure 22 includes a transmitting device 2, a receiving device 3, a transmitting packet processing device 6C, a receiving packet processing device 5C, a first network 4A, and a second network 4B.

[0112] The transmitting packet processing unit 6C is connected to the receiving packet processing unit 5C via a route 0 of the first network 4A, and also via a route 1 of the second network 4B, which is different from the first network 4A.

[0113] Figure 23 is an explanatory diagram showing an example of a transmitting packet processing unit 6C. The transmitting packet processing unit 6C shown in Figure 23 has an SN (Sequence Number) counter 61, an SN assignment unit 62, and a packet copy unit 63. The SN counter 61 counts the SNs that identify the sequential numbers of packets in the same flow. The SN assignment unit 62 assigns an SN to a packet when it is sent to the receiving packet processing unit 5C. The packet copy unit 63 copies the packets with the assigned SNs and transmits them via the 0-series path of the first network 4A and via the 1-series path of the second network 4B. The receiving packet processing unit 5C can recognize that the packets are the same based on the flow ID and SN in the packets received via the 0-series path of the first network 4A and the flow ID and SN in the packets received via the 1-series path of the second network 4B.

[0114] Figure 24 is an explanatory diagram showing an example of the table configuration of the SN counter 61. The SN counter 61 shown in Figure 24 manages the current SN61B for each flow ID 61A. The SN assignment unit 62 refers to the current SN61B corresponding to the flow ID 61A in the SN counter 61 and assigns an SN to the packet.

[0115] Figure 25 is an explanatory diagram showing an example of a receiving-side packet processing unit 5C. The packet processing unit 10 within the receiving-side packet processing unit 5C shown in Figure 25 includes an SN management unit 11C, a distribution control unit 13, a current TS management unit 14, and a current TS counter 15 within the receiving unit 11. The packet processing unit 10 includes a TS information table 31, a delay information table 32, a buffer management table 33, and an SN management table 34. When the SN management unit 11C receives a first received packet from a route 0 of the first network 4A, it obtains the flow ID and SN of the first received packet. The SN management unit 11C also obtains the flow ID and SN of a second received packet when it receives a second received packet from a route 1 of the second network 4B. The SN management unit 11C identifies the first-arriving packet and the second-arriving packet, which are received later than the first-arriving packet, from among identical packets received from routes 0 and 1, respectively.

[0116] Figure 26 is an explanatory diagram showing an example of the table structure of the SN management table 34. The SN management table 34 shown in Figure 26 manages the expected SN 34B and missing SN information 34C for each flow ID 34A. The expected SN 34B is the SN of the next packet to be received. The missing SN information 34C contains the SN of the missing preceding packet and the FIFO number of the FIFO 21A that the preceding packet should have stored. The SN management unit 11C refers to the SN management table 34 and recognizes the expected SN and missing SN for each flow ID 34A. For flow ID #1, the SN management unit 11C recognizes the expected SN "16", the missing SNs "8~12", and the FIFO numbers "TS3". The SN management unit 11C refers to the SN management table 34 and can recognize the SN to be expected to be received next, the SN of the preceding packet with the same SN that is missing and needs to be filled in by a subsequent packet with the same SN, and the FIFO number for buffering that packet.

[0117] The SN management unit 11C within the receiving unit 11 measures the packet delay difference of the same SN between a 0-series path via the first network 4A and a 1-series path via the second network 4B for each flow ID identified by a VLAN ID, etc. When the number of delay difference samples in the SN management unit 11C reaches a predetermined number of samples, it calculates the delay difference of the flow by adding a predetermined margin to the maximum delay difference among the delay differences of the predetermined number of samples. For example, if the predetermined number of samples is 100 and the delay differences are in the range of 4.2 to 4.8 milliseconds, the SN management unit 11C calculates the insertion delay of the flow as 5 milliseconds, which is the maximum delay difference of 4.8 milliseconds plus a predetermined margin, for example, 0.2 milliseconds.

[0118] The SN management unit 11C then converts the delay difference obtained for each flow into TS units and calculates the TS-converted delay difference for that flow as the insertion delay. Specifically, if 1 TS = 0.1 ms and the delay difference of the flow is 5 ms, the insertion delay, which is the TS-converted delay difference, will be 50 TS. The SN management unit 11C then calculates the insertion delay, which is the TS-converted delay difference for that flow, and stores the calculated insertion delay in the delay information table 32 for each flow ID that identifies that flow.

[0119] Figure 27 is an explanatory diagram illustrating an example of the buffering operation of the receiving packet processing unit 5C. The receiving packet processing unit 5C at site B is connected to the transmitting packet processing unit 6C in the transmitting device 2C1 at site A, to the 0-series path of the first network 4A and the 1-series path of the second network 4B. The receiving packet processing unit 5C is also connected to the transmitting packet processing unit 6C in the transmitting device 2C2 at site C, to the 0-series path of the first network 4A and the 1-series path of the second network 4B.

[0120] The receiving packet processing unit 5C assumes that when using the 0-series path, it receives packets of flow #1 from the transmitting device 2C1 at site A in 0 milliseconds, and when using the 1-series path, it receives packets of flow #1 from the transmitting device 2C1 at site A in 5 milliseconds. In other words, among the packets from the transmitting device 2C1 at site A, packets from the 0-series path are considered first-arriving packets, and packets from the 1-series path are considered later-arriving packets. The packet delay of flow #1 between the transmitting device 2C1 at site A and the 1-series path is 5 milliseconds compared to the 0-series path. For example, if 1 TS = 0.1 milliseconds, the 5-millisecond delay difference for flow #1 is 50 TS. The delay information table 32 then stores, for example, "a delay of +50 TS on the 0-series path" as the insertion delay for flow #1.

[0121] The receiving packet processing unit 5C assumes that when using the 0-system route, it receives packets of flow #2 from the transmitting device 2C2 at site C in 4 ms, and when using the 1-system route, it receives packets of flow #2 from the transmitting device 2C2 at site C in 1 ms. In other words, among the packets from the transmitting device 2C2 at site C, packets from the 0-system route are considered late packets, and packets from the 1-system route are considered early packets. The packet delay of flow #2 between the transmitting device 2C2 at site C and the 0-system route is 3 ms compared to the 1-system route. In other words, the delay difference of 3 ms for flow #2 is 30 TS. The delay information table 32 then stores, for example, "+30 TS delay on the 1-system route" as the insertion delay of flow #1.

[0122] The distribution control unit 13, upon receiving the first packet of flow #1 from the 0-series path and confirming that the current TS number is TS1, refers to the insertion delay of flow #1 in the delay information table 32 and calculates TS1 + 50TS = TS51 as the TS number corresponding to the destination FIFO number. The distribution control unit 13 controls the distribution unit 22 to distribute the first packet of flow #1 to an available FIFO 21A corresponding to the calculated FIFO number of TS51.

[0123] Furthermore, when the first packet of flow #2 arrives from the route of system 1, the distribution control unit 13 refers to the insertion delay of flow #2 in the delay information table 32 and calculates TS1 + 30TS = TS31 as the TS number corresponding to the FIFO number of the distribution destination. The distribution control unit 13 controls the distribution unit 22 to distribute the first packet of flow #2 to an available FIFO 21A corresponding to the FIFO number of the calculated TS31.

[0124] The switching control unit 24 controls the selector 23 to sequentially switch the FIFO 21A to be read from among the multiple FIFO 21A assigned TS numbers, in order of TS number at predetermined intervals of TS, for example, every 1 millisecond.

[0125] The distribution control unit 13 refers to the delay information table 32 and distributes the received packets of the flow to an available FIFO 21A among the multiple FIFOs 21A with a FIFO number corresponding to the insertion delay of the flow.

[0126] Figure 28 is a flowchart showing an example of the processing operation of the receiving packet processing device 5C involved in the fourth receiving process. In Figure 28, the SN management unit 11C within the receiving unit 11 of the receiving packet processing device 5C determines whether or not a received packet has been received (step S71). If the SN management unit 11C has received a received packet (step S71: Yes), it obtains the flow ID, received TS number, and SN from the received packet (step S72).

[0127] Furthermore, the distribution control unit 13 obtains the current TS number from the current TS counter 15 (step S73). The distribution control unit 13 refers to the delay information table 32 and obtains the insertion delay 32B and the latest FIFO number 32C corresponding to the flow ID 32A (step S74). The distribution control unit 13 determines whether the received packet is a first-arriving packet or not (step S75).

[0128] If the received packet is a first-arriving packet (step S75: Yes), the distribution control unit 13 determines whether the SN of the received packet is the expected SN (step S76). If the SN of the received packet is the expected SN (step S76: Yes), the distribution control unit 13 calculates a candidate FIFO number corresponding to a TS number equivalent to (current TS number + insertion delay) (step S77). The distribution control unit 13 determines whether the calculated candidate FIFO number is greater than or equal to the latest FIFO number (step S78).

[0129] If the candidate FIFO number is greater than or equal to the latest FIFO number (step S78: Yes), the distribution control unit 13 refers to the buffer management table 33 and obtains the FIFO number of the nearest available FIFO 21A from the candidate FIFO number (step S79). The distribution control unit 13 stores the received packet in the available FIFO 21A corresponding to the obtained FIFO number (step S80). Furthermore, the distribution control unit 13 adds the packet length of the received packet to the queue length of the FIFO 21A where the received packet is stored and updates the contents of the buffer management table 33 (step S81). Finally, the distribution control unit 13 updates the contents of the delay information table 32 with the FIFO number of the FIFO 21A where the received packet is stored as the latest FIFO number (step S82), and terminates the processing operation shown in Figure 28.

[0130] If the distribution control unit 13 finds that the candidate FIFO number is not equal to or greater than the latest FIFO number (step S78: No), it refers to the buffer management table 33. Then, the distribution control unit 13 obtains the FIFO number of the nearest available FIFO 21A from the latest FIFO number onward (step S83) and proceeds to the process in step S80.

[0131] If the distribution control unit 13 has not received a received packet (step S71: No), it terminates the processing operation shown in Figure 28.

[0132] If the received packet is not the first-arriving packet (step S75: No), the distribution control unit 13 determines that the received packet is a later-arriving packet and determines whether or not there are any missing packets in the first-arriving packet (step S86). If there are missing packets in the first-arriving packet (step S86: Yes), the distribution control unit 13 stores the later-arriving packet in the FIFO 21A with the missing SN (step S87) and proceeds to the processing in step S81.

[0133] If there are no missing packets in the first packet to arrive (step S86: No), the distribution control unit 13 discards the next packet (step S88) and terminates the processing operation shown in Figure 28.

[0134] Furthermore, if the SN of the received packet is not the expected SN (step S76: No), the distribution control unit 13 determines that the received packet is missing (step S84). Then, the distribution control unit 13 discards the received packet until the next switching timing of the selector 23 (step S85), and terminates the processing operation shown in Figure 28.

[0135] The distribution control unit 13 calculates a candidate FIFO number using (current TS number + insertion delay) if the received packet is the first-arriving packet and the received packet's SN is the expected SN. The distribution control unit 13 determines whether the candidate FIFO number is greater than or equal to the latest FIFO number. If the candidate FIFO number is greater than or equal to the latest FIFO number, the distribution control unit 13 determines the nearest available FIFO number from the candidate FIFO number. As a result, the destination FIFO 21A for the first-arriving packet can be determined.

[0136] If the distribution control unit 13 is not equal to or greater than the latest FIFO number, it determines the nearest available FIFO number from the latest FIFO number onward. As a result, it can determine the destination FIFO 21A for the first arriving packet.

[0137] The distribution control unit 13 stores the later-arriving packet in the FIFO 21A containing the missing signal identifier (SN) if there are missing packets in the later-arriving packet or the earlier-arriving packet. As a result, even if there are missing packets in the earlier-arriving packet, they can be compensated for by the later-arriving packet.

[0138] The distribution control unit 13 discards the later-arriving packet if there are no missing packets in the later-arriving or earlier-arriving packets of the received packet. As a result, the storage of duplicate packets can be suppressed.

[0139] Figure 29 is a flowchart showing an example of the processing operation of the receiving packet processing device 5C involved in the expected SN update process. The SN management unit 11C within the receiving packet processing device 5C determines whether it is currently the switching timing for selector 23 (step S91). If it is currently the switching timing (step S91: Yes), the SN management unit 11C increments the current SN of the received packet by +1 to update the expected SN in the SN management table 34 (step S92), and then terminates the processing operation shown in Figure 29.

[0140] If the SN management unit 11C does not currently have a switching timing (step S91: No), it terminates the processing operation shown in Figure 29.

[0141] Here, in order to compare with the packet communication system 1C of Example 5, the packet communication system 200 of Comparative Example 1 and the packet communication system 100 of Comparative Example 2 will be described. Figure 30 is an explanatory diagram showing an example of the packet communication system 200 of Comparative Example 1. The packet communication system 200 shown in Figure 30 has a transmitting device 201 at site A, a receiving device 202 at site B, a first network 203A, and a second network 203B. The first network 203A and the second network 203B are provided between the transmitting device 201 and the receiving device 202 for redundancy. The transmitting device 201 copies packets and transmits them to the receiving device 202 via the first network 203A and also via the second network 203B.

[0142] The receiving device 202 includes a first adjustment buffer 202A, a second adjustment buffer 202B, and a selector 202C. The first adjustment buffer 202A is a delay adjustment buffer connected to the first network 203A and buffers received packets from the first network 203A. The second adjustment buffer 202B is a delay adjustment buffer connected to the second network 203B and buffers received packets from the second network 203B. The selector 202C selects and outputs received packets from the adjustment buffers, either the first adjustment buffer 202A or the second adjustment buffer 202B.

[0143] The transmitting device 201 copies the packet and sends it to the receiving device 202, for example, using the first network 203A and the second network 203B. The receiving device 202 then selects one packet from the packets received on the first network 203A and the second network 203B, respectively. In addition, to compensate for the delay difference between the first network 203A and the second network 203B, the receiving device 202 adjusts the delay on a per-path basis by making the packet received on the path that arrives first wait by the amount of delay.

[0144] Figures 31A, 31B, and 31C are explanatory diagrams showing an example of the buffering state in Comparative Example 1. In the packet communication system 200 of Comparative Example 1, a first adjustment buffer 202A and a second adjustment buffer 202B are prepared at each site, which increases the amount of memory used for the adjustment buffers used for delay adjustment. However, since it is unknown at each site which of the 0 / 1 paths will arrive first, adjustment buffers are required for both paths.

[0145] For example, consider a scenario where, in a 10 Gbps ring, we want to absorb a delay difference of up to 1000 km (5 ms) between the path 0 and the path 1 between the transmitter 201 and the receiver 202.

[0146] In the receiving device 202, as shown in Figure 31A, for example, if the path of system 0 is approximately 0 km and the path of system 1 is approximately 1000 km, and packets on the path of system 0 arrive first, then the second adjustment buffer 202B connected to the path of system 1 does not need a buffer. However, the first adjustment buffer 202A connected to the path of system 0 requires a 50-megabit buffer.

[0147] Furthermore, in the receiving device 202, as shown in Figure 31B, for example, if the path of system 1 is approximately 0 km and the path of system 0 is approximately 1000 km, and packets from system 1 arrive first, the first adjustment buffer 202A connected to the path of system 0 does not need a buffer. However, the second adjustment buffer 202B connected to the path of system 1 requires a 50 Mbit buffer.

[0148] In other words, in the packet communication system 200, it is impossible to know which packet will arrive first, the one on the 0-series path or the 1-series path, depending on the relative positions of the transmitting device 201 and the receiving device 202. Therefore, the receiving device 202 requires a 50Mbit adjustment buffer for both the 0 and 1-series paths.

[0149] In contrast, in the receiving packet processing device 5C of Example 5, if the first arriving packet is stored in the corresponding FIFO 21A, the distribution control unit 13 preceding the FIFO 21A discards the subsequent arriving packet. As a result, only packets from either the 0-series route or the 1-series route are buffered, allowing the FIFO 21A to be shared between the 0-series route and the 1-series route.

[0150] Figure 32 is an explanatory diagram showing an example of a packet communication system 100 of Comparative Example 2. The packet communication system 100 shown in Figure 32 includes a transmitting device 101A at site A, a transmitting device 101B at site C, a receiving device 102 at site B, a first network 103A, and a second network 103B.

[0151] The receiving device 102 includes a first adjustment buffer 102A, a second adjustment buffer 102B, a third adjustment buffer 102C, a fourth adjustment buffer 102D, and a selector 102E. The first adjustment buffer 102A is a delay adjustment buffer connected to the first network 103A and buffers received packets from the first network 103A. The second adjustment buffer 102B is a delay adjustment buffer connected to the second network 103B and buffers received packets from the second network 103B. The third adjustment buffer 102C is a delay adjustment buffer connected to the first network 103A and buffers received packets from the first network 103A. The fourth adjustment buffer 102D is a delay adjustment buffer connected to the second network 103B and buffers received packets from the second network 103B. The selector 102E selects and outputs received packets from among the adjustment buffers: the first adjustment buffer 102A, the second adjustment buffer 102B, the third adjustment buffer 102C, and the fourth adjustment buffer 102D.

[0152] Figures 33A, 33B, and 33C are explanatory diagrams showing an example of the buffering state in Comparative Example 2. The first transmission time from the time a received packet from the transmitter 101A at site A is received by the receiver 102 at site B via the first network 103A is 8 milliseconds. The second transmission time from the time a received packet from the transmitter 101B at site C is received by the receiver 102 at site B via the second network 103B is 3 milliseconds.

[0153] As shown in Figure 33A, for example, between the transmitter 101 at site A and the receiver 102 at site B, the path of the first network 103A (system 0) is approximately 0 km (0 m seconds), and the path of the second network 103B (system 1) is approximately 1000 km (5 m seconds). At the receiver 102 at site B, the first adjustment buffer 102A is not used, and a 5 m second delay is introduced using the second adjustment buffer 102B.

[0154] As shown in Figure 33B, for example, the path of the first network 103A (system 0) from the transmitter 101 at site C to the receiver 102 at site B is approximately 800 km (4 ms), and the path of the second network 103B (system 1) is approximately 200 km (1 ms). At the receiver 102 at site B, the third adjustment buffer 102C is not used, and a 3 ms delay is introduced using the fourth adjustment buffer 102D.

[0155] As shown in Figure 33C, at the receiving device 102 at site B, the waiting time and delay adjustment time differ for the path from site A to site B and the path from site C to site B. Therefore, a delay adjustment buffer must be prepared for each site. Moreover, at the receiving device 102 at site B, 10 gigabits of traffic can arrive instantaneously, so a 50 megabit adjustment buffer is required for each path. In other words, in the packet communication system 100, the amount of delay differs from site to site, so the adjustment buffer cannot be shared between sites, and an adjustment buffer is required for each site.

[0156] In contrast, the receiving packet processing device 5C of Example 5 only needs to distribute the first-arriving packets to the FIFO21A with a FIFO number that reflects the insertion delay. As a result, the FIFO21A of the transmitting device 2 at all locations can be shared without having to set up a separate FIFO21A for each location.

[0157] The receiving packet processing unit 5C of Embodiment 5 manages the insertion delay according to the packet delay difference between the first network 4A and the second network 4B when receiving packets with the same SN from the first network 4A and the second network 4B, respectively. When the distribution control unit 13 receives a packet with the same SN from the first network 4A or the second network 4B, it calculates the destination TS number (FIFO number) according to the insertion delay of the flow to which the packet belongs. The distribution control unit 13 determines the FIFO 21A of the calculated destination FIFO number from the FIFO group 21 as the destination FIFO 21A. The distribution unit 22 distributes the first arriving packets from the packets received from the first network 4A and the second network 4B to the destination FIFO 21A. As a result, jitter and delay can be adjusted while all locations share the FIFO 21A, not only for the 0-series and 1-series routes. Compared to Comparative Examples 1 and 2, significant reductions are possible by sharing FIFO21A.

[0158] The distribution control unit 13 calculates the destination FIFO number based on the TS number and SN of each received packet, and the flow ID insertion delay corresponding to the packet delay difference between the first network 4A and the second network 4B. Based on the calculated destination FIFO number, the distribution control unit 13 distributes the first arriving packets with the same flow ID, the same TS number, and the same SN to the destination FIFO 21A. As a result, the first arriving packets with the same SN can be distributed from the shared FIFO group 21.

[0159] The distribution control unit 13 stores the first arriving packet with the same flow ID, same TS number, and same SN in the destination FIFO 21A, and then discards the subsequent arriving packet if it receives a subsequent packet with the same flow ID, same TS number, and same SN. As a result, the storage of duplicate packets in the FIFO can be suppressed.

[0160] The distribution control unit 13 assumes that the first packet with the same flow ID, same TS number, and same SN is missing, and that a subsequent packet with the same flow ID, same TS number, and same SN is received. In this case, the distribution control unit 13 distributes the subsequent packet to the destination FIFO 21A based on the calculated destination FIFO number. As a result, even if the first packet is missing, it can be compensated for by the subsequent packet.

[0161] Furthermore, the packet processing device 5 of this embodiment can be applied to relay devices that perform packet processing, such as Ethernet switches and routers, or to terminal devices that send and receive packets, such as PCs and servers.

[0162] In the above embodiment, the distribution control unit 13, the current TS counter 15, and the current TS management unit 14 are located in the packet processing unit 10. However, for example, the distribution control unit 13, the current TS counter 15, and the current TS management unit 14 may be located inside an FPGA or CPU (not shown), and this can be changed as appropriate.

[0163] Furthermore, the components of each part shown in the diagram do not necessarily have to be physically configured as depicted. In other words, the specific forms of distribution and integration of each part are not limited to those shown in the diagram, and all or part of them can be functionally or physically distributed and integrated in any unit according to various loads, usage conditions, etc.

[0164] Furthermore, the various processing functions performed by each device may be executed in whole or in part on a CPU (Central Processing Unit) (or a microcomputer such as an MPU (Micro Processing Unit) or MCU (Micro Controller Unit)). It goes without saying that the various processing functions may also be executed in whole or in part on a program analyzed and executed by the CPU (or a microcomputer such as an MPU or MCU), or on wired logic hardware.

[0165] Furthermore, the various processes described in this embodiment can be realized by having a pre-prepared program executed by a processor such as a CPU within the information processing device.

[0166] Furthermore, the following additional information is disclosed regarding the above embodiments.

[0167] (Note 1) A packet processing device having a packet processing unit for processing received packets and a buffering unit for storing received packets, The buffering unit is, Multiple buffers for storing each of the received packets, A selector for selecting the buffer that outputs the packet, The system includes a switching control unit that controls the selector to sequentially switch between the buffers from which to read from the plurality of buffers, The packet processing unit, The distribution control unit, upon receiving the aforementioned packet, determines the destination buffer based on the insertion delay amount for each flow to which the packet belongs. A packet processing device characterized by the following features.

[0168] (Note 2) The switching control unit is, The selector is controlled at a constant period to sequentially switch the buffers, The distribution control unit, Furthermore, the packet processing device according to Appendix 1 is characterized in that it determines the destination buffer based on the constant period of the selector.

[0169] (Note 3) The distribution control unit is, The packet processing device according to Appendix 1, characterized in that it distributes the time selected and read by the selector to a buffer corresponding to a timing that is later by the amount of the insertion delay for each flow.

[0170] (Note 4) The distribution control unit is, The packet processing device according to Appendix 1, characterized in that it extracts time information from a received packet and determines the destination buffer for distribution according to the extracted time information and the insertion delay amount.

[0171] (Note 5) The distribution control unit is, The packet processing device according to Appendix 1, characterized in that it extracts time information from a received packet and determines the destination buffer according to the extracted time information, the insertion delay amount, and the number of buffers.

[0172] (Note 6) The packet processing unit is, The system has a first path for transmitting the packets from the opposing device, and a second path different from the first path, and a management unit that acquires flow identification information, time information, and sequence number of the packets received from the first path and the second path, respectively. The distribution control unit, The packet processing device according to Appendix 1, characterized in that it determines the destination buffer for distribution based on information regarding the time of packets of the same sequence number received from the first route and the second route, respectively, and the amount of insertion delay of the flow identification information corresponding to the packet delay difference between the first route and the second route.

[0173] (Note 7) The buffer mentioned above is The packet processing device according to Appendix 1, characterized in that it is a FIFO for storing the aforementioned packets.

[0174] (Note 8) The distribution control unit is, The packet processing device according to Appendix 6, characterized in that, based on the determined destination buffer, it distributes the first-arriving packets with the same flow identification information, the same time information, and the same sequence number from the packets received from the first route and the second route, respectively, to the destination buffer.

[0175] (Note 9) The distribution control unit is, The packet processing device according to Appendix 8, characterized in that, after storing the first-arriving packet in the buffer of the distribution destination, if a later-arriving packet is received from the first route and the second route, respectively, that packet has the same flow identification information, the same time information, and the same sequence number, the later-arriving packet is discarded.

[0176] (Note 10) The distribution control unit is The packet processing device according to Appendix 8, characterized in that, when the aforementioned first-arriving packet is missing, and a subsequent-arriving packet with the same flow identification information, the same time information, and the same sequence number is received from the first route and the second route respectively, the subsequent-arriving packet is distributed to the distribution destination buffer based on the determined distribution destination buffer.

[0177] (Note 11) A packet communication system having a transmitting-side packet processing device connected to a transmitting device and a receiving-side packet processing device connected to a receiving device, The receiving packet processing unit, It comprises a packet processing unit that processes packets received from the transmitting packet processing unit, and a buffering unit that stores and processes the received packets. The buffering unit is, Multiple buffers for storing each of the received packets, A selector for selecting the buffer that outputs the packet, The system includes a switching control unit that controls the selector to sequentially switch between the buffers from which to read from the plurality of buffers, The packet processing unit, The distribution control unit, upon receiving the aforementioned packet, determines the destination buffer based on the insertion delay amount for each flow to which the packet belongs. A packet communication system characterized by the following features.

[0178] (Note 12) After synchronizing the current time information between the transmitting packet processing device and the receiving packet processing device, The transmitting packet processing unit is: When transmitting the packet to the receiving packet processing device, the packet containing information about the current first time is transmitted. The receiving packet processing unit, The packet communication system according to Appendix 11, characterized in that, when the packet is received from the transmitting packet processing device, the receiving packet processing device corrects the current second time information counted by the receiving packet processing device based on the first time information in the packet.

[0179] (Note 13) The transmitting packet processing device is: When transmitting the packet to the receiving packet processing device, the packet containing information about the current first time is transmitted to the receiving packet processing device. The receiving packet processing unit, When the packet is received from the transmitting packet processing device, information regarding the first time is extracted from the packet, and information regarding the current second time is obtained. A control packet containing the information regarding the first time and the information regarding the second time is transmitted to the transmitting packet processing device. The transmitting packet processing unit is: When the control packet is received, information regarding the current third time is obtained, and the information regarding the first time and the information regarding the second time within the control packet are extracted. The packet communication system according to Appendix 12, characterized in that it corrects the current time information counted by the transmitting packet processing unit based on the first time information, the second time information, and the third time information.

[0180] (Note 14) A packet processing circuit in a packet processing device having a buffering unit comprising: a plurality of buffers for storing each received packet; a selector for selecting a buffer for outputting the packet; and a switching control unit for controlling the selector to sequentially switch the buffer from which to read the packet. The distribution control unit, upon receiving the aforementioned packet, determines the destination buffer based on the insertion delay amount for each flow to which the packet belongs. A packet processing circuit characterized by the following features.

[0181] (Note 15) A packet processing device having a packet processing unit for processing received packets and a buffering unit for storing received packets, wherein the buffering unit has a plurality of buffers for storing each of the received packets, a selector for selecting a buffer for outputting the packets, and a switching control unit for controlling the selector to sequentially switch the buffer from which to read the packets, When the aforementioned packet is received, the destination buffer is determined based on the insertion delay amount for each flow to which the packet belongs. A packet processing method characterized by performing processing. [Explanation of symbols]

[0182] 1. Packet communication system 2 Transmitter 3. Receiving device 4 Network 4A First Network 4B Second Network 5. Packet Processing Unit 5A, 5B, 5C Receiver-side packet processing unit 6A, 6B, 6C Transmitter-side packet processing unit 11 Receiving unit 11A Time synchronization part 11C SN Management Department 13 Distribution Control Unit 15 Current TS counter 21 FIFO group 21A FIFO 22 Sorting section 23 Selector 24 Switching Control Unit 32 Delay Information Table 55 Time Synchronization Section

Claims

1. A packet processing device having a packet processing unit for processing received packets and a buffering unit for storing and processing received packets, The buffering unit is, Multiple buffers for storing each of the received packets, A selector for selecting the buffer that outputs the packet, The system includes a switching control unit that controls the selector to sequentially switch between the buffers from which to read from the plurality of buffers, The packet processing unit, The distribution control unit, upon receiving the aforementioned packet, determines the destination buffer based on the insertion delay amount for each flow to which the packet belongs. A packet processing device characterized by the following features.

2. The switching control unit described above, The selector is controlled at a constant period to sequentially switch the buffers, The distribution control unit, Furthermore, the packet processing device according to claim 1 is characterized in that it determines the destination buffer based on the constant period of the selector.

3. The distribution control unit, The time selected and read by the aforementioned selector is allocated to the buffer corresponding to the timing that is later by the amount of the insertion delay for each flow. The packet processing device according to feature 1.

4. The distribution control unit, The system extracts time information from the received packet and determines the destination buffer based on the extracted time information and the insertion delay amount. The packet processing device according to feature 1.

5. The distribution control unit, The system extracts time information from the received packet and determines the destination buffer based on the extracted time information, the insertion delay amount, and the number of buffers. The packet processing device according to feature 1.

6. The packet processing unit, The system has a first path for transmitting the packets from the opposing device, and a second path different from the first path, and a management unit that acquires flow identification information, time information, and sequence number of the packets received from the first path and the second path, respectively. The distribution control unit, The packet processing device according to claim 1, characterized in that it determines the destination buffer based on information regarding the time of packets of the same sequence number received from the first route and the second route, respectively, and the amount of insertion delay of the flow identification information corresponding to the packet delay difference between the first route and the second route.

7. The distribution control unit, Among the packets received from the first route and the second route, the first packet to arrive among those having the same flow identification information, the same time information, and the same sequence number is distributed to the distribution buffer. In packets received from the first and second routes respectively, the later-arriving packet is discarded if it has the same flow identification information, the same time information, and the same sequence number. The packet processing device according to feature 6.

8. The distribution control unit, The packet processing device according to claim 7, characterized in that, when the aforementioned first-arriving packet is missing, and a subsequent-arriving packet with the same flow identification information, the same time information, and the same sequence number is received from the first route and the second route respectively, the subsequent-arriving packet is distributed to the distribution destination buffer based on the determined distribution destination buffer.

9. A packet processing circuit within a packet processing device having a buffering unit comprising: a plurality of buffers for storing each received packet; a selector for selecting a buffer for outputting the packets; and a switching control unit for controlling the selector to sequentially switch the buffer from which to read the packets, The distribution control unit, upon receiving the aforementioned packet, determines the destination buffer based on the insertion delay amount for each flow to which the packet belongs. A packet processing circuit characterized by the following features.

10. A packet processing device comprising a packet processing unit for processing received packets, and a buffering unit for storing received packets, wherein the buffering unit comprises a plurality of buffers for storing each of the received packets, a selector for selecting a buffer for outputting the packets, and a switching control unit for controlling the selector to sequentially switch the buffer from which to read the packets, When the aforementioned packet is received, the destination buffer is determined based on the insertion delay amount for each flow to which the packet belongs. A packet processing method characterized by performing processing.

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