Neuronal circuit, and method for driving the neuronal circuit

Abstract

Increase the number of inputs to the neuron circuit. [Solution] The neuron circuit 100 includes a first switch (switch SW1), a plurality of capacitive elements C1 to C3 to which a predetermined reference potential is applied to one end electrode when the first switch is connected, and a plurality of second switches (switches SW21 to SW23) to which an independent first set of input signals (inhibitory input voltages Va1 to Va3) is applied when the first switch is connected, and an independent second set of input signals (excitatory input voltages Vb1 to Vb3) is applied when the first switch is disconnected, to the other end electrodes of the capacitive elements C1 to C3.

Description

【Technical Field】 【0001】 The present invention relates to a neuron circuit that operates by mimicking neurons, and a method for driving the neuron circuit. 【Background Art】 【0002】 Conventionally, there is known a neuron MOS transistor that has a floating gate and a plurality of input coupling electrodes capacitively coupled to the floating gate, calculates a weighted average of input signals of the plurality of input coupling electrodes at the floating gate level, and controls the on / off of a transistor based on the result (see, for example, Patent Document 1). 【Prior Art Documents】 【Patent Documents】 【0003】 【Patent Document 1】 Japanese Patent Application Laid-Open No. 7-161942 【Summary of the Invention】 【Problems to be Solved by the Invention】 【0004】 In the neuron MOS transistor as described above, it is necessary to provide input coupling electrodes for the number of input signals, and the circuit area tends to increase. Therefore, it has been difficult to increase the number of input signals. 【0005】 The present invention has been made in view of the above points, and an object thereof is to make it possible to easily increase the number of inputs of a neuron circuit. 【Means for Solving the Problems】 【0006】 In order to achieve the above object, the present invention a first switch, a plurality of capacitive elements to which a predetermined reference potential is applied to one end side electrode, respectively, when the first switch is in a connected state, When the first switch is connected, an independent first set of input signals is connected to the other end electrode of each of the capacitive elements, When the first switch described above is in the off state, a plurality of second switches connect an independent second set of input signals to the other end electrode of each of the capacitive elements, It is characterized by having the following features. 【0007】 Also, The first switch, When the first switch described above is connected, a plurality of sets of capacitance elements are formed, each of which has a predetermined reference potential applied to one end electrode of the respective capacitance element. When the first switch is connected, for each set of capacitive elements, an independent set of input signals is connected to the other end electrode of the capacitive element selected according to the coupling load, and a predetermined coupling load zero potential is connected to the other end electrode of the other capacitive elements. When the first switch described above is in the off state, a plurality of second switches connect an independent second set of input signals to the other end electrode of the capacitive element selected according to the coupling load for each set of capacitive elements, and connect the coupling load zero potential to the other end electrode of other capacitive elements. It is characterized by having the following features. 【0008】 Also, The first switch, When the first switch described above is connected, a plurality of sets of capacitance elements are formed, each of which has a predetermined reference potential applied to one end electrode of the respective capacitance element. When the first switch is connected, in the capacitive element set corresponding to the inhibitory input signal, the inhibitory input signal is connected to the other end electrode of the capacitive element selected according to the coupling load, and a predetermined coupling load 0 potential is connected to the other capacitive elements not selected according to the coupling load, and to the other end electrodes of all capacitive elements in the capacitive element set corresponding to the excitatory input signal, When the first switch is in the off state, a second switch connects the excitatory input signal to the other end electrode of the capacitive element selected according to the coupling load in the capacitive element set corresponding to the excitatory input signal, and connects a predetermined coupling load 0 potential to the other capacitive elements not selected according to the coupling load, and to the other end electrodes of all capacitive elements in the capacitive element set corresponding to the inhibitory input signal. It is characterized by having the following features. 【0009】 As a result, when the first switch is connected, an independent first set of input signals is connected to the other end electrode of each of the capacitive elements, while when the first switch is disconnected, an independent second set of input signals is connected to the other end electrode of each of the capacitive elements, allowing for a greater number of input signals than the number of capacitive elements. Furthermore, it becomes easy to combine the input signals according to the coupling load, or to combine them as inhibitory or excitatory inputs. [Effects of the Invention] 【0010】 In this invention, the number of inputs to a neuron circuit can be easily increased. [Brief explanation of the drawing] 【0011】 [Figure 1] A circuit diagram showing the configuration of the main parts of the neuron circuit of Embodiment 1. [Figure 2] A graph showing an example of the operation of the neuron circuit in Embodiment 1. [Figure 3] A circuit diagram showing the configuration of the main parts of the neuron circuit in the comparative example. [Figure 4] A graph showing an example of the operation of a neuron circuit in a comparative example. [Figure 5] A circuit diagram showing the configuration of the main parts of the neuron circuit of Embodiment 2. [Figure 6] A graph showing an example of the operation of the neuron circuit in Embodiment 2. [Figure 7] A circuit diagram showing the configuration of the main parts of the neuron circuit of Embodiment 3. [Figure 8]Graph showing an example of the operation of the neuron circuit of Embodiment 3. [Figure 9] Circuit diagram showing the configuration of the main part of the neuron circuit of Embodiment 4. [Figure 10] Circuit diagram showing the configuration of the main part of the neuron circuit of Embodiment 5. [Figure 11] Graph showing an example of the operation of the neuron circuit of Embodiment 5. [Figure 12] Graph showing an example of the operation of the neuron circuit of the comparative example. 【Mode for Carrying Out the Invention】 【0012】 Hereinafter, embodiments of the present invention will be described in detail based on the drawings. In each of the following embodiments, components having the same functions as those in other embodiments are denoted by the same reference numerals, and the description thereof will be omitted. Also, the components shown in each embodiment etc. may be combined in various ways as long as it is logically possible. 【0013】 (Embodiment 1) (Configuration of Neuron Circuit 100) As Embodiment 1, an example of a neuron circuit 100 with a total of 6 inputs, consisting of 3 excitatory inputs and 3 inhibitory inputs, will be described. As shown in Figure 1, this neuron circuit 100 includes three capacitive elements C1 to C3, whose one-end electrodes are connected to each other, switches SW21 to SW23 that selectively switch and connect independent inhibitory input voltages Va1 to Va3 or excitatory input voltages Vb1 to Vb3 to the other-end electrodes of the capacitive elements C1 to C3, and a two-stage CMOS inverter circuit INV1·INV2 (transistor element) in which the one-end electrodes of the capacitive elements C1 to C3 are connected to a floating gate FG. A switch SW1 is connected between the floating gate FG, which is the input side of the CMOS inverter circuit INV1, and the output side. When connected (during pre-charge, reset phase), the floating gate FG is set to the threshold voltage Vth (reference voltage) of the CMOS inverter circuit INV1 and applied to the one-end electrodes of the capacitive elements C1 to C3. Furthermore, by switching between switches SW21 and SW23, when switch SW1 is connected, suppressive input voltages Va1 to Va3 are connected to the other ends of capacitive elements C1 to C3, while when switch SW1 is disconnected, excitatory input voltages Vb1 to Vb3 are connected to the other ends of capacitive elements C1 to C3. 【0014】 Here, the capacitive elements C1 to C3 may take various forms, such as a so-called capacitive element formed by providing an insulator between a pair of electrodes, or by providing an input coupling electrode that capacitively couples to the gate electrode of the CMOS inverter circuit INV1 via an insulating film. The CMOS inverter circuits INV1 to INV2 output a VDD level or ground level digital signal depending on whether the potential of the floating gate FG is higher or lower than the threshold potential, and can also generate a threshold potential and apply it to the floating gate FG when switch SW1 is closed and the input and output are connected. However, they are not limited to this, and may also be provided in combination with a binarization circuit such as an amplifier circuit or comparator and a threshold voltage generation circuit. Switches SW21 to SW23 may be configured such that one end of a plurality of disconnecting switches is connected to each other so that one of the disconnecting switches is exclusively in a conductive state, or a changeover switch having a plurality of selection terminals and a connection terminal that selectively connects to one of them may be used. 【0015】 (Operation of neuron circuit 100) In the neuronal circuit 100 configured as described above, the following operations are performed. 【0016】 First, when switch SW1 is connected, switches SW21~SW23 are switched to connect to the suppression input voltages Va1~Va3. Then, the threshold voltage of the CMOS inverter circuit INV1 is applied to one end electrode of each capacitive element C1~C3. A suppression input voltage Va1 to Va3 is applied to the electrode on the other end, and a charge corresponding to the voltage difference between the threshold voltage and the suppression input voltage is accumulated. 【0017】 Next, as switch SW1 is turned off, switches SW21 to SW23 are switched to connect to the excitatory input voltages Vb1 to Vb3. As a result, the electrodes on one end of the capacitive elements C1 to C3, and therefore the floating gate FG of the CMOS inverter circuit INV1, generate a floating gate voltage VF corresponding to the excitatory input voltages Vb1 to Vb3, along with the charge accumulated in the capacitive elements C1 to C3 by the suppressive input voltages Va1 to Va3. 【0018】 More specifically, the floating gate voltage VF and the output Vout of the CMOS inverter circuits INV1·INV2 are expressed as (Equation 1) and (Equation 2), generalizing the number of capacitive elements to n. 【0019】 Here, The CT is the sum of the capacitances of capacitive elements C1 to Cn connected to the floating gate FG (more precisely, the sum of parasitic capacitances occurring in the floating gate FG, such as the gate capacitance of the transistor in the CMOS inverter circuit INV1). Vth is the threshold voltage of the CMOS inverter circuit INV1. Va1~Van are suppression input voltages. Vb1 to Vbn are the excitatory input voltages. Vdd is the power supply voltage. 【0020】 【number】 【0021】 【number】 【0022】 A more specific example of operation will be explained based on Figure 2. This figure shows the floating gate voltage VF when, with switch SW1 in the connected state, a suppression input voltage Va1 of 0.3V, 0.6V, 0.9V, 1.2V, 1.5V, or 1.8V is applied, and after 10ns, switch SW1 is turned off, switches SW21 to SW23 are switched to the excitatory input voltage Vb1, and the excitatory input voltage Vb1 is gradually changed from 0V to the power supply voltage of 1.8V (Va2, Va3, Vb2, Vb3 are 0V). Here, in the example of Figure 2, the capacitance of capacitive elements C1 to C3 is assumed to be 16fF, for example, and parasitic capacitances such as the gate capacitance of the transistor are also included. 【0023】 Figure 3 shows an example, as a comparative example, in which six capacitive elements C1 to C6 are provided corresponding to six input voltages V1 to V6. In such a neuron circuit, when switch SW1 is connected, a common reference voltage Vref is input to all capacitive elements C1 to C6, and when switch SW1 is disconnected, the six input voltages V1 to V6 are input to each of the capacitive elements C1 to C6. In this case, the floating gate voltage VF and the output Vout of the CMOS inverter circuits INV1 and INV2 are expressed as (Equation 3) and (Equation 4), generalizing the number of capacitive elements to n. 【0024】 【number】 【0025】 【number】 【0026】 Furthermore, if we assume that the reference voltage Vref input to capacitive elements C1~C6 is 0.9V when switch SW1 is connected (Reset phase), that switch SW1 is disconnected at a time of 10ns, and that switches SW21~SW26 are switched to input voltages V1~V6, and that input voltage V2 is 0.3V, 0.6V, 0.9V, 1.2V, 1.5V, or 1.8V, and in each case the input voltage V1 is changed from 0V to the power supply voltage of 1.8V, then the floating gate voltage VF will be as shown in Figure 4. 【0027】 As described above, when switch SW1 is connected, independent suppressive input voltages Va1 to Va3 are connected to the other end electrodes of each capacitive element C1 to C3, and when switch SW1 is disconnected, independent excitatory input voltages Vb1 to Vb3 are connected to the other end electrodes of each capacitive element C1 to C3, allowing twice the number of input signals as there are capacitive elements. Furthermore, since the ratio of the capacitance of each capacitive element to the sum of the capacitances of the capacitive elements is also doubled, the change in the floating gate voltage VF in response to a change in input voltage becomes double (approximately double when considering the effects of parasitic capacitance, etc.), and the noise margin can also be doubled. 【0028】 In the example above, a threshold voltage Vth is generated and applied to the electrodes at one end of the capacitive elements C1 to C3 by connecting the input and output of the CMOS inverter circuit INV1, to which one end is connected, with a switch SW1. However, the example is not limited to this, and other predetermined reference voltages may be generated and applied. 【0029】 Here, assuming the threshold voltage Vth is VDD / 2, and the lowest voltage of the input voltages Va1~Va3·Vb1~Vb3 is 0V and the highest voltage is VDD, the floating gate voltage VF when switches SW21~SW23 are switched to input voltage Vb1 will be -VDD / 2~3VDD / 2. If a transfer gate is used for switch SW1, current flows to the power supply or ground through the parasitic diode of the transfer gate. If the forward voltage of the parasitic diode is VD, the floating gate voltage VF will gradually decrease or increase over time and converge to -VD or VDD+VD. To suppress such time variation of the floating gate voltage VF, if the input voltages Va1~Va3·Vb1~Vb3 are in the range of 0V~VDD, for example, if a capacitance equal to the total capacitance CT of the capacitive elements is added between the floating gate FG and ground, the floating gate voltage VF will be 0V~VDD, and its change over time can be suppressed. 【0030】 Furthermore, the floating gate voltage VF when switches SW21 to SW23 are switched to the input voltage Vb1 is not limited to being set to 0V to VDD, but may be set to a range such as -VD to VDD+VD, where the time variation of the floating gate voltage VF due to the effect of parasitic diodes is suppressed or reduced to an acceptable level. In addition, instead of adding capacitance between the floating gate FG and ground, the input voltage range may be set (limited) so that the floating gate voltage VF is within a predetermined range. 【0031】 (Embodiment 2) As an example of the neuron circuit 100 of Embodiment 2, an example of a neuron circuit 100 in which the coupling load can be set will be described with reference to Figure 5. In this neuron circuit 100, three capacitive elements 1C, 2C, and 4C are provided for each pair of inhibitory input voltages and excitatory input voltages. The capacitance ratio of these capacitive elements is set to, for example, 1:2:4. The electrode on one end of each capacitive element is connected to the floating gate FG of the CMOS inverter circuit, as in Embodiment 1. The electrode on the other end of each capacitive element is selectively connected to the inhibitory input voltages Va1 to Van, the excitatory input voltages Vb1 to Vbn, or ground (potential when the coupling load is 0) via switches SW2(1,1~3) to SW2(n,1~3). 【0032】 More specifically, for example, if the coupling load of the inhibitory input voltage Va1 is -3, when switch SW1 is connected, the inhibitory input Va1 is connected to capacitive elements 1C and 2C, and capacitive element 4C is connected to ground. Also, if the coupling load of the excitatory input voltage Vb1 is 4, when switch SW1 is disconnected, the excitatory input voltage Vb1 is connected to capacitive element 4C, and capacitive elements 1C and 2C are connected to ground. 【0033】 In the neuron circuit 100 described above, for example, as shown in Figure 6, which shows an example with 3 excitatory inputs and 3 inhibitory inputs, the floating gate voltage VF is shown when, for each case in which the inhibitory input voltage Va1 is 0.6V and the coupling weights are -1, -3, -5, and -7 when switch SW1 is connected, switch SW1 is turned off at time 10ns, and switches SW2(1,1~3)~SW2(3,1~3) are switched to the excitatory input voltage Vb1, and the excitatory input voltage Vb1 is gradually changed from 0V to the power supply voltage of 1.8V. Note that the example shows Va2~Va3 and Vb2~Vb3 as 0V. 【0034】 As described above, when switch SW1 is connected, a threshold voltage Vth (a predetermined reference potential) of the CMOS inverter circuit INV1 is applied to one end electrode of each capacitance element in multiple sets of capacitance element groups. When switch SW1 is connected, for each set of capacitance element, independent suppression input voltages Va1 to Va3 are connected to the other end electrode of the capacitance element selected according to the coupling load, and ground (potential at 0 coupling load) is connected to the other end electrode of the other capacitance element. On the other hand, when switch SW1 is disconnected, for each set of capacitance element, according to the coupling load, By providing a plurality of switches SW2(1,1~3)~SW2(3,1~3) that connect independent excitatory input voltages Vb1~Vb3 to the other end electrodes of the capacitive elements being treated, and connecting ground (potential at 0 coupling load) to the other end electrodes of other capacitive elements, that is, when switch SW1 is connected and when it is disconnected, one or more of the plurality of capacitive elements constituting the set of capacitive elements are selectively connected to either an inhibitory input voltage or an excitatory input voltage, respectively, it is possible to input twice the number of input signals as the number of capacitive element sets and obtain an output corresponding to the coupling load. 【0035】 In the example above, three capacitance elements with capacities in a 1:2:4 ratio were shown for each pair of inhibitory and excitatory input voltages. However, the example is not limited to this; capacitance elements with the same capacitance or capacitance elements with different capacitance relationships may also be provided. 【0036】 (Embodiment 3) The same input voltages V1 to Vn can be connected to the electrodes on the other end of the capacitive elements when switch SW1 is connected and when it is disconnected, thereby enabling the setting of positive and negative coupling loads (allowing the input voltage to be either an inhibitory or excitatory input voltage). In this neuron circuit 100, as shown in Figure 7, the electrodes on the other end of each capacitive element are selectively connected to input voltages V1 to Vn or ground (potential when coupling load is 0) via switches SW2(1,1~3)~SW2(n,1~3). In this neuron circuit 100, the number of inputs is the same as the number of capacitive element sets, but when the coupling load is negative, the input voltages V1 to Vn are connected to the capacitive elements corresponding to the magnitude of the coupling load when switch SW1 is connected, and when the coupling load is positive, the input voltages V1 to Vn are connected to the capacitive elements corresponding to the magnitude of the coupling load when switch SW1 is disconnected, thereby enabling the setting of positive and negative coupling loads. 【0037】 In the neuron circuit 100 described above, as shown in Figure 8, for example, the floating gate voltage VF is shown for each case where the input voltage V1 is 0.9V, 1.8V, and the coupling load is applied from -7 to +7, when the switch SW1 is in the connected or disconnected state. Note that V2 and V3 are shown as examples where they are 0V. 【0038】 As described above, when switch SW1 is connected, multiple sets of capacitance elements are formed, each of which has a threshold voltage (a predetermined reference potential) of the CMOS inverter circuit INV1 applied to one end electrode of the respective capacitance element. When the above switch SW1 is connected, in the capacitive element set corresponding to the inhibitory input signal, the inhibitory input signal is connected to the other end electrode of the capacitive element selected according to the coupling load, and ground (a predetermined coupling load 0 potential) is connected to the other capacitive elements not selected according to the coupling load, and to the other end electrodes of all capacitive elements in the capacitive element set corresponding to the excitatory input signal, When the above switch SW1 is in the off state, the system includes a plurality of switches SW2(1,1~3)~SW2(n,1~3) which connect the excitatory input signal to the other end electrode of the capacitive element selected according to the coupling load in the capacitive element set corresponding to the excitatory input signal, and connect to ground to the other end electrodes of the other capacitive elements not selected according to the coupling load, and to all capacitive elements in the capacitive element set corresponding to the inhibitory input signal, thereby enabling the output of voltages with set positive and negative coupling loads. 【0039】 As a more concrete example of operation, let's consider a case where there are three inputs, V1 to V3, with weights of 2 for V1, 6 for V2, and 3 for V3, and V1 and V3 are inhibitory inputs, while V2 is an excitatory input (weight of V1 -2, weight of V2 +6, weight of V3 -3). Here, the capacitance ratio of 1C, 2C, and 4C is 1:2:4. 【0040】 When switch SW1 is in the connected state (Reset phase), 2C connected to switch SW2(1,2) is connected to V1. The 1C and 4C connected to switches SW2(1,1) and SW2(1,3) are connected to ground. The 1C to 4C wires connected to switches SW2(2,1) to SW2(2,3) are all connected to ground. Switches SW2(3,1) and SW2(3,2) have 1C and 2C connected to them, and these are connected to V3. 4C, which is connected to switch SW2(3,3), is connected to ground. 【0041】 Next, when switch SW1 is in the disconnected state, The 1C to 4C cables connected to switches SW2(1,1) to SW2(1,3) are all connected to ground. 1C, which is connected to switch SW2(2,1), is connected to ground. The 2C and 4C cables connected to switches SW2(2,2) and SW2(2,3) are connected to V2. The 1C to 4C wires connected to switches SW2(3,1) to SW2(3,3) are all connected to ground. 【0042】 In this way, weighted V1 and V3 can be used as inhibitory inputs, and weighted V2 as an excitatory input. 【0043】 In the example above, the coupling coefficient can be set to 15 levels from -7 to +7, but it is not limited to this. Various numbers of levels are possible, or each level can simply be set to a single level with only positive or negative (-1 or +1). If you want to set it to positive or negative, for example, in Figure 7, you can omit switches SW2(1,2~3), SW2(2,2~3), ...SW2(n,2~3). 【0044】 (Embodiment 4) The neuron circuit 100 may be configured to output an analog signal. For example, as shown in Figure 9, a single-stage CMOS inverter circuit INV1 may be connected to one end electrode of the capacitive elements C1 to Cn, and the transfer characteristics of the CMOS inverter circuit INV1 may be used as the activation function to create a neuron circuit 100 with analog voltage input and analog voltage output. In such a neuron circuit 100, the basic operation and the ability to easily increase the number of input voltages remain the same. When a single-stage CMOS inverter circuit INV1 or the like is connected to a floating gate FG to create a neuron circuit 100 with analog voltage input and analog voltage output, the output analog voltage can be further input to other neuron circuits 100 in multiple stages to increase the overall fan-in or to configure a more complex neural network. 【0045】 Note that the floating gate FG is not limited to the CMOS inverter circuit INV1; an amplification circuit, buffer circuit, etc., may also be connected to it so that an analog signal is output. In this case, during the pre-charge phase (reset phase), a predetermined reference voltage may be generated separately and applied to one end electrode of the capacitive elements C1 to Cn. When an amplification circuit, etc., is connected as described above, for example, the weighting when input to the next stage may be set by the amplification factor. In addition, the characteristics of the output voltage with respect to the input voltage may be set in various ways to obtain a nonlinear characteristic. 【0046】 (Embodiment 5) The neuron circuit 100 may be configured to receive digital signals as input. For example, a Hamming distance lookup circuit can be configured as shown in Figure 10. This figure shows a circuit for n bits, where if the Hamming distance DH between input A (a1, a2, ..., ai, ..., an) and input B (b1, b2, ..., bi, ..., bn) is within the range of the number DHR (reference distance) set by the number of logical values ​​of 1 in the number setting signal REF (REF1, REF2, ..., REBi, ..., REFn), then VOUT becomes VDD. In this example, switches SW21 to SW2n are composed of three NAND gates and are switched by a control signal X that is linked to switch SW1. Switches SW21 to SW2n each receive the output of an XOR circuit with inputs A (a1, a2, ...) and B (b1, b2, ...), respectively, and a number setting signal REF (REF1, REF2, ...). These signals are sequentially selected and input to n capacitive elements as either inhibitory or excitatory inputs, resulting in an output corresponding to the difference between them. 【0047】 In the neuron circuit 100 described above, Figure 11 shows an example of the floating gate voltage VF for an 8-bit Hamming distance lookup circuit when DHR-DH is -8 to +8. As a comparative example, Figure 12 shows an example of the floating gate voltage VF for a neuron circuit equipped with 16 capacitive elements, each receiving the output of an XOR circuit to which inputs A(a1, a2, ...) and B(b1, b2, ...) are input, and the number setting signal REF(REF1, REF2, ...) is simultaneously input. In this way, by switching the signals input to the capacitive elements depending on whether switch SW1 is connected or disconnected, and ensuring that independent input signals are input in each case, the number of capacitive elements can be kept to a minimum, making it easy to reduce the circuit size, and easily doubling the difference in floating gate voltage with respect to the difference in Hamming distance, thereby doubling the noise margin. [Explanation of symbols] 【0048】 100 Neuron Circuits C1~C3 Capacitive element C1~Cn Capacitance element INV1 / INV2 CMOS Inverter Circuit (Binarization Circuit) SW1 Switch (First switch) SW21~SW23 Switch SW2(1,1~3)~SW2(3,1~3) Switch (Second switch) SW2(1,1~3)~SW2(n,1~3) Switch (Second switch) Va1~Va3 Suppression input voltage (first set of input signals) Va1~Van: Suppression input voltage (first set of input signals) Vb1~Vb3 Excitatory input voltages (second set of input signals) Vb1~Vbn Excitatory input voltages (second set of input signals)

Claims

[Claim 1] The first switch, When the first switch described above is connected, a plurality of capacitive elements are provided, each having a predetermined reference potential applied to one end electrode, When the first switch is connected, an independent first set of input signals is connected to the other end electrode of each of the capacitive elements, When the first switch is in the off state, a plurality of second switches connect an independent second set of input signals to the other end electrode of each of the capacitive elements, A neuron circuit characterized by having the following features. [Claim 2] The first switch, When the first switch described above is connected, a plurality of sets of capacitance elements are formed, each of which has a predetermined reference potential applied to one end electrode of the capacitance element. When the first switch is connected, for each set of capacitive elements, an independent set of input signals is connected to the other end electrode of the capacitive element selected according to the coupling load, and a predetermined coupling load zero potential is connected to the other end electrode of the other capacitive elements. When the first switch is in the off state, a plurality of second switches connect an independent second set of input signals to the other end electrode of a capacitive element selected according to the coupling load for each set of capacitive elements, and connect the coupling load zero potential to the other end electrode of other capacitive elements. A neuron circuit characterized by having the following features. [Claim 3] The first switch, When the first switch described above is connected, a plurality of sets of capacitance elements are formed, each of which has a predetermined reference potential applied to one end electrode of the capacitance element. When the first switch is connected, in the capacitive element set corresponding to the inhibitory input signal, the inhibitory input signal is connected to the other end electrode of the capacitive element selected according to the coupling load, and a predetermined coupling load zero potential is connected to the other capacitive elements not selected according to the coupling load, and to the other end electrodes of all capacitive elements in the capacitive element set corresponding to the excitatory input signal, When the first switch is in the off state, a second switch connects the excitatory input signal to the other end electrode of the capacitive element selected according to the coupling load in the capacitive element set corresponding to the excitatory input signal, and connects a predetermined coupling load zero potential to the other capacitive elements not selected according to the coupling load, and to the other end electrodes of all capacitive elements in the capacitive element set corresponding to the inhibitory input signal. A neuron circuit characterized by having the following features. [Claim 4] A neuron circuit according to any one of claims 1 to 3, Furthermore, the neuron circuit is characterized by comprising a binarization circuit connected to one end electrode of the above-mentioned capacitive element, and outputting a digital signal. [Claim 5] A neuron circuit according to claim 4, The above binarization circuit is a neuron circuit characterized by being configured using a CMOS inverter circuit. [Claim 6] A neuron circuit according to claim 5, The above CMOS inverter circuit is provided in two stages. The first switch described above is a neuron circuit characterized by disconnecting the input and output of the first-stage CMOS inverter circuit. [Claim 7] A neuron circuit according to any one of claims 1 to 3, A neuron circuit characterized by outputting an analog signal corresponding to the potential of one end electrode of the above-mentioned capacitive element. [Claim 8] A neuron circuit according to claim 1, A neuron circuit characterized in that digital signals are input as the first set of input signals and the second set of input signals described above. [Claim 9] A neuron circuit according to claim 8, The first set of input signals is a signal obtained by the exclusive OR operation of each bit of a multi-bit signal, and the neuron circuit is characterized in that it outputs a signal of a level corresponding to a comparison between the number of active-level signals among the exclusive OR signals and the number of active-level signals among the second set of input signals. [Claim 10] A method for driving a neuron circuit having multiple capacitive elements connected to each other, wherein a voltage corresponding to an input signal input to the other end electrode of the capacitive elements is output from the one end electrode, The steps include applying a predetermined reference potential to one end electrode of the plurality of capacitive elements and inputting a first set of independent input signals to the other end electrode of each of the capacitive elements, The steps include stopping the application of the reference potential to the one-end electrode of each of the multiple capacitive elements, and inputting a second set of independent input signals to the other-end electrode of each of the capacitive elements, A method for driving a neuron circuit, characterized by having [a certain feature]. [Claim 11] A method for driving a neuron circuit having multiple sets of capacitive elements, each set of multiple capacitive elements with one end electrode connected to each other, wherein a voltage corresponding to an input signal input to the other end electrode of the capacitive element is output from the one end electrode, The steps include applying a predetermined reference potential to one end electrode of the plurality of capacitive elements, inputting an independent first set of input signals to the other end electrode of the capacitive element selected according to the coupling load for each set of capacitive elements, and inputting a predetermined coupling load zero potential to the other end electrode of the other capacitive elements, The steps include: stopping the application of the reference potential to the one-end electrode of the plurality of capacitive elements, and for each set of capacitive elements, inputting a second set of independent input signals to the other-end electrode of the capacitive element selected according to the coupling load, and inputting the coupling load zero potential to the other-end electrode of the other capacitive elements; A method for driving a neuron circuit, characterized by having [a certain feature]. [Claim 12] A method for driving a neuron circuit having multiple sets of capacitive elements, each set of multiple capacitive elements with one end electrode connected to each other, wherein a voltage corresponding to an input signal input to the other end electrode of the capacitive element is output from the one end electrode, The steps include: applying a predetermined reference potential to one end electrode of the plurality of capacitive elements; inputting the inhibitory input signal to the other end electrode of the capacitive element selected according to the coupling load in the capacitive element set corresponding to the inhibitory input signal; and inputting a predetermined coupling load zero potential to the other capacitive elements not selected according to the coupling load, and to the other end electrodes of all capacitive elements in the capacitive element set corresponding to the excitatory input signal; The steps include: stopping the application of the reference potential to the one-end electrodes of the plurality of capacitive elements mentioned above; inputting the excitatory input signal to the other-end electrode of the capacitive element selected according to the coupling load in the capacitive element set corresponding to the excitatory input signal; and inputting a predetermined coupling load zero potential to the other capacitive elements not selected according to the coupling load, and to the other-end electrodes of all capacitive elements in the capacitive element set corresponding to the inhibitory input signal; A method for driving a neuron circuit, characterized by having [a certain feature].

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