Semiconductor laminate, method for manufacturing a semiconductor laminate, and optical semiconductor device

Abstract

The present invention provides a semiconductor laminate comprising a p-type InGaAs layer with high carrier density and carrier mobility, a method for manufacturing the semiconductor laminate, and an optoelectronic semiconductor device. [Solution] The semiconductor laminate according to this disclosure comprises a first semiconductor layer formed of a III-V compound semiconductor, and a p-type InGaAs layer laminated on the first semiconductor layer, wherein the impurity generating majority carriers is carbon. The resistivity of the p-type InGaAs layer is 2.0 × 10⁻⁶ -3 It is less than or equal to Ωcm.

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor stack, a method for manufacturing a semiconductor stack, and an optoelectronic semiconductor device. [Background technology]

[0002] Semiconductor devices such as optoelectronic devices and semiconductor electronic devices utilize semiconductor laminates in which semiconductor layers formed from III-V compound semiconductors are stacked on a substrate formed from III-V compound semiconductors. Since semiconductor devices operate using electric current, metal electrodes for conducting the current are formed on the surface of the semiconductor laminate. In this case, a contact layer is necessary to reduce the contact resistance between the electrodes and the semiconductor laminate, and a high-density semiconductor layer with a high carrier density is used for the contact layer to reduce contact resistance. Furthermore, in a pn junction formed by joining a p-type semiconductor layer and an n-type semiconductor layer, a high-density semiconductor layer with a high carrier density is necessary to form a tunnel junction region with reduced operating voltage.

[0003] For example, in a semiconductor laminate in which semiconductor layers are stacked on a substrate formed of InP (indium phosphide), a semiconductor layer (InGaAs layer) formed of InGaAs (indium gallium arsenide) that is lattice-matched with InP is used as a high-density semiconductor layer. Here, when fabricating a p-type InGaAs layer, carbon (C), which can be doped to a high concentration, is attracting attention as an acceptor impurity. By using carbon as an acceptor, 1.8 × 10⁻¹⁰ 19 / cm 3 From 7.0 x 10 19 / cm 3 p-type InGaAs layers with a carrier density of a certain degree have been fabricated (see, for example, Patent Documents 1 and 2, and Non-Patent Document 1). [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-086135 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-180115 [Non-Patent Document]

[0005] [Non-Patent Document 1] K. Hong et al, “Heavily carbon doped InGaAs lattice matched to InP grown by LP-MOCVD using TMIn, TMGa and liquid CCl / sub 4 / ”, May 1995, IEEE [Summary of the Invention] [Problems to be Solved by the Invention]

[0006] When a p-type InGaAs layer is used as a contact layer, a higher carrier density results in a lower contact resistance with an electrode. When used as a semiconductor layer forming a tunnel junction, a higher carrier density results in a lower operating voltage. However, in order to reduce the contact resistance and operating voltage as described above, it is necessary to increase not only the carrier density but also the carrier mobility of the p-type InGaAs layer.

[0007] Therefore, one object of the present disclosure is to provide a semiconductor laminate including a p-type InGaAs layer having a high carrier density and a high carrier mobility, a method of manufacturing the semiconductor laminate, and an optical semiconductor device. [Means for Solving the Problems]

[0008] A semiconductor laminate according to the present disclosure includes a first semiconductor layer formed of a Group III-V compound semiconductor, and a p-type InGaAs layer laminated on the first semiconductor layer and containing carbon as an impurity for generating a majority carrier. The specific resistance of the p-type InGaAs layer is 2.0×10 -3 Ωcm or less. [Advantages of the Invention]

[0009] According to this disclosure, a semiconductor laminate is provided which comprises a p-type InGaAs layer with high carrier density and carrier mobility. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 is a schematic cross-sectional view illustrating the structure of a semiconductor laminate according to an embodiment. [Figure 2] Figure 2 is a schematic flowchart of the method for manufacturing a semiconductor laminate according to the embodiment. [Figure 3] Figure 3 is a schematic diagram illustrating the structure of a semiconductor laser, which is an optical semiconductor device according to the embodiment. [Figure 4] Figure 4 is a graph showing the carrier density and carrier mobility for each sample. [Modes for carrying out the invention]

[0011] [Description of Embodiments in this Disclosure] First, the embodiments of this disclosure will be listed and described.

[0012] (1) A semiconductor stack according to this disclosure comprises a first semiconductor layer formed of a III-V compound semiconductor and a p-type InGaAs layer stacked on the first semiconductor layer, wherein the impurity generating majority carriers is carbon. The resistivity of the p-type InGaAs layer is 2.0 × 10⁻⁶ -3 It is less than or equal to Ωcm.

[0013] In this disclosure, the expression "formed by (a certain element)" means that it is formed using a certain element, and may include elements other than that element.

[0014] In a semiconductor stack according to this disclosure, the resistivity of the p-type InGaAs layer is 2.0 × 10⁻⁶ -3It is below Ωcm and has a low specific resistance. Therefore, in the p-type InGaAs layer, the density of majority carriers (referred to as "carrier density" in this disclosure) is high, and the mobility of majority carriers (referred to as "carrier mobility" in this disclosure) is high. Thus, according to this disclosure, a semiconductor laminate including a p-type InGaAs layer with high carrier density and high carrier mobility is provided.

[0015] (2) In the semiconductor laminate of (1) above, the mobility of majority carriers in the p-type InGaAs layer may be 40 cm 2 / Vs or more. According to such a semiconductor laminate, the specific resistance of the p-type InGaAs layer is further reduced.

[0016] (3) In the semiconductor laminate of (1) or (2) above, the density of majority carriers in the p-type InGaAs layer may be 8.0×10 19 cm -3 or more. According to such a semiconductor laminate, the specific resistance of the p-type InGaAs layer is further reduced.

[0017] (4) In the semiconductor laminate of any one of (1) to (3) above, the activation rate of impurities in the p-type InGaAs layer may be 50% or more. According to such a semiconductor laminate, since the carbon that is not activated among the carbon contained as impurities in the p-type InGaAs layer is reduced, the quality of the p-type InGaAs layer becomes good and the reliability of the p-type InGaAs layer is improved. Also, the unactivated carbon contained in the p-type InGaAs layer causes a decrease in carrier mobility. Therefore, by reducing the unactivated carbon, the carrier mobility of the p-type InGaAs layer is improved.

[0018] The optical semiconductor device according to this disclosure includes any one of the semiconductor laminates of (1) to (4) above and an electrode disposed in contact with the p-type InGaAs layer of the semiconductor laminate.

[0019] The optical semiconductor device according to this disclosure includes a semiconductor stack according to this disclosure, wherein a p-type InGaAs layer with low resistivity and high carrier density and carrier mobility contacts the electrode which will be the anode as a p-type contact layer. Therefore, the contact resistance of the p-type contact layer with respect to the electrode is reduced. Thus, according to this disclosure, an optical semiconductor device having low contact resistance is provided.

[0020] A method for manufacturing a semiconductor laminate according to this disclosure comprises the steps of: preparing a substrate formed of a III-V compound semiconductor; stacking a semiconductor layer formed of a III-V compound semiconductor on the substrate by epitaxial growth; and heat-treating the semiconductor layer. The step of stacking the semiconductor layer includes stacking a p-type InGaAs layer in which the impurity generating the majority carrier is carbon, by chemical vapor deposition using organometallic gases as raw materials for indium, gallium, and arsenic. In the step of stacking the p-type InGaAs layer, the raw material for arsenic is tert-butylarsine, and the temperature of the substrate is 500°C or lower. In the step of heat-treating the semiconductor layer, the semiconductor layer is heated to a temperature of 500°C or lower in an inert gas atmosphere.

[0021] In the method for manufacturing a semiconductor laminate according to this disclosure, the arsenic source gas in the process of stacking p-type InGaAs layers is tert-butylarsine. Tert-butylarsine is an organometallic compound and does not easily produce hydrogen upon thermal decomposition. Therefore, according to the method for manufacturing a semiconductor laminate according to this disclosure, the incorporation of hydrogen into the p-type InGaAs layer during stacking and the subsequent deactivation of carbon by hydrogen combining with carbon, which is an impurity, is reduced.

[0022] Furthermore, in the semiconductor laminate manufacturing method according to this disclosure, the substrate temperature during the process of laminating the p-type InGaAs layer is 500°C or lower. Carbon, an impurity, is an amphoteric element, and in order to dope with a high concentration of carbon, it is necessary to laminate the p-type InGaAs layer at a low temperature. Also, carbon tends to become inactive at high temperatures. According to the semiconductor laminate manufacturing method according to this disclosure, because the substrate temperature during lamination of the p-type InGaAs layer is low, at 500°C or lower, carbon is doped at a high concentration, and carbon inactivation is reduced. In addition, in order to increase the amount of carbon doping, it is necessary to laminate the p-type InGaAs layer at a low temperature, and tert-butylarsine, a raw material gas for arsenic, has a low decomposition temperature and undergoes thermal decomposition at low temperatures of 500°C or lower. Therefore, even at low temperatures of 500°C or lower, the p-type InGaAs layer can be grown with good crystallinity, and high-quality p-type InGaAs layers are laminated by low-temperature crystal growth.

[0023] Furthermore, in the method for manufacturing a semiconductor laminate according to this disclosure, the heat treatment of the semiconductor layer in the step of heat treatment of the semiconductor layer is carried out in an inert gas atmosphere and at a heating temperature of 500°C or lower. By heat treating the semiconductor layer in an inert gas atmosphere where hydrogen is absent, the effect of deactivation of carbon, an impurity, is reduced. Also, carbon tends to become deactivated at high temperatures. Therefore, in the method for manufacturing a semiconductor laminate according to this disclosure, the deactivation of carbon is reduced because the temperature during heat treatment is low, at 500°C or lower.

[0024] As described above, the semiconductor laminate manufacturing method according to this disclosure improves the activation rate of carbon contained as an impurity in the p-type InGaAs layer, thereby providing a semiconductor laminate with a p-type InGaAs layer having a higher carrier density and carrier concentration and low resistivity. Furthermore, the semiconductor laminate manufacturing method according to this disclosure improves the activation rate of carbon contained as an impurity in the p-type InGaAs layer and reduces the amount of unactivated carbon. Therefore, a semiconductor laminate with a highly reliable p-type InGaAs layer is provided.

[0025] Furthermore, in the semiconductor laminate manufacturing method according to this disclosure, the arsenic source gas used in the process of stacking the p-type InGaAs layer is tert-butylarsine, which decomposes at low temperatures of 500°C or below. Therefore, according to the semiconductor laminate manufacturing method according to this disclosure, the p-type InGaAs layer can be stacked even at low temperatures of 500°C or below, and the crystallinity of the p-type InGaAs layer can be improved by stacking at low temperatures.

[0026] [Details of the embodiments of this disclosure] Next, embodiments of a semiconductor stack, a method for manufacturing a semiconductor stack, and an optoelectronic device according to this disclosure will be described with reference to the drawings. In the following description, the same or corresponding parts in the drawings will be given the same reference numeral, and their descriptions will not be repeated.

[0027] (Explanation of the structure of semiconductor stacks) Figure 1 is a schematic cross-sectional view illustrating the structure of a semiconductor laminate 1 according to one embodiment of the present disclosure. Referring to Figure 1, the semiconductor laminate 1 comprises a substrate 2, an n-type cladding layer 3, an active layer 4, a p-type cladding layer 5, and a p-type contact layer 6. The semiconductor laminate 1 has a double heterostructure in which the substrate 2, n-type cladding layer 3, active layer 4, p-type cladding layer 5, and p-type contact layer 6 are stacked in this order.

[0028] In the semiconductor laminate 1 according to this embodiment, the substrate 2, n-type cladding layer 3, active layer 4, and p-type cladding layer 5 are first semiconductor layers 7 formed from III-V compound semiconductors. Furthermore, the p-type contact layer 6 is a p-type InGaAs layer laminated on the first semiconductor layer 7, in which the impurity generating majority carriers is carbon.

[0029] The substrate 2 has a pair of parallel main surfaces, a first main surface 21 and a second main surface 22, located at both ends in the film thickness direction. The film thickness of the substrate 2 can be greater than, for example, 0 μm and 700 μm or less. In this disclosure, unless otherwise specified, "film thickness" refers to the minimum value of the film thickness. The diameter of the substrate 2 can be, for example, 50 mm or more, and can be, for example, 3 inches. From the viewpoint of improving the production efficiency and yield of semiconductor devices such as optoelectronic devices using the semiconductor laminate 1, the diameter of the substrate 2 can be 80 mm or more (for example, 4 inches). Furthermore, the diameter of the substrate 2 can be 100 mm or more (for example, 5 inches), and further 130 mm or more (for example, 6 inches).

[0030] Substrate 2 is formed from a III-V compound semiconductor. For example, InP, which has an n-type conductivity, can be used as the III-V compound semiconductor forming substrate 2. For example, sulfur (S) and silicon (Si) can be used as impurities that act as donors for generating majority carriers in substrate 2. Substrate 2 has a higher impurity concentration than the n-type cladding layer 3, and therefore has a higher carrier density than the n-type cladding layer 3. The carrier density of substrate 2 is, for example, 1.0 × 10⁻⁶. 17 cm -3 The above 1.0 × 10 19 cm -3 The following is possible:

[0031] Carrier density refers to the density of majority carriers (p-type carriers (holes) or n-type carriers (electrons)) generated by impurities in a semiconductor, excluding inactive impurities.

[0032] Carrier density can be measured by methods such as CV (capacitance-voltage) measurement and Hall measurement (a method for measuring the Hall effect). For example, carrier density can be measured using the ECV-pro, an ECV (Electrochemical Capacitance-Voltage) measurement device manufactured by Nanometrics.

[0033] The n-type cladding layer 3 is a semiconductor layer with n-type conductivity. The n-type cladding layer 3 is formed from a III-V compound semiconductor. As the III-V compound semiconductor forming the n-type cladding layer 3, for example, InP, which has n-type conductivity, can be used. As the impurities that act as donors in the n-type cladding layer 3, for example, sulfur and silicon can be used. The carrier density of the n-type cladding layer 3 is, for example, 1.0 × 10⁻⁶. 17 cm -3 The above 1.0 × 10 19 cm -3 The following is possible:

[0034] The n-type cladding layer 3 has a pair of parallel main surfaces, a first main surface 31 and a second main surface 32, located at both ends in the film thickness direction. The film thickness of the n-type cladding layer 3 can be, for example, 0.1 μm or more and 10 μm or less. The n-type cladding layer 3 is arranged such that the first main surface 31 is in contact with the second main surface 22 of the substrate 2. The n-type cladding layer 3 is laminated on the second main surface 22 of the substrate 2, for example, by epitaxial growth.

[0035] The active layer 4 has a structure in which multiple semiconductor layers formed from III-V compound semiconductors are stacked. The active layer 4 can be an SCH-MQW (Separate Confinement Heterostructure Multiple Quantum Well) including, for example, an InGaAs layer and an InGaAsP (indium gallium arsenide phosphide) layer.

[0036] The active layer 4 has a pair of parallel main surfaces, a first main surface 41 and a second main surface 42, located at both ends in the film thickness direction. The film thickness of the active layer 4 can be, for example, 0.1 μm or more and 1.0 μm or less. The active layer 4 is arranged such that the first main surface 41 is in contact with the second main surface 32 of the n-type cladding layer 3. The active layer 4 is laminated on the second main surface 32 of the n-type cladding layer 3, for example, by epitaxial growth.

[0037] The p-type cladding layer 5 is a semiconductor layer with p-type conductivity. The p-type cladding layer 5 is formed from a III-V compound semiconductor. Examples of III-V compound semiconductors that form the p-type cladding layer 5 include InP and InGaAs, both of which have p-type conductivity. Examples of impurities that act as acceptors to generate majority carriers in the p-type cladding layer 5 include zinc (Zn) and carbon (C). The carrier density of the p-type cladding layer 5 is, for example, 1.0 × 10⁻⁶. 17 cm -3 The above 1.0 × 10 19 cm -3 The following is possible:

[0038] The p-type cladding layer 5 has a pair of parallel main surfaces, a first main surface 51 and a second main surface 52, located at both ends in the film thickness direction. The film thickness of the p-type cladding layer 5 can be, for example, 0.1 μm or more and 10.0 μm or less. The p-type cladding layer 5 is arranged such that the first main surface 51 is in contact with the second main surface 42 of the active layer 4. The p-type cladding layer 5 is laminated on the second main surface 42 of the active layer 4, for example, by epitaxial growth.

[0039] The p-type contact layer 6 is a semiconductor layer with a p-type conductivity. The p-type contact layer 6 is a semiconductor layer formed of InGaAs, a III-V compound semiconductor with a low bandgap and lattice matching to InP. In the p-type InGaAs layer forming the p-type contact layer 6, the indium content can be, for example, 30% to 40% by mass. The gallium content can be, for example, 15% to 25% by mass. The arsenic content can be, for example, 40% to 50% by mass.

[0040] The p-type contact layer 6 has a pair of parallel main surfaces, a first main surface 61 and a second main surface 62, located at both ends in the film thickness direction. The film thickness of the p-type contact layer 6 can be, for example, 0.01 μm or more and 1.0 μm or less. The p-type contact layer 6 is arranged such that the first main surface 61 is in contact with the second main surface 52 of the p-type cladding layer 5. The p-type contact layer 6 is laminated on the second main surface 52 of the p-type cladding layer 5, for example, by epitaxial growth. The second main surface 62 of the p-type contact layer 6 is in contact with the first electrode 11 (anode), which will be described later.

[0041] The p-type contact layer 6 contains carbon as an acceptor impurity. The p-type contact layer 6 is doped with a high concentration of carbon. The concentration of carbon doped is higher than the concentration of impurities doped into the substrate 2, n-type cladding layer 3, and p-type cladding layer 5. The concentration of carbon doped is set to increase the carrier density of the p-type contact layer 6, for example, to 1.0 × 10⁻⁶. 20 cm -3 It can be set to the above, and furthermore, 5.0 × 10 20 cm -3 The above can be used. Furthermore, the concentration of carbon to be doped should be, for example, 10.0 × 10, from the viewpoint of preventing a decrease in the activation rate of carbon, improving the quality of the p-type contact layer 6, and increasing the carrier mobility of the p-type contact layer 6. 20 cm -3 The following is possible:

[0042] The concentration of impurities (carbon) in the p-type contact layer 6 can be measured by methods such as SIMS (Secondary Ion Mass Spectrometry) and GDMS (Glow Discharge Mass Spectrometry).

[0043] The carrier density of the p-type contact layer 6 is, for example, 8.0 × 10⁻⁶. 19 cm -3 It can be set to the above, and furthermore, 5.0 × 10 20 cm -3The above can be achieved. The carrier density of the p-type contact layer 6 is, for example, 10.0 × 10⁻⁶. 20 cm -3 The following is possible: The carrier density of the p-type contact layer 6 is 8.0 × 10⁻⁶. 19 cm -3 As a result of the above, the contact resistance of the p-type contact layer 6 with respect to the first electrode 11 can be reduced.

[0044] The carrier mobility of the p-type contact layer 6 is, for example, 40 cm². 2 It can be set to / Vs or higher, and furthermore, 45cm 2 It can be set to / Vs or higher, and furthermore, 48cm 2 The carrier mobility of the p-type contact layer 6 can be, for example, 50 cm². 2 It can be set to / Vs or less. Carrier mobility can be measured, for example, by Hall measurement. The carrier mobility of the p-type contact layer 6 is 40 cm². 2 By having a value of / Vs or higher, the contact resistance of the p-type contact layer 6 with respect to the first electrode 11 can be reduced.

[0045] The activation rate of impurities (carbon) in the p-type contact layer 6 can be, for example, 50% or more, further 70% or more, and even 90% or more. The activation rate is defined as (carrier density) / (concentration of doped impurities (carbon)) × 100 (%). By increasing the activation rate of impurities (carbon) in the p-type contact layer 6 to 50% or more and reducing the amount of unactivated carbon, the quality of the p-type contact layer 6 can be improved. As a result, the reliability of the p-type contact layer 6 can be improved. In addition, since unactivated carbon contained in the p-type contact layer 6 causes a decrease in carrier mobility, reducing the amount of unactivated carbon can improve the carrier mobility of the p-type contact layer 6.

[0046] The p-type contact layer 6 has low resistivity due to its high carrier density, carrier mobility, and activation rate of impurities (carbon). The resistivity of the p-type contact layer 6 is 2.0 × 10⁻⁶. -3It is less than or equal to Ωcm. The resistivity of the p-type contact layer 6 is set to 1.6 × 10⁻⁶ from the viewpoint of further improving the conductivity of the p-type contact layer 6. -3 It can be made less than Ωcm, and furthermore, 1.5 × 10 -3 The resistivity can be set to Ωcm or less. The resistivity of the p-type contact layer 6 can be measured by methods such as the four-probe method or the two-probe method.

[0047] The resistivity of the p-type contact layer 6 is 2.0 × 10 -3 When the carrier density is less than or equal to Ωcm, the carrier density and carrier mobility of the p-type contact layer 6 are, for example, 8.0 × 10⁻⁶. 19 cm -3 The above, plus a carrier mobility of 40cm 2 It can be set to / Vs or higher. Furthermore, the carrier density is 8.0 × 10⁻¹⁶. 19 cm -3 The above, plus a carrier mobility of 48cm. 2 It can be set to / Vs or higher, or the carrier density can be 1.0 × 10⁻⁶. 20 cm -3 The above, plus a carrier mobility of 40cm 2 It can be set to / Vs or higher.

[0048] In the semiconductor laminate 1 according to this embodiment, the resistivity of the p-type InGaAs layer forming the p-type contact layer 6 is 2.0 × 10 -3 The resistivity is less than Ωcm. Therefore, the carrier density of the p-type contact layer 6 is high, as is its carrier mobility. Thus, the contact resistance of the p-type contact layer 6 with respect to the anode electrode (hereinafter referred to as the "first electrode") 11 can be reduced, and the first electrode 11 can make ohmic contact with the p-type contact layer 6.

[0049] In the semiconductor laminate 1 according to this embodiment, the concentration of carbon doped into the p-type InGaAs layer forming the p-type contact layer 6 is 1.0 × 10⁻¹⁶. 20 cm -3The carrier density is high, and the carbon activation rate is high, exceeding 50%. Therefore, the carrier density of the p-type contact layer 6 can be increased, and the resistivity of the p-type contact layer 6 can be reduced. Furthermore, by reducing the amount of unactivated carbon contained in the p-type contact layer 6, the carrier mobility of the p-type contact layer 6 can be increased, and the resistivity of the p-type contact layer 6 can be reduced. Moreover, the quality of the p-type contact layer 6 can be improved, thereby enhancing its reliability.

[0050] As described above, the present disclosure provides a semiconductor laminate 1 comprising a p-type contact layer 6 having low contact resistance to the anode electrode, and having high reliability of the p-type contact layer 6.

[0051] (Explanation of the manufacturing method for semiconductor laminates) Next, an example of a method for manufacturing a semiconductor laminate according to this embodiment will be described with reference to Figure 2. Figure 2 shows a block diagram illustrating the procedure for manufacturing a semiconductor laminate according to this embodiment. Referring to Figure 2, the method for manufacturing a semiconductor laminate according to this embodiment comprises a substrate preparation step of preparing a substrate 2 as ST1 step, a semiconductor layer lamination step of laminating semiconductor layers 3-6 on the substrate 2 as ST2 step, and a heat treatment step of heat treating the semiconductor layers 3-6 laminated on the substrate 2 as ST3 step.

[0052] First, in the ST1 process, a substrate 2 formed from n-type InP, a III-V compound semiconductor, is prepared. Specifically, an ingot formed from InP is sliced ​​to obtain the substrate 2 made of InP. The substrate 2 undergoes processes such as polishing and cleaning to ensure the flatness and cleanliness of the second main surface 22.

[0053] Next, in the ST2 process, semiconductor layers 3-6, formed from III-V compound semiconductors, are stacked on the substrate 2 prepared in the ST1 process by epitaxial growth. The semiconductor layers 3-6 consist of an n-type cladding layer 3, an active layer 4, a p-type cladding layer 5, and a p-type contact layer 6, which are sequentially stacked on the second main surface 22 of the substrate 2. As for the epitaxial growth method, a vapor phase growth method such as metal-organic chemical vapor deposition is employed. The stacking of semiconductor layers 3-6 is carried out, for example, as follows: The substrate 2 is placed in a growth furnace and heated to a predetermined temperature by a heater. In this state, appropriate raw material gas is supplied to the growth furnace, and the temperature and pressure inside the growth furnace are appropriately adjusted to grow the semiconductor to a predetermined thickness, thereby sequentially stacking the semiconductor layers 3-6 on the substrate 2.

[0054] In the ST20 process, which involves laminating the n-type cladding layer 3 in the ST2 process, a semiconductor layer formed of, for example, n-type InP is laminated on the second main surface 22 of the substrate 2. In the ST20 process, trimethylindium (TMIn), an organometallic gas, is used as the raw material gas for indium. Tertiary butylphosphine (TBP), an organometallic gas, is used as the raw material gas for phosphorus. Sulfur is used as a donor to generate majority carriers.

[0055] In the ST21 process, which involves laminating the active layer 4 from the ST2 process, a semiconductor layer containing, for example, an InGaAs layer and an InGaAsP layer is laminated on the second main surface 32 of the n-type cladding layer 3. In the ST21 process, trimethylindium, an organometallic gas, is used as the raw material gas for indium. Triethylgallium (TEGa), an organometallic gas, is used as the raw material gas for gallium. Tert-butylarsine (TBAs), an organometallic gas, is used as the raw material gas for arsenic. Tert-butylphosphine, an organometallic gas, is used as the raw material gas for phosphorus.

[0056] In the ST22 process, which involves stacking the p-type cladding layer 5 from the ST2 process, a semiconductor layer formed, for example, from p-type InP, is stacked on the second main surface 42 of the active layer 4. In the ST22 process, trimethylindium, an organometallic gas, is used as the raw material gas for indium. Tert-butylphosphine, an organometallic gas, is used as the raw material gas for phosphorus. Zinc, for example, is used as the acceptor that generates majority carriers, and diethylzinc (DEZn), an organometallic gas, is used as the raw material gas for zinc. The first semiconductor layer 7 is produced by this ST22 process.

[0057] In the ST23 process, which involves laminating the p-type contact layer 6 in the ST2 process, a p-type InGaAs layer is laminated as a semiconductor layer on the second main surface 52 of the p-type cladding layer 5. In the ST23 process, organometallic gases are used as raw materials for indium, gallium, and arsenic. For example, trimethylindium is used as the raw material gas for indium. For example, triethylgallium is used as the raw material gas for gallium. For example, tert-butylarsine is used as the raw material gas for arsenic. Carbon is used as an acceptor to generate majority carriers, and for example, the organometallic gas carbon tetrabromide (CBr4) is used as the raw material gas for carbon.

[0058] In the ST23 step, which involves laminating a p-type InGaAs layer, which is the p-type contact layer 6, the concentration of doped carbon is, for example, 1.0 × 10⁻⁶. 20 / cm -3 It can be set to the above, and furthermore, 5.0 × 10 20 cm -3 This can be done.

[0059] In the ST23 process, the temperature of substrate 2 is set to 500°C or lower. That is, substrate 2 is heated to 500°C or lower by a heater. The temperature of substrate 2 may be set to 300°C or higher and 500°C or lower, or even to 350°C or higher and 450°C or lower.

[0060] Next, in the ST3 process, the semiconductor layers 3-6, which are the n-type cladding layer 3, active layer 4, p-type cladding layer 5, and p-type contact layer 6 stacked on the substrate 2 in the ST2 process, are subjected to heat treatment to activate the doped impurities.

[0061] In the ST3 process, the temperature at which the semiconductor layer 3-6 is heated during heat treatment is set to 500°C or lower. In other words, the semiconductor layer 3-6 is heated to 500°C or lower in the furnace. The heating temperature during heat treatment may be set to 300°C or higher and 500°C or lower, or even 350°C or higher and 500°C or lower. The heat treatment time can be, for example, 10 minutes. The heat treatment is carried out in an inert gas atmosphere. Examples of inert gases include nitrogen gas and argon gas.

[0062] In the semiconductor laminate manufacturing method according to this embodiment, the arsenic raw material gas in step ST23, which involves stacking p-type InGaAs layers forming the p-type contact layer 6, is tert-butylarsine. Conventionally, arsine (AsH3) has been used as the arsenic raw material gas, but arsine is a compound of arsenic and hydrogen, and hydrogen is produced by thermal decomposition. When hydrogen is incorporated into the semiconductor during the crystal growth of the p-type InGaAs layer, the carbon impurity is deactivated by bonding with hydrogen, causing the carbon to cease functioning as an acceptor. As a result, the carrier density of the p-type InGaAs layer decreases compared to the concentration of carbon doped into the p-type InGaAs layer. In contrast, when tert-butylarsine is used as the arsenic raw material gas, tert-butylarsine is an organometallic compound, and hydrogen is less likely to be produced by thermal decomposition, thus reducing the deactivation of carbon. This improves the activation rate of carbon contained in the p-type InGaAs layer.

[0063] Furthermore, in the semiconductor laminate manufacturing method according to this embodiment, the temperature of the substrate 2 in step ST23, in which the p-type InGaAs layer forming the p-type contact layer 6 is laminated, is 500°C or lower. Carbon, which is an impurity, is an amphoteric element, and in order to dope with carbon at a high concentration as an acceptor, it is necessary to grow the p-type InGaAs layer at a low temperature. Also, carbon tends to become inactive at high temperatures. By keeping the temperature of the substrate 2 at a low temperature of 500°C or lower during the crystal growth of the p-type InGaAs layer, carbon is doped at a high concentration as an acceptor, and the inactivation of carbon is reduced.

[0064] Furthermore, in the method for manufacturing the semiconductor laminate according to this embodiment, step ST3, in which the semiconductor layers 3-6 including the p-type contact layer 6 are heat-treated, is carried out in an inert gas atmosphere and at a heating temperature of 500°C or lower. By heat-treating the semiconductor layers 3-6 in an inert gas atmosphere such as a nitrogen atmosphere where hydrogen is absent, the effect of deactivation of the carbon doped into the p-type InGaAs layer is reduced. In addition, since carbon tends to become inactive at high temperatures, the deactivation of the carbon doped into the p-type InGaAs layer is reduced by keeping the heat treatment temperature low, at 500°C or lower.

[0065] As described above, the semiconductor laminate manufacturing method of this disclosure makes it possible to improve the activation rate of carbon contained in the p-type InGaAs layer forming the p-type contact layer 6. Therefore, a semiconductor laminate 1 is provided that has a p-type InGaAs layer with a low resistivity and increased carrier density and carrier concentration. Furthermore, since the activation rate of carbon contained in the p-type InGaAs layer is high and the amount of unactivated carbon is reduced, a semiconductor laminate 1 with high reliability of the p-type InGaAs layer is provided.

[0066] Furthermore, in the semiconductor laminate manufacturing method according to this embodiment, the arsenic raw material gas in step ST23, in which the p-type InGaAs layer forming the p-type contact layer 6 is laminated, is tert-butylarsine. In order to increase the amount of carbon doping, it is necessary to laminate the p-type InGaAs layer at a low temperature. However, if arsine is used as the arsenic raw material gas, a p-type InGaAs layer with good crystallinity cannot be laminated at low temperatures of 500°C or below. In contrast, if tert-butylarsine is used as the arsenic raw material gas, tert-butylarsine has a low decomposition temperature and undergoes thermal decomposition at low temperatures of 500°C or below. Therefore, even at low temperatures of 500°C or below, the p-type InGaAs layer can be grown with good crystallinity, and a high-quality p-type InGaAs layer is laminated by low-temperature crystal growth.

[0067] Furthermore, in the semiconductor laminate manufacturing method according to this embodiment, a semiconductor layer with an n-type conductivity is not laminated on the p-type InGaAs layer that forms the p-type contact layer 6. When laminating an n-type semiconductor layer on a p-type InGaAs layer by epitaxial growth, it is necessary to raise the temperature above 500°C in order to dope it with silicon (Si) or the like as a donor. However, at temperatures above 500°C, the carbon contained in the p-type InGaAs layer tends to become inactive. According to the semiconductor laminate manufacturing method of this embodiment, since an n-type semiconductor layer is not laminated on the p-type InGaAs layer, the inactivation of the carbon contained in the p-type InGaAs layer is reduced.

[0068] In semiconductor laminate 1, the p-type InGaAs layer forming the p-type contact layer 6 does not need to be the outermost surface. A cap layer formed of a III-V compound semiconductor such as InP may be laminated on the p-type InGaAs layer.

[0069] Furthermore, in the semiconductor laminate manufacturing method according to this embodiment, the p-type InGaAs layer is not heated above 500°C in step ST23, where the p-type InGaAs layer forming the p-type contact layer 6 is laminated, and in step ST3, which follows step ST23. In other words, in step ST23 and subsequent steps, the temperature at which the p-type InGaAs layer is heated is 500°C or lower. According to the semiconductor laminate manufacturing method of this embodiment, since the p-type InGaAs layer is not heated above 500°C, the deactivation of carbon contained in the p-type InGaAs layer is reduced.

[0070] (Explanation of the structure of a light-emitting device using a semiconductor stack) Next, with reference to Figure 3, a semiconductor laser 10, which is a light-emitting element, will be described as an example of an optical semiconductor element that can be fabricated using the semiconductor laminate 1 according to this embodiment. Figure 3 is a schematic diagram showing the structure of the semiconductor laser 10, which is an optical semiconductor element according to this embodiment. The semiconductor laser 10 according to this embodiment is fabricated using the semiconductor laminate 1 according to this embodiment described above, and comprises a substrate 2, an n-type cladding layer 3, an active layer 4, a p-type cladding layer 5, and a p-type contact layer 6. Furthermore, the semiconductor laser 10 comprises a first electrode 11 which serves as the anode, a second electrode 12 which serves as the cathode, and an insulating film 13. The semiconductor laser 10 is not particularly limited, but for example, it is an end-face emitting type laser diode having a Fabry-Perot structure.

[0071] The insulating film 13 is formed from an insulator such as silicon nitride or silicon oxide. The insulating film 13 can be formed, for example, by chemical vapor deposition.

[0072] The insulating film 13 has a pair of parallel main surfaces, a first main surface 131 and a second main surface 132, located at both ends in the thickness direction. The thickness of the insulating film 13 can be, for example, 0.1 μm or more and 100 μm or less. The insulating film 13 is arranged such that the first main surface 131 is in contact with the second main surface 62 of the p-type contact layer 6. The insulating film 13 has an opening 130 that penetrates through the insulating film 13 in the thickness direction.

[0073] The first electrode 11 is positioned to be in contact with the second main surface 132 of the insulating film 13. The first electrode 11 is made of a conductor such as a metal. For example, the first electrode 11 can be made of a metal layer in which a titanium (Ti) layer, a platinum (Pt) layer, and a gold (Au) layer are stacked in that order. The first electrode 11 is filled into an opening 130 formed in the insulating film 13. As a result, the first electrode 11 is in contact with the second main surface 62 of the p-type contact layer 6 that is exposed at the opening 130.

[0074] The first electrode 11 can be formed, for example, as follows. First, a mask having an opening is formed on the insulating film 13 in the region where the opening 130 of the insulating film 13 will be formed. Then, after the opening 130 is formed in the insulating film 13 using the mask, the first electrode 11 is formed by a suitable conductor, for example, by a vapor deposition method.

[0075] The second electrode 12 is positioned to be in contact with the first main surface 21 of the substrate 2. The second electrode 12 is formed from a conductor such as a metal. For example, the second electrode 12 can be formed from a metal layer in which a titanium layer, a platinum layer, and a gold layer are stacked in that order. The second electrode 12 can be formed on the first main surface 21 of the substrate 2, for example, by a vapor deposition method.

[0076] When a voltage is applied between the first electrode 11 and the second electrode 12, a current flows between them. At this time, holes are injected into the active layer 4 from the first electrode 11 and electrons from the second electrode 12. Then, within the active layer 4, the holes and electrons recombine, generating light. The generated light is confined within the active layer 4, sandwiched between the n-type cladding layer 3 and the p-type cladding layer 5, in the direction of the film thickness of the active layer 4. This light repeatedly reflects between the edges of the active layer 4. As a result, phase-aligned light is amplified, and laser oscillation is achieved. Then, laser light is emitted along arrow α.

[0077] The semiconductor laser 10 according to this embodiment comprises a semiconductor laminate 1 according to this embodiment. Therefore, according to this disclosure, a semiconductor laser 10 having low contact resistance is provided.

[0078] [Explanation of variations] In the embodiments described above, a semiconductor laser (laser diode) is given as an example of the optical semiconductor element of this disclosure, and a semiconductor laminate suitable for the fabrication of a semiconductor laser is also given as an example. The optical semiconductor element of this disclosure is not limited to a semiconductor laser. The optical semiconductor element of this disclosure may be, for example, an LED (Light Emitting Diode) or a solar cell.

[0079] The semiconductor stack of this disclosure does not need to be suitable for the fabrication of optical semiconductor elements, and can be broadly applied to semiconductor devices where it is necessary to reduce the contact resistance of the p-type contact layer to the anode electrode. If the p-type InGaAs layer of this disclosure is used as the p-type contact layer, the layer structure and shape of the first semiconductor layer can be appropriately modified depending on the semiconductor device to which it is applied. Furthermore, in a pn junction formed by joining a p-type semiconductor layer and an n-type semiconductor layer, a semiconductor layer with a high carrier density is necessary to form a tunnel junction region with reduced operating voltage. The semiconductor stack of this disclosure can be broadly applied to semiconductor devices utilizing tunnel junctions. If the p-type InGaAs layer of this disclosure is used as the high-density p-type semiconductor having a high carrier density, the layer structure and shape of the first semiconductor layer can be appropriately modified depending on the semiconductor device to which it is applied. [Examples]

[0080] The relationship between resistivity, carrier density, and carrier mobility of the p-type InGaAs layer described herein was investigated. The investigation procedure is as follows. The resistivity of the p-type InGaAs layer was measured by a four-probe method using the Van der Pauw method after depositing a Ti / Au electrode onto the sample. The carrier density of the p-type InGaAs layer was measured by Hall assay. The carrier mobility of the p-type InGaAs layer was calculated from the measured resistivity and carrier density using the formula (elementary charge × carrier density × carrier mobility × resistivity = 1).

[0081] First, Sample 1 and Sample 2 were prepared using the method described below. Specifically, an InGaAs layer was deposited on a semi-insulating substrate formed of InP doped with iron (Fe) as an impurity by growing undoped InGaAs using metal-organic vapor deposition (CMD). The substrate thickness was 350 nm. The InGaAs layer thickness was 150 nm.

[0082] Then, on this semi-insulating substrate and InGaAs layer, a p-type InGaAs layer was laminated by growing carbon-doped InGaAs using metal-organic vapor deposition (CMD). Carbon tetrabromide was used as the carbon source gas. The concentration of doped carbon was 1.4 × 10⁻⁶. 20 / cm 3 In addition, trimethylindium was used as the raw material gas for indium, triethylgallium for gallium, and tert-butylarsine for arsenic. The substrate temperature when the p-type InGaAs layer was stacked was 400°C.

[0083] Then, a semiconductor laminate in which a p-type InGaAs layer was stacked on a III-V compound semiconductor layer was subjected to heat treatment. The atmosphere, temperature, time, and pressure for the heat treatment of Sample 1 were 450°C, 10 minutes, and 100kPa, respectively. The atmosphere, temperature, time, and pressure for the heat treatment of Sample 2 were nitrogen gas atmosphere, 475°C, 10 minutes, and 100kPa, respectively.

[0084] Table 1 shows the results of measuring the resistivity, carrier density, carrier mobility, and carbon activation rate of the p-type InGaAs layer for Sample 1 and Sample 2, respectively. Figure 4 shows graphs for Sample 1 and Sample 2 with the carrier density of the p-type InGaAs layer on the x-axis and the carrier mobility on the y-axis.

[0085] Samples 3 through 6, for comparison with Samples 1 and 2, are semiconductor stacks described in Non-Patent Document 1. In Samples 3 through 6, p-type InGaAs layers are stacked on a III-V compound semiconductor layer made of InP by growing InGaAs doped with carbon as an impurity using metal-organic vapor deposition.

[0086] In samples 3 through 6, carbon tetrachloride was used as the raw material gas for carbon. The flow rates of carbon tetrachloride used for doping were 1 sccm for sample 3, 4 sccm for sample 4, 7 sccm for sample 5, and 10 sccm for sample 6, as read from the data plotted on the graph shown in Non-Patent Literature 1. In addition, trimethylindium was used as the raw material gas for indium. Triethylgallium was used as the raw material gas for gallium. Arsine was used as the raw material gas for arsenic. The substrate temperature when the p-type InGaAs layer was laminated was 430°C. The atmosphere, temperature, and time of the heat treatment in samples 3 through 6 were argon gas atmosphere, 600°C, and 1 / 6 minute, respectively.

[0087] Table 1 shows the resistivity, carrier density, and carrier mobility of the p-type InGaAs layers for Samples 3 to 6, obtained from data plotted on the graph shown in Non-Patent Literature 1. Figure 4 shows graphs for Samples 3 to 6, with carrier density on the x-axis and carrier mobility on the y-axis. According to Non-Patent Literature 1, the carbon activation rate in Sample 3 is 83.3%.

[0088] [Table 1]

[0089] As can be seen from Table 1 and Figure 4, the resistivity is 2.0 × 10⁻⁶ -3 The semiconductor stacks of Sample 1 and Sample 2, each equipped with a p-type InGaAs layer with a resistivity of Ωcm or less, have a resistivity of 2.0 × 10⁻⁶. -3 Compared to the semiconductor stacks of Samples 3 to 6, which had p-type InGaAs layers exceeding Ωcm, it was confirmed that the p-type InGaAs layer had a higher carrier density and higher carrier mobility.

[0090] The embodiments and examples disclosed herein are illustrative in all respects and should be understood not to be restrictive in any way. The scope of the invention is defined by the claims and not by the foregoing description, and all modifications within the meaning and scope of the claims are intended to be included. [Explanation of Symbols]

[0091] 1. Semiconductor stack 2 circuit boards 3 n-type cladding layer 4 Active layer 5 p-type cladding layer 6. p-type contact layer (p-type InGaAs layer) 7. First Semiconductor Layer 10 Semiconductor lasers 11 1st electrode 12 Second electrode 13 Insulating Film 21 First main surface of the substrate 22 Second main surface of the substrate 31 First main surface of n-type cladding layer 32 Second principal surface of n-type cladding layer 41 First main surface of the active layer 42 Second main surface of the active layer 51 First main surface of the p-type cladding layer 52 Second main surface of the p-type cladding layer 61 First main surface of the p-type contact layer 62 Second main surface of the p-type contact layer 130 Aperture of the insulating film 131 First main surface of insulating film 132 Second main surface of insulating film α arrow

Claims

1. A first semiconductor layer formed from a III-V compound semiconductor, A p-type InGaAs layer is stacked on the first semiconductor layer, and the impurity that generates majority carriers is carbon. Equipped with, The resistivity of the p-type InGaAs layer is 2.0 × 10 －３ A semiconductor laminate with a density of Ωcm or less.

2. The mobility of the majority carriers in the p-type InGaAs layer is 40 cm ２ The semiconductor laminate according to claim 1, wherein the value is / Vs or greater.

3. The density of the majority carriers in the p-type InGaAs layer is 8.0 × 10⁻¹⁶. １９ cm －３ The semiconductor laminate according to claim 1 or 2.

4. The semiconductor laminate according to claim 1 or 2, wherein the activation rate of the impurities in the p-type InGaAs layer is 50% or more.

5. The device comprises a first semiconductor layer formed of a III-V compound semiconductor, and a p-type InGaAs layer stacked on the first semiconductor layer, wherein the impurity generating majority carriers is carbon, and the resistivity of the p-type InGaAs layer is 2.0 × 10⁻¹⁰. －３ A semiconductor laminate with a density of Ωcm or less, An electrode disposed in contact with the p-type InGaAs layer of the semiconductor stack, An optical semiconductor device equipped with the following features.

6. A step of preparing a substrate formed from a III-V compound semiconductor, The process involves stacking semiconductor layers formed from III-V compound semiconductors on the aforementioned substrate by epitaxial growth, A step of heat-treating the semiconductor layer, Equipped with, The process of stacking the semiconductor layer includes stacking a p-type InGaAs layer in which carbon is the impurity that generates the majority carrier, by chemical vapor deposition using organometallic gas as raw material indium, gallium, and arsenic. In the process of laminating the p-type InGaAs layer, the arsenic raw material is tertiary-butylarsine, and the temperature of the substrate is 500°C or lower. A method for manufacturing a semiconductor laminate, wherein in the step of heat-treating the semiconductor layer, the semiconductor layer is heated to a temperature of 500°C or less in an inert gas atmosphere.

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