Flash memory device and method for erasing the same

Abstract

A flash memory device and a method for erasing the same are provided. [Solution] The erasure method includes the steps of: applying an erasure voltage to a target memory block in a memory block; performing a first erasure verification on the target memory block using a first erasure verification voltage; if there are memory cell groups in the target memory block that have not passed the first erasure verification, performing a second erasure verification on the target memory block using a second erasure verification voltage that is higher than the first erasure verification voltage; and, based on the verification results of the first and second erasure verifications, setting a first erasure flag and a second erasure flag corresponding to each memory cell group in the target memory block, classifying each memory cell group, and thereby adjusting the amount of increase in the erasure voltage.

Description

Technical Field

[0001] The present invention relates to a memory device, and particularly to a kind of flash memory device and its erasing method.

Background Art

[0002] A flash memory device can perform write operations, erase operations, and read operations, among which the time required for the erase operation is the longest. Therefore, it can be said that the length of the time required for the erase operation dominates the performance of the flash memory device. If the erase verification still cannot pass after applying the erase voltage multiple times, the erase voltage is increased to reduce the time required for the erase operation. However, the erase speed of each memory cell in a memory block is not the same. Even if only memory cells remain in a memory block and the erase verification has not passed, applying an erase voltage to the entire memory block not only causes an increase in the erase time but also an increase in the leakage current.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The present invention provides a flash memory device and its erasing method, which dynamically adjusts the increase amount of the erase voltage and the application range of the erase voltage to improve the overall efficiency of the erase operation.

Means for Solving the Problems

[0004] The erasure method of the present invention is applied to a flash memory device including a plurality of memory blocks. Each memory block is divided into a plurality of memory cell groups. The erasure method of the flash memory device includes the steps of: applying an erasure voltage to a target memory block in the memory block; performing a first erasure verification on the target memory block using a first erasure verification voltage; if there are memory cell groups in the target memory block that have not passed the first erasure verification, performing a second erasure verification on the target memory block using a second erasure verification voltage that is higher than the first erasure verification voltage; and, based on the verification results of the first and second erasure verifications, setting a first erasure flag and a second erasure flag corresponding to each memory cell group in the target memory block, classifying each memory cell group, and thereby adjusting the amount of increase in the erasure voltage.

[0005] The flash memory device of the present invention includes a memory array, a flag register, and a control circuit. The memory array has a plurality of memory blocks, each memory block is divided into a plurality of memory cell groups. The flag register is configured to store a first erase flag and a second erase flag corresponding to each memory cell group. The control circuit is connected to the memory array and the flag register and is configured to perform an erase operation on a target memory block in the memory blocks. The control circuit applies an erase voltage to the target memory block and performs a first erase verification on the target memory block using a first erase verification voltage. If there are memory cell groups in the target memory block that have not passed the first erase verification, the control circuit performs a second erase verification on the target memory block using a second erase verification voltage that is higher than the first erase verification voltage, and based on the verification results of the first and second erase verifications, sets a first erase flag and a second erase flag corresponding to each memory cell group in the target memory block, classifies each memory cell group, and adjusts the amount of increase in the erase voltage accordingly. [Effects of the Invention]

[0006] Based on the above, the flash memory device and erasure method of the present invention can dynamically adjust the amount of increase in erasure voltage and the application range of erasure voltage based on the type of memory cell group that has not yet passed erasure verification. This not only reduces the erasure time required for the erasure operation, but also avoids an increase in leakage current and improves the overall efficiency of the erasure operation.

[0007] To better understand the above-mentioned features and advantages of the present invention, examples are given below and described in detail with reference to the accompanying drawings. [Brief explanation of the drawing]

[0008] [Figure 1] This is a schematic diagram illustrating the overview of a flash memory device according to one embodiment of the present invention. [Figure 2A] This is a step flowchart of a method for erasing a flash memory device according to one embodiment of the present invention. [Figure 2B] This is a step flowchart of a method for erasing a flash memory device according to one embodiment of the present invention. [Figure 3A] This is a step flowchart of a method for erasing a flash memory device according to one embodiment of the present invention. [Figure 3B] This is a step flowchart of a method for erasing a flash memory device according to one embodiment of the present invention. [Figure 4A] This is a step flowchart of a method for erasing a flash memory device according to one embodiment of the present invention. [Figure 4B] This is a step flowchart of a method for erasing a flash memory device according to one embodiment of the present invention. [Figure 4C] This is a step flowchart of a method for erasing a flash memory device according to one embodiment of the present invention. [Modes for carrying out the invention]

[0009] Referring to Figure 1, a flash memory device 100 of one embodiment of the present invention is, for example, a not-or (NOR) type and includes a memory array 110, a flag register 120, and a control circuit 130. The memory array 110 has a plurality of memory blocks 112. Each memory block 112 is divided into a plurality of memory cell groups 114. Each memory cell group 114 includes a plurality of memory cells, for example, a memory tunnel oxide (ETOX) structure. Each memory block 112 includes, for example, 16 sectors (i.e., 64K bytes) of memory cells, but the present invention does not limit the number of memory blocks 112, memory cell groups 114, and memory cells.

[0010] The flag register 120 stores the erase flag F1 and erase flag F2 corresponding to each memory cell group 114. The initial values ​​of the erase flags F1 and F2 corresponding to each memory cell group 114 are the second logical value (e.g., logical 0). In Figure 1, the flag register 120 is shown independently of the memory array 110 and the control circuit 130, but the flag register 120 may be integrated into the memory array 110 or the control circuit 130.

[0011] The control circuit 130 is connected to the memory array 110 and the flag register 120. Based on the received erase command ECM, the control circuit 130 selects a target memory block 112T from among multiple memory blocks 112 in the memory array 110 and performs an erase operation on the target memory block 112T. The control circuit 130 may be a hardware circuit designed using, for example, a state machine, a central processing unit, or other programmable general-purpose or special-purpose microprocessor, digital signal processor, programmable controller, special-purpose integrated circuit, programmable logic device, or a combination thereof, as well as a hardware description language or any other known digital circuit design method, and implemented using methods such as a field-programmable gate array or a composite programmable logic device.

[0012] Referring simultaneously to Figures 1 and 2A, the erasure method of this embodiment is applied to the flash memory device 100 of Figure 1, and the steps of the erasure method of the embodiment of the present invention will be described below by combining each element of the flash memory device 100. First, in step S200, the control circuit 130 applies an erasure voltage Vers to the target memory block 112T. The initial value of the erasure voltage Vers is, for example, about 15 volts.

[0013] Next, in step S202, the control circuit 130 performs a first erase verification on the target memory block 112T using the first erase verification voltage EV0. Specifically, because the number of sensing amplifiers is limited, the control circuit 130 can only obtain the threshold voltages of multiple memory cells (e.g., 16-byte memory cells) addressed by the access address within the selected memory cell group (one of the memory cell groups 114) of the target memory block 112T at a time, and compares the threshold voltages with the first erase verification voltage EV0. If the threshold voltage is smaller than the first erase verification voltage EV0, it indicates that the corresponding memory cell has passed the first erase verification (erasure successful). If the threshold voltage is not smaller than the first erase verification voltage EV0, it indicates that the corresponding memory cell has not passed the first erase verification (erasure failed).

[0014] Furthermore, the detailed steps for performing the first erase verification on the target memory block 112T using the first erase verification voltage EV0 can be found in each step of Figure 2B. First, in step S210, the control circuit 130 uses the first erase verification voltage EV0 to determine whether the selected memory cell group in the target memory block 112T has passed the first erase verification. As shown in Figure 2B, step S210 includes steps S211, S212, and S213. In step S211, the control circuit 130 uses the first erase verification voltage EV0 to determine whether the multiple memory cells addressed by the access address in the selected memory cell group in the target memory block 112T have passed the first erase verification. If the addressed memory cells have not passed the first erase verification, in step S214, the control circuit 130 determines that the target memory block 112T has not passed the first erase verification. Incidentally, when performing an erase operation on the target memory block 112T, the selected memory cell group is initially, for example, the first memory cell group 114 in the target memory block 112T, and the initial value of the access address corresponds to, for example, the initial address of the first memory cell group 114.

[0015] If the addressed memory cell passes the first erase verification, in step S212 the control circuit 130 determines whether the current access address corresponds to the last address in the selected memory cell group. If NO, in step S213 the control circuit 130 increments the access address to address the remaining memory cells in the selected memory cell group, and returns to step S211 to continue the first erase verification.

[0016] If the current access address corresponds to the last address of the selected memory cell group, in step S215, the control circuit 130 determines that the selected memory cell group has passed the first erase verification. Next, in step S216, the control circuit 130 determines whether the selected memory cell group is the last memory cell group 114 in the target memory block 112T. If NO, in step S217, the control circuit 130 selects the next memory cell group 114 in the target memory block 112T as the selected memory cell group, and returns to step S211 to continue the first erase verification.

[0017] If the selected memory cell group is the last memory cell group 114 in the target memory block 112T, in step S218, the control circuit 130 determines that the target memory block 112T has passed the first erase verification.

[0018] In addition, in this embodiment, when performing the first erase verification on the target memory block 112T each time, the first erase verification is performed on a plurality of memory cells specified by the current access address. Since the access address increases when the addressed memory cells have passed the first erase verification, the first erase verification is not performed repeatedly on the memory cells that have already passed the first erase verification.

[0019] Returning to FIG. 2A, in step S204, if there is a memory cell group 114 in the target memory block 112T that has not passed the first erase verification (that is, the target memory block 112T has not passed the first erase verification), the control circuit 130 performs a second erase verification on the target memory block 112T using a second erase verification voltage EV1 that is higher than the first erase verification voltage EV0. The second erase verification voltage EV1 is, for example, 0.5 to 1 volt higher than the first erase verification voltage EV0.

[0020] Finally, in S206, based on the verification results of the first erase verification and the second erase verification, the control circuit 130 sets the erase flag F1 and the erase flag F2 corresponding to each memory cell group 114 in the target memory block 112T, classifies each memory cell group 114, and thereby adjusts the increase amount of the erase voltage Vers.

[0021] Specifically, the control circuit 130 sets the erase flag F1 corresponding to each memory cell group 114 that has passed the second erase verification to a first logical value (for example, logical 1), and sets the erase flag F2 corresponding to each memory cell group 114 that has not passed the second erase verification to the first logical value. Then, the control circuit 130 classifies the memory cell group 114 in which the erase flag F1 is set to the first logical value (the memory cell group 114 without slow erase cells) as a normal group with a normal erase speed, and classifies the memory cell group 114 in which the erase flag F2 is set to the first logical value (the memory cell group 114 with slow erase cells) as a slow group with a slow erase speed. By the above method, the control circuit 130 can increase the increase amount of the erase voltage Vers for the memory cell group 114 classified into the slow group, reduce the erase time required for the slow group, and improve the overall efficiency of the erase operation.

[0022] The erasure method of this disclosure will be described in more detail below with reference to the embodiments shown in Figures 3A and 3B. Referring simultaneously to Figures 1, 3A, and 3B, each step of the erasure method of the embodiment of the present invention will be described below by combining each element of the flash memory device 100. In this embodiment, parts that are the same or similar to those of the previously described embodiments will not be repeated. First, in step S300, the control circuit 130 applies an erasure voltage Vers to the target memory block 112T. Next, in step S302, the control circuit 130 uses a first erasure verification voltage EV0 to determine whether the target memory block 112T has passed the first erasure verification. Specifically, the control circuit 130 can determine whether a plurality of memory cells addressed by the current access address in the target memory block 112T have passed the first erasure verification. If a plurality of memory cells addressed by the current access address have passed the first erasure verification, the control circuit 130 continues to increase the access address and repeatedly performs the first erasure verification on the subsequent plurality of memory cells. In step S302, if the control circuit 130 determines that the last memory cell group 114 in the target memory block 112T has also passed the first erase verification, it indicates that the target memory block 112T has passed the first erase verification. At this point, the control circuit 130 terminates the erase method of this embodiment.

[0023] In step S302, if multiple memory cells addressed by the current access address have not passed the first erase verification, it indicates that there is a group of memory cells 114 in the target memory block 112T that has not passed the first erase verification (i.e., the target memory block 112T has not passed the first erase verification). At this time, in step S304, the control circuit 130 accumulates the number of times the erase voltage Vers has been applied and determines whether the number of applications has reached a specified number (e.g., 8 or 16 times). If NO, in step S306 the control circuit 130 holds the erase voltage Vers without changing it, and then returns to step S300 to continue applying the erase voltage Vers to the target memory block 112T. In this way, the control circuit 130 repeatedly applies the erase voltage Vers to the target memory block 112T until all memory cell groups 114 in the target memory block 112T have passed the first erase verification.

[0024] Each time the number of times the erase voltage Vers is applied reaches a specified number (if YES is given in step S304), in step S308 the control circuit 130 resets the number of applications and sequentially performs a second erase verification on all memory cell groups 114 in the target memory block 112T using the second erase verification voltage EV1, thereby identifying all memory cell groups 114 in the target memory block 112T that can pass the second erase verification.

[0025] Next, in step S310, the control circuit 130 sets the erase flag F1 corresponding to each memory cell group 114 that has passed the second erase verification to the first logical value, and sets the erase flag F2 corresponding to each memory cell group 114 that has not passed the second erase verification to the first logical value.

[0026] Next, in step S312, the control circuit 130 determines whether all memory cell groups 114 in the target memory block 112T, where the erase flag F1 is set to the first logical value, have passed the first erase verification. If NO, in step S314, the control circuit 130 raises the erase voltage Vers by a first increment ΔVA (e.g., 0.4 to 0.5 volts), and then returns to step S300 to continue applying the now adjusted erase voltage Vers to the target memory block 112T.

[0027] If all memory cell groups 114 in the target memory block 112T, where the erase flag F1 is set to the first logical value, pass the first erase verification, it indicates that all memory cell groups 114 classified as normal have passed the first erase verification, and only the memory cell groups 114 classified as slow have not passed the first erase verification. At this point, the process proceeds to step S316 in Figure 3B via node A. In step S316, the control circuit 130 increases the erase voltage Vers by a second increase amount ΔVB (e.g., 0.8 to 1 volt) which is greater than the first increase amount ΔVA. Next, in step S318, the control circuit 130 applies the erase voltage Vers only to all memory cell groups 114 in the target memory block 112T where the erase flag F2 is set to the first logical value (all memory cell groups 114 classified as slow).

[0028] Next, in step S320, the control circuit 130 uses the first erase verification voltage EV0 to determine whether all memory cell groups 114 in the target memory block 112T, where the erase flag F2 is set to the first logical value, have passed the first erase verification. Specifically, the control circuit 130 determines whether multiple memory cells addressed by the current access address in the target memory block 112T have passed the first erase verification. If multiple memory cells addressed by the current access address have passed the first erase verification, the control circuit 130 can continue to adjust the access address based on the addresses of all memory cell groups 114 (all memory cell groups 114 classified as slow groups) where the erase flag F2 is set to the first logical value, and repeatedly perform the first erase verification on subsequent memory cells within the memory cell groups 114 classified as slow groups. If the control circuit 130 determines that the last memory cell group 114 among all memory cell groups 114 where the erase flag F2 is set to the first logical value has passed the first erase verification, it indicates that all memory cell groups 114 classified as slow groups have passed the first erase verification (if YES in step S320). At this point, the control circuit 130 terminates the erasure method of this embodiment.

[0029] If multiple memory cells addressed by the current access address have not passed the first erase verification, it indicates that there is a memory cell group 114 in the target memory block 112T that has not yet passed the first erase verification and whose erase flag F2 is set to the first logical value (i.e., a memory cell group 114 classified as a slow group) (if NO in step S320). At this time, in step S322, the control circuit 130 accumulates the number of times the erase voltage Vers has been applied and determines whether the number of applications has reached a specified number. If NO, in step S324 the control circuit 130 holds the erase voltage Vers without changing it, and then returns to step S318 to continue applying the erase voltage Vers to all memory cell groups 114 in the target memory block 112T whose erase flag F2 is set to the first logical value. As a result, the control circuit 130 can repeatedly apply the erase voltage Vers to all memory cell groups 114 in the target memory block 112T where the erase flag F2 is set to the first logical value (i.e., all memory cell groups 114 classified as slow groups) until all memory cell groups 114 in the target memory block 112T where the erase flag F2 is set to the first logical value pass the first erase verification.

[0030] Each time the number of times the erase voltage Vers is applied reaches a specified number (if YES is given in step S322), in step S326 the control circuit 130 resets the number of applications, then returns to step S316 to increase the erase voltage Vers by the second increment amount ΔVB, and in step S318 continues to apply the currently adjusted erase voltage Vers to the target memory block 112T.

[0031] By the method described above, the control circuit 130 can increase the amount of erase voltage Vers after all memory cell groups 114 classified as normal have passed the first erase verification, and can limit the application range of erase voltage Vers to memory cell groups 114 classified as slow. This not only reduces the erase time required for slow groups but also prevents normal groups from continuously generating leakage current, thereby improving the overall efficiency of the erase operation.

[0032] The erasure method of the present invention will be described in detail below with reference to another embodiment. Referring simultaneously to Figures 1 and 4A to 4C, each step of the erasure method of the embodiment of the present invention will be described below by combining each element of the flash memory device 100. In this embodiment, parts that are the same or similar to those of the previously described embodiments will not be repeated. First, in step S400, the control circuit 130 applies the erasure voltage Vers to the target memory block 112T. Next, in step S402, the control circuit 130 uses the first erasure verification voltage EV0 to sequentially perform the first erasure verification on all memory cell groups 114 in the target memory block 112T, and identifies all memory cell groups 114 in the target memory block 112T that can pass the first erasure verification.

[0033] Next, in step S404, the control circuit 130 sets the erase flag F1 corresponding to each memory cell group 114 in the target memory block 112T that has passed the first erase verification to the first logical value. Next, in step S406, the control circuit 130 determines whether there is a memory cell group 114 in the target memory block 112T whose erase flag F1 is held as the second logical value. If NO, it indicates that all memory cell groups 114 in the target memory block 112T have passed the first erase verification. At this point, the control circuit 130 terminates the erase method of this embodiment.

[0034] If there is a memory cell group 114 in the target memory block 112T in which the erase flag F1 is held as the second logical value, in step S408 the control circuit 130 uses the second erase verification voltage EV1 to sequentially perform a second erase verification on all memory cell groups 114 in the target memory block 112T in which the erase flag F1 is held as the second logical value, and identifies all memory cell groups 114 in the target memory block 112T that can pass the second erase verification.

[0035] Next, in step S410, the control circuit 130 sets the erase flag F2 corresponding to each memory cell group 114 that has not passed the second erase verification to the first logical value, and then proceeds to step S412 in Figure 4B via node B.

[0036] In step S412, the control circuit 130 increases the erase voltage Vers by a first increment ΔVA. Next, in step S414, the control circuit 130 applies the erase voltage Vers only to all memory cell groups 114 in the target memory block 112T where both erase flag F1 and erase flag F2 are held at the second logical value. Next, in step S416, the control circuit 130 uses the first erase verification voltage EV0 to determine whether all memory cell groups 114 in the target memory block 112T where both erase flag F1 and erase flag F2 are held at the second logical value have passed the first erase verification. If NO, in step S418, the control circuit 130 determines whether the number of times the erase voltage Vers has been applied has reached a specified number. If the number of times the erase voltage Vers has been applied has not reached the specified number of times, in step S420 the control circuit 130 holds the erase voltage Vers without changing it, and then returns to step S414 to continue applying the erase voltage Vers to all memory cell groups 114 in the target memory block 112T where both erase flag F1 and erase flag F2 are held at the second logical value. In this way, the control circuit 130 can repeatedly apply the erase voltage Vers to all memory cell groups 114 in the target memory block 112T where both erase flag F1 and erase flag F2 are held at the second logical value until all memory cell groups 114 in the target memory block 112T where both erase flag F1 and erase flag F2 are held at the second logical value pass the first erase verification.

[0037] Each time the number of times the erase voltage Vers is applied reaches a specified number (if YES is given in step S418), in step S422 the control circuit 130 resets the number of applications, then returns to step S412 to increase the erase voltage Vers by the first increment ΔVA, and in step S414 continues to apply the currently adjusted erase voltage Vers to all memory cell groups 114 in the target memory block 112T where both erase flag F1 and erase flag F2 are held at the second logical value.

[0038] If all memory cell groups 114 in the target memory block 112T where both erase flag F1 and erase flag F2 are held at the second logical value pass the first erase verification (if YES in step S416), in step S424 the control circuit 130 sets the erase flag F1 corresponding to each memory cell group 114 that passed the first erase verification to the first logical value, and then proceeds to step S426 in Figure 4C via node C.

[0039] In step S426, the control circuit 130 increases the erase voltage Vers by the second increment ΔVB. Next, in step S428, the control circuit 130 applies the erase voltage Vers only to all memory cell groups 114 in the target memory block 112T where the erase flag F1 is held at the second logical value and the erase flag F2 is set to the first logical value. Next, in step S430, the control circuit 130 uses the first erase verification voltage EV0 to determine whether all memory cell groups 114 in the target memory block 112T where the erase flag F1 is held at the second logical value and the erase flag F2 is set to the first logical value have passed the first erase verification. If NO, in step S432, the control circuit 130 determines whether the number of times the erase voltage Vers has been applied has reached a specified number. If the number of times the erase voltage Vers has been applied has not reached the specified number of times, in step S434 the control circuit 130 holds the erase voltage Vers without changing it, and then returns to step S428 to continue applying the erase voltage Vers to all memory cell groups 114 in the target memory block 112T where the erase flag F1 is held at the second logical value and the erase flag F2 is set to the first logical value. In this way, the control circuit 130 can repeatedly apply the erase voltage Vers to all memory cell groups 114 in the target memory block 112T where the erase flag F1 is held at the second logical value and the erase flag F2 is set to the first logical value until all memory cell groups 114 in the target memory block 112T where the erase flag F1 is held at the second logical value and the erase flag F2 is set to the first logical value pass the first erase verification.

[0040] Each time the number of times the erase voltage Vers is applied reaches a specified number (if YES is given in step S432), in step S436 the control circuit 130 resets the number of applications, then returns to step S426 to increase the erase voltage Vers by the second increment amount ΔVB, and in step S428 continues to apply the currently adjusted erase voltage Vers to all memory cell groups 114 in the target memory block 112T where the erase flag F1 is held at the second logical value and the erase flag F2 is set to the first logical value.

[0041] If all memory cell groups 114 in the target memory block 112T where the erase flag F1 is held as the second logical value and the erase flag F2 is set as the first logical value pass the first erase verification (if YES in step S430), then in step S438 the control circuit 130 sets the erase flag F1 corresponding to each memory cell group 114 that passed the first erase verification to the first logical value.

[0042] In one embodiment, if the total number of times the control circuit 130 applies the erase voltage Vers to the target memory block 112T becomes too high, the control circuit 130 can directly abandon (stop) the erase operation performed on the target memory block 112T, thereby avoiding excessive waste of erase time.

[0043] In summary, the flash memory device and erasure method of the present invention can dynamically adjust the amount of increase in erasure voltage and the application range of erasure voltage based on the type of memory cell group that has not yet passed erasure verification. This not only reduces the number of times the erasure voltage is applied and the erasure time required for the erasure operation, but also prevents memory cell groups classified as normal from continuously generating leakage current, thereby improving the overall efficiency of the erasure operation. [Industrial applicability]

[0044] The flash memory device and erasure method of the present invention can be applied to perform a memory erasure operation. [Explanation of Symbols]

[0045] 100 Flash memory devices 110 memory arrays 112 memory blocks 112T Target Memory Block 114 Memory Cell Groups 120 Flag Register 130 Control circuits ECM erase command EV0 First erasure verification voltage EV1 Second erasure verification voltage F1 First Elimination Flag F2 Second erase flag ΔVA First increase ΔVB Second increase S200~S206, S210~S218, S300~S326, S400~S438 Step

Claims

1. A method for erasing a flash memory device, wherein the flash memory device includes a plurality of memory blocks, and each of the plurality of memory blocks is divided into a plurality of memory cell groups, The erasure method described above is: The steps include applying an erase voltage to a target memory block among the plurality of memory blocks, A step of performing a first erase verification on the target memory block using the first erase verification voltage, If there is a group of memory cells in the target memory block that has not passed the first erasure verification, the step of performing a second erasure verification on the target memory block using a second erasure verification voltage that is higher than the first erasure verification voltage, Based on the verification results of the first erasure verification and the second erasure verification, a first erasure flag and a second erasure flag corresponding to each of the plurality of memory cell groups in the target memory block are set, each of the plurality of memory cell groups is classified, and the amount of increase in the erasure voltage is adjusted accordingly. A method of erasure that includes [this].

2. The step of performing the first erasure verification on the target memory block using the first erasure verification voltage is: Using the first erasure verification voltage, it is determined whether the selected memory cell group in the target memory block has passed the first erasure verification, If the selected memory cell group passes the first erasure verification, it is determined whether the selected memory cell group is the last memory cell group in the target memory block. If YES, it is determined that the target memory block has passed the first erase verification, If NO, the next group of memory cells in the target memory block is selected as the first erase verification group. The erasure method according to claim 1, including the method described in claim 1.

3. The step of determining whether the selected memory cell group in the target memory block has passed the first erasure verification using the first erasure verification voltage is: Using the first erasure verification voltage, it is determined whether a plurality of memory cells addressed by the access address in the selected memory cell group have passed the first erasure verification. If the multiple memory cells that have been addressed have passed the first erasure verification, it is determined whether the current access address corresponds to the last address of the selected memory cell group. If YES, it is determined that the selected memory cell group has passed the first erasure verification, If NO, the access address is increased to specify a number of subsequent memory cells in the selected memory cell group and perform the first erase verification. The erasure method according to claim 2, including the method described in claim 2.

4. If there is a group of memory cells in the target memory block that has not passed the first erase verification, the step of performing the second erase verification on the target memory block using a second erase verification voltage that is higher than the first erase verification voltage is: If there are memory cell groups in the target memory block that have not passed the first erase verification, the erase voltage is repeatedly applied to the target memory block until all of the plurality of memory cell groups in the target memory block have passed the first erase verification. The number of times the erase voltage is applied is accumulated, Each time the number of applications reaches a predetermined number, the number of applications is reset, and the second erase verification is performed sequentially on all memory cell groups in the target memory block using the second erase verification voltage, The step of setting the first erase flag and the second erase flag corresponding to each of the plurality of memory cell groups in the target memory block based on the verification results of the first erase verification and the second erase verification is as follows: The first erase flag corresponding to each of the plurality of memory cell groups that has passed the second erase verification is set to the first logical value, and the second erase flag corresponding to each of the plurality of memory cell groups that has not passed the second erase verification is set to the first logical value. The erasure method according to claim 1, including the method described in claim 1.

5. The step of classifying each of the plurality of memory cell groups is: The memory cell group in which the first erase flag is set to the first logical value is classified as a normal group, The memory cell group in which the second erase flag is set to the first logical value is classified as a slow group, The erasure method according to claim 4, including the method described in claim 4.

6. The step of adjusting the amount of increase in the erase voltage is as follows: Determining whether all of the plurality of memory cell groups in the target memory block, where the first erase flag is set to the first logical value, have passed the first erase verification, If NO, the erase voltage is increased by the first increment, and the erase voltage is continuously applied to the target memory block. In the case of YES, the erase voltage is increased by a second increase amount greater than the first increase amount, and the erase voltage is applied to all of the plurality of memory cell groups in the target memory block where the second erase flag is set to the first logical value. The erasure method according to claim 4, including the method described in claim 4.

7. After the step of applying the erase voltage to all of the plurality of memory cell groups in the target memory block in which the second erase flag is set to the first logical value, Using the first erase verification voltage, it is determined whether all of the plurality of memory cell groups in the target memory block, where the second erase flag is set to the first logical value, have passed the first erase verification. If NO, the erase voltage is repeatedly applied to all of the plurality of memory cell groups in the target memory block where the second erase flag is set to the first logical value, until all of the plurality of memory cell groups in the target memory block where the second erase flag is set to the first logical value pass the first erase verification. Each time the number of times the erase voltage is applied reaches the specified number of times, the number of applications is reset and the erase voltage is increased by the second increment amount. The erasure method according to claim 6, including the method described in claim 6.

8. If there is a group of memory cells in the target memory block that has not passed the first erase verification, the step of performing the second erase verification on the target memory block using a second erase verification voltage that is higher than the first erase verification voltage is: The first erase flag corresponding to each of the plurality of memory cell groups that have passed the first erase verification in the target memory block is set to a first logical value, To determine whether there is a group of memory cells in the target memory block in which the first erase flag is held as a second logical value, In the case of YES, the second erase verification is performed sequentially for all of the plurality of memory cell groups in the target memory block in which the first erase flag is held in the second logical value, using the second erase verification voltage. The erasure method according to claim 1, including the method described in claim 1.

9. The step of setting the first erase flag and the second erase flag corresponding to each of the plurality of memory cell groups in the target memory block based on the verification results of the first erase verification and the second erase verification is as follows: This includes setting the second erase flag corresponding to each of the plurality of memory cell groups that has not passed the second erase verification to the first logical value, The step of adjusting the amount of increase in the erase voltage is as follows: The erase voltage is increased by the first increase amount, Applying the erase voltage to all of the plurality of memory cell groups in the target memory block in which both the first erase flag and the second erase flag are held in the second logical value, Using the first erasure verification voltage, it is determined whether all of the plurality of memory cell groups in the target memory block, in which both the first erasure flag and the second erasure flag are held in the second logical value, have passed the first erasure verification. In the case of YES, the first erase flag corresponding to each of the plurality of memory cell groups that has passed the first erase verification is set to the first logical value, If NO, the erase voltage is repeatedly applied to all of the plurality of memory cell groups in the target memory block where both the first erase flag and the second erase flag are held in the second logical value, until all of the plurality of memory cell groups in the target memory block where both the first erase flag and the second erase flag are held in the second logical value pass the first erase verification. Each time the number of times the erase voltage is applied reaches a predetermined number, the number of applications is reset and the erase voltage is increased by the first increment amount. The erasure method according to claim 8, including the method described in claim 8.

10. After the step of setting the first erase flag corresponding to each of the plurality of memory cell groups that have passed the first erase verification to the first logical value, further, The erase voltage is increased by a second increase amount that is greater than the first increase amount, The erase voltage is applied to all of the plurality of memory cell groups in the target memory block in which the first erase flag is held in the second logical value and the second erase flag is set to the first logical value. Using the first erase verification voltage, it is determined whether all of the plurality of memory cell groups in the target memory block, in which the first erase flag is held in the second logical value and the second erase flag is set to the first logical value, have passed the first erase verification. In the case of YES, the first erase flag corresponding to each of the plurality of memory cell groups that has passed the first erase verification is set to the first logical value, If NO, the erase voltage is repeatedly applied to all of the plurality of memory cell groups in the target memory block where the first erase flag is held at the second logical value and the second erase flag is set at the first logical value, until all of the plurality of memory cell groups in the target memory block where both the first erase flag and the second erase flag are held at the second logical value pass the first erase verification. Each time the number of times the erase voltage is applied reaches the specified number of times, the number of applications is reset and the erase voltage is increased by the second increment amount. The erasure method according to claim 9, including the method described in claim 9.

11. A memory array having multiple memory blocks, each of which is divided into multiple memory cell groups, A flag register configured to store a first erase flag and a second erase flag corresponding to each of the plurality of memory cell groups, A control circuit connected to the memory array and the flag register, configured to perform an erase operation on a target memory block among the plurality of memory blocks, It has, The control circuit applies an erase voltage to the target memory block and performs a first erase verification on the target memory block using the first erase verification voltage. If there are memory cell groups in the target memory block that have not passed the first erase verification, the control circuit performs a second erase verification on the target memory block using a second erase verification voltage that is higher than the first erase verification voltage, and based on the verification results of the first and second erase verifications, sets the first erase flag and the second erase flag corresponding to each of the plurality of memory cell groups in the target memory block, classifies each of the plurality of memory cell groups, and thereby adjusts the amount of increase in the erase voltage, in a flash memory device.

12. The control circuit uses the first erase verification voltage to determine whether the selected memory cell group in the target memory block has passed the first erase verification. If the selected memory cell group passes the first erase verification, the control circuit determines whether the selected memory cell group is the last memory cell group in the target memory block; if YES, the control circuit determines that the target memory block has passed the first erase verification; if NO, the control circuit performs the first erase verification on the next memory cell group in the target memory block as the selected memory cell group, according to claim 11.

13. The control circuit uses the first erase verification voltage to determine whether a plurality of memory cells addressed by the access address in the selected memory cell group have passed the first erase verification. If the multiple memory cells that have been addressed have passed the first erase verification, the control circuit determines whether the current access address corresponds to the last address of the selected memory cell group; if YES, the control circuit determines that the selected memory cell group has passed the first erase verification; if NO, the control circuit increments the access address to address the subsequent multiple memory cells in the selected memory cell group and performs the first erase verification, the flash memory device according to claim 12.

14. If there are memory cell groups in the target memory block that have not passed the first erase verification, the control circuit repeatedly applies the erase voltage to the target memory block until all of the plurality of memory cell groups in the target memory block have passed the first erase verification. The control circuit accumulates the number of times the erase voltage is applied, and each time the number of applications reaches a predetermined number, the control circuit resets the number of applications and sequentially performs the second erase verification on all of the multiple memory cell groups in the target memory block using the second erase verification voltage. The flash memory device according to claim 11, wherein the control circuit sets the first erase flag corresponding to each of the plurality of memory cell groups that have passed the second erase verification to the first logical value, and sets the second erase flag corresponding to each of the plurality of memory cell groups that have not passed the second erase verification to the first logical value.

15. The flash memory device according to claim 14, wherein the control circuit classifies the memory cell group in which the first erase flag is set to the first logical value into a normal group, and the memory cell group in which the second erase flag is set to the first logical value into a slow group.

16. The flash memory device according to claim 14, wherein the control circuit determines whether all of the plurality of memory cell groups in the target memory block whose first erase flag is set to the first logical value have passed the first erase verification; if NO, the control circuit increases the erase voltage by a first increment and continues to apply the erase voltage to the target memory block; if YES, the control circuit increases the erase voltage by a second increment greater than the first increment and applies the erase voltage to all of the plurality of memory cell groups in the target memory block whose second erase flag is set to the first logical value.

17. The control circuit uses the first erase verification voltage to determine whether all of the plurality of memory cell groups in the target memory block, where the second erase flag is set to the first logical value, have passed the first erase verification. If NO, the control circuit repeatedly applies the erase voltage to all of the plurality of memory cell groups in the target memory block, where the second erase flag is set to the first logical value, until all of the plurality of memory cell groups in the target memory block, where the second erase flag is set to the first logical value, have passed the first erase verification. The flash memory device according to claim 16, wherein each time the number of times the erase voltage is applied reaches the predetermined number of times, the control circuit resets the number of applications and increases the erase voltage by the second increment amount.

18. The control circuit sets the first erase flag corresponding to each of the plurality of memory cell groups that have passed the first erase verification in the target memory block to a first logical value. The flash memory device according to claim 11, wherein the control circuit determines whether there is a memory cell group in the target memory block in which the first erase flag is held as a second logical value, and if YES, the control circuit uses the second erase verification voltage to sequentially perform the second erase verification on all of the plurality of memory cell groups in the target memory block in which the first erase flag is held as a second logical value.

19. The control circuit sets the second erase flag corresponding to each of the plurality of memory cell groups that has not passed the second erase verification to the first logical value. The control circuit increases the erase voltage by a first increment and applies the erase voltage to all of the plurality of memory cell groups in the target memory block where both the first erase flag and the second erase flag are held in the second logical value. The control circuit uses the first erase verification voltage to determine whether all of the plurality of memory cell groups in the target memory block, where both the first erase flag and the second erase flag are held at the second logical value, have passed the first erase verification. If YES, the control circuit sets the first erase flag corresponding to each of the plurality of memory cell groups that have passed the first erase verification to the first logical value. If NO, the control circuit repeatedly applies the erase voltage to all of the plurality of memory cell groups in the target memory block, where both the first erase flag and the second erase flag are held at the second logical value, until all of the plurality of memory cell groups in the target memory block, where both the first erase flag and the second erase flag are held at the second logical value, have passed the first erase verification. The flash memory device according to claim 18, wherein each time the number of times the erase voltage is applied reaches a predetermined number of times, the control circuit resets the number of applications and increases the erase voltage by the first increment amount.

20. The control circuit increases the erase voltage by a second increase amount that is greater than the first increase amount, and applies the erase voltage to all of the plurality of memory cell groups in the target memory block in which the first erase flag is held at the second logical value and the second erase flag is set to the first logical value. The control circuit uses the first erase verification voltage to determine whether all of the plurality of memory cell groups in the target memory block in which the first erase flag is held at the second logical value and the second erase flag is set at the first logical value have passed the first erase verification. If YES, the control circuit sets the first erase flag corresponding to each of the plurality of memory cell groups that have passed the first erase verification to the first logical value. If NO, the control circuit repeatedly applies the erase voltage to all of the plurality of memory cell groups in the target memory block in which the first erase flag is held at the second logical value and the second erase flag is set at the first logical value until all of the plurality of memory cell groups in the target memory block in which both the first erase flag and the second erase flag are held at the second logical value have passed the first erase verification. The flash memory device according to claim 19, wherein each time the number of times the erase voltage is applied reaches the predetermined number of times, the control circuit resets the number of applications and increases the erase voltage by the second increment amount.

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