Memory systems and semiconductor memory devices

Abstract

To provide a memory system and semiconductor memory device that can reduce circuit area. [Solution] The memory system comprises a plurality of semiconductor memory devices and a control device. Each of the plurality of semiconductor memory devices comprises a first memory cell array, a second memory cell array, a first data signal input / output terminal usable for outputting data read from the first memory cell array, a second data signal input / output terminal usable for outputting data read from the second memory cell array, and a first control terminal capable of receiving a toggle signal from the control device when outputting data read from at least one of the first memory cell array and the second memory cell array. The control device toggles the signal of the first control terminal at a substantially constant frequency, regardless of whether data input / output is being performed via the first data signal input / output terminal and the second data signal input / output terminal.

Claims

1. Multiple semiconductor memory devices, Control device and Equipped with, Each of the aforementioned plurality of semiconductor memory devices is: A first memory cell array including multiple first memory cell transistors connected in series, A second memory cell array including multiple second memory cell transistors connected in series, A first data signal input / output terminal that can be used for outputting data read from the first memory cell array and inputting data to be written to the first memory cell array, A second data signal input / output terminal that can be used for outputting data read from the second memory cell array and inputting data to be written to the second memory cell array, When outputting data read from at least one of the first memory cell array and the second memory cell array, a first control terminal capable of receiving a toggle signal from the control device and Equipped with, The control device is Regardless of whether data input / output is being performed via the first data signal input / output terminal and the second data signal input / output terminal, the signal of the first control terminal is toggled at a substantially constant frequency. Memory system.

2. The first data signal input / output terminal is, A data signal path is provided between the first memory cell array and the first memory cell array, It does not have a data signal path between the second memory cell array and the other, The second data signal input / output terminal is, A data signal path is provided between the second memory cell array and the second memory cell array, It does not have a data signal path to the first memory cell array. The memory system according to claim 1.

3. The data read from the first memory cell array is output from the first data signal input / output terminal and not from the second data signal input / output terminal. The data read from the second memory cell array is output from the second data signal input / output terminal and not from the first data signal input / output terminal. The memory system according to claim 1.

4. The control device is From the timing of the start of input of a command set instructing the semiconductor memory to perform a read operation to the timing of the end of input of a command set instructing the semiconductor memory to perform a data out operation, the signal of the first control terminal is toggled at the substantially constant frequency. The memory system according to claim 1.

5. When the control device starts the data-out operation, it inputs a command set and a first command to the semiconductor memory device to instruct the data-out operation. The semiconductor memory device starts outputting data after the first control terminal has been toggled multiple times following the input of the first command. The memory system according to claim 1.

6. When the control device starts the data-out operation, it inputs a command set and a first command to the semiconductor memory device to instruct the data-out operation. The semiconductor memory device outputs dummy data after the first command is input and the first control terminal is toggled multiple times, and then starts outputting data. The memory system according to claim 1.

7. The control device, upon completion of the data output operation, inputs a second command to the semiconductor memory device. The semiconductor memory device terminates data output after the first control terminal has been toggled multiple times following the input of the second command. The memory system according to claim 5.

8. The control device, upon completion of the data output operation, inputs a second command to the semiconductor memory device. The semiconductor memory device terminates data output after the first control terminal has been toggled multiple times following the input of the second command. The memory system according to claim 6.

9. Each of the aforementioned semiconductor memory devices further comprises a data strobe signal input / output terminal, During the data output operation, the data output via at least one of the first data signal input / output terminal and the second data signal input / output terminal is switched at the timing of the falling edge and rising edge of the voltage of the data strobe signal input / output terminal. The memory system according to claim 1.

10. Each of the aforementioned semiconductor memory devices further comprises a data strobe signal input / output terminal, At the first timing, the data-out operation corresponding to the first memory cell array is initiated. At a second timing after the first timing, the data-out operation corresponding to the second memory cell array is initiated. The data-out operation corresponding to the first memory cell array is completed at a third timing that occurs after the second timing. If the data-out operation corresponding to the second memory cell array is completed at a fourth timing after the third timing, The signals at the aforementioned data strobe signal input / output terminals continue to switch from the first timing to the fourth timing. The memory system according to claim 1.

11. The input of data to be written to the first memory cell array can be performed in parallel with the output of data read from the second memory cell array and the input of data to be written to the second memory cell array. The memory system according to claim 1.

12. A first memory cell array including multiple first memory cell transistors connected in series, A second memory cell array including multiple second memory cell transistors connected in series, A first data signal input / output terminal that can be used for outputting data read from the first memory cell array and inputting data to be written to the first memory cell array, A second data signal input / output terminal that can be used for outputting data read from the second memory cell array and inputting data to be written to the second memory cell array, Equipped with, The first data signal input / output terminal is, A data signal path is provided between the first memory cell array and the first memory cell array, It does not have a data signal path between the second memory cell array and the other, The second data signal input / output terminal is, A data signal path is provided between the second memory cell array and the second memory cell array, It does not have a data signal path to the first memory cell array. Semiconductor memory device.

13. The data read from the first memory cell array is output from the first data signal input / output terminal and not from the second data signal input / output terminal. The data read from the second memory cell array is output from the second data signal input / output terminal and not from the first data signal input / output terminal. The semiconductor memory device according to claim 12.

14. Further equipped with a first control terminal, The semiconductor memory device starts outputting data after the first control terminal has been toggled multiple times following the input of the first command. The semiconductor memory device according to claim 12.

15. Further equipped with a first control terminal, The semiconductor memory device outputs dummy data after the first command is input and the first control terminal is toggled multiple times, and then starts outputting data. The semiconductor memory device according to claim 12.

16. The semiconductor memory device terminates data output after the first control terminal has been toggled multiple times following the input of the second command. The semiconductor memory device according to claim 14.

17. The semiconductor memory device terminates data output after the first control terminal has been toggled multiple times following the input of the second command. The semiconductor memory device according to claim 15.

18. It is further equipped with data strobe signal input / output terminals, During the data output operation, the data output via at least one of the first data signal input / output terminal and the second data signal input / output terminal is switched at the timing of the falling edge and rising edge of the voltage of the data strobe signal input / output terminal. The semiconductor memory device according to claim 12.

19. It is further equipped with data strobe signal input / output terminals, At the first timing, the data-out operation corresponding to the first memory cell array is initiated. At a second timing after the first timing, the data-out operation corresponding to the second memory cell array is initiated. The data-out operation corresponding to the first memory cell array is completed at a third timing that occurs after the second timing. If the data-out operation corresponding to the second memory cell array is completed at a fourth timing after the third timing, The signals at the aforementioned data strobe signal input / output terminals continue to switch from the first timing to the fourth timing. The semiconductor memory device according to claim 12.

20. The input of data to be written to the first memory cell array can be performed in parallel with the output of data read from the second memory cell array and the input of data to be written to the second memory cell array. The semiconductor memory device according to claim 12.

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