Pixel circuit and display device including pixel circuit

Abstract

The present invention provides a pixel circuit capable of adjusting the optical viewing angle using a single light-emitting element, and a display device including the pixel circuit. [Solution] The pixel circuit according to the present invention comprises a light-emitting element, a driving element for driving the light-emitting element, a compensation circuit including a first capacitor including a first electrode to which a first data voltage is applied through a data line and a second electrode connected to the gate electrode of the driving element, a first switch element to which a predetermined second data voltage is supplied through the data line, and a second capacitor including a first electrode connected to the second electrode of the first switch element and a second electrode connected to a power line to which a common voltage is applied.

Description

Technical Field

[0001] The present invention relates to a pixel circuit and a display device including the pixel circuit.

Background Art

[0002] A viewing angle variable technology is applied to a display device. The viewing angle variable technology can project video content and visual information reproduced by the display device only to users within a narrow viewing angle range, or project it to a plurality of users existing within a wide viewing angle range.

[0003] As the future car market such as electric vehicles and autonomous driving vehicles expands, the demand for vehicle display devices is rapidly increasing. Research is underway on a method of dividing the screen of a vehicle display device and controlling a part of the screen at a narrow viewing angle and another part at a wide viewing angle. This technology drives pixels with a narrow viewing angle arranged in a partial area of the screen to display personal content and information that can be viewed only by specific users, and drives pixels with a wide viewing angle arranged in other areas of the screen to display shared content that can be viewed by many users together.

[0004] In a vehicle display device, the display panel of an organic light emitting display device has attracted attention. The organic light emitting display device includes an organic light emitting diode (hereinafter referred to as "OLED") that emits light by itself, and has advantages such as a fast response speed, high luminous efficiency, high brightness, and a large viewing angle. The organic light emitting display device not only has a fast response speed, excellent luminous efficiency, brightness, viewing angle, etc., but also can express the black gradation as a complete black, so it is also excellent in contrast ratio and color reproducibility. The display panel of the organic light emitting display device can be bent flexibly, so a curved surface can be easily realized. As a result, the market share of the organic light emitting display device in the vehicle display device market has been rapidly increasing.

Summary of the Invention

Problems to be Solved by the Invention

[0005] Each pixel applied to a vehicle display device includes two lenses with different optical viewing angles and two light-emitting elements. Since the two light-emitting elements are connected to a single transistor, the size of the light-emitting element is reduced, and therefore the lifespan of the light-emitting element is also shortened.

[0006] The present invention aims to solve the aforementioned needs and / or problems.

[0007] The present invention provides a pixel circuit capable of adjusting the optical viewing angle using a single light-emitting element, and a display device including the same.

[0008] The problems that the present invention addresses are not limited to those mentioned above, and any further problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0009] A pixel circuit according to an embodiment of the present invention may include a light-emitting element, a driving element for driving the light-emitting element, a compensation circuit including a first capacitor which includes a first electrode to which a first data voltage is applied through a data line and a second electrode connected to the gate electrode of the driving element, a first switch element to which a predetermined second data voltage is supplied through the data line, and a second capacitor which includes a first electrode connected to the second electrode of the first switch element and a second electrode connected to a power line to which a common voltage is applied.

[0010] A display device according to an embodiment of the present invention comprises a display panel including a display area in which a plurality of subpixels are arranged, the display panel comprising a substrate, a circuit layer disposed on the upper part of the substrate, a light-emitting element layer disposed on the upper part of the circuit layer, a sealing layer disposed on the upper part of the light-emitting element layer, a first electrode including a plurality of electrode patterns disposed spaced apart from each other on the upper part of the sealing layer, a liquid crystal layer covering the first electrode, and a second electrode disposed on the upper part of the liquid crystal layer, wherein a predetermined data voltage can be applied to each of the plurality of electrode patterns included in the first electrode, and a predetermined common voltage can be applied to the second electrode. [Effects of the Invention]

[0011] The present invention provides one light-emitting element for each pixel, forms a liquid crystal lens layer on top of the light-emitting element layer where the light-emitting elements are arranged, and selectively applies a data voltage to the liquid crystal lens layer, thereby enabling adjustment of the optical viewing angle using only one light-emitting element without using two lenses and two light-emitting elements.

[0012] Since this invention uses one light-emitting element per pixel, there is no need to reduce the size of the light-emitting elements, which can potentially extend the lifespan of the light-emitting elements.

[0013] The present invention can embody various forms of liquid crystal lens layers, either pixel-wise or region-wise.

[0014] This invention can improve the lifespan of light-emitting elements and enable operation at low power.

[0015] The effects of the present invention are not limited to those mentioned above, and any further effects not mentioned will be clearly understood by those skilled in the art from the description of the claims. [Brief explanation of the drawing]

[0016] [Figure 1] This is a block diagram showing a display device according to a first embodiment of the present invention. [Figure 2]This is a diagram showing a pixel circuit according to the first embodiment of the present invention. [Figure 3a] This is a diagram showing the driving waveforms for each mode of the pixel circuit shown in FIG. 2. [Figure 3b] This is a diagram showing the driving waveforms for each mode of the pixel circuit shown in FIG. 2. [Figure 4a] This is a diagram for explaining the operating principle of the pixel circuit based on the waveform shown in FIG. 3b. [Figure 4b] This is a diagram for explaining the operating principle of the pixel circuit based on the waveform shown in FIG. 3b. [Figure 4c] This is a diagram for explaining the operating principle of the pixel circuit based on the waveform shown in FIG. 3b. [Figure 4d] This is a diagram for explaining the operating principle of the pixel circuit based on the waveform shown in FIG. 3b. [Figure 5] This is a diagram showing the cross-section of a pixel in the display panel shown in FIG. 1. [Figure 6a] This is a diagram for explaining the shape of the first electrode shown in FIG. 5. [Figure 6b] This is a diagram for explaining the shape of the first electrode shown in FIG. 5. [Figure 7a] This is a diagram for explaining the liquid crystal lens layer shown in FIG. 5. [Figure 7b] This is a diagram for explaining the liquid crystal lens layer shown in FIG. 5. [Figure 7c] This is a diagram for explaining the liquid crystal lens layer shown in FIG. 5. [Figure 8] This is a diagram for explaining the principle of adjusting the light viewing angle in pixel units. [Figure 9a] This is a diagram showing the form of the electrode pattern formed for each sub-pixel. [Figure 9b] This is a diagram showing the form of the electrode pattern formed for each sub-pixel. [Figure 10a] This is a diagram for explaining another shape of the first electrode shown in FIG. 5. [Figure 10b] This is a diagram for explaining another shape of the first electrode shown in FIG. 5. [Figure 11] This diagram illustrates the principle by which the optical field of view is adjusted on a region-by-region basis. [Figure 12a] This is a diagram illustrating the principle of mode switching according to the first embodiment of the present invention. [Figure 12b] This is a diagram illustrating the principle of mode switching according to the first embodiment of the present invention. [Figure 12c] This is a diagram illustrating the principle of mode switching according to the first embodiment of the present invention. [Figure 12d] This is a diagram illustrating the principle of mode switching according to the first embodiment of the present invention. [Figure 13] This figure shows a pixel circuit according to a second embodiment of the present invention. [Figure 14a] This figure shows the mode-specific drive waveforms of the pixel circuit shown in Figure 13. [Figure 14b] This figure shows the mode-specific drive waveforms of the pixel circuit shown in Figure 13. [Figure 15a] Figure 14b is a diagram illustrating the operating principle of a pixel circuit based on the waveform shown. [Figure 15b] Figure 14b is a diagram illustrating the operating principle of a pixel circuit based on the waveform shown. [Figure 15c] Figure 14b is a diagram illustrating the operating principle of a pixel circuit based on the waveform shown. [Figure 15d] Figure 14b is a diagram illustrating the operating principle of a pixel circuit based on the waveform shown. [Modes for carrying out the invention]

[0017] The advantages and features of the present invention, as well as methods for achieving them, will become clearer with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and can be embodied in a variety of different forms, and the embodiments are provided merely to complete the disclosure of the present invention and to fully inform those who are ordinary skill in the art to which the present invention pertains, and the present invention is defined only by the scope of the claims.

[0018] The shapes, sizes, proportions, angles, numbers, etc., disclosed in the drawings illustrating embodiments of the present invention are illustrative, and the present invention is not limited to what is shown in the drawings. Throughout the specification, the same reference numerals represent the same components. Furthermore, in describing the present invention, if it is determined that a specific description of related prior art would unnecessarily obscure the gist of the present invention, such detailed description will be omitted.

[0019] Wherever words such as "equipped with," "possess," "include," "have," and "consist of" are used as referred to herein, other parts may be added unless "only" or "solely" is used. When a component is expressed singly, it may be interpreted as including multiple components unless otherwise explicitly stated.

[0020] When interpreting the constituent elements, they shall be interpreted as including a margin of error, even if not explicitly stated otherwise.

[0021] When describing a spatial relationship, for example, "on top of," "above," "below," or "next to," if the spatial relationship between two parts is described, then, unless "immediately" or "directly" is used, one or more other parts can be located between the two parts.

[0022] In describing the embodiments, terms such as "first," "second," etc., are used to describe various components, but these components are not limited by these terms. These terms are used simply to distinguish one component from another. Therefore, the first component referred to below may also be the second component within the technical concept of the present invention.

[0023] Throughout the specification, the same reference numeral represents the same component.

[0024] The features of the various embodiments can be partially or entirely combined or linked together, enabling a variety of technically interconnected and driven configurations. Each embodiment can be implemented independently of the others, or they can be implemented together in a related manner.

[0025] Various embodiments of the present invention will be described in detail below with reference to the attached drawings.

[0026] In the display device of the present invention, the pixel circuit and the gate drive circuit may include a plurality of transistors. The transistors may be oxide TFTs (Thin Film Transistors) containing oxide semiconductors, or LTPSTFTs containing low-temperature polysilicon (LTPS).

[0027] A transistor is a three-electrode device consisting of a gate, source, and drain. The source is the electrode that supplies carriers to the transistor. Within the transistor, carriers flow out from the source. The drain is the electrode through which carriers exit the transistor. In a transistor, carriers flow from the source to the drain. In an n-channel transistor, since the carriers are electrons, the source voltage is lower than the drain voltage so that electrons can flow from the source to the drain. In an n-channel transistor, the direction of current flows from the drain to the source. In a p-channel transistor, since the carriers are holes, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain may change depending on the applied voltage. Therefore, the invention is not limited by the source and drain of the transistor. In the following explanation, the source and drain of the transistor will be referred to as the first electrode and the second electrode.

[0028] The gate signal can swing between the gate-on voltage and the gate-off voltage. The gate-on voltage is set to a voltage higher than the transistor's threshold voltage. The gate-off voltage is set to a voltage lower than the transistor's threshold voltage.

[0029] A transistor turns on in response to the gate-on voltage and turns off in response to the gate-off voltage. In the case of an n-channel transistor, the gate-on voltage can be the gate-high voltage and the gate-off voltage can be the gate-low voltage. In the case of a p-channel transistor, the gate-on voltage can be the gate-low voltage and the gate-off voltage can be the gate-high voltage.

[0030] Figure 1 is a block diagram showing a display device according to a first embodiment of the present invention.

[0031] Referring to Figure 1, the display device according to the first embodiment of the present invention comprises a display panel 100 and a display panel driving circuit for writing pixel data to the pixels of the display panel 100. Furthermore, the display device comprises a power supply unit 150.

[0032] The display panel 100 may be, but is not limited to, a rectangular panel having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. For example, the display panel 100 may be an irregularly shaped panel in which at least a portion is curved or elliptical.

[0033] The display area AA of the display panel 100 includes a pixel array for displaying the input video. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 that intersect the data lines 102, and pixels arranged in a matrix. The display panel 100 may further include power lines commonly connected to the pixels. The power lines are commonly connected to the pixel circuits and can supply the voltage necessary to drive the pixels 101.

[0034] Each of the pixels 101 may be divided into a red subpixel, a green subpixel, and a blue subpixel for color embodiment. Each pixel may further contain a white subpixel. Each subpixel contains a pixel circuit for driving a light-emitting element. The light-emitting element may include an OLED or an inorganic LED (Light Emitting Diode). Each pixel circuit is connected to data lines, gate lines, and power lines. Hereafter, pixels may be interpreted as subpixels.

[0035] Display area AA includes multiple pixel lines L1 to Ln. Each of the pixel lines L1 to Ln contains one line of pixels arranged along the line direction (X-axis direction) in the pixel array of the display panel 100. Pixels arranged in one pixel line share the gate line 103. Subpixels arranged in the column direction Y along the data line direction share the same data line 102. One horizontal period is the time obtained by dividing one frame period by the total number of pixel lines L1 to Ln.

[0036] The display panel 100 can be implemented as an opaque display panel or a transparent display panel. A transparent display panel can be applied to a transparent display device in which an image is projected onto the screen and the real object in the background is visible through it. The display panel 100 can be manufactured from a flexible display panel that can be bent flexibly.

[0037] The power supply unit 150 receives an input voltage from the host system 300 and outputs the voltage necessary to drive the pixels 101 of the display panel 100 and the display panel drive circuit. For this purpose, the power supply unit 150 may include a DC-DC converter. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, etc. Through the DC-DC converter, the power supply unit 150 can output constant voltages (or DC voltages) such as gate-on voltage, gate-off voltage, pixel drive voltage, cathode voltage, reference voltage, and IC drive voltage of the display panel drive circuit. The gate-on voltage and gate-off voltage can be supplied to the level shifter 140 and the gate drive unit 120. Voltages such as the pixel drive voltage, cathode voltage, and reference voltage can be supplied to the pixels 101 through a power line commonly connected to the pixels 101.

[0038] The power supply unit 150 may further include a gamma voltage generation unit. The gamma voltage generation unit receives inputs of a high-potential reference voltage and a low-potential reference voltage and outputs a plurality of gamma reference voltages divided at predetermined intervals on a preset gamma curve, for example, a 2.2 gamma curve. The gamma reference voltages are supplied to the data drive unit 110. In the data drive unit 110, the gamma reference voltages are divided by a voltage divider circuit and subdivided into gradation voltages. The gamma voltage generation unit may be implemented by a programmable gamma circuit that can adjust the voltage of each gamma reference voltage according to the digital data. A timing controller 130 or a host system 300 or another external device can update the digital data stored in the register of the programmable gamma circuit via a communication interface.

[0039] The display panel drive circuit writes the pixel data of the input video to the pixels 101 of the display panel 100 under the control of the timing controller 130. The display panel drive circuit includes a data drive unit 110 and a gate drive unit 120.

[0040] The display panel drive circuit may further include a touch sensor drive unit for driving the touch sensor. The touch sensor drive unit is omitted in Figure 1. The data drive unit 110 and the touch sensor drive unit can be integrated into a single source drive IC.

[0041] The data drive unit 110 receives pixel data of the input video, which is received as a digital signal from the timing controller 130, and outputs a data voltage. The data drive unit 110 also receives a gamma reference voltage and can generate a gradation-specific gamma compensation voltage through a voltage divider circuit. The gradation-specific gamma compensation voltage is supplied to a digital-to-analog converter (DAC) located in each channel of the data drive unit 110.

[0042] The data drive unit 110 samples the digital data received from the timing controller 130, latches it, and then inputs the digital data to the DAC. Here, the digital data includes the pixel data of the input video. The DAC converts the pixel data into a gamma-compensated voltage and outputs the data voltage of the pixel data.

[0043] The gate drive unit 120 may be formed in the display panel 100 together with the circuit elements and wiring of the display area AA. The gate drive unit 120 may be positioned on at least one non-display area NA on the left and right sides outside the display area AA in the display panel 100, or at least a portion of it may be positioned within the display area AA.

[0044] The gate drive unit 120 sequentially outputs gate signal pulses to the gate line 103 under the control of the timing controller 130. The gate drive unit 120 can sequentially supply the gate signal to the gate line 103 by shifting the gate signal pulses using a shift register. When multiple gate signals are applied to each pixel, the gate drive unit 120 may include multiple shift registers. The gate signal may include a scan signal and an emission signal (or EM signal) input to the pixel circuit through multiple gate lines.

[0045] The gate drive unit 120 can be positioned in the non-display area using the GIP (Gate In Panel) method, or it can be positioned between subpixels (SP) in the display area AA using the GIA (Gate In Active Area) method.

[0046] The timing controller 130 receives digital video data of the input video and timing signals synchronized with this data from the host system 300. The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, etc. The vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted because the vertical and horizontal periods can be determined by counting the data enable signal DE. The horizontal synchronization signal Hsync and the data enable signal DE have a period of 1 horizontal period (1H).

[0047] The timing controller 130 can control the display panel drive circuit by generating data timing control signals to control the operation timing of the data drive unit 110, gate timing control signals to control the operation timing of the gate drive unit 120, etc., based on the vertical synchronization signal Vsync, horizontal synchronization signal Hsync, and data enable signal DE received from the host system 300. The timing controller 130 can synchronize the data drive unit 110 and the gate drive unit 120 by controlling the operation timing of the display panel drive circuit.

[0048] The gate timing control signal output from the timing controller 130 can be input to the shift register of the gate drive unit 120 via the level shifter 140. The level shifter 140 can convert the voltage level of the gate timing signal received from the timing controller 130 into a swing width between the gate on voltage and the gate off voltage, and supply it to the gate drive unit 120.

[0049] The timing controller 130 analyzes the input video frame by frame, generates a control signal to selectively output a gate signal according to the results of the analysis, and can provide the generated control signal to the shift register of the gate drive unit 120 via the level shifter 140.

[0050] The host system 200 may include one mainboard from among a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a vehicle system, a mobile terminal, or a wearable terminal. The host system 200 can scale the video signal from the video source to match the resolution of the display panel 100 and transmit it to the timing controller 130 along with the timing signal.

[0051] Figure 2 shows a pixel circuit according to a first embodiment of the present invention.

[0052] Referring to Figure 2, the pixel circuit according to the first embodiment of the present invention comprises a light-emitting element EL, a driving element DT for driving the light-emitting element EL, a compensation circuit 10 including a first capacitor Cst, a switching element T1, and a second capacitor Csel. The compensation circuit 10 further includes a plurality of switching elements T2 to T6. The driving element DT and the plurality of switching elements T1 to T6 may be, but are not limited to, p-channel transistors.

[0053] The driver element DT generates a current in response to the gate-source voltage Vgs to drive the light-emitting element EL. The driver element DT includes a first electrode connected to a first power line PL1 to which the pixel driving voltage VDD is applied, a gate electrode connected to a second node n2, and a second electrode connected to a third node n3.

[0054] A light-emitting element (EL) can be embodied by an OLED. The EL includes an anode electrode, a cathode electrode, and an organic compound layer formed between these electrodes. The anode electrode of the EL is connected to a fourth node n4, and the cathode electrode is connected to a second power line PL2 to which the pixel basis voltage VSS is applied. The organic compound layer may, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), a light emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The EL can also be embodied by a tandem structure in which multiple light emission layers are stacked. Tandem structures of ELs can improve pixel brightness and lifetime.

[0055] The first switch element T1 is connected between the fifth node n5 and the data line DL. The first switch element T1 is turned on in response to the gate-on voltage VGL of the third scan signal SCAN3, connecting the fifth node n5 to the data line DL to which the second data voltage Vdata2 is applied. The first switch element T1 includes a first electrode connected to the data line DL, a gate electrode to which the third scan signal SCAN3 is applied, and a second electrode connected to the fifth node n5.

[0056] The second switch element T2 is connected between the data line DL and the first node n1. The second switch element T2 is turned on in response to the gate-on voltage VGL of the first scan signal SCAN1 and applies the first data voltage Vdata1 of the pixel data to the first node n1. The second switch element T2 includes a first electrode connected to the data line DL, a gate electrode to which the first scan signal SCAN1 is applied, and a second electrode connected to the first node n1.

[0057] The third switching element T3 is connected between the second node n2 and the third node n3. The third switching element T3 is turned on in response to the gate-on voltage VGL of the second scan signal SCAN2, and connects the gate electrode of the driving element DT to the second electrode. The third switching element T3 includes a first electrode connected to the second node n2, a gate electrode to which the second scan signal SCAN2 is applied, and a second electrode connected to the third node n3.

[0058] The fourth switch element T4 is connected between the first node n1 and the third power supply line PL3. The fourth switch element T4 is turned on in response to the gate-on voltage VGL of the light emission control signal EM, connecting the first node n1 to the third power supply line PL3. The fourth switch element T4 includes a first electrode connected to the first node n1, a gate electrode to which the light emission control signal EM is applied, and a second electrode connected to the third power supply line PL3.

[0059] The fifth switch element T5 is connected between the third node n3 and the fourth node n4. The fifth switch element T5 is turned on in response to the gate-on voltage VGL of the light emission control signal EM, connecting the third node n3 to the fourth node n4. The fifth switch element T5 includes a first electrode connected to the third node n3, a gate electrode to which the light emission control signal EM is applied, and a second electrode connected to the fourth node n4.

[0060] The sixth switch element T6 is connected between the fourth node n4 and the third power line PL3. The sixth switch element T6 is turned on in response to the gate-on voltage VGL of the second scan signal SCAN2, connecting the fourth node n4 to the third power line PL3 to which the reference voltage Vref is applied. The sixth switch element T6 includes a first electrode connected to the third power line PL3, a gate electrode to which the second scan signal SCAN2 is applied, and a second electrode connected to the fourth node n4.

[0061] The first capacitor Cst is connected between the first node n1 and the second node n2. The second capacitor Csel is connected between the fifth node n5 and the fourth power line PL4 to which the common voltage VCOM is applied.

[0062] When the second switching element T2 is turned on, the first data voltage Vdata1 applied through the data line DL can charge the first capacitor Cst, and when the first switching element T1 is turned on, the second data voltage Vdata2 can charge the second capacitor Csel.

[0063] Figures 3a and 3b show the mode-specific drive waveforms of the pixel circuit shown in Figure 2, and Figures 4a to 4d are diagrams illustrating the operating principle of the pixel circuit shown in Figure 3b.

[0064] Referring to Figures 3a and 3b, the pixel circuit is driven in the following order in the first and second modes: initialization period Ti, data writing and sensing period Tw / s, selection period Tsel, and emission period Tem.

[0065] In the first mode, the light emitted from the light-emitting element can be emitted over a wide viewing angle, while in the second mode, the light emitted from the light-emitting element can be emitted over a narrow viewing angle.

[0066] Referring to Figure 4a, during the initialization period Ti, the first switch element T1 and the second switch element T2 are turned off, the third to sixth switch elements T3 to T6 are turned on, and the reference voltage Vref is applied to the first node n1 and the second node n2.

[0067] Referring to Figure 4b, during the data writing and sensing period Tw / s, the first switch element T1 and the fourth and fifth switch elements T4 and T5 are turned off, while the second switch element T2, the third switch element T3, and the sixth switch element T6 are turned on. As a result, the first data voltage Vdata1 of the pixel data is applied to the first node n1, the pixel drive voltage VDD is applied to the drive element, and the threshold voltage Vth of the drive element is sensed, so that the voltage at the second node n2 becomes VDD + Vth. In addition, the reference voltage Vref is applied to the fourth node n4.

[0068] Referring to Figure 4c, during the selection period Tsel, in the first mode, the first to sixth switch elements T1 to T6 are turned off; in the second mode, the second to sixth switch elements T2 to T6 are turned off, the first switch element T1 is turned on, and the second data voltage Vdata2 is applied to the fifth node n5.

[0069] Since the data writing and sensing period Tw / s and the selection period Tsel are intervals in which different data voltages are applied, the selection period Tsel can be started at least 1H after the end of the data writing and sensing period Tw / s in order to make the data voltage variable.

[0070] Referring to Figure 4d, during the light emission period Tem, the first to third switch elements T1 to T3 and the sixth switch element T6 are turned off, the fourth switch element T4 and the fifth switch element T5 are turned on, and the current generated according to the gate-source voltage of the drive element DT is supplied to the light-emitting element EL, causing it to emit light. As a result, the voltage at the first node n1 becomes "Vref", and the voltage at the second node n2 becomes "Vref - Vdata + VDD + Vth".

[0071] During the emission period TEM, in the first mode, the second data voltage Vdata2 is not applied to the second capacitor Csel, thus maintaining a wide optical field of view. In the second mode, the optical field of view narrows due to the second data voltage Vdata2 applied to the second capacitor Csel and the common voltage VCOM.

[0072] Figure 5 is a diagram showing a cross-section of a pixel in the display panel shown in Figure 1, Figures 6a and 6b are diagrams illustrating the shape of the first electrode shown in Figure 5, and Figures 7a to 7c are diagrams illustrating the liquid crystal lens layer shown in Figure 5.

[0073] Referring to Figure 5, the display panel 100 according to the first embodiment of the present invention may include a substrate 10, a circuit layer 12, a light-emitting element layer 14, a sealing layer 16, and a liquid crystal lens layer 18.

[0074] The substrate 10 may be made of a flexible plastic. For example, the substrate 10 may be made of a single-layer or multi-layer substrate of a material selected from polyimide, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyethersulfone, polyarylate, polysulfone, or cyclic-olefin copolymer, but is not limited to these. For example, the substrate 10 may be a ceramic substrate or a glass substrate.

[0075] The circuit layer 12 may include pixel circuits connected to wiring such as data lines, gate lines, and power lines, gate drive units connected to gate lines, and circuits for demultiplexer arrays and autoprobe testing, which are omitted in the drawings. The wiring and circuit elements of the circuit layer 12 may include multiple insulating layers, two or more metal layers separated by insulating layers, and an active layer containing semiconductor material. All transistors formed on the circuit layer 12 may, but are not limited to, n-channel type TFTs containing oxide semiconductors.

[0076] The light-emitting element layer 14 may include light-emitting elements (EL) driven by a pixel circuit. The light-emitting elements (EL) may include red (R) light-emitting elements, green (G) light-emitting elements, and blue (B) light-emitting elements. The light-emitting element layer 14 may include white light-emitting elements and a color filter. The light-emitting elements (EL) of the light-emitting element layer 14 may be covered by a protective layer including an organic film and a protective film.

[0077] The sealing layer 16 covers the light-emitting layer 14 so as to seal the circuit layer 12 and the light-emitting layer 14. The sealing layer 16 may also be a multilayer insulating film structure in which organic and inorganic films are alternately stacked. The inorganic film blocks the penetration of moisture and oxygen. The organic film flattens the surface of the inorganic film. When multiple layers of organic and inorganic films are stacked, the movement paths of moisture and oxygen become longer compared to a single layer, so the penetration of moisture and oxygen that would affect the light-emitting layer 14 can be effectively blocked.

[0078] A liquid crystal lens layer 18 can be formed on the sealing layer 16. The liquid crystal lens layer 18 plays a role in adjusting the optical viewing angle. The liquid crystal lens layer 18 includes a first glass layer GL1, a first electrode E1, a liquid crystal layer LCL, a second electrode E2, a second glass layer GL2, and a spacer SPA.

[0079] A first glass layer GL1 may be placed on top of the sealing layer 16. A first electrode E1 may be placed on top of the first glass layer GL1, and a liquid crystal layer LCL may be placed over the first electrode E1. A second electrode E2 may be placed on top of the liquid crystal layer LCL. A second glass layer GL2 may be placed on top of the second electrode E2.

[0080] The first electrode E1 includes multiple electrode patterns P1, P2, and P3, which are not electrically connected to each other. The multiple electrode patterns P1, P2, and P3 may be circular rings as shown in Figure 6a, or square rings as shown in Figure 6b, but are not limited to these.

[0081] Multiple electrode patterns P1, P2, and P3 may include a first electrode pattern P1, a second electrode pattern P2, and a third electrode pattern P3. The first electrode pattern P1 may be larger than the second electrode pattern P2, and the second electrode pattern P2 may be larger than the third electrode pattern P3. The thickness D of the first electrode pattern P1, the second electrode pattern P2, and the third electrode pattern P3 may be the same.

[0082] The second electrode pattern P2 may be positioned inside the first electrode pattern P1 at a certain distance L, and the third electrode pattern P3 may be positioned inside the second electrode pattern P2 at a certain distance L.

[0083] Unlike the first electrode, the second electrode E2 may be formed by a single electrode within the display area.

[0084] Spacer SPA can separate the liquid crystal layer at the pixel level to adjust the optical viewing angle, but is not limited to this. For example, spacer SPA can separate the liquid crystal layer at the region level.

[0085] A second data voltage is applied to the first electrode E1, and a common voltage is applied to the second electrode E2. This causes the refractive indices of the liquid crystal material within the liquid crystal layer to differ, which can result in different optical viewing angles.

[0086] In the first embodiment, as shown in Figure 7a, different second data voltages are applied to the first to third electrode patterns P1, P2, and P3 of the first electrode so that the refractive index of the liquid crystal material differs depending on the position. The level of the second data voltage applied to the first to third electrode patterns may decrease as you move from the central region of the pixel to the outer region. The first electrode pattern P1 located in the central region may be applied with the highest third-level second data voltage Vdata2_B, the second electrode pattern P2 may be applied with a second-level second data voltage Vdata2_G which is lower than the first level, and the third electrode pattern P3 located in the outermost region may be applied with a third-level second data voltage Vdata2_R which is lower than the second level.

[0087] A common voltage is applied to the second electrode, and different levels of second data voltages are applied to each of the first to third electrode patterns of the first electrode, so that the refractive index of the liquid crystal material differs depending on the region in which each of the first to third electrode patterns is arranged, as shown by the dotted line in Figure 7b.

[0088] For example, the region where the first electrode pattern is placed may be formed with the smallest refractive index, the region where the second electrode pattern is placed may be formed with an intermediate refractive index, and the region where the third electrode pattern is placed may be formed with the largest refractive index.

[0089] To explain further, as shown in Figure 7c, when the second data voltage is not applied to the first electrode E1, no electric field is applied to the liquid crystal material of the liquid crystal layer LCL. As a result, the liquid crystal molecules within the liquid crystal material take on a first axial direction horizontal to the first glass layer GL1, for example, the X-axis direction. This causes the light emitted by the light-emitting element to be scattered, thereby widening the optical viewing angle.

[0090] On the other hand, when a predetermined second data voltage is applied to the first electrode E1, an electric field is applied to the liquid crystal material of the liquid crystal layer LCL by the second data voltage applied to the first electrode E1 and the common voltage applied to the second electrode E2. As a result, the liquid crystal molecules in the liquid crystal material take on a second axis perpendicular to the first glass layer GL1, for example, the Y-axis direction. This causes the light emitted by the light-emitting element to maintain its straight-line propagation, thus narrowing the optical viewing angle.

[0091] At this time, the orientation of the liquid crystal molecules changes according to the level of the second data voltage. In other words, the higher the level of the second data voltage, the closer the liquid crystal molecules can get in the Y-axis direction.

[0092] Figure 8 is a diagram illustrating the principle by which the optical field of view is adjusted on a pixel-by-pixel basis, and Figures 9a and 9b show the morphology of the electrode patterns formed for each subpixel.

[0093] Referring to Figure 8, numerous electrode patterns P1, P2, and P3 are formed for each subpixel R, G, and B. If a second data voltage is not applied to these numerous electrode patterns P1, P2, and P3, a wide optical field of view can be formed.

[0094] On the other hand, if a second data voltage is applied to multiple electrode patterns P1, P2, and P3, but each of these electrode patterns has a different refractive index, as shown by the dotted line, then a narrow optical field of view may be formed.

[0095] In the first embodiment, a first electrode can be arranged for each pixel. For example, as shown in Figure 9a, a first electrode can be arranged for each red subpixel R, green subpixel G, and blue subpixel B, and the optical field of view can be adjusted on a pixel-by-pixel basis.

[0096] The first electrode pattern of each of the red subpixel R, green subpixel G, and blue subpixel B may be commonly applied with the second data voltage Vdata2_R applied to the red subpixel R; the second electrode pattern may be commonly applied with the second data voltage Vdata_G applied to the green subpixel G; and the third electrode pattern may be commonly applied with the second data voltage Vdata_B applied to the blue subpixel B.

[0097] As yet another example, as shown in Figure 9b, a first electrode is placed for each red subpixel R, green subpixel G, blue subpixel B, and white subpixel W, but the first electrode is composed of four first electrode patterns P1, second electrode pattern P2, third electrode pattern P3, and fourth electrode pattern P4, and the optical field of view can be adjusted on a pixel-by-pixel basis.

[0098] The first electrode pattern P1 of each of the red subpixel R, green subpixel G, blue subpixel B, and white subpixel W is commonly applied with the second data voltage Vdata2_W applied to the white subpixel W; the second electrode pattern P2 is commonly applied with the second data voltage Vdata2_R applied to the red subpixel R; the third electrode pattern P3 is commonly applied with the second data voltage Vdata_G applied to the green subpixel G; and the fourth electrode pattern P4 is commonly applied with the second data voltage Vdata_B applied to the blue subpixel B.

[0099] As shown in Figure 9b, when composed of four subpixels, the number of electrode patterns is greater and the refractive index distribution can be formed more gently than when composed of three subpixels, as shown in Figure 9a. The electrode patterns described here are merely examples and are not limited to them.

[0100] Figures 10a and 10b illustrate other shapes of the first electrode shown in Figure 5.

[0101] Referring to Figures 10a and 10b, multiple electrode patterns P1, P2, and P3 are formed in predetermined regions where multiple subpixels R, G, and B are arranged, and different second data voltages Vdata2_R, Vdata2_G, and Vdata2_B can be applied to each region. Therefore, the optical field of view can be adjusted on a region-by-region basis.

[0102] The numerous electrode patterns P1, P2, and P3 may be circular rings, as shown in Figure 9a, or square rings, as shown in Figure 9b, but are not limited to these.

[0103] The first electrode pattern P1 can be larger than the second electrode pattern P2, and the second electrode pattern P2 can be larger than the third electrode pattern P3. The thickness D of the first electrode pattern P1, the second electrode pattern P2, and the third electrode pattern P3 can be the same.

[0104] The second electrode pattern P2 may be positioned inside the first electrode pattern P1 at a certain distance L, and the third electrode pattern P3 may be positioned inside the second electrode pattern P2 at a certain distance L.

[0105] Here, we describe an example where three subpixels R, G, and B are placed in a single region, but this is not the only example. For instance, if the display area is divided into n regions, a number of electrode patterns P1, P2, and P3 can be formed in each of the n regions.

[0106] Figure 11 is a diagram illustrating the principle by which the optical field of view is adjusted on a region-by-region basis.

[0107] Referring to Figure 11, multiple electrode patterns P1, P2, and P3 are formed in each predetermined region where multiple subpixels R, G, and B are arranged, and the optical field of view can be widened when no second data voltage is applied to the multiple electrode patterns P1, P2, and P3.

[0108] On the other hand, if a second data voltage is applied to multiple electrode patterns P1, P2, and P3, but each of the multiple electrode patterns P1, P2, and P3 has a different refractive index from the others, as shown by the dotted line, then the optical field of view may be narrowed.

[0109] Figures 12a to 12d are diagrams illustrating the principle of mode switching according to the first embodiment of the present invention.

[0110] Referring to Figure 12a, in the first embodiment of the present invention, when the display area is divided into nine regions, a number of electrode patterns P1, P2, and P3 can be formed in each of the nine regions. Each of these nine divided regions can be driven individually in the first mode and the second mode.

[0111] As an example, as shown in Figure 12b, the display area can be further divided into two zones, with six zones A11, A12, A13, A21, A22, and A23 contained within one zone being driven in the first mode, and the remaining three zones A31, A32, and A33 contained within the other zone being driven in the second mode.

[0112] As another example, as shown in Figure 12c, the display area can be further divided into two zones, with six zones A11, A21, A31, A12, A22, and A32 contained within one zone being driven in the first mode, and the remaining three zones A13, A23, and A33 contained within the other zone being driven in the second mode.

[0113] As another example, as shown in Figure 12d, the display area can be further divided into two zones, with eight zones A11, A12, A13, A21, A23, A31, A32, and A33 contained within one zone being driven in the first mode, and the remaining zone A22 contained within the other zone being driven in the second mode.

[0114] The reason why such various driving modes are possible is that the mode can be switched on a pixel-by-pixel or region-by-region basis. The examples described here are just a few examples and are not limited to them.

[0115] Figure 13 shows a pixel circuit according to a second embodiment of the present invention.

[0116] Referring to Figure 13, a pixel circuit according to a second embodiment of the present invention comprises a light-emitting element EL, a driving element DT for driving the light-emitting element EL, a compensation circuit 10 including a first capacitor Cst, a switching element T1, and a second capacitor Csel. The compensation circuit 10 further includes a plurality of switching elements T2 to T10. The driving element DT and the plurality of switching elements T1 to T9 may be, but are not limited to, p-channel transistors.

[0117] The driving element DT generates a current in accordance with the gate-source voltage Vgs and drives the light-emitting element EL. The driving element DT includes a first electrode connected to the third node n3, a gate electrode connected to the fourth node n4, and a second electrode connected to the fifth node n5.

[0118] A light-emitting element (EL) can be embodied by an OLED. The EL includes an anode electrode, a cathode electrode, and an organic compound layer formed between these electrodes. The anode electrode of the EL is connected to a sixth node n6, and the cathode electrode is connected to a second power line PL2 to which the pixel basis voltage VSS is applied. The organic compound layer may, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), a light emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The EL can also be embodied by a tandem structure in which multiple light emission layers are stacked. Tandem structures of ELs can improve pixel brightness and lifetime.

[0119] The first switch element T1 is connected between the data line DL and the seventh node n7. The first switch element T1 is turned on in response to the gate-on voltage VGL of the third scan signal SCAN3 and applies the data voltage to the seventh node n7. The first switch element T1 includes a first electrode connected to the data line DL, a gate electrode to which the third scan signal SCAN3 or a mode selection signal is applied, and a second electrode connected to the seventh node n7.

[0120] The second switch element T2 is connected between the first power supply line PL1 and the first node n1. The second switch element T2 is turned on in response to the gate-on voltage VGL of the first scan signal SCAN1 and applies the pixel drive voltage VDD to the first node n1. The second switch element T2 includes a first electrode connected to the first node n1, a gate electrode to which the first scan signal SCAN1 is applied, and a second electrode connected to the first power supply line PL1 to which the pixel drive voltage is applied.

[0121] The third switch element T3 is connected between the third power supply line PL3 and the fourth node n4. The third switch element T3 is turned on in response to the gate-on voltage VGL of the first scan signal SCAN1 and applies the initialization voltage Vini to the fourth node n4. The third switch element T3 includes a first electrode connected to the fourth node n4, a gate electrode to which the first scan signal SCAN1 is applied, and a second electrode connected to the third power supply line PL3 to which the initialization voltage Vini is applied.

[0122] The fourth switch element T4 is connected between the data line DL and the third node n3. The fourth switch element T4 is turned on in response to the gate-on voltage VGL of the second scan signal SCAN2 and applies the pixel data voltage Vdata to the third node n3. The fourth switch element T4 includes a first electrode connected to the third node n3, a gate electrode to which the second scan signal SCAN2 is applied, and a second electrode connected to the data line DL to which the data voltage Vdata is applied.

[0123] The fifth switch element T5 is connected between the fourth node n4 and the fifth node n5. The fifth switch element T5 is turned on in response to the gate-on voltage VGL of the second scan signal SCAN2, and connects the gate electrode of the drive element DT to the second electrode. The fifth switch element T5 includes a first electrode connected to the fourth node n4, a gate electrode to which the second scan signal SCAN2 is applied, and a second electrode connected to the fifth node n5.

[0124] The sixth switch element T6 is connected between the fourth power line and the first node. The sixth switch element T6 is turned on in response to the gate-on voltage VGL of the second scan signal SCAN2 and applies a reference voltage Vref to the first node n1. The sixth switch element T6 includes a first electrode connected to the fourth power line PL4 to which the reference voltage Vref is applied, a gate electrode to which the second scan signal SCAN2 is applied, and a second electrode connected to the first node n1.

[0125] The seventh switch element T7 is connected between the third power supply line PL3 and the sixth node n6. The seventh switch element T7 is turned on in response to the gate-on voltage VGL of the second scan signal SCAN2 and applies the initialization voltage Vini to the sixth node n6. The seventh switch element T7 includes a first electrode connected to the third power supply line PL3 to which the initialization voltage Vini is applied, a gate electrode to which the second scan signal SCAN2 is applied, and a second electrode connected to the sixth node n6.

[0126] The eighth switch element T8 is connected between the first power line PL1 and the third node n3. The eighth switch element T8 is turned on in response to the gate-on voltage VGL of the light emission control signal EM, connecting the first power line PL1 and the third node n3. The eighth switch element T8 includes a first electrode connected to the first power line PL1, a gate electrode to which the light emission control signal EM is applied, and a second electrode connected to the third node n3.

[0127] The ninth switch element T9 is connected between the first power line PL1 and the second node n2. The ninth switch element T9 is turned on in response to the gate-on voltage VGL of the light emission control signal EM and applies the pixel drive voltage VDD to the second node n2. The ninth switch element T9 includes a first electrode connected to the first power line PL1, a gate electrode to which the light emission control signal EM is applied, and a second electrode connected to the second node n2.

[0128] The tenth switch element T10 is connected between the fifth node n5 and the sixth node n6. The tenth switch element T10 is turned on in response to the gate-on voltage VGL of the light emission control signal EM, connecting the fifth node n5 and the sixth node n6. The tenth switch element T10 includes a first electrode connected to the fifth node n5, a gate electrode to which the light emission control signal EM is applied, and a second electrode connected to the sixth node n6.

[0129] The first capacitor Cst is connected between the second node n2 and the fourth node n4. The second capacitor Csel is connected between the seventh node n7 and the fifth power line PL5 to which a common voltage is applied.

[0130] Figures 14a and 14b show the mode-specific drive waveforms of the pixel circuit shown in Figure 13, and Figures 15a to 15d are diagrams for explaining the operating principle of the pixel circuit based on the waveform shown in Figure 14b.

[0131] Referring to Figures 14a and 14b, the pixel circuit is driven in the following order in the first and second modes: initialization period Ti, data writing and sensing period Tw / s, selection period Tsel, and emission period Tem.

[0132] Referring to Figure 15a, during the initialization period Ti, the first switch element T1 and the fourth to tenth switch elements T4 to T10 are turned off, the second switch element T2 and the third switch element T3 are turned on, the pixel drive voltage is applied to the first node n1, and the initialization voltage Vini is applied to the second node n2.

[0133] Referring to Figure 15b, during the data writing and sensing period Tw / s, the first to third switch elements T1 to T3 and the eighth to tenth switch elements T8 to T10 are turned off, the fourth to seventh switch elements T4 to T7 are turned on, the first data voltage Vdata1 is applied to the drive element, and the threshold voltage Vth of the drive element is sensed, so that the voltage at the second node n2 becomes Vdata1 + Vth. In addition, the reference voltage Vref is applied to the first node n1, and the initialization voltage Vini is applied to the sixth node n6.

[0134] Referring to Figure 15c, during the selection period Tsel, in the first mode, the first to tenth switch elements T1 to T10 are turned off, and in the second mode, the second to tenth switch elements T2 to T10 are turned off, the first switch element T1 is turned on, and the second data voltage Vdata2 is applied to the seventh node n7. As a result, the voltage at the seventh node n7 becomes "Vdata2".

[0135] Since the data writing and sensing period Tw / s and the selection period Tsel are intervals in which different data voltages are applied, the selection period Tsel can be started at least 1H after the end of the data writing and sensing period Tw / s in order to make the data voltage variable.

[0136] Referring to Figure 15d, during the light emission period Tem, the first to seventh switching elements T1 to T7 are turned off, and the eighth to tenth switching elements T8 to T10 are turned on. A current generated according to the gate-source voltage of the driving element DT is supplied to the light-emitting element EL, causing the light-emitting element EL to emit light. As a result, the voltage at the second node n2 becomes "VDD", and the voltage at the fourth node n4 becomes "VDD - Vref + Vdata + Vth".

[0137] During the emission period TEM, in the first mode, the second data voltage Vdata2 is not applied to the second capacitor Csel, so a wide optical field of view is maintained. In the second mode, the optical field of view narrows due to the second data voltage Vdata2 applied to the second capacitor Csel and the common voltage VCOM.

[0138] While embodiments of the present invention have been described in more detail above with reference to the attached drawings, the present invention is not necessarily limited to these embodiments and can be implemented in various modified forms without departing from the technical concept of the present invention. Therefore, the embodiments disclosed herein are for illustrative purposes only, not to limit the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by such embodiments. Accordingly, the embodiments described above should be understood as illustrative in all respects and not limiting. The scope of protection of the present invention should be interpreted as defined by the claims, and all technical concepts within an equivalent scope should be interpreted as being included within the scope of the rights of the present invention. [Explanation of Symbols]

[0139] 100: Display Panel 110: Data-driven unit 120: Gate drive unit 130: Timing Controller 140: Level Shifter 150: Power supply section

Claims

1. Light-emitting element and A drive element that drives the light-emitting element, A compensation circuit including a first capacitor, which includes a first electrode to which a first data voltage is applied through a data line and a second electrode connected to the gate electrode of the drive element, A first switch element is supplied with a predetermined second data voltage through the aforementioned data line, A second capacitor including a first electrode connected to the second electrode of the first switch element and a second electrode connected to a power line to which a common voltage is applied, A pixel circuit equipped with this feature.

2. The pixel circuit according to claim 1, wherein the light-emitting element is covered by a liquid crystal lens layer and emits light at a first viewing angle in a first mode depending on whether or not the second data voltage is supplied, and emits light at a second viewing angle narrower than the first viewing angle in a second mode.

3. The pixel circuit according to claim 2, wherein the second data voltage is applied to an electrode in the liquid crystal lens layer to change the refractive index of the liquid crystal material in the liquid crystal lens layer.

4. The pixel circuit according to claim 2, wherein the first switching element is turned off in the first mode and turned on in the second mode.

5. The pixel circuit according to claim 2, wherein the first switching element includes a first electrode connected to the data line, a gate electrode to which a gate signal is applied, and a second electrode connected to the first electrode of the second capacitor.

6. The driving element includes a first electrode connected to a power line to which a pixel driving voltage is applied, a gate electrode connected to a second node, and a second electrode connected to a third node. The first capacitor is connected between the first node and the second node, The aforementioned compensation circuit is A second switch element includes a first electrode connected to the data line, a gate electrode to which a first scan signal is applied, and a second electrode connected to the first node. A third switch element includes a first electrode connected to the second node, a gate electrode to which a second scan signal is applied, and a second electrode connected to the third node, A fourth switch element includes a first electrode connected to the first node, a gate electrode to which a light emission control signal is applied, and a second electrode connected to a power line to which a reference voltage is applied. A fifth switch element includes a first electrode connected to the third node, a gate electrode to which the light emission control signal is applied, and a second electrode connected to the fourth node, A sixth switch element including a first electrode connected to a power line to which the reference voltage is applied, a gate electrode to which the second scan signal is applied, and a second electrode connected to the fourth node, The pixel circuit according to claim 4, further comprising:

7. The pixel circuit is driven in the following order: initialization stage, data writing and sensing stage, selection stage, and light emission stage. During the data writing and sensing stage, the second switch element, the third switch element, and the sixth switch element are turned on, and the first data voltage is applied to the first electrode of the first capacitor. After the data writing and sensing steps, in the selection step, the first switch element is turned on and the second data voltage is applied to the first electrode of the second capacitor. The pixel circuit according to claim 6.

8. The pixel circuit according to claim 7, wherein the selection step is driven after a predetermined time has elapsed from the end of the data writing and sensing step.

9. The driving element includes a first electrode connected to the third node, a gate electrode connected to the fourth node, and a second electrode connected to the fifth node. The first capacitor is connected between the second node and the fourth node, The aforementioned compensation circuit is A second switch element includes a first electrode connected to a first node, a gate electrode to which a first scan signal is applied, and a second electrode connected to a power line to which a pixel driving voltage is applied. A third switch element includes a first electrode connected to the fourth node, a gate electrode to which the first scan signal is applied, and a second electrode connected to a power line to which an initialization voltage is applied. A fourth switch element including a first electrode connected to the third node, a gate electrode to which a second scan signal is applied, and a second electrode connected to the data line, A fifth switch element includes a first electrode connected to the fourth node, a gate electrode to which the second scan signal is applied, and a second electrode connected to the fifth node, A sixth switch element includes a first electrode connected to a power line to which a reference voltage is applied, a gate electrode to which the second scan signal is applied, and a second electrode connected to the first node, A seventh switch element includes a first electrode connected to a power line to which the initialization voltage is applied, a gate electrode to which the second scan signal is applied, and a second electrode connected to the anode electrode of the light-emitting element, An eighth switch element including a first electrode connected to a power line to which the pixel driving voltage is applied, a gate electrode to which a light emission control signal is applied, and a second electrode connected to the third node, A ninth switch element includes a first electrode connected to a power line to which the pixel driving voltage is applied, a gate electrode to which a light emission control signal is applied, and a second electrode connected to the second node, A tenth switch element includes a first electrode connected to the fifth node, a gate electrode to which a light emission control signal is applied, and a second electrode connected to the anode electrode of the light-emitting element, The pixel circuit according to claim 4, further comprising:

10. The pixel circuit according to claim 1, wherein the number of light-emitting elements is one.

11. It comprises a display panel including a display area in which multiple subpixels are arranged, The aforementioned display panel is circuit board and A circuit layer is placed on top of the aforementioned substrate, A light-emitting layer is disposed on top of the circuit layer, A sealing layer disposed on top of the light-emitting layer, A liquid crystal lens layer comprising a first electrode including a plurality of electrode patterns spaced apart from each other on the upper part of the sealing layer, a liquid crystal layer covering the first electrode, and a second electrode disposed on the upper part of the liquid crystal layer, Equipped with, A predetermined data voltage is applied to each of the numerous electrode patterns included in the first electrode, and a predetermined common voltage is applied to the second electrode. Display device.

12. The aforementioned subpixels include a first subpixel, a second subpixel, and a third subpixel. The aforementioned numerous electrode patterns are A first electrode pattern to which the data voltage applied to the first subpixel is applied, A second electrode pattern to which the data voltage applied to the second subpixel is applied, A third electrode pattern to which the data voltage applied to the third subpixel is applied, The display device according to claim 11, including the following:

13. The display device according to claim 12, wherein the plurality of electrode patterns are in the shape of a circular ring or a square ring.

14. The second electrode pattern is formed separately inside the first electrode pattern. The third electrode pattern is formed inside the second electrode pattern, separated from it. The display device according to claim 13.

15. The display device according to claim 14, wherein the data voltage applied to the second electrode pattern is higher than the data voltage applied to the first electrode pattern and lower than the data voltage applied to the third electrode pattern.

16. The display device according to claim 12, wherein the plurality of electrode patterns are formed for each subpixel or for each plurality of subpixels.

17. The display device according to claim 16, wherein the liquid crystal lens layer further includes spacers formed for each subpixel or for each number of subpixels.

18. Each of the aforementioned subpixels is, Light-emitting element and A drive element that drives the light-emitting element, A compensation circuit including a first capacitor, which includes a first electrode to which a first data voltage is applied through a data line and a second electrode connected to the gate electrode of the drive element, A first switch element is supplied with a predetermined second data voltage through the aforementioned data line, A second capacitor including a first electrode connected to the second electrode of the first switch element and a second electrode connected to a power line to which a common voltage is applied, The display device according to claim 11, comprising:

19. The display device according to claim 18, wherein the number of light-emitting elements is one.

20. The display device according to claim 18, wherein the light-emitting element is covered by a liquid crystal lens and, depending on whether or not the second data voltage is supplied, emits light at a first viewing angle in the first mode and emits light at a second viewing angle narrower than the first viewing angle in the second mode.

21. The display device according to claim 20, wherein the first switch element is turned off in the first mode and turned on in the second mode.

22. The display device according to claim 21, wherein the first switching element includes a first electrode connected to the data line, a gate electrode to which a gate signal is applied, and a second electrode connected to the first electrode of the second capacitor.

23. A pixel circuit for driving a pixel, wherein the pixel includes a first subpixel, a second subpixel, and a third subpixel, and the pixel circuit includes a first subpixel circuit for the first subpixel, a second subpixel circuit for the second subpixel, and a third subpixel circuit for the third subpixel. Each of the first subpixel circuit, the second subpixel circuit, and the third subpixel circuit is, Light-emitting element and A drive element that drives the light-emitting element, A compensation circuit including a first capacitor, which includes a first electrode to which a first data voltage is applied through a data line and a second electrode connected to the gate electrode of the drive element, A first switch element is supplied with a predetermined second data voltage through the aforementioned data line, A second capacitor including a first electrode connected to the second electrode of the first switch element and a second electrode connected to a power line to which a common voltage is applied, Includes, The second data voltages applied to the first subpixel circuit, the second subpixel circuit, and the third subpixel circuit are different from each other. Pixel circuit.

24. The light-emitting elements of the first subpixel circuit, the second subpixel circuit, and the third subpixel circuit are entirely covered by a liquid crystal lens layer. Depending on whether the second data voltage is supplied to the first subpixel circuit, the second subpixel circuit, and the third subpixel circuit, the first mode emits light at a first viewing angle, and the second mode emits light at a second viewing angle that is narrower than the first viewing angle. The pixel circuit according to claim 23.

25. The liquid crystal lens layer includes an electrode having a plurality of electrode patterns, and the plurality of electrode patterns are The first electrode pattern to which the second data voltage of the first subpixel circuit is applied, The second electrode pattern to which the second data voltage of the second subpixel circuit is applied, The third electrode pattern to which the second data voltage of the third subpixel circuit is applied and The pixel circuit according to claim 24, including the following:

26. The second electrode pattern is formed inside the first electrode pattern and separated from the first electrode pattern. The third electrode pattern is formed inside the second electrode pattern and separated from the second electrode pattern. The pixel circuit according to claim 25.

27. The pixel circuit according to claim 26, wherein the second data voltage of the second subpixel circuit is higher than the second data voltage of the first subpixel circuit and lower than the second data voltage of the third subpixel circuit.

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