Electrical conversion system

Abstract

The present invention provides a converter having three phase modules equipped with flying capacitors. [Solution] The electrical conversion system comprises an electrical converter having three phase modules, each phase module connected to two DC input nodes and a single three-phase AC output node. Each phase module includes a controllable switch and a flying capacitor. The control system receives three phase modulation signals (V m The logic control signals generated for the phase module as a function of the phase modulation signal (V) are sent to the switch. m ) is generated using DPWM technology and consists of three sinusoidal phase signals (V sin ) with phase-modulated signals (V) at different intervals m The homopolar signals generated are added together so that the modulated signal (V) to be saturated at a higher or lower endpoint. f The combination of circulating currents in the three-phase module's flying capacitors is selected to minimize the circulating currents.

Description

[Technical Field]

[0001] The present invention is developed in the field of power converters, particularly power converters for interface connecting photovoltaic (PV) or battery-assisted (BESS) systems with three-phase networks. More specifically, the present invention relates to DPWM (discontinuous pulse-width modulation) control techniques that minimize stress on the converter capacitor. [Background technology]

[0002] In photovoltaic or BESS power generation applications, the electrical converter must interface the DC bus on the photovoltaic panel or battery side with a three-phase system such as a power grid.

[0003] A known example of a converter that represents a good compromise between several switches and capacitors is the flying capacitor multilevel topology (or flycap) with three levels of output voltage.

[0004] PWM (pulse width modulation) control techniques for electrical converter switches, applicable to various types of converters including those described, are known in the art. The switch then receives a logic control signal provided by a sequence of square wave pulses alternating between logic high and logic low states. These logic states correspond to the opening and closing of the switch.

[0005] The width of these pulses determines the length of time that current flows through the switch or not, and the specific voltage level obtained at the output during that time. The pulse width is determined by comparing a carrier signal with a specific switching period, such as a sawtooth or triangular wave, with a sinusoidal modulated signal having a specific fundamental period longer than the switching period.

[0006] As is known, thanks to this technique, although the output voltage is a sequence of a limited set of discrete voltage levels (e.g., three voltage levels: maximum, minimum, and zero), by applying appropriate filters and / or considering the average of the output signal over a suitable time, the output voltage can be approximated to a sinusoidal waveform of the modulated signal.

[0007] As an evolution of PWM technology, a technique called DPWM, or discontinuous PWM, is also known.

[0008] DPWM (Dual Power Wave Modulation) technology is typically used to reduce switching losses in switches. Specifically, a fundamental period interval is selected where losses are assumed to be greatest, for example, an interval where the output phase voltage is close to the peak of a sine wave. At such intervals, the sinusoidal modulated signal is modified to saturate, i.e., flatten to a constant value that is either the maximum or minimum. At this interval, the modulated signal no longer crosses the carrier, and therefore, the switches controlled by this comparison remain active or inactive for the entire duration of the interval. This reduces switching losses.

[0009] In a three-phase system, it is preferable not to alter the single-phase modulation, as single-phase modulation leads to alterations in the three-phase current and therefore the system's operation. Instead, it is known that if the alterations necessary for saturation are introduced as homopolar components in all three phases, the three-phase current remains unchanged, at least in the case of a purely sinusoidal waveform. Thus, at each interval in which one of the three phase-modulated signals is saturated, the modulated signals of the other two phases also deviate from a sinusoidal waveform, even though they are not saturated.

[0010] To provide the maximum temporal extension during these periods, the saturation interval has a duration of 60°, and as a result, in the basic period (360°), each phase saturates twice at its maximum and minimum values.

[0011] U.S. Patent No. 7,391,181 provides an example of DPWM control, in which the saturation interval can be changed according to the power factor. [Prior art documents] [Patent Documents]

[0012] [Patent Document 1] U.S. Patent No. 7391181 [Overview of the project] [Problems that the invention aims to solve]

[0013] In a 3-level flycap topology, the most expensive component is typically the flying capacitor. The capacitor sizing must ensure that it does not exceed a certain voltage ripple depending on the RMS current circulating through it. Therefore, minimizing the RMS current flowing through the capacitor is desirable. [Means for solving the problem]

[0014] The objective of the present invention is to solve the problems of the prior art by limiting the current of the capacitors in an electric converter, particularly the flying capacitors, and thus enabling less burdensome sizing.

[0015] This and other objectives are achieved by the electrical conversion system described in any of the appended claims.

[0016] The present invention provides a converter having three phase modules, each equipped with a flying capacitor.

[0017] The control system generates a logic control signal for the converter switch using DPWM technology and a homopolar component obtained by a criterion that thus minimizes the combination of circulating currents in the flying capacitor, preferably by minimizing the sum of their squares, or by minimizing the sum of their rms (root mean square) values. The homopolar component saturates one of the three phase-modulated signals at each interval, resulting in a flattened-modulated signal at that interval.

[0018] Next, at each interval, the optimal flattened modulation signal, for example, the one that achieves the proposed minimization at that interval, is selected from among the three phase modulation signals.

[0019] This generally generates saturation intervals that can be offset to the peaks that the voltage and sinusoidal current will have and have different durations from each other, thus resulting in a final modulated signal that is significantly different from the modulated signals obtained from prior art, although still employing DPWM technology, solely for the purpose of reducing switching losses. The saturation interval, and the selection of which phase modulated signal to saturate at each time, generally vary depending on the phase shift between voltage and current.

[0020] The applicant has found that the most severe conditions for current circulation in a flying capacitor occur when the reference phase duty cycle is close to 0.5, i.e., when the output phase voltage is close to zero. Therefore, the control tends to avoid or temporarily limit the occurrence of a phase modulation signal having a duty cycle close to 0.5 and simultaneously having a high current in that phase.

[0021] Advantageously, by minimizing the current circulating within the capacitor at each interval, it is possible to reduce the thermal effects of the current within the flying capacitor, even under the most stringent conditions regarding current intensity and phase shift, and thus significantly reduce the size of the flying capacitor. To better understand the following detailed description, several embodiments of the present invention are shown in the accompanying drawings. [Brief explanation of the drawing]

[0022] [Figure 1] This diagram schematically shows an electrical conversion system according to one embodiment of the present invention. [Figure 2] This diagram schematically shows the phase module of the converter in the electrical conversion system shown in Figure 1, along with the dedicated control system. [Figure 3] This figure shows a time graph of an example of circulating current in the phase module's switches and flying capacitors during the switching period. [Figure 4] This figure shows time graphs of two sets of theoretically modulated signals for three phases, assuming always maximum or always minimum saturation. [Figure 5] This figure shows graphs representing the phase coefficient, phase current, and circulating current in a flying capacitor as a function of the reference phase duty cycle when the power factor is equal to 1. [Figure 6] This figure shows time graphs of the sinusoidal phase signal, phase current, and phase modulation signal when the power factor is 1. [Figure 7] This figure shows the time graphs corresponding to the time graphs in Figures 5 and 6 when the power factor is equal to 0. [Figure 8] This figure shows the time graphs corresponding to the time graphs in Figures 5 and 6 when the power factor is equal to 0. [Figure 9] This figure shows the time graphs corresponding to the time graphs in Figures 5 and 6 when the power factor is 0.7. [Figure 10] This figure shows the time graphs corresponding to the time graphs in Figures 5 and 6 when the power factor is 0.7. [Modes for carrying out the invention]

[0023] The electrical conversion system, as shown by number 1, comprises an electrical converter 2 and a control system 3 for controlling the operation of the converter 2 (only single-phase is shown in Figure 2).

[0024] The electrical converter 2 comprises two input nodes 211, 212, which are positive node 211 and negative node 212. The input nodes 211, 212 can be connected to a DC bus. The DC bus is preferably connected to a photovoltaic (PV) system (not shown) and / or an electrical storage system (not shown), such as a battery energy storage system (BESS). The DC bus can optionally be connected to a bus capacitor other than those described below, as a flying capacitor.

[0025] The two input nodes 211 and 212 have opposite polarities and reference voltage value V dc It is configured to operate with two voltages that have equal modulus. Therefore, the total voltage between the positive input node 211 and the negative input node 212 is twice the reference voltage, 2V. dc The DC bus may or may not have a ground point at zero potential between, for example, two halves of the bus capacitor.

[0026] The electrical converter 2 also includes three output nodes 213 that can be connected to each of the three AC phase conductors of the three-phase system. For simplicity, it is assumed below that the converter 2 exchanges the three-phase system with an AC current that is in positive phase, substantially sinusoidal, and has a constant amplitude. Thus, the three currents are out of phase by 120° from each other over a given fundamental period. However, it should be noted that the control system 3 described can also be adapted during current transients when the current is not exactly sinusoidal without significantly altering its operation, achieving substantially the same advantageous effects.

[0027] Converter 2 has three phase modules 22, one for each phase conductor of the three-phase system. All three phase modules 22 are connected to both input nodes 211 and 212. Furthermore, each phase module 22 is connected to its own unique output node 213, distinct from the output nodes 213 connected to the other phase modules 22.

[0028] Each phase module 22 includes a number of controllable switches 23 that connect the input nodes 211, 212 and the output node 213 to each other. The controllable switches 23 are, in particular, transistors configured to take on two conducting states: an active (or closed) state and an inactive (or open) state. Each switch 23 is configured to switch between the two conducting states in response to a properly received control signal.

[0029] As is common in many converters 2, it is also intended that a circulating diode be provided in parallel with each switch 23. Furthermore, each switch 23 described can actually be identified by several switches 23 in series with each other that share the same current.

[0030] In a preferred embodiment, converter 2 is a type of converter called a fly-cap converter. In such an embodiment, each phase module 22 comprises a pair of legs 221, each leg connected between an output node 213 connected to the phase module 22 and separate input nodes 211, 212. Thus, a positive leg 221 is provided between the output node 213 and the positive input node 211, and a negative leg 221 is provided between the output node 213 and the negative input node 212.

[0031] Each leg 221 comprises two switches 23 connected in series with each other at an intermediate node 222 (but not necessarily sharing the same current, as will become apparent below). In particular, each leg 221 of each phase module 22 comprises an internal switch 231 connected between the output node 213 and the intermediate node 222, and an external switch 232 connected between the input nodes 211, 212 (which may be positive or negative input nodes 211, 212) connected to the leg 221 and the intermediate node 222.

[0032] Next, the phase module 22 includes a flying capacitor 223 connected to a controllable switch 23. In a preferred embodiment, the flying capacitor 223 is connected between the intermediate nodes 222 of the two legs 221. Preferably, the flying capacitor 223 is not connected to any other nodes besides the intermediate nodes 222, and therefore all current circulating within the flying capacitor 223 is always input and / or drawn from both intermediate nodes 222 simultaneously.

[0033] The flying capacitor 223 is connected to the reference voltage V dc It is configured to operate at a voltage equal to half the voltage between the positive input node 211 and the negative input node 212. As will be apparent from below, the individual intermediate nodes 222 at the endpoint of the flying capacitor 223 may be at different voltage levels at different times, based on the conduction state of the different switches 23 of the phase module 22.

[0034] The main task of the control system 3 is to control the switches 23 of the converter 2 so that they instantaneously take on a combination of conduction states that results in a predetermined voltage at the output node 213. In a preferred embodiment, the control system 3 is configured to control the switches 23 of each phase module 22 according to four combinations of states so that the voltage at the output node 213 can take on three different levels.

[0035] These states are described with reference to FIG. 3, and the first four graphs represent the current circulating within switch 23 of phase module 22 during the switching period when a positive but not maximum output phase voltage is obtained, or similarly the control logic signal of switch 23. The first four graphs of FIG. 3 represent, in particular, the current I 232 of the external switch 232 of the positive leg 221, the current I 231 of the internal switch 231 of the positive leg 221, the current I 231 of the internal switch 231 of the negative leg 221, and the current I 232 of the external switch 232 of the negative leg 221.

[0036] In the first combination of states of the phase module, both switches 23 of the positive leg 221 are active and both switches 23 of the negative leg are inactive. This combination is represented in FIG. 3 by the moment when the active state Ton periods of the first two graphs overlap. In the first combination of states, the voltage of the output node 213 of phase module 22 is equal to the voltage of the positive input node 211, i.e., the reference voltage V dc .

[0037] In the second combination of states of the phase module, both switches 23 of the positive leg 221 are inactive and both switches 23 of the negative leg are active. This combination is symmetric to the previous one and is not shown in FIG. 3 because it is desirable to obtain a positive average voltage. In the second combination of states, the voltage of the output node 213 of phase module 22 is equal to the voltage of the negative input node 212, i.e., the inverse of the reference voltage -V dc .

[0038] In the third and fourth state combinations, the internal switches 231 and external switches 232 of two separate legs 221 are (exclusively) active. For example, in the third combination, the internal switch 231 of the positive leg 221 and the external switch 232 of the negative leg 221 (second and fourth graphs) are active, and in the fourth combination, the internal switch 231 of the negative leg 221 and the external switch 232 of the positive leg 221 (first and third graphs) are active. In either combination, the remaining two switches 23 are inactive. In the third and fourth state combinations, the absolute difference between the voltage at the output node 213 of the phase module 22, i.e., the voltage at one of the input nodes 211 or 212, and the voltage at the flying capacitor 223 is zero.

[0039] The fifth and last graphs in Figure 3 show the circulating current I of the flying capacitor 223. 223 This represents the result of the combination of the first four graphs. Importantly, in the first and third combinations of states, the circulating current I in the flying capacitor 223 223 It is zero. Therefore, the output phase voltage is equal to the reference voltage V dc or its inverse -V dc When equal to this, the flying capacitor 223 receives no current.

[0040] Instead, in the third and fourth combinations of states, the circulating current I in the flying capacitor 223 223 is the phase current I 213 It is equal to and positive or negative. Therefore, when the output phase voltage is zero, the flying capacitor 223 has a phase current I 213 Stress proportional to the intensity (phase current I 213 (If a zero voltage occurs when the stress is zero, then the stress may be effectively zero.)

[0041] Generally, during the switching period, the circulating current I in the flying capacitor 223 of the phase module 22 223 The average rms value is the phase current I relative to the phase coefficient C. 213It is given by the product of , which depends on the alternation of the four combinations of states, as will be detailed below.

[0042] To control switch 23, the control system 3 is configured to generate a set of logical control signals and transmit them to switch 23 on the phase module 22, for example, to determine whether to switch switch 23 between open and closed states.

[0043] As is already known about PWM control and DPWM control, the set of logic control signals is, for example, each carrier signal V c For comparison, for the phase module 22, the three respective phase modulation signals V m It is generated accordingly.

[0044] As is well known, the carrier signal V c This is a periodic signal (usually triangular or sawtooth) with a predetermined switching period. Alternatively, the modulated signal V m It is preferable that this is a periodic signal (e.g., a sine wave) having a constant fundamental period longer than the switching period.

[0045] Instead, the logic control signal having the same waveform as the currents in the first four graphs of Figure 3 is a signal with two distinct levels, one level determining the closed state of switch 23 and the other level determining the open state.

[0046] As is well known, each switch 23 of the phase module 22 controls the corresponding phase modulation signal V m Accordingly, both remain active and inactive during the active state period Ton and the inactive state period Toff, respectively, which are within the switching period. For each switch 23, the time relationship between the active state period and the switching period is also called the duty cycle.

[0047] Next, the control system 3 determines that the respective output phase voltages are, with respect to the average over the switching period, the modulated signal V mThe switches 23 of each phase module 22 are controlled by alternating different combinations of conduction states in proportion to the strength of the current. The duty cycle of the switches 23 of the positive leg 221 (where the same individual duty cycles are shared between switches) is also called the reference phase duty cycle D, and the duty cycle of the switches 23 of the negative leg 221 (where the same individual duty cycles are shared similarly) is equal to the one's complement of the reference phase duty cycle D, i.e., 1-D. Note that the reference phase duty cycle D changes linearly with the phase output voltage, ranging from a minimum value of 0 to a maximum value of 1.

[0048] A preferred example that is known in itself is a single modulated signal V m However, it is used to generate logic control signals for different switches 23 of the same phase module 22. For the internal and external switches 231, 232 of leg 221, for example, the positive leg 221, the same modulated signal V m However, two separate carriers, for example, two separate carriers that are offset from each other by only half a switching period or have opposite signs to each other, are compared. For the switch 23 of the other leg 221, the carrier and the modulated signal V m While it is not necessary to perform a new comparison between them, as can be seen from the first four graphs in Figure 3, it is possible to use complementary logic control signals that have already been generated for the first leg 221, particularly pairs of complementary logic control signals for the two external switches 232, and pairs of complementary logic control signals for the two internal switches 231.

[0049] Modulated signal V m Note that the value is variable between the upper and lower limits, and that the upper and lower limits correspond to the maintenance of the first and second combinations of states throughout the switching period, and thus to the maximum or minimum output phase voltage, respectively.

[0050] In fact, the modulated signal V mIf the modulated signal V remains within a certain interval equal to the upper or lower limit (a reference duty cycle D equal to 1 or 0, i.e., the first and second endpoint duty cycles), then during that interval, m and Carrier V c There is no intersection with the other values, and it is variable even between the same endpoints; therefore, no switching occurs in the switch 23 controlled in this manner.

[0051] On the other hand, the modulated signal V m When is zero (reference duty cycle D equal to 0.5, i.e., the central duty cycle), only the third and fourth combinations of states alternate, and the output phase voltage is constant and zero.

[0052] Modulated signal V m When is in an intermediate state between zero and an endpoint, the first combination of states alternates with the third and fourth combinations for positive modulation signals (as shown in the graph in Figure 3), and the second combination of states alternates with the third and fourth combinations for negative modulation signals. These alternations are, - Output phase voltage is modulated V m It remains proportional to, - The third and fourth combinations of states are maintained for an equivalent time between them so as not to change the charge state of the flying capacitor 223. It is based on time.

[0053] From what has been described so far, the third and fourth combinations of states, namely the combination in which the stress on the flying capacitor 223 of the phase module 22 is maximized, are when the duty cycle is 0 or 1 (output phase voltage V dc or -V dc It can be seen that this is avoided when it is equal to ) and is maintained permanently when the duty cycle is equal to 0.5 (output phase voltage is equal to 0) (one alternates with the other).

[0054] In the graphs of Figures 5, 7, and 9, the aforementioned phase coefficient C, i.e., the circulating current I in the flying capacitor 223 of the phase module 22 with respect to the rms value during the switching period, is shown. 223 And, phase current I 213 The ratio between the two is shown. The phase coefficient C is essentially the phase current I in the flying capacitor 223 during the commutation period relative to the switching period. 213 This represents the cycle time. Therefore, this phase coefficient C is equal to the unit value of the phase current I 213 This also shows the stress state of the flying capacitor 223.

[0055] The phase coefficient C is a predetermined function of the reference phase duty cycle D, or equivalently, the phase-modulated signal. This function is maximum (equal to 1) for a reference phase duty cycle D equal to 0.5, and therefore corresponds to the phase-modulated signal and zero output phase voltage, and minimum (equal to 0) for a reference phase duty cycle D equal to 0 or 1, and therefore corresponds to the maximum or minimum modulated signal and output phase voltage.

[0056] For the midpoint of the duty cycle and / or phase-modulated signal and / or output phase voltage, the phase coefficient C changes linearly between the three indicated points and therefore increases as it approaches the reference duty cycle D of 0.5.

[0057] Control system 3 uses DPWM technology to generate three phase-modulated signals V m It is configured to generate three phase-modulated signals V m The starting point for generating is three sinusoidal phase signals V that have periodicity equal to the fundamental period and equal amplitude, and are phase-shifted by 120° relative to each other. sin It consists of the following: Next, the three sinusoidal signals V shown in Figures 6, 8, and 10 sin These are distinguished by three phases. These sine waves V sin The signal is what could have been used as the modulated waveform if DPWM technology had not been used.

[0058] Each phase modulated signal Vm These are the respective phase sinusoidal signals V sin It is obtained by adding a specific homopolar signal to it. The homopolar signal is common to the three phase modules 22. Therefore, the phase modulation signal V m and the sinusoidal phase signal V sin The difference between the two is equal for all phase modules 22 at each moment. Also, the three phase modulation signals V m The positive-sequence component is the three sinusoidal phase signals V sin It corresponds to.

[0059] sine wave signal V sin and phase current I 213 For three different phase shifts between V and V, particularly for power factors equal to 1, 0, and 0.7, the phase-modulated signal V m Three examples are shown in Figures 6, 8, and 9. Therefore, in these three cases, the same sinusoidal signal V sin Even so, different time shapes exist for homopolar signals.

[0060] As is known, the homopolar component of voltage cannot generate current in a three-phase system, and therefore the phase-modulated signal V m Introducing a homopolar signal to the sine wave signal V sin For what would have been obtained using as the modulation signal, the phase current I 213 Do not change it.

[0061] The homopolar signal generally has different time shapes for different intervals in the sequence of fundamental period intervals, generally at least six different intervals (or possibly multiples of six, e.g., 12 intervals in Figures 8 and 10). In particular, at each interval of the sequence, three saturated phase modulated signals V m The most optimal V f A homopolar signal is generated such that it saturates, that is, it becomes a flattened modulated signal of a constant value throughout the entire interval. This constant value can be equal to one of the upper or lower limits, i.e., a value at which no switching occurs during the interval.

[0062] Therefore, within that interval, the homopolar signal is not constant, but rather a constant value and a sinusoidal signal V sin This is equal to the difference between this and the corresponding phase-modulated signal V. This homopolar signal is equal to the difference between this and the corresponding phase-modulated signal V within its interval. m The other two phase sine wave signals V do not saturate. sin It is also added to. Therefore, at each interval, the three modulated signals V m All of these correspond to the same phase sinusoidal signal V sin It is being translated relative to [the given element].

[0063] At each interval, the optimal flattened modulated signal V f That is, the phase-modulated signal V is brought to a saturated state. m The three phase-modulated signals V are based on criteria that will be explained in more detail below. m Selected from. In particular, for each interval, three phase modulation signals V m From among these, alternative selections of candidate flattened modulated signals are considered.

[0064] It is emphasized that in each interval, one of the three flattened modulation signal candidates must always be discarded. This is especially true for the other two phase sinusoidal signals V during the interval. sin The sine wave signal V between them sin This is a candidate flattened modulated signal corresponding to [the specified phase]. In fact, if that particular phase saturates, one of the other phases will exceed either the upper or lower limit of the phase modulated signal V. m It has.

[0065] For the only phase beyond the endpoint, even if it is achievable by the electronics of control system 3, the output phase voltage is no longer the phase modulation signal V m It is not proportional to the output phase voltage, and therefore the forward component of the output phase voltage is altered, introducing an unacceptable reverse phase voltage.

[0066] Therefore, the optimal flattened modulation signal V in the interval f The only possible option is the maximum phase sinusoidal signal V sin The corresponding signal (saturated at the upper limit), or the least phase sinusoidal signal V sinThis corresponds to (saturates at the lower limit).

[0067] In other words, at each interval, a choice must be made to proceed to saturation at the upper limit or to saturation at the lower limit (in either case, the only phase that can be saturated during the interval is saturated). Figure 4 shows the first set of theoretical modulation signals with three phases V, assuming that saturation is always selected at the upper limit. mth1 And, assuming that saturation is always selected at the lower limit, a second set of theoretical modulation signals with three phases V mth2 This selection is shown by indicating that, at each interval, three phase-modulated signals V m This is the first or second set V of the theoretical modulation signal. mth1 , V mth2 It corresponds to one of the following.

[0068] Among these flattened modulation signal candidates, the optimal selection is given by the sum of their squares, or equivalently their RMS values, of the circulating currents I in the flying capacitor 223 of the three-phase module 22 over the interval under consideration. 223 This minimizes the combination of factors. Therefore, the optimal flattened modulated signal V f The selection is based on the homopolar signal required for saturation, and all three phase modulation signals V m This makes it possible to calculate the instantaneous value of [the value].

[0069] Preferably, the optimal flattened modulated signal V f To select, the circulating current I in the flying capacitor 223 of the three-phase module 22 223 This is calculated during the interval for each of the possible alternative candidate flattened modulated signals.

[0070] In particular, the circulating current I in the interval has different possible alternative choices. 223 To calculate this, the control system 3 determines the reference phase duty cycle D of all three phases for each alternative selection. Then, it calculates the circulating current I in the flying capacitors 223 of each phase module 22. 223is calculated as a function of each phase and the phase current I 213 and the respective reference phase duty cycle D. More specifically, the phase coefficient C is determined according to the aforementioned predetermined function of the reference phase duty cycle D, and the phase current I 213 is multiplied by the phase coefficient C to determine the circulating current I 223 of the phase module 22. This product is graphically shown in FIGS. 5, 7 and 9.

[0071] In this way, for each possible alternative of the flattened modulation signal candidate, the circulating current I 223 in the three flying capacitors 223 of the phase module 22 is obtained.

[0072] Preferably, as expected, minimizing the combination of the circulating currents I 223 in the flying capacitors 223 of the three phase modules 22 is to select, as the optimal flattened modulation signal V f the candidate flattened modulation signal for which the sum of the squares or the rms value of these circulating currents I 223 is minimized.

[0073] With this control strategy, at each interval of the sequence, the switches 23 of the phase module 22 associated with the optimal flattened modulation signal V f remain in their respective active or inactive states throughout the interval, and the circulating current I f in the flying capacitor 223 of the phase module 22 associated with the optimal flattened modulation signal V 223 remains zero throughout the interval.

[0074] However, the most beneficial effect of the proposed control is usually not at the phase where the optimal flattened modulation signal V f is obtained, but at the intermediate phase modulation signal V m (or equivalently the sinusoidal signal V sinNote that this is the phase in which the phase coefficient C is obtained. In fact, this phase is the phase in which the phase coefficient C is maximum. Therefore, in many cases (as can be seen from Figures 7 and 9), the circulating current I 223 The phase coefficient C and phase current I are also high, that is, the phase coefficient C and phase current I 213 The product of these two factors is also high. Therefore, when this phase-modulated signal is moved towards an appropriate endpoint, saturation is not reached, but its phase coefficient C and its circulating current I 223 It will decrease significantly.

[0075] In other cases (as shown in Figure 5), despite a high C-phase coefficient value, the phase current I 213 Because it can be lower than its phase, the phase with intermediate modulation may not be the most important.

[0076] It should be noted that among the three phase modules 22, some may be negatively affected because they are neither in the phase of the intermediate modulation signal nor the phase where the modulation signal is saturated. This phase is generally directed towards a phase coefficient close to 1.

[0077] However, the optimal flattened modulation signal V that minimizes the sum of the rms values ​​of the circulating currents for the three phases is... f Since this is selected, and considering that there are several intervals in the fundamental period, and that in some of these intervals the phase current conditions are substantially the same across the entire fundamental period in terms of different phases, the average stress of each flying capacitor 223 is reduced, making it possible to reduce their size.

[0078] As already mentioned, within the fundamental period, the sequence of intervals generally includes at least six intervals. In fact, a situation proposed at a particular interval for one positively saturated phase is repeated correspondingly at other intervals for the other two phases, and also correspondingly at another interval with negative saturation. Thus, generally, the duration of these intervals is less than or equal to 60° of the fundamental period.

[0079] Therefore, in some embodiments, an interval having a fixed duration of 60° and optionally having predetermined spaced ends can simply be adopted. Thus, the duration is determined by the phase current I 213 It remains unchanged despite the possibility of changes in its intensity and phase.

[0080] However, in a preferred embodiment, the duration of each interval is not fixed in advance, nor is the number of its endpoints or intervals fixed. Instead, the control system 3 controls the circulating current I in the flying capacitor 223 of the three-phase module 22. 223 However, the current optimal flattened modulation signal V f A new, optimally flattened modulated signal V f When it is determined that the current optimal flattened modulated signal V is low, preferably by at least a predetermined delta value, f From a new, optimally flattened modulated signal V f By switching to this setting, it is configured to determine the end of the current interval in the sequence and the start of a new interval.

[0081] More specifically, the control system 3 can be configured to repeatedly screen for possible alternative selections of candidate flattened modulated signals at frequencies given by a computation time shorter than the fundamental period, generally shorter than each interval, for example, equal to the switching period. Then, each interval of the sequence is used to select the optimal flattened modulated signal V f The optimal flattened modulated signal V is identified by a series of consecutive computation times in which the selection remains the same, and the computation differs. f It ends when it brings about a certain outcome.

[0082] The optional introduction of the delta value mentioned above results in the optimal flattened modulated signal V f To avoid the risks of excessively frequent changes, a hysteresis function is introduced into the control.

[0083] From the graphs in Figures 6, 8, and 10, it can be seen that the control results in intervals that may or may not be matched to the current and / or voltage peaks of the relevant phases, depending on the power factor. Furthermore, it can be seen that there may be six intervals, each with a duration corresponding to 60°, but there may be more, and they may generally have different durations from one another. For example, when added within the fundamental period, the maximum saturation interval for each phase may cumulatively reach 60°, and the same is true for the minimum saturation interval.

[0084] It will be obvious to those skilled in the art that numerous equivalent modifications can be made to the above-mentioned variations without departing from the scope of protection defined by the attached claims. [Explanation of Symbols]

[0085] 1. Electrical Conversion System 2 Electrical converters 3. Control System 22-phase module 23 controllable switches 211 input nodes 212 input nodes 213 Output Nodes 221 First Leg 222 intermediate nodes 223 Flying Capacitor 231 Internal switch 232 External switch C phase coefficient D Reference phase duty cycle, reference duty cycle I 213 phase current I 223 circulating current V dc Reference voltage V sin sine wave signal V f Flattened Modulated Signal V m Phase-modulated signal

Claims

1. Two input nodes (211, 212) that can be connected to a DC bus, Three output nodes (213) that can be connected to each of the three AC phase conductors of the three-phase system (1), and Three phase modules (22), each connected to the two input nodes (211, 212) and a single output node (213), wherein each phase module (22) comprises a plurality of controllable switches (23) and a flying capacitor (223) connected to the controllable switches (23). An electrical converter (2) equipped with, Each of the three phase-modulated signals (V ｍ A control system (3) is configured to generate a set of logical control signals according to the above and transmit them to the switch (23) of the phase module (22) to switch the switch (23) between an open state and a closed state, for example. Equipped with, The control system (3) Three sinusoidal phase signals with a fundamental period (V ｓｉｎ ) is combined with a homopolar signal common to the three phase modules (22) and the three phase modulated signals (V) are obtained using DPWM (Discontinuous Pulse Width Modulation) technology. ｍ ) generates, For the sequence of intervals within the basic period, in each interval, the three phase modulation signals (V ｍ The optimal flattened modulation signal (V) selected from among ) ｆ The homopolar signal is generated such that ) takes a constant value equal to the upper or lower limit. It is configured in such a way, The control system (3) For each interval of the sequence, within that interval, the circulating current (I) in the flying capacitor (223) of the three phase modules (22) ２２３ To minimize a predetermined combination of ) the three phase modulation signals (V ｍ ) from among the above, the optimal flattened modulation signal (V ｆ Select ) It is characterized by being configured in such a way, The circulating current (I ２２３ ) of the flying capacitor (223) of the three-phase modules (22) in the predetermined combination is the sum of the squares or the rms value of the circulating current (I ２２３ ), and For each interval, the control system (3) controls the optimal flattened modulation signal (V ｆ When selecting ), Using multiple alternative selections of flattened modulation signal candidates, the circulating current (I) in the flying capacitor (223) of the three phase modules (22) during the interval is determined. ２２３ ) calculate, Regarding the interval, the predetermined combination (I ２２３ ) calculate, and From among the candidates for the flattened modulation signal, the one that minimizes the predetermined combination calculated for the interval is the optimal flattened modulation signal (V ｆ ) Select as The electrical conversion system (1) is configured as follows.

2. The control system (3) controls the circulating current (I) in the flying capacitor (223). ２２３ When calculating ), for each flattened modulation signal candidate, To determine the reference phase duty cycle (D) for each phase with respect to the interval and the flattened modulation signal candidate, For each phase module (22), the circulating current (I) of the flying capacitor (223) ２２３ ) and phase current (I ２１３ ) and to be calculated as a function of the respective reference phase duty cycle (D) The system (1) according to claim 1, which is configured as follows.

3. For each phase module (22), the circulating current (I) of the flying capacitor (223) ２２３ ) can be calculated The phase coefficient (C) is determined according to a predetermined function of the reference phase duty cycle (D), preferably such that the predetermined function is maximized for the reference phase duty cycle (D) corresponding to the zero output phase voltage, particularly for a reference phase duty cycle (D) equal to 0.

5. The phase coefficient (C) is equal to the phase current (I ２１３ The circulating current (I) of the phase module (22) is multiplied by the circulating current (I ２２３ ) to decide The system (1) according to claim 2, including the above.

4. The system (1) according to claim 2 or 3, wherein each phase module (22) is configured to generate a maximum output phase voltage of a first endpoint reference phase duty cycle (D) preferably equal to 1, a minimum output phase voltage of a second endpoint reference phase duty cycle (D) preferably equal to 0, and a zero output phase voltage of a central reference phase duty cycle (D) preferably equal to 0.

5.

5. Each phase module (22) comprises a pair of legs (221), each leg (221) connected between the output node (213) of the phase module (22) and its respective separate input nodes (211, 212), and each leg (221) comprises two controllable switches (23) connected in series to each other at an intermediate node (222), For each phase module (22), the flying capacitor (223) is connected between the intermediate nodes (222) of the two legs (221). The system (1) according to any one of claims 1 to 4.

6. Each leg (221) of each phase module (22) is equipped with an internal switch (231) connected to the respective output node (213) and an external switch (232) connected to the respective input nodes (211, 212). For each phase module (22), the set of logic control signals includes separate signals for all the switches (23) of the two legs (221), including an active state period and an inactive state period. The active state period of each external switch (232) overlaps with the active state period of the internal switch (231) of the two legs (221), and as a result, when the internal switch (231) and external switch (232) of the two separate legs (221) are in the active state period at the same time, the flying capacitor (223) generates a circulating current (I ２２３ ) to receive The system (1) according to claim 5.

7. In each interval of the sequence, the optimal flattened modulated signal (V ｆ The switches (23) of the phase module (22) associated with the interval remain active or inactive for the entire duration of the interval, and the optimal flattened modulation signal (V ｆ The circulating current (I ２２３ The system (1) according to any one of claims 1 to 6, wherein ) is zero over the entire period of the interval.

8. The control system (3) controls the circulating current (I) in the flying capacitor (223) of the three phase modules (22). ２２３ ) is the actual optimal modulation signal (V ｆ A new, optimal flattened modulation signal (V) ｆ When it is determined to be small in the sequence, the end of the current interval and the actual optimal flattened modulation signal (V ｆ ) from the new optimal flattened modulation signal (V ｆ The system (1) according to any one of claims 1 to 7, configured to determine the start of a new interval involving a transition to ).

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