Semiconductor equipment

Abstract

To provide a semiconductor device with reduced circuit area. [Solution] This is a semiconductor device having first and second cell arrays and a first conversion circuit. The first cell array has first and second cells in the same row, and the second cell array has third and fourth cells in the same row. The first cell is electrically connected to first and second wiring, the second cell is electrically connected to first and third wiring, the third cell is electrically connected to fourth and sixth wiring, and the fourth cell is electrically connected to fifth and seventh wiring. The sixth wiring is also electrically connected to seventh wiring. The first to fourth cells have the function of outputting a current corresponding to the product of the held data and the input data. Specifically, the first cell outputs current to the second wiring, the second cell to the third wiring, the third cell to the sixth wiring, and the fourth cell to the seventh wiring. The first conversion circuit has the function of sending data corresponding to the total amount of current flowing through the second and third wirings to the fourth and fifth wirings.

Description

[Technical Field]

[0001] One aspect of the present invention relates to semiconductor devices, display devices, and electronic devices.

[0002] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. The technical field of the invention disclosed herein relates to a product, a driving method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. More specifically, examples of the technical field of one aspect of the present invention disclosed herein include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, energy storage devices, imaging devices, memory devices, signal processing devices, processors, electronic devices, systems, methods for driving them, methods for manufacturing them, or methods for inspecting them. [Background technology]

[0003] Currently, there is a great deal of activity in developing integrated circuits that mimic the structure of the human brain. These integrated circuits incorporate the brain's structure as electronic circuits, possessing circuits that correspond to the "neurons" and "synapses" of the human brain. For this reason, such integrated circuits are sometimes called, for example, "neuromorphic," "brainmorphic," or "brain-inspired." These integrated circuits have a non-von Neumann architecture and are expected to be able to perform parallel processing with extremely low power consumption compared to von Neumann architectures, where power consumption increases with increasing processing speed.

[0004] A model of information processing that mimics a neural network having "neurons" and "synapses" is called an artificial neural network (ANN). For example, Non-Patent Documents 1 and 2 disclose a computing device that constructs an artificial neural network using SRAM (Static Random Access Memory).

[0005] Furthermore, attempts are being made to use computing devices that constitute artificial neural networks for, for example, correcting images displayed on display devices. For example, Patent Document 1 discloses a display device that uses a computing circuit that constitutes an artificial neural network to adjust the brightness and color tone of the displayed image to suit the viewer's preferences. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2018-36639 [Non-patent literature]

[0007] [Non-Patent Document 1] M. Kang et al., “IEEE Journal Of Solid-State Circuits”, 2018, Volume 53, No.2, p.642-655. [Non-Patent Document 2] J. Zhang et al., “IEEE Journal Of Solid-State Circuits”, 2017, Volume 52, No.4, p.915-924. [Overview of the Initiative] [Problems that the invention aims to solve]

[0008] An example of a computing device that constitutes an artificial neural network is a computing circuit that performs a sum-of-products operation by adding up analog currents corresponding to the product of weight coefficients and input data. Because this computing circuit uses analog current for its calculations, its circuit size can be reduced compared to computing circuits composed of digital circuits, thus reducing the circuit area. Furthermore, by designing this computing circuit to handle small analog currents in its calculations, the power consumption of the computing circuit can be reduced.

[0009] One example of the above-mentioned calculation circuit is a configuration having a cell array in which calculation cells that perform the product of a weight coefficient and input data and output the result of the product as an analog current are arranged in a matrix. Furthermore, by, for example, adding up the analog currents output from calculation cells arranged in a single row, the sum of the analog currents can be treated as the sum of the products of the weight coefficient and input data, thus enabling faster calculation than performing sum-of-product calculations using digital circuits.

[0010] By the way, in a hierarchical neural network, which is a type of artificial neural network, the number of neurons differs at each layer. For example, the number of neurons in one layer corresponds to the number of products to be added in a multiply-accumulate operation, so in the above arithmetic circuit, the number of calculation cells required differs for each calculation (each layer). Therefore, when performing multiply-accumulate operations in each layer of a hierarchical neural network using an arithmetic circuit of the same cell array size, there may be calculation cells that are not used in the calculation depending on the layer. In other words, increasing the number of calculation cells in the cell array of an arithmetic circuit is suitable for performing large-scale calculations (calculations with a large number of products to be added), but when performing small-scale calculations (calculations with a small number of products to be added), the number of calculation cells that are not used in the calculation increases, resulting in lower computational efficiency per unit area.

[0011] One aspect of the present invention aims to provide a semiconductor device with a reduced circuit area. Alternatively, one aspect of the present invention aims to provide a semiconductor device that does not suffer a decrease in computational efficiency per unit area even when performing small-scale calculations. Alternatively, one aspect of the present invention aims to provide a display device including any of the above-described semiconductor devices. Alternatively, one aspect of the present invention aims to provide an electronic device having the above-described display device. Alternatively, one aspect of the present invention aims to provide a novel semiconductor device, a novel display device, or a novel electronic device.

[0012] It should be noted that the problems addressed by one aspect of the present invention are not limited to those listed above. The problems listed above do not preclude the existence of other problems. These other problems are those not mentioned in this section, as described below. Those not mentioned in this section can be derived from the description in the specification or drawings, etc., by those skilled in the art, and can be appropriately extracted from these descriptions. It should be noted that one aspect of the present invention solves at least one of the problems listed above and other problems. It should be noted that one aspect of the present invention does not need to solve all of the problems listed above and other problems. [Means for solving the problem]

[0013] (1) One aspect of the present invention is a semiconductor device having a first cell array, a second cell array, and a first conversion circuit. The first cell array has a first cell and a second cell arranged in the same row as the first cell, and the second cell array has a third cell and a fourth cell arranged in the same row as the third cell. The first conversion circuit has a plurality of input terminals and a plurality of output terminals. The first cell is electrically connected to a first wiring and a second wiring, and the second cell is electrically connected to a first wiring and a third wiring. Each of the plurality of input terminals of the first conversion circuit is electrically connected to a second wiring and a third wiring, and each of the plurality of output terminals of the first conversion circuit is electrically connected to a fourth wiring and a fifth wiring. The third cell is electrically connected to a fourth wiring and a sixth wiring, and the fourth cell is electrically connected to a fifth wiring and a seventh wiring. The sixth wiring is electrically connected to the seventh wiring. The first cell has the function of supplying a first current to the second wire in an amount corresponding to the product of the first data held in the first cell and the second data input to the first cell from the first wire. The second cell has the function of supplying a second current to the third wire in an amount corresponding to the product of the third data held in the second cell and the fourth data input to the second cell from the first wire. The first conversion circuit also has the function of supplying a fifth data to the fourth wire in an amount corresponding to the total amount of current that has flowed from the second wire, and a sixth data to the fifth wire in an amount corresponding to the total amount of current that has flowed from the third wire. The third cell has the function of supplying a third current to the sixth wire in an amount corresponding to the product of the seventh data held in the third cell and the fifth data input to the third cell from the fourth wire. The fourth cell has the function of supplying a fourth current to the seventh wire in an amount corresponding to the product of the eighth data held in the fourth cell and the sixth data input to the fourth cell from the fifth wire.

[0014] (2) Alternatively, in one aspect of the present invention, the configuration in (1) above may include a second conversion circuit. In particular, the second conversion circuit has an input terminal and an output terminal, and it is preferable that the input terminal of the second conversion circuit is electrically connected to the sixth wiring. Furthermore, it is preferable that the second conversion circuit has a function to output a ninth data corresponding to the total amount of current flowing from the sixth wiring to the output terminal of the second conversion circuit.

[0015] (3) Alternatively, in one aspect of the present invention, the configuration in (1) or (2) above may include a fifth cell, a sixth cell, and a seventh cell. In particular, it is preferable that each of the first cell, second cell, third cell, and fourth cell includes a first transistor, a second transistor, and a first capacitor. It is also preferable that each of the fifth cell, sixth cell, and seventh cell includes a third transistor, a fourth transistor, and a second capacitor. In each of the first cell, second cell, third cell, and fourth cell, it is preferable that the gate of the first transistor is electrically connected to the first terminal of the first capacitor and the first terminal of the second transistor, and the first terminal of the first transistor is electrically connected to the second terminal of the second transistor. Furthermore, in the first cell, it is preferable that the first terminal of the first transistor is electrically connected to the second wiring, and the second terminal of the first capacitor is electrically connected to the first wiring. Furthermore, in the second cell, it is preferable that the first terminal of the first transistor is electrically connected to the third wiring, and the second terminal of the first capacitor is electrically connected to the first wiring. Furthermore, in the third cell, it is preferable that the first terminal of the first transistor is electrically connected to the sixth wiring, and the second terminal of the first capacitor is electrically connected to the fourth wiring. Furthermore, in the fourth cell, it is preferable that the first terminal of the first transistor is electrically connected to the seventh wiring, and the second terminal of the first capacitor is electrically connected to the fifth wiring. Furthermore, in each of the fifth, sixth, and seventh cells, it is preferable that the gate of the third transistor is electrically connected to the first terminal of the second capacitor and the first terminal of the fourth transistor, and the first terminal of the third transistor is electrically connected to the second terminal of the fourth transistor. Furthermore, in the fifth cell, it is preferable that the first terminal of the third transistor is electrically connected to the first wiring, and the second terminal of the second capacitor is electrically connected to the first wiring. Furthermore, in the sixth cell, it is preferable that the first terminal of the third transistor is electrically connected to the fourth wiring, and the second terminal of the second capacitor is electrically connected to the fourth wiring. Furthermore, in the seventh cell, it is preferable that the first terminal of the third transistor is electrically connected to the fifth wiring, and the second terminal of the second capacitor is electrically connected to the fifth wiring.

[0016] (4) Alternatively, in one aspect of the present invention, the (3) above may have a first circuit and a second circuit, wherein the first circuit is electrically connected to the first wiring and the second circuit is electrically connected to the fourth wiring and the fifth wiring. In particular, it is preferable that the first circuit has the function of inputting second data to the first wiring and the second circuit has the function of supplying current to the fourth wiring and the fifth wiring.

[0017] (5) Alternatively, one aspect of the present invention is a display device having a first layer including any one of the semiconductor devices described in (1) to (4) above, and a second layer including a display unit, wherein the second layer has an area superimposed on the first layer.

[0018] (6) Alternatively, one aspect of the present invention is an electronic device having the display device described in (5) above and a housing.

[0019] In this specification, a semiconductor device refers to a device that utilizes semiconductor properties, specifically a circuit containing semiconductor elements (e.g., transistors, diodes, and photodiodes), or a device having such a circuit. It also refers to any device that can function by utilizing semiconductor properties. For example, integrated circuits, chips equipped with integrated circuits, and electronic components with chips housed in packages are all examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices may themselves be semiconductor devices or may contain semiconductor devices.

[0020] Furthermore, where it is stated in this specification that X and Y are connected, this specification shall include cases where X and Y are electrically connected, functionally connected, and directly connected. Therefore, it shall not be limited to predetermined connection relationships, such as those shown in the figures or text, but shall also include connection relationships other than those shown in the figures or text. X and Y shall be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, and layers).

[0021] One example of a case where X and Y are electrically connected is that one or more elements that enable the electrical connection between X and Y (e.g., switches, transistors, capacitive elements, inductors, resistors, diodes, display devices, light-emitting devices, and loads) can be connected between X and Y. Note that a switch has the function of being controlled to be on or off. In other words, a switch has the function of controlling whether or not current flows by being in a conductive state (on state) or a non-conductive state (off state).

[0022] One example of a functional connection between X and Y is when one or more circuits that enable the functional connection between X and Y (e.g., logic circuits (e.g., inverters, NAND gates, and NOR gates), signal conversion circuits (e.g., digital-to-analog conversion circuits, analog-to-digital conversion circuits, and gamma correction circuits), potential level conversion circuits (e.g., power supply circuits (e.g., boost circuits, and buck circuits), and level shifter circuits that change the potential level of a signal), voltage sources, current sources, switching circuits, amplification circuits (e.g., circuits that can increase the signal amplitude or current, operational amplifiers, differential amplifiers, source follower circuits, and buffer circuits), signal generation circuits, memory circuits, and control circuits) can be connected between X and Y. Note that, as an example, even if another circuit is placed between X and Y, if a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0023] Furthermore, when it is explicitly stated that X and Y are electrically connected, this includes both cases where X and Y are electrically connected (i.e., connected with another element or circuit in between) and cases where X and Y are directly connected (i.e., connected without another element or circuit in between).

[0024] Furthermore, this specification deals with circuit configurations in which multiple elements are electrically connected to wiring (wiring that supplies a constant potential or wiring that transmits a signal). For example, if X and wiring are directly connected, and Y and the wiring are directly connected, this specification may state that X and Y are directly electrically connected.

[0025] Furthermore, it can be expressed as, for example, "X, Y, the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and the connection is in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Alternatively, it can be expressed as, "The source (or first terminal, etc.) of the transistor is electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Alternatively, it can be expressed as, "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using similar notation to these examples to define the order of connections in a circuit configuration, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished and their technical scope determined. Note that these notational methods are examples only and are not limited to them. Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, and layers).

[0026] Even if independent components are shown as electrically connected in a circuit diagram, a single component may possess the functions of multiple components. For example, if part of a wire also functions as an electrode, a single conductive film possesses the functions of both a wire and an electrode. Therefore, in this specification, "electrically connected" includes cases where a single conductive film possesses the functions of multiple components.

[0027] Furthermore, in this specification, "resistive element" can refer to, for example, a circuit element having a resistance value higher than 0Ω, or wiring having a resistance value higher than 0Ω. Therefore, in this specification, "resistive element" includes wiring having a resistance value, transistors, diodes, coils, etc., through which current flows between the source and drain. Therefore, the term "resistive element" can sometimes be replaced with terms such as "resistance," "load," and "region having a resistance value." Conversely, the terms "resistance," "load," and "region having a resistance value" can sometimes be replaced with the term "resistive element." The resistance value can be, for example, preferably 1mΩ or more and 10Ω or less, more preferably 5mΩ or more and 5Ω or less, and even more preferably 10mΩ or more and 1Ω or less. Also, for example, 1Ω or more and 1 × 10 9 It may also be less than or equal to Ω.

[0028] Furthermore, in this specification, "capacitive element" may refer to, for example, a circuit element having a capacitance value higher than 0F, a region of wiring having a capacitance value higher than 0F, parasitic capacitance, or the gate capacitance of a transistor. Also, the terms "capacitive element," "parasitic capacitance," and "gate capacitance" may be replaced with the term "capacitance." Conversely, the term "capacitance" may be replaced with the terms "capacitive element," "parasitic capacitance," and "gate capacitance." In addition, the term "pair of electrodes" in relation to "capacitance" may be replaced with "pair of conductors," "pair of conductive regions," or "pair of regions." The capacitance value may be, for example, 0.05fF or more and 10pF or less. Alternatively, it may be, for example, 1pF or more and 10μF or less.

[0029] Furthermore, in this specification, a transistor has three terminals called the gate, source, and drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as source or drain are the input and output terminals of the transistor. Depending on the conductivity type of the transistor (n-channel type, p-channel type) and the potential applied to the three terminals of the transistor, one of the two input and output terminals becomes the source and the other becomes the drain. For this reason, in this specification, terms such as source and drain may be interchangeable. Also, in this specification, when describing the connection relationships of a transistor, the notation "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) is used. Depending on the structure of the transistor, in addition to the three terminals described above, there may be a back gate. In this case, in this specification, one of the gate or back gate of the transistor may be called the first gate, and the other of the gate or back gate of the transistor may be called the second gate. Furthermore, in the same transistor, the terms "gate" and "back gate" may be interchangeable. Furthermore, if a transistor has three or more gates, in this specification, each gate may be referred to as the first gate, second gate, third gate, and so on.

[0030] For example, in this specification, a transistor with a multi-gate structure having two or more gate electrodes can be used as an example of a transistor. In a multi-gate structure, the channel formation regions are connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-current and improve the transistor's breakdown voltage (improve reliability). Alternatively, the multi-gate structure allows for a voltage-current characteristic with a flat slope, where the current between the drain and source does not change much even when the voltage between the drain and source changes during operation in the saturation region. By utilizing this flat voltage-current characteristic, an ideal current source circuit or an active load with very high resistance can be realized. As a result, for example, a differential circuit or current mirror circuit with good characteristics can be realized.

[0031] Furthermore, even if a single circuit element is depicted in a circuit diagram, that element may actually comprise multiple circuit elements. For example, if one resistor is shown in a circuit diagram, it includes cases where two or more resistors are electrically connected in series. Similarly, if one capacitor is shown in a circuit diagram, it includes cases where two or more capacitors are electrically connected in parallel. Similarly, if one transistor is shown in a circuit diagram, it includes cases where two or more transistors are electrically connected in series and the gates of each transistor are electrically connected to each other. Likewise, if one switch is shown in a circuit diagram, it includes cases where the switch has two or more transistors, and these two or more transistors are electrically connected in series or in parallel, and the gates of each transistor are electrically connected to each other.

[0032] Furthermore, in this specification, the term "node" can be replaced with "terminal," "wiring," "electrode," "conductive layer," "conductor," or "impurity region," depending on the circuit configuration and device structure. Also, "terminal" or "wiring" can be replaced with "node."

[0033] Furthermore, in this specification, "voltage" and "potential" may be used interchangeably as appropriate. "Voltage" is the potential difference from a reference potential; for example, if the reference potential is the ground potential (earth potential), then "voltage" can be replaced with "potential." Note that the ground potential does not necessarily mean 0V. Also, potential is relative, and as the reference potential changes, the potential applied to the wiring, the potential applied to the circuit, and the potential output from the circuit also change.

[0034] Furthermore, in this specification, the terms "high-level potential" and "low-level potential" do not refer to specific potentials. For example, if two wires are described as "functioning as wires that supply a high-level potential," the high-level potentials provided by each wire do not have to be equal. Similarly, if two wires are described as "functioning as wires that supply a low-level potential," the low-level potentials provided by each wire do not have to be equal.

[0035] "Electric current" refers to the phenomenon of electric charge movement (electrical conduction). For example, the statement "electrical conduction of positively charged material is occurring" can be rephrased as "electrical conduction of negatively charged material is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "electric current" refers to the phenomenon of electric charge movement associated with the movement of carriers (electrical conduction). Carriers here include, for example, electrons, holes, anions, cations, and complex ions, and the carriers differ depending on the system through which the current flows (e.g., semiconductors, metals, electrolytes, and vacuum). Furthermore, the "direction of current" in wiring, etc., is the direction in which positively charged carriers move and is expressed as a positive current quantity. In other words, the direction in which negatively charged carriers move is the opposite direction to the direction of the current and is expressed as a negative current quantity. Therefore, in this specification, unless otherwise specified regarding the positive or negative (or direction) of the current, a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A." Furthermore, any statement such as "current is input to element A" can be rephrased as "current is output from element A."

[0036] Furthermore, the ordinal numbers "1st," "2nd," and "3rd" in this specification are used to avoid confusion of constituent elements. Therefore, they do not limit the number of constituent elements, nor do they limit the order of the constituent elements. For example, a constituent element referred to as "1st" in one embodiment of this specification may be referred to as "2nd" in another embodiment or in the claims. Also, for example, a constituent element referred to as "1st" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0037] Furthermore, in this specification, terms indicating placement such as "above" and "below" are sometimes used for convenience to explain the positional relationship between components with reference to the drawings. Also, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms explained in the specification are not limited to those described and can be appropriately rephrased depending on the situation. For example, the expression "insulator located on the upper surface of the conductor" can be rephrased as "insulator located on the lower surface of the conductor" by rotating the orientation of the drawing shown by 180 degrees.

[0038] Furthermore, the terms "above" or "below" do not limit the positional relationship of the components to being directly above or below each other and in direct contact. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude cases where other components are included between insulating layer A and electrode B.

[0039] Furthermore, in this specification, the terms "rows" and "columns" may be used to describe the matrix-like arrangement of components and their positional relationships. The positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terminology used is not limited to that described in the specification and can be appropriately rephrased depending on the situation. For example, the expression "row direction" can sometimes be rephrased as "column direction" by rotating the orientation of the drawing shown by 90 degrees.

[0040] Furthermore, in this specification, the terms "film" and "layer" can be interchanged as needed. For example, the term "conductive layer" may be changed to "conductive film." Or, for example, the term "insulating film" may be changed to "insulating layer." Alternatively, depending on the circumstances, the terms "film" and "layer" can be omitted and replaced with other terms. For example, the terms "conductive layer" or "conductive film" may be changed to "conductor." Or, for example, the terms "insulating layer" or "insulating film" may be changed to "insulator."

[0041] Furthermore, in this specification, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, "electrode" may be used as part of "wiring," and vice versa. Moreover, the terms "electrode" or "wiring" include cases where multiple "electrodes" or "wiring" are formed as a single unit. Similarly, for example, "terminal" may be used as part of "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" also includes cases where multiple "electrodes," "wiring," or "terminals" are formed as a single unit. Therefore, for example, an "electrode" can be part of "wiring" or a "terminal," and for example, a "terminal" can be part of "wiring" or an "electrode." In addition, terms such as "electrode," "wiring," or "terminal" may be replaced with terms such as "region" depending on the context.

[0042] Furthermore, in this specification, terms such as "wiring," "signal line," and "power line" can be interchanged depending on the circumstances or situation. For example, the term "wiring" may be changed to the term "signal line." Similarly, the term "wiring" may be changed to the term "power line." The reverse is also true; the terms "signal line" or "power line" may be changed to the term "wiring." The term "power line" may be changed to the term "signal line." Similarly, the reverse is also true; the term "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to the wiring may be changed to the term "signal" depending on the circumstances or situation. Similarly, the term "signal" may be changed to the term "potential."

[0043] In this specification, semiconductor impurities refer to elements other than the main components that make up the semiconductor layer. For example, elements with a concentration of less than 0.1 atomic percent are impurities. The presence of impurities can cause, for example, an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that alter the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components. In particular, examples include hydrogen (which is also found in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Specifically, when the semiconductor is a silicon layer, examples of impurities that alter the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, and Group 15 elements (excluding oxygen and hydrogen).

[0044] In this specification, a switch refers to a device that has the function of controlling whether or not to allow current to flow by being in a conductive (on) state or a non-conductive (off) state. Alternatively, a switch refers to a device that has the function of selecting and switching the path through which current flows. Therefore, a switch may have two or more terminals for conducting current in addition to the control terminal. For example, an electrical switch or a mechanical switch can be used. In other words, a switch is not limited to any particular type, as long as it can control current.

[0045] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, and diode-connected transistors), or logic circuits combining these. When a transistor is used as a switch, the "conducting state" of the transistor refers to a state where, for example, the source and drain electrodes of the transistor can be considered electrically short-circuited, or a state where current can flow between the source and drain electrodes. Conversely, the "non-conducting state" of the transistor refers to a state where the source and drain electrodes of the transistor can be considered electrically disconnected. When a transistor is simply operated as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0046] One example of a mechanical switch is a switch using MEMS (Micro-Electro-Mechanical Systems) technology. This switch has mechanically movable electrodes, and it operates by controlling the conduction and non-conductivity through the movement of these electrodes.

[0047] Furthermore, in this specification, devices fabricated using a metal mask or FMM (Fine Metal Mask, a high-resolution metal mask) may be referred to as MM (Metal Mask) structured devices. Also, in this specification, devices fabricated without using a metal mask or FMM may be referred to as MML (Metal Maskless) structured devices.

[0048] In this specification, a structure in which different light-emitting layers are created or painted for each color of light-emitting device (here, blue (B), green (G), and red (R)) may be referred to as an SBS (Side By Side) structure. Also, in this specification, a light-emitting device capable of emitting white light may be referred to as a white light-emitting device. A white light-emitting device can be combined with a colored layer (for example, a color filter) to create a full-color display device.

[0049] Furthermore, light-emitting devices can be broadly classified into single structures and tandem structures. A single-structure device has one light-emitting unit between a pair of electrodes, and it is preferable that this light-emitting unit includes one or more light-emitting layers. When obtaining white light emission using two light-emitting layers, the light-emitting layers should be selected such that the light-emitting colors of each layer are complementary. For example, by making the light-emitting color of the first light-emitting layer and the light-emitting color of the second light-emitting layer complementary, a configuration that emits white light as a whole can be obtained. Also, when obtaining white light emission using three or more light-emitting layers, the light-emitting device should be configured so that the light-emitting colors of the three or more layers combine to emit white light as a whole.

[0050] A tandem device preferably has two or more light-emitting units between a pair of electrodes, and each light-emitting unit preferably includes one or more light-emitting layers. To obtain white light emission, the device should be configured such that the light from the light-emitting layers of the multiple light-emitting units is combined to produce white light emission. The configuration for obtaining white light emission is the same as that for a single-structure device. In a tandem device, it is preferable to provide an intermediate layer, such as a charge-generating layer, between the multiple light-emitting units.

[0051] Furthermore, when comparing the aforementioned white light-emitting devices (single or tandem structure) with SBS structure light-emitting devices, SBS structure light-emitting devices can consume less power than white light-emitting devices. If you want to keep power consumption low, it is preferable to use SBS structure light-emitting devices. On the other hand, white light-emitting devices are preferable because their manufacturing process is simpler than that of SBS structure light-emitting devices, which can lead to lower manufacturing costs or higher manufacturing yields.

[0052] In this specification, "parallel" means a state in which two lines are positioned at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Furthermore, "approximately parallel" or "roughly parallel" means a state in which two lines are positioned at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" means a state in which two lines are positioned at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. Furthermore, "approximately perpendicular" or "roughly perpendicular" means a state in which two lines are positioned at an angle of 60° or more and 120° or less. [Effects of the Invention]

[0053] According to one aspect of the present invention, a semiconductor device with a reduced circuit area can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device that does not suffer a decrease in computational efficiency per unit area even when performing small-scale calculations can be provided. Alternatively, according to one aspect of the present invention, a display device including any of the above-described semiconductor devices can be provided. Alternatively, according to one aspect of the present invention, an electronic device having the above-described display device can be provided. Alternatively, according to one aspect of the present invention, a novel semiconductor device, a novel display device, or a novel electronic device can be provided.

[0054] The effects of one aspect of the present invention are not limited to those listed above. The effects listed above do not preclude the existence of other effects. These other effects are those described below and not mentioned in this section. Those not mentioned in this section can be derived from the description in the specification or drawings, etc., by those skilled in the art, and can be appropriately extracted from these descriptions. One aspect of the present invention has at least one of the effects listed above and other effects. Therefore, one aspect of the present invention may, in some cases, not have the effects listed above. [Brief explanation of the drawing]

[0055] [Figure 1] Figure 1 is a block diagram showing an example configuration of a semiconductor device. [Figure 2] Figure 2 is a block diagram showing an example configuration of a semiconductor device. [Figure 3] Figure 3 is a circuit diagram showing an example of a semiconductor device configuration. [Figure 4] Figure 4A is a block diagram showing an example of the circuit configuration included in a semiconductor device, Figure 4B is a circuit diagram showing an example of the circuit configuration included in a semiconductor device, and Figure 4C is a block diagram showing an example of the circuit configuration included in a semiconductor device. [Figure 5] Figures 5A to 5D are circuit diagrams showing example configurations of circuits included in semiconductor devices. [Figure 6] Figure 6 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 7] Figure 7 is a timing chart showing an example of the operation of a semiconductor device. [Figure 8] Figure 8 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 9] Figure 9 is a block diagram showing an example configuration of a semiconductor device. [Figure 10] Figure 10 is a block diagram showing an example of the circuit configuration included in a semiconductor device. [Figure 11] Figure 11 is a circuit diagram showing an example of a semiconductor device configuration. [Figure 12] Figures 12A and 12B are circuit diagrams showing example configurations of circuits included in a semiconductor device. [Figure 13] Figure 13 is a block diagram showing an example of a semiconductor device configuration. [Figure 14] Figure 14 is a block diagram showing an example of a display device configuration. [Figure 15] Figure 15 illustrates an example of a display device configuration. [Figure 16] Figures 16A and 16B illustrate a hierarchical neural network. [Figure 17] Figure 17 is a schematic cross-sectional view showing an example of the configuration of a display device. [Figure 18] Figures 18A to 18D are schematic diagrams showing examples of the configuration of a light-emitting device. [Figure 19] Figure 19 is a schematic cross-sectional view showing an example of the configuration of a display device. [Figure 20] Figures 20A and 20B are schematic cross-sectional diagrams showing examples of the configuration of a display device. [Figure 21] Figures 21A and 21B are schematic cross-sectional diagrams showing examples of the configuration of a display device. [Figure 22] Figures 22A and 22B are schematic cross-sectional diagrams showing examples of the configuration of a display device. [Figure 23] Figures 23A and 23B are schematic cross-sectional diagrams showing examples of the configuration of a display device. [Figure 24]Figures 24A to 24F are cross-sectional views showing an example of a method for manufacturing a display device. [Figure 25] Figure 25A is a circuit diagram showing an example of the configuration of a pixel circuit included in a display device, and Figure 25B is a schematic perspective view showing an example of the configuration of a pixel circuit included in a display device. [Figure 26] Figures 26A to 26D are circuit diagrams showing examples of the configuration of pixel circuits included in a display device. [Figure 27] Figures 27A to 27D are circuit diagrams showing examples of the configuration of pixel circuits included in a display device. [Figure 28] Figures 28A and 28B are plan views showing examples of the configuration of a light-emitting device and a light-receiving device included in a display device. [Figure 29] Figures 29A to 29D are schematic cross-sectional diagrams showing examples of the configuration of a light-emitting device, a light-receiving device, and connecting electrodes included in a display device. [Figure 30] Figures 30A to 30G are plan views showing an example of a pixel. [Figure 31] Figures 31A to 31F are plan views showing an example of a pixel. [Figure 32] Figures 32A to 32H are plan views showing an example of a pixel. [Figure 33] Figures 33A to 33D are plan views showing an example of a pixel. [Figure 34] Figures 34A to 34D are plan views showing an example of a pixel, and Figure 34E is a cross-sectional view showing an example of a display device. [Figure 35] Figures 35A and 35B show examples of the configuration of a display module. [Figure 36] Figures 36A to 36F show examples of the configuration of electronic equipment. [Figure 37] Figures 37A to 37D show examples of the configuration of electronic equipment. [Figure 38] Figures 38A to 38C show examples of the configuration of electronic equipment. [Modes for carrying out the invention]

[0056] In this specification, "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also called oxide semiconductors or simply OS), etc. For example, if a metal oxide is included in the channel formation region of a transistor, that metal oxide may be referred to as an oxide semiconductor. In other words, if a metal oxide can constitute the channel formation region of a transistor having at least one of amplification, rectification, and switching functions, that metal oxide can be referred to as a metal oxide semiconductor. Furthermore, when an OS transistor is described, it can be rephrased as a transistor having a metal oxide or oxide semiconductor.

[0057] Furthermore, in this specification, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Alternatively, metal oxides containing nitrogen may be called metal oxynitrides.

[0058] Furthermore, in this specification, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. Also, if multiple configuration examples are shown within one embodiment, these configuration examples can be appropriately combined with each other.

[0059] Furthermore, any content described in one embodiment (even partial content) may be applied to, combined with, or substituted for at least one of the contents described in another embodiment (even partial content) and one or more other embodiments (even partial content).

[0060] The content described in the embodiments refers to the content described using various figures or the content described using text in the specification in each embodiment.

[0061] Furthermore, a diagram (even a part of it) described in one embodiment can be combined with another part of that diagram, another diagram (even a part of it) described in the same embodiment, and at least one diagram (even a part of it) described in one or more other embodiments to form even more diagrams.

[0062] The embodiments described herein are explained with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope thereof. Therefore, the present invention is not to be interpreted as being limited to the contents described in the embodiments. In the configuration of the invention in the embodiments, the same reference numerals are used in common across different drawings for the same parts or parts having similar functions, and repeated explanations may be omitted. Also, in perspective views and the like, some components may be omitted in order to ensure clarity of the drawings.

[0063] Furthermore, in the drawings of this specification, plan views may be used to explain the configuration of each embodiment. A plan view is, for example, a diagram showing the surface (cut) of a configuration cut horizontally. In addition, hidden lines (e.g., dashed lines) can be included in the plan view to show the positional relationships of multiple elements included in the configuration, or the relationships of overlap of such multiple elements. In this specification, the term "plan view" may be replaced with the terms "projection view," "top view," or "bottom view." Also, depending on the situation, a surface (cut) cut in a direction other than the horizontal direction, rather than a surface (cut) cut horizontally, may be referred to as a plan view.

[0064] Furthermore, in the drawings of this specification, cross-sectional views may be used to explain the configuration of each embodiment. A cross-sectional view is, for example, a diagram showing the surface (cut) of a configuration cut in the vertical direction. In this specification, the term "cross-sectional view" may be replaced with the terms "front view" or "side view." Also, depending on the situation, a surface (cut) cut in a direction other than the vertical direction may be referred to as a cross-sectional view.

[0065] In this specification, when the same reference numeral is used for multiple elements, and especially when it is necessary to distinguish them, the reference numeral may be accompanied by an identifying numeral such as "_1", "[n]", or "[m,n]". In addition, in drawings, etc., when an identifying numeral such as "_1", "[n]", or "[m,n]" is accompanied by a reference numeral, the identifying numeral may be omitted in this specification if it is not necessary to distinguish them.

[0066] Furthermore, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, they may include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences.

[0067] (Embodiment 1) This embodiment describes a semiconductor device according to one aspect of the present invention.

[0068] <Configuration Example 1> Figure 1 is a block diagram showing an example configuration of an arithmetic circuit in a semiconductor device according to one aspect of the present invention. This arithmetic circuit has, for example, a function to calculate the sum of products of a plurality of first data and a plurality of second data, and a function to perform a function operation using the result of the sum of products as an input value. Furthermore, this sum of products arithmetic circuit also has, for example, a function to perform operations on a hierarchical neural network.

[0069] The arithmetic circuit 10 shown in Figure 1 includes, as an example, region L1 and region L2. Regions L1 and L2 each include, as an example, a cell array CA, circuit WCS, circuit WSD, and circuit ITS. In addition, region L1 differs from region L2 in that it includes circuit XCS.

[0070] In each of regions L1 and L2, the cell array CA is, for example, composed of multiple calculation cells arranged in a matrix. Furthermore, the cell array CA is divided into multiple sub-arrays, for example. Specifically, for example, in each of regions L1 and L2, the multiple calculation cells arranged in the cell array CA are divided into regions of sub-array SA_1 to sub-array SA_p (where p is an integer of 2 or more).

[0071] In region L1, each of the subarrays SA_1 to SA_p has, for example, multiple cells IM that function as computation cells. In particular, in each of the subarrays SA_1 to SA_p contained in region L1, the cells IM are arranged in a matrix of m rows and n columns (where m is an integer greater than or equal to 1, and n is an integer greater than or equal to 1). Therefore, in Figure 1, the cell array CA has m × n × p cells IM.

[0072] In region L2, each of the subarrays SA_1 to SA_p has, for example, multiple cells IM that function as computation cells. In particular, in each of the subarrays SA_1 to SA_p contained in region L2, the cells IM are arranged in a matrix of n rows and k columns (where k is an integer greater than or equal to 1). Therefore, in Figure 1, the cell array CA has n × k × p cells IM.

[0073] Here, by setting k=n, the number of columns in the cell array CA of region L1 becomes equal to the number of columns in the cell array CA of region L2. By making the number of columns in the cell array CA of region L1 and the number of columns in the cell array CA of region L2 equal, the cells IM can be efficiently arranged when viewed as a whole in the arithmetic circuit 10, and thus the area required to form the arithmetic circuit 10 can be reduced.

[0074] The commas [ , ] attached to the cell IM in Figure 1 indicate the address within the subarray where that cell IM is located. For example, cell IM[x,y] indicates that cell IM[x,y] is located in the x-row, y-column position of that subarray.

[0075] In region L1, circuit WCS is electrically connected, for example, to wiring WCL[1]_1 to wiring WCL[n]_1 and wiring WCL[1]_p to wiring WCL[n]_p. Although not shown in Figure 1, when p is 3 or greater, circuit WCS is also electrically connected to wiring WCL[1] to wiring WCL[n] in sub-array SA other than sub-array SA_1 and sub-array SA_p. Similarly, circuit ITS is electrically connected, for example, to wiring WCL[1]_1 to wiring WCL[n]_1 and wiring WCL[1]_p to wiring WCL[n]_p. Although not shown in Figure 1, when p is 3 or greater, circuit ITS is also electrically connected to wiring WCL[1] to wiring WCL[n] in sub-array SA other than sub-array SA_1 and sub-array SA_p.

[0076] Furthermore, each of the wirings WCL[1]_1 through WCL[n]_1 is electrically connected to a cell IM included in subarray SA_1. Specifically, wiring WCL[1]_1 is electrically connected to cells IM[1,1] through IM[m,1] located in the first column of subarray SA_1, and wiring WCL[n]_1 is electrically connected to cells IM[1,n] through IM[m,n] located in the nth column of subarray SA_1. In addition, each of the wirings WCL[1]_p through WCL[n]_p is electrically connected to a cell IM included in subarray SA_p. Specifically, wiring WCL[1]_p is electrically connected to cells IM[1,1] through IM[m,1] located in the first column of subarray SA_p, and wiring WCL[n]_p is electrically connected to cells IM[1,n] through IM[m,n] located in the nth column of subarray SA_p.

[0077] In region L1, circuit XCS is electrically connected, for example, to wiring XCL[1] to wiring XCL[m].

[0078] Furthermore, each of the wirings XCL[1] through XCL[m] is electrically connected to the cell IM contained in each of the subarrays SA_1 through SA_p. Specifically, wiring XCL[1] is electrically connected to the cells IM[1,1] through IM[1,n] located in the first row of each of the subarrays SA_1 through SA_p. Also, wiring XCL[m] is electrically connected to the cells IM[m,1] through IM[m,n] located in the m row of each of the subarrays SA_1 through SA_p.

[0079] In region L1, circuit WSD is electrically connected, for example, to wiring WSL[1] to wiring WSL[m].

[0080] Furthermore, each of the wirings WSL[1] through WSL[m] is electrically connected to the cell IM contained in each of the subarrays SA_1 through SA_p. Specifically, wiring WSL[1] is electrically connected to the cells IM[1,1] through IM[1,n] located in the first row of each of the subarrays SA_1 through SA_p. Also, wiring WSL[m] is electrically connected to the cells IM[m,1] through IM[m,n] located in the m row of each of the subarrays SA_1 through SA_p.

[0081] The circuit ITS contained in region L1 is electrically connected to wiring OL[1]_1 through OL[n]_1 and wiring OL[1]_p through OL[n]_p, respectively. Although not shown in Figure 1, when p is 3 or greater, the circuit ITS is also electrically connected to wiring OL[1]_s through OL[n]_s (where s is an integer between 2 and p-1).

[0082] Furthermore, each of the wirings OL[1]_1 to OL[n]_1 contained in region L1 is electrically connected one-to-one to each of the wirings XCL[1]_1 to XCL[n]_1 contained in region L2, and each of the wirings OL[1]_p to OL[n]_p contained in region L1 is electrically connected one-to-one to each of the wirings XCL[1]_p to XCL[n]_p contained in region L2.

[0083] In region L2, circuit WCS is electrically connected, for example, to wiring WCL[1]_1 through WCL[k]_1 and wiring WCL[1]_p through WCL[k]_p. Although not shown in Figure 1, when p is 3 or greater, circuit WCS is also electrically connected to wiring WCL[1] through WCL[n] in sub-array SA other than sub-array SA_1 and sub-array SA_p.

[0084] Furthermore, wiring WCL[1]_1 is electrically connected to wiring WCL[1]_p. Although not shown in Figure 1, if p is 3 or greater, wiring WCL[1]_1 is electrically connected to each of the wirings WCL[1]_2 through WCL[1]_p-1 that extend to the first column of each of the different sub-arrays SA. Also, wiring WCL[k]_1 is electrically connected to wiring WCL[k]_p. Although not shown, if p is 3 or greater, wiring WCL[k]_1 is electrically connected to each of the wirings WCL[k]_2 through WCL[k]_p-1 that extend to the k column of each of the different sub-arrays SA.

[0085] Furthermore, each of the wirings WCL[1]_1 through WCL[k]_1 is electrically connected to a cell IM included in subarray SA_1. Specifically, wiring WCL[1]_1 is electrically connected to cells IM[1,1] through IM[n,1] located in the first column of subarray SA_1, and wiring WCL[k]_1 is electrically connected to cells IM[1,k] through IM[n,k] located in the kth column of subarray SA_1. Additionally, each of the wirings WCL[1]_p through WCL[k]_p is electrically connected to a cell IM included in subarray SA_p. Specifically, wiring WCL[1]_p is electrically connected to cells IM[1,1] through IM[n,1] located in the first column of subarray SA_p, and wiring WCL[k]_p is electrically connected to cells IM[1,k] through IM[n,k] located in the kth column of subarray SA_p.

[0086] In region L2, each of the wirings XCL[1]_1 through XCL[n]_1 is electrically connected to a cell IM contained in subarray SA_1. Specifically, wiring XCL[1]_1 is electrically connected to cells IM[1,1] through IM[1,k] located in the first row of subarray SA_1. Also, wiring XCL[n]_1 is electrically connected to cells IM[n,1] through IM[n,k] located in the nth row of subarray SA_1. Furthermore, each of the wirings XCL[1]_p through XCL[n]_p is electrically connected to a cell IM contained in subarray SA_p. Specifically, wiring XCL[1]_p is electrically connected to cells IM[1,1] through IM[1,k] located in the first row of subarray SA_p. Also, wiring XCL[n]_p is electrically connected to cells IM[n,1] through IM[n,k] located in the nth row of subarray SA_p.

[0087] In region L2, circuit WSD is electrically connected, for example, to wiring WSL[1] through wiring WSL[n].

[0088] Furthermore, each of the wirings WSL[1] through WSL[n] is electrically connected to the cell IM contained in each of the subarrays SA_1 through SA_p. Specifically, wiring WSL[1] is electrically connected to the cells IM[1,1] through IM[1,k] located in the first row of each of the subarrays SA_1 through SA_p. Also, wiring WSL[n] is electrically connected to the cells IM[n,1] through IM[n,k] located in the nth row of each of the subarrays SA_1 through SA_p.

[0089] In region L2, each of the wirings WCL[1]_1 through WCL[k]_1 is electrically connected to circuit ITS. Circuit ITS is also electrically connected to the wirings OL[1] through OL[k].

[0090] Next, the cell IM, circuit WCS, circuit XCS, circuit WSD, and circuit ITS of the arithmetic circuit 10 in Figure 1 will be described.

[0091] Cell IM in region L1 and region L2, for example, has the function of holding the first data. Furthermore, when a signal to be used as the second data is input to cell IM, it has the function of outputting a current to wiring WCL in an amount corresponding to the product of the first data and the second data.

[0092] In region L1, the circuit WCS has the function of supplying signals (e.g., either or both current and voltage) corresponding to the first data to wiring WCL[1]_1 to wiring WCL[n]_1 and wiring WCL[1]_p to wiring WCL[n]_p. When p is 3 or greater, the circuit WCS also has the function of supplying signals corresponding to the first data to wiring WCL[1] to wiring WCL[n] in sub-array SA other than sub-array SA_1 and sub-array SA_p. Furthermore, in region L2, the circuit WCS has the function of supplying signals (e.g., either or both current and voltage) corresponding to the first data to wiring WCL[1]_1 to wiring WCL[k]_1 and wiring WCL[1]_p to wiring WCL[k]_p. In other words, the circuit WCS has the function of supplying the first data to be stored in the cell IM when the writing transistor contained in the cell IM is in the ON state.

[0093] In region L1, circuit XCS has the function of supplying signals (e.g., either or both current and voltage) corresponding to the second data or reference data described later to wiring XCL[1] to wiring XCL[m]. In other words, in the arithmetic circuit 10 of Figure 1, circuit XCS has the function of supplying signals (e.g., either or both current and voltage) corresponding to the second data or reference data to each of the cells IM of the cell array CA in region L1.

[0094] In region L1, the circuit WSD has the function of selecting the row of the cell array CA to which the first data will be written by supplying predetermined signals to wiring WSL[1] to wiring WSL[m] when writing the first data to each cell of the cell array CA. For example, the circuit WSD can supply a high-level potential to wiring WSL[1] and a low-level potential to wiring WSL[2] (not shown) to wiring WSL[m], thereby turning on the writing transistor with a gate electrically connected to wiring WSL[1] and turning off the writing transistors with gates electrically connected to each of wiring WSL[2] to wiring WSL[m]. Similarly, in region L2, the circuit WSD has the function of selecting the row of the cell array CA to which the first data will be written by supplying predetermined signals to wiring WSL[1] to wiring WSL[n] when writing the first data to each cell of the cell array CA.

[0095] In region L1, the circuit ITS has the function of converting the amount of current input from each of the wirings WCL[1]_1 to WCL[n]_1 and WCL[1]_p to WCL[n]_p into a voltage value. For example, the amount of current flowing from wiring WCL[1]_1 to the circuit ITS is the sum of the amounts of current output from each of the cells IM[1,1] to IM[m,1] in the first column of subarray SA_1. In other words, the sum of the amounts of current corresponds to the sum of the products of the multiple first data held in each of the cells IM[1,1] to IM[m,1] and the multiple second data input to each of the cells IM[1,1] to IM[m,1]. Therefore, the circuit ITS generates a voltage value from the sum of the amounts of current corresponding to the sum of the products of the multiple first data and the multiple second data. The circuit ITS may also have the function of converting this voltage value into a current quantity.

[0096] Furthermore, the circuit ITS has the function of transmitting signals such as the voltage and the current converted from that voltage value to each of the wirings OL[1]_1 to OL[n]_1 and OL[1]_p to OL[n]_p. Specifically, the circuit ITS has the function of outputting a signal to wiring OL[1]_1 corresponding to the amount of current input from wiring WCL[1]_1. Similarly, the circuit ITS has the function of outputting a signal to wiring OL[n]_1 corresponding to the amount of current input from wiring WCL[n]_1, outputting a signal to wiring OL[1]_p corresponding to the amount of current input from wiring WCL[1]_p, and outputting a signal to wiring OL[n]_p corresponding to the amount of current input from wiring WCL[n]_p.

[0097] In region L2, the circuit ITS has the function of converting the amount of current input from each of the wirings WCL[1]_1 to WCL[k]_1 and WCL[1]_p to WCL[k]_p into a voltage value. For example, the amount of current flowing from wiring WCL[1]_1 and wiring WCL[1]_p to the circuit ITS is the sum of the amounts of current output from the first column cells IM[1,1] to IM[n,1] of each of the subarrays SA_1 to SA_p. In other words, the sum of the amounts of current corresponds to the sum of the products of the multiple first data held in each cell IM[1,1] to IM[n,1] of subarrays SA_1 to SA_p and the multiple second data input to each cell IM[1,1] to IM[n,1] of subarrays SA_1 to SA_p. Therefore, the ITS circuit generates a voltage value corresponding to the sum of the products of the multiple first data and the multiple second data from the sum of the amounts of current. The ITS circuit may also have a function to convert this voltage value into an amount of current.

[0098] Furthermore, the circuit ITS has the function of transmitting signals such as the voltage and the current converted from that voltage value to each of the wirings OL[1] to OL[k]. Specifically, the circuit ITS has the function of outputting a signal to wiring OL[1] corresponding to the amount of current input from wirings WCL[1]_1 to WCL[1]_p. Similarly, the circuit ITS has the function of outputting a signal to wiring OL[k]_1 corresponding to the amount of current input from wirings WCL[k]_1 to WCL[k]_p.

[0099] In particular, in each of regions L1 and L2, the circuit ITS may have a function to perform a function operation using the sum of products of multiple first data and multiple second data as input values. The circuit ITS may also output the result of the function operation as a signal (for example, one or both of current and voltage) to wiring OL[1]_1 to wiring OL[n]_1, wiring OL[1]_p to wiring OL[n]_p (wiring OL[1] to wiring OL[k]). The above-mentioned function may be, for example, a sigmoid function, a tanh function, a softmax function, a ReLU function, or a threshold function.

[0100] As described above, by dividing the cell array CA contained in region L2 into sub-arrays SA_1 to SA_p, and by configuring the input of multiple results calculated by the cell array CA contained in region L1 and the circuit ITS as signals in the row direction of each sub-array SA_1 to SA_p, the cells IM can be efficiently arranged in the arithmetic circuit 10. Furthermore, by setting k=n, the cells IM can be arranged even more efficiently. As a result, the number of cells IM not used in calculations during calculations in the arithmetic circuit 10 can be reduced, thereby increasing the calculation efficiency per unit area of ​​the arithmetic circuit 10.

[0101] <Configuration Example 2> By the way, in the cell array CA of the arithmetic circuit 10 in Figure 1, cell IM is shown as an arithmetic cell. However, depending on the arithmetic method, in addition to cell IM, dummy arithmetic cells, reference arithmetic cells, etc., may be required. Therefore, the arithmetic circuit 10 in Figure 1 may also have separate dummy arithmetic cells or reference arithmetic cells depending on the arithmetic method.

[0102] The arithmetic circuit 10A in Figure 2 is a modified version of the arithmetic circuit 10 in Figure 1, and is a circuit configuration for when a reference arithmetic cell is required for the sum-of-products operation.

[0103] In region L1, the cell array CA includes, for example, subarrays SA_1 to SA_p, as well as subarray SAr. Subarray SAr includes, for example, cells IMref[1] to IMref[m].

[0104] Each of cells IMref[1] through IMref[m] is electrically connected on a one-to-one basis to, for example, wiring WSL[1] through WSL[m]. Furthermore, each of cells IMref[1] through IMref[m] is electrically connected on a one-to-one basis to, for example, wiring XCL[1] through XCL[m].

[0105] In region L2, the cell array CA includes, for example, subarrays SA_1 to SA_p, as well as subarrays SAr_1 to SAr_p. Each of subarrays SAr_1 to SAr_p includes, for example, cells IMref[1] to IMref[n].

[0106] Each cell IMref[1] through IMref[n] contained in subarray SAr_1 is electrically connected one-to-one to wiring WSL[1] through WSL[n], for example. Also, each cell IMref[1] through IMref[n] contained in subarray SAr_1 is electrically connected one-to-one to wiring XCL[1]_1 through XCL[n]_1, for example. Also, each cell IMref[1] through IMref[n] contained in subarray SAr_p is electrically connected one-to-one to wiring WSL[1] through WSL[n], for example. Also, each cell IMref[1] through IMref[n] contained in subarray SAr_p is electrically connected one-to-one to wiring XCL[1]_p through XCL[m]_p, for example.

[0107] Next, we will explain specific configuration examples for cell IM and cell IMref.

[0108] Figure 3 is a circuit diagram showing specific configuration examples of cell IM and cell IMref of the arithmetic circuit 10A in Figure 2. Figure 3 also shows excerpts of sub-arrays SAr and SA_s (where s is an integer between 1 and p). Furthermore, Figure 3 shows excerpts of circuits WCS, XCS, WSD, and ITS to illustrate their electrical connections with cell array CA.

[0109] Each of cells IM[1,1] through IM[m,n] has, for example, a transistor F1, a transistor F2, and a capacitor C5, and each of cells IMref[1] through IMref[m] has, for example, a transistor F1m, a transistor F2m, and a capacitor C5m.

[0110] In particular, it is preferable that the size of transistor F1 contained in each of cells IM[1,1] to IM[m,n] (e.g., channel length, channel width, transistor configuration, etc.) is equal to that of each cell IM[1,1] to IM[m,n], and that the size of transistor F2 contained in each of cells IM[1,1] to IM[m,n] is equal to that of each cell. Furthermore, it is preferable that the size of transistor F1m contained in each of cells IMref[1] to IMref[m] is equal to that of each cell. Furthermore, it is preferable that the sizes of transistor F1 and transistor F1m are equal to that of each cell. Furthermore, it is preferable that the sizes of transistor F2 and transistor F2m are equal to that of each cell.

[0111] By making the sizes of transistors equal, the electrical characteristics of each transistor can be made approximately equal. Therefore, by making the size of transistor F1 contained in each of cells IM[1,1] to IM[m,n] equal, and by making the size of transistor F2 contained in each of cells IM[1,1] to IM[m,n] equal, each of cells IM[1,1] to IM[m,n] can perform approximately the same operation under identical conditions. Here, identical conditions refer to, for example, the potentials of the source, drain, and gate of transistor F1, the potentials of the source, drain, and gate of transistor F2, and the potentials input to each of cells IM[1,1] to IM[m,n]. Furthermore, by making the size of transistor F1m contained in each of cells IMref[1] to IMref[m] equal, and by making the size of transistor F2m contained in each of cells IMref[1] to IMref[m] equal, for example, the operation and the results of that operation can be made approximately identical for cells IMref[1] to IMref[m]. They can perform almost identical operations when the conditions are the same for all of them. The same conditions here refer to, for example, the potentials of the source, drain, and gate of transistor F1m, the potentials of the source, drain, and gate of transistor F2m, and the potentials input to each of cells IMref[1] through IMref[m].

[0112] Unless otherwise specified, transistors F1 and F1m are assumed to operate in the linear region when they are ON. That is, the gate voltage, source voltage, and drain voltage of each of the transistors described above are assumed to be appropriately biased to voltages within the range in which they operate in the linear region. However, one aspect of the present invention is not limited thereto. For example, one or both of transistors F1 and F1m may operate in the saturation region when they are ON, or they may operate in a mixture of the linear region and the saturation region.

[0113] Furthermore, unless otherwise specified, transistors F2 and F2m are assumed to operate in the subthreshold region (i.e., in transistor F2 or F2m, when the gate-source voltage is lower than the threshold voltage, more preferably when the drain current increases exponentially with respect to the gate-source voltage). That is, the gate voltage, source voltage, and drain voltage of each of the transistors described above are assumed to be appropriately biased to voltages within the range of operation in the subthreshold region. For this reason, transistors F2 and F2m are assumed to operate such that an off-current (sometimes called a leakage current) flows between the source and drain.

[0114] Furthermore, it is preferable that one or both of transistors F1 and F1m are OS transistors, for example. In addition, it is more preferable that the channel-forming regions of one or both of transistors F1 and F1m be an oxide containing at least one of indium, gallium, and zinc. Alternatively, an oxide containing at least one of indium, element M (for example, one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium) and zinc may be used. It is even more preferable that one or both of transistors F1 and F1m have the transistor structure described in Embodiment 6.

[0115] By using OS transistors as one or both of transistors F1 and F1m, the leakage current of one or both of transistors F1 and F1m can be suppressed, thereby reducing the power consumption of the arithmetic circuit. Specifically, when one or both of transistors F1 and F1m are in a non-conductive state, the leakage current from the holding node to the write word line can be made very small, thus reducing the refresh operation of the holding node's potential. Furthermore, by reducing the refresh operation, the power consumption of the arithmetic circuit can be reduced. In addition, by making the leakage current from the holding node to wiring WCL or wiring XCL very small, the cell can hold the potential of the holding node for a long time, thus improving the calculation accuracy of the arithmetic circuit.

[0116] Furthermore, by using OS transistors for either or both of transistors F2 and F2m, they can be operated within a wide current range in the subthreshold region, thereby reducing current consumption. Also, by using OS transistors for transistors F2 and F2m, they can be fabricated simultaneously with transistors F1 and F1m, potentially shortening the fabrication process for the arithmetic circuit. In addition, either or both of transistors F2 and F2m can be transistors containing silicon in the channel formation region (hereinafter referred to as Si transistors), other than OS transistors. Examples of silicon that can be used include amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, and monocrystalline silicon.

[0117] Incidentally, when semiconductor devices are highly integrated onto a chip, heat may be generated on the chip due to the operation of the circuit. This heat can cause the temperature of transistors to rise, altering their characteristics, such as changes in field-effect mobility or a decrease in operating frequency. OS transistors have higher thermal resistance than Si transistors, making them less susceptible to changes in field-effect mobility due to temperature changes, and also less prone to a decrease in operating frequency. Furthermore, OS transistors tend to maintain the characteristic that the drain current increases exponentially with respect to the gate-source voltage, even at high temperatures. Therefore, using OS transistors makes it easier to perform calculations even in high-temperature environments. For this reason, when constructing a semiconductor device that is resistant to heat generated by operation, it is preferable to use OS transistors.

[0118] In each of cells IM[1,1] through IM[m,n], the first terminal of transistor F1 is electrically connected to the gate of transistor F2. The first terminal of transistor F2 is electrically connected to wiring VE. The first terminal of capacitor C5 is electrically connected to the gate of transistor F2.

[0119] Furthermore, in each of cells IMref[1] through IMref[m], the first terminal of transistor F1m is electrically connected to the gate of transistor F2m. The first terminal of transistor F2m is electrically connected to wiring VE. The first terminal of capacitor C5m is electrically connected to the gate of transistor F2m.

[0120] In Figure 3, back gates are shown for transistors F1, F2, F1m, and F2m. Although the connection configuration of these back gates is not shown, the electrical connection destination of the back gates can be determined at the design stage. For example, in a transistor with a back gate, the gate and back gate may be electrically connected to increase the on-current of the transistor. That is, for example, the gate and back gate of transistor F1 may be electrically connected, or the gate and back gate of transistor F1m may be electrically connected. Alternatively, in a transistor with a back gate, for example, wiring may be provided to electrically connect the back gate of the transistor to an external circuit, etc., in order to vary the threshold voltage of the transistor or to reduce the off-current of the transistor, thereby providing a potential to the back gate of the transistor through the external circuit, etc.

[0121] Furthermore, although transistors F1 and F2 shown in Figure 3 have back gates, the semiconductor device according to one embodiment of the present invention is not limited to this. For example, transistors F1 and F2 shown in Figure 3 may be configured without back gates, that is, single-gate transistors. Alternatively, some transistors may have back gates, while others may not.

[0122] Furthermore, although transistors F1 and F2 shown in Figure 3 are n-channel type transistors, the semiconductor device according to one embodiment of the present invention is not limited to this. For example, some or all of transistors F1 and F2 may be replaced with p-channel type transistors.

[0123] Furthermore, the above examples of changes to the structure and polarity of transistors are not limited to transistors F1 and F2. For example, the same applies to transistors F1m, F2m, and other transistors described elsewhere in the specification or illustrated in other drawings.

[0124] Wiring VE is a wiring for conducting current between the first and second terminals of transistor F2 in cells IM[1,1], IM[m,1], IM[1,n], and IM[m,n], and also functions as wiring for conducting current between the first and second terminals of transistor F2 in cells IMref[1] and IMref[m]. For example, wiring VE functions as wiring that supplies a constant voltage. This constant voltage can be, for example, a low-level potential or ground potential.

[0125] In cell IM[1,1], the second terminal of transistor F1 is electrically connected to wiring WCL[1]_s, and the gate of transistor F1 is electrically connected to wiring WSL[1]. The second terminal of transistor F2 is electrically connected to wiring WCL[1]_s, and the second terminal of capacitor C5 is electrically connected to wiring XCL[1]. In Figure 3, the connection point between the first terminal of transistor F1, the gate of transistor F2, and the first terminal of capacitor C5 in cell IM[1,1] is defined as node NN[1,1].

[0126] In cell IM[m,1], the second terminal of transistor F1 is electrically connected to wiring WCL[1]_s, and the gate of transistor F1 is electrically connected to wiring WSL[m]. The second terminal of transistor F2 is electrically connected to wiring WCL[1]_s, and the second terminal of capacitor C5 is electrically connected to wiring XCL[m]. In Figure 3, the connection point between the first terminal of transistor F1, the gate of transistor F2, and the first terminal of capacitor C5 in cell IM[m,1] is defined as node NN[m,1].

[0127] In cell IM[1,n], the second terminal of transistor F1 is electrically connected to wiring WCL[n]_s, and the gate of transistor F1 is electrically connected to wiring WSL[1]. The second terminal of transistor F2 is electrically connected to wiring WCL[n]_s, and the second terminal of capacitor C5 is electrically connected to wiring XCL[1]. In Figure 3, the connection point between the first terminal of transistor F1, the gate of transistor F2, and the first terminal of capacitor C5 in cell IM[1,n] is defined as node NN[1,n].

[0128] In cell IM[m,n], the second terminal of transistor F1 is electrically connected to wiring WCL[n]_s, and the gate of transistor F1 is electrically connected to wiring WSL[m]. The second terminal of transistor F2 is electrically connected to wiring WCL[n]_s, and the second terminal of capacitor C5 is electrically connected to wiring XCL[m]. In Figure 3, the connection point between the first terminal of transistor F1, the gate of transistor F2, and the first terminal of capacitor C5 in cell IM[m,n] is defined as node NN[m,n].

[0129] In cell IMref[1], the second terminal of transistor F1m is electrically connected to wiring XCL[1]_s, and the gate of transistor F1m is electrically connected to wiring WSL[1]. The second terminal of transistor F2m is electrically connected to wiring XCL[1], and the second terminal of capacitor C5 is electrically connected to wiring XCL[1]_s. In Figure 3, the connection point between the first terminal of transistor F1m, the gate of transistor F2m, and the first terminal of capacitor C5 in cell IMref[1] is designated as node NNref[1].

[0130] In cell IMref[m], the second terminal of transistor F1m is electrically connected to wiring XCL[m]_s, and the gate of transistor F1m is electrically connected to wiring WSL[m]. The second terminal of transistor F2m is electrically connected to wiring XCL[m], and the second terminal of capacitor C5 is electrically connected to wiring XCL[m]_s. In Figure 3, the connection point between the first terminal of transistor F1m, the gate of transistor F2m, and the first terminal of capacitor C5 in cell IMref[m] is defined as node NNref[m].

[0131] Furthermore, nodes NN[1,1] through NN[m,n] and nodes NNref[1] through NNref[m] function as holding nodes for their respective cells.

[0132] In cells IM[1,1] through IM[m,n], for example, when transistor F1 is ON, transistor F2 is configured as a diode connection. With the constant voltage supplied by wiring VE as the ground potential (GND), when transistor F1 is ON and a current of amount I flows from wiring WCL to the second terminal of transistor F2, the potential of the gate (node ​​NN) of transistor F2 is determined according to the current amount I. Ideally, the potential of the second terminal of transistor F2 is equal to that of the gate (node ​​NN) of transistor F2 because transistor F1 is ON. By turning transistor F1 OFF, the potential of the gate (node ​​NN) of transistor F2 is maintained. As a result, transistor F2 can supply a current of amount I between its source and drain, corresponding to the ground potential of its first terminal and the potential of its gate (node ​​NN). In this specification, such operation is referred to as "setting (programming) the amount of current flowing between the source and drain of transistor F2 of cell IM to I."

[0133] Next, we will explain specific configuration examples for each of the following: circuit WCS, circuit XCS, circuit WSD, circuit ITS, and cell IMref.

[0134] <<Circuit WCS>> Circuit WCS includes, for example, circuit SWS1 and circuit WCG_s. Circuit WCG_s also includes, for example, circuits WCSa[1] to WCSa[n].

[0135] Circuit SWS1 includes, for example, switches SW3[1] to SW3[n]. The first terminal of switch SW3[1] is electrically connected to wiring WCL[1]_s, the second terminal of switch SW3[1] is electrically connected to circuit WCSa[1], and the control terminal of switch SW3[1] is electrically connected to wiring SWL1. The first terminal of switch SW3[n] is electrically connected to wiring WCL[n]_s, the second terminal of switch SW3[n] is electrically connected to circuit WCSa[n], and the control terminal of switch SW3[n] is electrically connected to wiring SWL1.

[0136] Wiring SWL1 functions, for example, as wiring for switching between the ON and OFF states of switches SW3[1] through SW3[n]. Therefore, either a high-level potential or a low-level potential is supplied to wiring SWL1.

[0137] Each of switches SW3[1] to SW3[n] may be an electrical switch such as an analog switch, or a mechanical switch. Alternatively, one of the electrical switches may be a transistor applicable to transistor F1 or transistor F2. In particular, it is preferable that the transistor be an OS transistor.

[0138] As described above, circuit SWS1 functions as a circuit that makes the connection between circuit WCG_s and each of the wirings WCL[1]_s to WCL[n]_s either conductive or nonconductive. In other words, circuit SWS1 uses switches SW3[1] to SW3[n] as switching elements to switch the connection between circuit WCG_s and each of the wirings WCL[1]_s to WCL[n]_s between conductive and nonconductive states.

[0139] Circuit WCG_s has the function of supplying a signal to wiring WCL[1]_s to wiring WCL[n]_s in an amount corresponding to the first data. In other words, when switches SW3[1] to SW3[n] are ON, circuit WCG_s supplies the first data to be stored in each cell IM of the cell array CA. In the case of the calculation circuit 10A in Figure 3, it is preferable that the signal is current.

[0140] For example, circuit WCG_s can have the configuration shown in Figure 4A. Figure 4A also shows circuit SWS1, switch SW3, wiring SWL1, and wiring WCL to illustrate the electrical connections between circuit WCG_s and its surrounding circuits.

[0141] For example, circuit WCG_s has as many circuits WCSa as there are columns in the subarray SA. In other words, in the case of the arithmetic circuit 10A shown in Figures 2 and 3, circuit WCG_s has n circuits WCSa.

[0142] Furthermore, circuit SWS1 also has as many switches SW3 as there are wires WCL. In other words, circuit SWS1 also has n switches SW3.

[0143] Therefore, the switch SW3 shown in Figure 4A can be any one of the switches SW3[1] to SW3[n] included in the calculation circuit 10A in Figure 3. Similarly, the wiring WCL can be any one of the wiring WCL[1] to WCL[n] included in the calculation circuit 10A in Figure 3.

[0144] Therefore, each of the wirings WCL[1] through WCL[n] is electrically connected to a separate circuit WCSa via a separate switch SW3.

[0145] The circuit WCSa shown in Figure 4A includes a switch SWW as an example. The first terminal of switch SWW is electrically connected to the second terminal of switch SW3, and the second terminal of switch SWW is electrically connected to wiring VINIL1. Wiring VINIL1 functions as a wire that provides an initialization potential to wiring WCL, and the initialization potential can be ground potential (GND), low level potential, or high level potential. Note that switch SWW is ON only when providing an initialization potential to wiring WCL, and OFF at all other times.

[0146] The switch SWW can be an electrical switch, such as an analog switch or a transistor. If a transistor is used as the switch SWW, it can be a transistor with the same structure as transistor F1 or transistor F2. In addition to electrical switches, mechanical switches may also be used.

[0147] Furthermore, the circuit WCSa in Figure 4A has multiple current sources CS as an example. Specifically, the circuit WCSa has K bits (2 K It has the function of outputting the first data of value (K is an integer greater than or equal to 1) as a current quantity, and in this case, circuit WCSa is 2 K -It has one current source CS. For example, circuit WCSa has one current source CS that outputs information corresponding to the value of the 1st bit as current, two current sources CS that output information corresponding to the value of the 2nd bit as current, and two current sources CS that output information corresponding to the Kth bit as current. K-1 They possess it individually.

[0148] In FIG. 4A, each current source CS has a terminal T1 and a terminal T2. The terminal T1 of each current source CS is electrically connected to the second terminal of the switch SW3 of the circuit SWS1. Also, the terminal T2 of one current source CS is electrically connected to the wiring DW[1], and each of the terminals T2 of the two current sources CS is electrically connected to the wiring DW[2], and each of the terminals T2 of the K-1 two current sources CS is electrically connected to the wiring DW[K].

[0149] The plurality of current sources CS included in the circuit WCSa each have a function of outputting the same constant current I Wut from the terminal T1. In practice, in the manufacturing stage of the arithmetic circuit 10A, an error may occur due to variations in the electrical characteristics of the transistors included in each current source CS. Therefore, the error of the constant current I Wut output from each of the terminals T1 of the plurality of current sources CS is preferably within 10%, more preferably within 5%, and even more preferably within 1%. In the present embodiment, it is described that there is no error in the constant current I Wut output from the terminals T1 of the plurality of current sources CS included in the circuit WCSa.

[0150] The wirings DW[1] to DW[K] function as wirings for transmitting a control signal for outputting the constant current I Wut from the electrically connected current source CS. Specifically, for example, when a high-level potential is applied to the wiring DW[1], the current source CS electrically connected to the wiring DW[1] flows I Wut as a constant current to the second terminal of the switch SW3, and when a low-level potential is applied to the wiring DW[1], the current source CS electrically connected to the wiring DW[1] does not output I Wut . Also, for example, when a high-level potential is applied to the wiring DW[2], the two current sources CS electrically connected to the wiring DW[2] output a total of 2I WutWhen a constant current of is applied to the second terminal of switch SW3, and a low-level potential is applied to wiring DW[2], the current source CS electrically connected to wiring DW[2] is 2I in total. Wut It does not output a constant current. Also, for example, when a high-level potential is applied to wiring DW[K], 2 are electrically connected to wiring DW[K]. K-1 The current sources CS total 2 K-1 I Wut When a constant current of is applied to the second terminal of switch SW3, and a low-level potential is applied to wiring DW[K], the current source CS electrically connected to wiring DW[K] is 2 K-1 I Wut It does not output a constant current.

[0151] The current flowing through one current source CS electrically connected to wiring DW[1] corresponds to the value of the first bit, the current flowing through two current sources CS electrically connected to wiring DW[2] corresponds to the value of the second bit, and the amount of current flowing through K current sources CS electrically connected to wiring DW[K] corresponds to the value of the K bit. Now, consider circuit WCSa when K is 2. For example, when the value of the first bit is "1" and the value of the second bit is "0", a high-level potential is applied to wiring DW[1] and a low-level potential is applied to wiring DW[2]. At this time, a constant current I is supplied from circuit WCSa to the second terminal of switch SW3 of circuit SWS1. Wut A current flows. Also, for example, when the value of the first bit is "0" and the value of the second bit is "1", a low-level potential is applied to wiring DW[1] and a high-level potential is applied to wiring DW[2]. At this time, a constant current of 2I is supplied from circuit WCSa to the second terminal of switch SW3 of circuit SWS1. Wut A current flows. Also, for example, when the value of the first bit is "1" and the value of the second bit is "1", a high-level potential is applied to wiring DW[1] and wiring DW[2]. At this time, a constant current of 3I is supplied from circuit WCSa to the second terminal of switch SW3 of circuit SWS1. WutIt flows. Also, for example, when the value of the first bit is "0" and the value of the second bit is "0", a low-level potential is applied to the wiring DW[1] and the wiring DW「2」. At this time, no constant current flows from the circuit WCSa to the second terminal of the switch SW3 of the circuit SWS1.

[0152] In addition, in FIG. 4A, the circuit WCSa in the case where K is an integer of 3 or more is illustrated. When K is 1, the circuit WCSa in FIG. 4A may be configured without providing the current source CS electrically connected to the wirings DW[2] to DW[K]. When K is 2, the circuit WCSa in FIG. 4A may be configured without providing the current source CS electrically connected to the wirings DW[3] to DW[K].

[0153] Next, a specific configuration example of the current source CS will be described.

[0154] The current source CS1 shown in FIG. 5A is a circuit applicable to the current source CS included in the circuit WCSa of FIG. 4A. The current source CS1 has a transistor Tr1 and a transistor Tr2.

[0155] The first terminal of the transistor Tr1 is electrically connected to the wiring VDDL. The second terminal of the transistor Tr1 is electrically connected to the gate of the transistor Tr1, the back gate of the transistor Tr1, and the first terminal of the transistor Tr2. The second terminal of the transistor Tr2 is electrically connected to the terminal T1, and the gate of the transistor Tr2 is electrically connected to the terminal T2. Also, the terminal T2 is electrically connected to the wiring DW.

[0156] The wiring DW is any one of the wirings DW[1] to DW[K] in FIG. 4A.

[0157] The wiring VDDL functions as a wiring for applying a constant voltage. As the constant voltage, for example, a high-level potential can be used.

[0158] When the constant voltage supplied by the wiring VDDL is set to a high-level potential, a high-level potential is input to the first terminal of transistor Tr1. The potential at the second terminal of transistor Tr1 is lower than this high-level potential. In this case, the first terminal of transistor Tr1 functions as the drain, and the second terminal functions as the source. Furthermore, since the gate and the second terminal of transistor Tr1 are electrically connected, the gate-source voltage of transistor Tr1 is 0V. Therefore, if the threshold voltage of transistor Tr1 is within an appropriate range, a current (drain current) within the subthreshold current range flows between the first and second terminals of transistor Tr1. The amount of this current, for example, 1.0 × 10⁻¹⁰, is an OS transistor. -8 It is preferable that it be less than or equal to A, and also 1.0 × 10 -12 It is more preferable that it be less than or equal to A, and also 1.0 × 10 -15 It is more preferable that the current is less than or equal to A. Furthermore, for example, it is more preferable that the current increases exponentially with respect to the gate-source voltage. In other words, transistor Tr1 functions as a current source for supplying a current within the current range when operating in the subthreshold region. Note that this current is as described above I Wut , or I as described later Xut It corresponds to this.

[0159] Transistor Tr2 functions as a switching element. When the potential of the first terminal of transistor Tr2 is higher than the potential of the second terminal of transistor Tr2, the first terminal of transistor Tr2 functions as a drain and the second terminal of transistor Tr2 functions as a source. Also, since the back gate of transistor Tr2 and the second terminal of transistor Tr2 are electrically connected, the back gate-source voltage is 0V. Therefore, when the threshold voltage of transistor Tr2 is within an appropriate range, transistor Tr2 will turn on when a high-level potential is input to its gate, and will turn off when a low-level potential is input to its gate. Specifically, when transistor Tr2 is on, a current within the current range of the subthreshold region described above flows from the second terminal of transistor Tr1 to terminal T1, and when transistor Tr2 is off, no current flows from the second terminal of transistor Tr1 to terminal T1.

[0160] Note that the current source CS included in the circuit WCSa in Figure 4A is not limited to the current source CS1 in Figure 5A. For example, in current source CS1, the back gate of transistor Tr2 and the second terminal of transistor Tr2 are electrically connected, but the back gate of transistor Tr2 may be electrically connected to another wire. An example of such a configuration is shown in Figure 5B. In current source CS2 shown in Figure 5B, the back gate of transistor Tr2 is electrically connected to the wire VTHL. With current source CS2, the wire VTHL is electrically connected to an external circuit, and the external circuit provides a predetermined potential to the wire VTHL, thereby providing the predetermined potential to the back gate of transistor Tr2. This makes it possible to change the threshold voltage of transistor Tr2. In particular, by increasing the threshold voltage of transistor Tr2, the off-current of transistor Tr2 can be reduced.

[0161] Furthermore, for example, current source CS1 is configured such that the back gate of transistor Tr1 is electrically connected to the second terminal of transistor Tr1, but the voltage between the back gate and the second terminal of transistor Tr2 may be maintained by a capacitance. An example of such a configuration is shown in Figure 5C. Current source CS3 shown in Figure 5C has transistor Tr3 and capacitance C6 in addition to transistors Tr1 and Tr2. Current source CS3 differs from current source CS1 in that the second terminal of transistor Tr1 is electrically connected to the back gate of transistor Tr1 via capacitance C6, and the back gate of transistor Tr1 is electrically connected to the first terminal of transistor Tr3. Also, current source CS3 is configured such that the second terminal of transistor Tr3 is electrically connected to wiring VTL, and the gate of transistor Tr3 is electrically connected to wiring VWL. Current source CS3 can create a conductive state between wiring VTL and the back gate of transistor Tr1 by applying a high-level potential to wiring VWL and turning on transistor Tr3. At this time, a predetermined potential can be input from the wiring VTL to the back gate of transistor Tr1. Then, by applying a low-level potential to the wiring VWL and turning off transistor Tr3, the voltage between the second terminal of transistor Tr1 and the back gate of transistor Tr1 can be maintained by capacitor C6. In other words, by determining the voltage that wiring VTL applies to the back gate of transistor Tr1, the threshold voltage of transistor Tr1 can be varied, and the threshold voltage of transistor Tr1 can be fixed by transistor Tr3 and capacitor C6.

[0162] Furthermore, for example, the current source CS4 shown in Figure 5D may be applied to the current source CS included in the circuit WCSa in Figure 4A. In the current source CS4, the back gate of transistor Tr2 is electrically connected to the wiring VTHL instead of the second terminal of transistor Tr2, as in the current source CS3 in Figure 5C. In other words, the current source CS4, like the current source CS2 in Figure 5B, can vary the threshold voltage of transistor Tr2 by the potential supplied by the wiring VTHL.

[0163] In the current source CS4, when a large current flows between the first and second terminals of transistor Tr1, it is necessary to increase the on-current of transistor Tr2 in order to allow this current to flow from terminal T1 to the outside of the current source CS4. In this case, the current source CS4 applies a high-level potential to the wiring VTHL, lowering the threshold voltage of transistor Tr2 and increasing the on-current of transistor Tr2, thereby allowing the large current flowing between the first and second terminals of transistor Tr1 to flow from terminal T1 to the outside of the current source CS4.

[0164] By applying current sources CS1 to CS4 shown in Figures 5A to 5D as the current source CS included in the circuit WCSa in Figure 4A, the circuit WCSa can output a current corresponding to the first K-bit data. Furthermore, the amount of this current can be, for example, the amount of current flowing between the first and second terminals within the range in which transistor F1 operates in the subthreshold region.

[0165] Alternatively, the circuit WCSa shown in Figure 4B may be used instead of the circuit WCSa shown in Figure 4A. The circuit WCSa in Figure 4B has one current source CS shown in Figure 5A connected to each of the wires DW[1] to DW[K]. Furthermore, when the channel width of transistor Tr1[1] is w[1], the channel width of transistor Tr1[2] is w[2], and the channel width of transistor Tr1[K] is w[K], the ratio of their respective channel widths is w[1]:w[2]:w[K]=1:2:2 K-1Therefore, since the current flowing between the source and drain of a transistor operating in the subthreshold region is proportional to the channel width, the circuit WCSa shown in Figure 4B can output a current corresponding to the first K-bit data, similar to the circuit WCSa in Figure 4A.

[0166] Furthermore, transistors Tr1 (including transistors Tr1[1] to Tr1[K]), transistor Tr2 (including transistors Tr2[1] to Tr2[K]), and transistor Tr3 can be, for example, transistors applicable to transistor F1 or transistor F2. In particular, it is preferable to use OS transistors for transistors Tr1 (including transistors Tr1[1] to Tr1[K]), transistor Tr2 (including transistors Tr2[1] to Tr2[K]), and transistor Tr3.

[0167] <<Circuit XCS>> Circuit XCS includes, for example, circuits XCSa[1] to XCSa[m].

[0168] In Figure 3, circuit XCSa[1] is electrically connected to wiring XCL[1], for example, and circuit XCSa[m] is electrically connected to wiring XCL[m], for example.

[0169] Circuit XCSa has the function of supplying a signal to wiring XCL[1]_s to wiring XCL[n]_s in an amount corresponding to the second data. In the case of the calculation circuit 10A in Figure 3, it is preferable that the signal be current.

[0170] Figure 4C is a block diagram showing an example of circuit XCS that can be applied to the arithmetic circuit 10A in Figures 2 and 3. Figure 4C also shows wiring XCL to illustrate the electrical connections between circuit XCS and surrounding circuits.

[0171] The circuit XCS has, for example, as many circuit XCSa and switches SW5 as the number of wirings XCL. That is, the circuit XCS has m circuit XCSa and m switches SW5.

[0172] Therefore, the wiring XCL shown in FIG. 4C can be any one of the wirings XCL[1] to XCL[m] included in the arithmetic circuit 10A of FIG. 3. Accordingly, the first terminals of the respective different switches SW5 are electrically connected to the respective wirings XCL[1] to XCL[m], and the respective second terminals of the m switches SW5 are electrically connected to the respective different circuit XCSa.

[0173] Note that depending on the circuit configuration of the arithmetic circuit, the circuit XCS in FIG. 4C may be configured without the switch SW5.

[0174] The circuit XCSa shown in FIG. 4C has, as an example, a switch SWX. The first terminal of the switch SWX is electrically connected to the wiring XCL, and the second terminal of the switch SWX is electrically connected to the wiring VINIL2. The wiring VINIL2 functions as a wiring for applying an initialization potential to the wiring XCL, and the initialization potential can be a ground potential (GND), a low-level potential, or a high-level potential. Also, the initialization potential applied by the wiring VINIL2 may be equal to the potential applied by the wiring VINIL1. Note that the switch SWX is in an on state only when applying an initialization potential to the wiring XCL, and is in an off state otherwise.

[0175] As the switch SWX, for example, a switch applicable to the switch SWW can be used.

[0176] Also, the circuit configuration of the circuit XCSa in FIG. 4C can be made substantially the same as the circuit configuration of the circuit WCSa in FIG. 4A. Specifically, the circuit XCSa has a function of outputting reference data as a current amount and a function of outputting second data of L bits (2 L values) (L is an integer of 1 or more) as a current amount. In this case, the circuit XCSa is 2 L-It has one current source CS. Circuit XCSa has one current source CS that outputs information corresponding to the value of the 1st bit as current, two current sources CS that output information corresponding to the value of the 2nd bit as current, and two current sources CS that output information corresponding to the Lth bit as current. L-1 They possess it individually.

[0177] By the way, the reference data that circuit XCSa outputs as current can, for example, be information where the value of the first bit is "1" and the values ​​of the second bit and subsequent bits are "0".

[0178] In Figure 4C, terminal T2 of one current source CS is electrically connected to wiring DX[1], and terminal T2 of each of the two current sources CS is electrically connected to wiring DX[2], 2 L-1 Each of the terminals T2 of the current source CS is electrically connected to the wiring DX[L].

[0179] The multiple current sources CS in circuit XCSa each have the same constant current I Xut It has the function of outputting from terminal T1. In addition, wiring DX[1] to wiring DX[L] are electrically connected to current source CS and I Xut It functions as a wire that transmits a control signal to output. In other words, circuit XCSa has the function of supplying a current to wire XCL corresponding to the information of the L bit sent from wires DX[1] to DX[L].

[0180] Specifically, consider the circuit XCSa where L is 2. For example, when the value of the first bit is "1" and the value of the second bit is "0", a high-level potential is applied to wiring DX[1] and a low-level potential is applied to wiring DX[2]. At this time, a constant current I is supplied from circuit XCSa to wiring XCL. Xut A current flows. Also, for example, when the value of the first bit is "0" and the value of the second bit is "1", a low-level potential is applied to wiring DX[1] and a high-level potential is applied to wiring DX[2]. At this time, a constant current of 2I is applied from circuit XCSa to wiring XCL. XutA current flows. Also, for example, when the value of the first bit is "1" and the value of the second bit is "1", a high-level potential is applied to wiring DX[1] and wiring DX[2]. At this time, a constant current of 3I is supplied from circuit XCSa to wiring XCL. Xut A current flows. Also, for example, when the value of the first bit is "0" and the value of the second bit is "0", a low-level potential is applied to wiring DX[1] and wiring DX[2]. At this time, no constant current flows from circuit XCSa to wiring XCL. Note that in this specification, etc., it may be said that a current of zero flows from circuit XCSa to wiring XCL. Also, the current output of circuit XCSa is zero, I Xut , 2I Xut , 3I Xut These can be used as the second data output by circuit XCSa, and in particular, the current quantity I output by circuit XCSa Xut This can be used as the reference data output by circuit XCSa.

[0181] Furthermore, if errors occur in circuit XCSa due to variations in the electrical characteristics of the transistors included in each current source CS, the constant current I output from each of the terminals T1 of the multiple current sources CS will be reduced. Xut The error is preferably within 10%, more preferably within 5%, and most preferably within 1%. In this embodiment, the constant current I output from terminal T1 of the multiple current sources CS included in circuit XCSa Xut We will explain assuming there is no error.

[0182] Furthermore, as the current source CS of circuit XCSa, any of the current sources CS1 to CS4 shown in Figures 5A to 5D can be applied, similar to the current source CS of circuit WCSa. In this case, the wiring DW shown in Figures 5A to 5D should be replaced with wiring DX. This allows circuit XCSa to supply current within the subthreshold current range to wiring XCL as reference data or the second data of the L bit.

[0183] Furthermore, the same circuit configuration as the circuit WCSa shown in Figure 4B can be applied to the circuit XCSa in Figure 4C. In this case, one should replace the circuit WCSa shown in Figure 4B with circuit XCSa, replace wiring DW[1] with wiring DX[1], replace wiring DW[2] with wiring DX[2], replace wiring DW[K] with wiring DX[L], replace switch SWW with switch SWX, and replace wiring VINIL1 with wiring VINIL2.

[0184] <<Circuit WSD>> As described above, the circuit WSD has the function of selecting the row of the cell array CA to which the first data will be written by supplying a predetermined signal to the wiring WSL[1] to the wiring WSL[m] when writing the first data to cells IM[1,1] to IM[m,n]. For example, by supplying a high-level potential to wiring WSL[1] and a low-level potential to wiring WSL[2] (not shown) to wiring WSL[m], the circuit WSD can turn on the gate-containing transistor F1 electrically connected to wiring WSL[1] and turn off the gate-containing transistor F1 electrically connected to each of the wirings WSL[2] to WSL[m], thereby selecting the cell IM electrically connected to wiring WSL[1] as the cell IM to which the data will be written.

[0185] <<Circuit ITS>> In Figure 3, circuit ITS includes, for example, circuit SWS2 and circuit ITG_s. Circuit ITG_s also includes, for example, conversion circuits ITRZ[1] to ITRZ[n].

[0186] Circuit SWS2 includes, for example, switches SW4[1] to SW4[n]. The first terminal of switch SW4[1] is electrically connected to wiring WCL[1]_s, the second terminal of switch SW4[1] is electrically connected to the input terminal of conversion circuit ITRZ[1], and the control terminal of switch SW4[1] is electrically connected to wiring SWL2. The first terminal of switch SW4[n] is electrically connected to wiring WCL[n]_s, the second terminal of switch SW4[n] is electrically connected to the input terminal of conversion circuit ITRZ[n], and the control terminal of switch SW4[n] is electrically connected to wiring SWL2.

[0187] Furthermore, the output terminal of the conversion circuit ITRZ[1] is electrically connected to the wiring OL[1]_s, for example, and the output terminal of the conversion circuit ITRZ[n] is electrically connected to the wiring OL[n]_s.

[0188] Wiring SWL2 functions, for example, as wiring for switching between the ON and OFF states of switches SW4[1] through SW4[n]. Therefore, either a high-level potential or a low-level potential is supplied to wiring SWL2.

[0189] Each of the switches SW4[1] through SW4[n] can be, for example, a switch that can be applied to switches SW3[1] through SW3[n], etc.

[0190] As described above, circuit SWS2 has the function of making the connection between wiring WCL[1]_s to wiring WCL[n]_s and circuit ITG_s conductive or non-conductive. In other words, circuit SWS1 uses switches SW4[1] to SW4[n] as switching elements to switch the connection between circuit ITS and wiring WCL[1]_s to wiring WCL[n]_s between conductive and non-conductive states.

[0191] Each of the conversion circuits ITRZ[1] to ITRZ[n] has the function of converting the amount of current input to the input terminal into a voltage corresponding to the amount of current input to the input terminal and outputting it from the output terminal. The voltage can be, for example, an analog voltage, a digital voltage, etc. Furthermore, each of the conversion circuits ITRZ[1] to ITRZ[n] may have a function-based arithmetic circuit. In this case, for example, the converted voltage may be used by the arithmetic circuit to perform a function calculation and the result of the calculation may be output to the wiring OL[1]_s to OL[n]_s.

[0192] The conversion circuit ITRZ1 shown in Figure 6 is an example of a circuit that can be applied to the conversion circuits ITRZ[1] to ITRZ[n] in Figure 3. Figure 6 also shows the circuit SWS2, wiring WCL, wiring SWL2, switch SW4, and wiring OL to illustrate the electrical connections between the conversion circuit ITRZ1 and its surrounding circuits. Wiring WCL is one of the wirings WCL[1] to WCL[n] included in the calculation circuit 10A in Figure 3, switch SW4 is one of the switches SW4[1] to SW4[n] included in the calculation circuit 10A in Figure 3, and wiring OL is one of the wirings OL[1]_s to OL[n]_s included in the calculation circuit 10A in Figure 3.

[0193] The conversion circuit ITRZ1 in Figure 6 is electrically connected to the wiring WCL via switch SW4. The conversion circuit ITRZ1 is also electrically connected to the wiring OL. The conversion circuit ITRZ1 has the function of converting the amount of current flowing from the conversion circuit ITRZ1 to the wiring WCL, or from the wiring WCL to the conversion circuit ITRZ1, into an analog voltage, and then converting that analog voltage into a digital voltage and then an analog current, and outputting that analog current to the wiring OL.

[0194] The conversion circuit ITRZ1 in Figure 6, as an example, includes a load LE, an operational amplifier OP1, an analog-to-digital conversion circuit ADC, and a circuit ZCSa.

[0195] The inverting input terminal of operational amplifier OP1 is electrically connected to the first terminal of load LE and the second terminal of switch SW4. The non-inverting input terminal of operational amplifier OP1 is electrically connected to wiring VRL. The output terminal of operational amplifier OP1 is electrically connected to the second terminal of load LE and the input terminal of analog-to-digital conversion circuit ADC. The output terminal of analog-to-digital conversion circuit ADC is electrically connected to circuit ZCSa via wiring DZ. Circuit ZCSa is electrically connected to wiring OL.

[0196] Wiring VRL functions as wiring that provides a constant voltage. This constant voltage can be, for example, the ground potential (GND) or the low-level potential.

[0197] Examples of load LEs include resistors, diodes, and transistors.

[0198] In the conversion circuit ITRZ1, the configuration of the operational amplifier OP1 and the load LE allows the current flowing from the wiring WCL to the inverting input terminal of operational amplifier OP1 and the first terminal of the load LE via switch SW4, or the current flowing from the inverting input terminal of operational amplifier OP1 and the first terminal of the load LE to the wiring WCL via switch SW4, to be converted into an analog voltage. This analog voltage is then input to the input terminal of the analog-to-digital conversion circuit ADC.

[0199] In particular, by setting the constant voltage supplied by wiring VRL to ground potential (GND), the inverting input terminal of operational amplifier OP1 becomes a virtual ground, and therefore the analog voltage output to wiring OL can be a voltage referenced to ground potential (GND).

[0200] An analog-to-digital converter (ADC) has the function of outputting a digital voltage corresponding to an analog voltage to a wiring DZ when an analog voltage is input to the input terminal of the ADC.

[0201] Note that the wiring DZ here refers to one or more wires. The number of wiring DZs is determined, for example, by the resolution of the analog-to-digital converter (ADC). For example, if the resolution of the ADC is 1 bit, the number of wiring DZs can be 1, and if the resolution of the ADC is 8 bits, the number of wiring DZs can be 8.

[0202] Circuit ZCSa, for example, has the function of generating an analog current based on the digital voltage input to wiring DZ and outputting it to wiring OL. Specifically, for example, circuit ZCSa can have the same circuit configuration as circuit WCSa in Figure 4A, circuit WCSa in Figure 4B, or circuit XCSa in Figure 4C. When applying circuit XCSa in Figure 4C as circuit ZCSa, one can replace wiring DX[1] to wiring DX[K] shown in Figure 4C with wiring DZ.

[0203] Furthermore, if circuit XCSa in Figure 4C is applied as circuit ZCSa, a new logic circuit may be provided in circuit ZCSa (not shown). In particular, it is preferable that each of the wires DZ is electrically connected to the input terminals of the logic circuit, and that the control terminal of switch SWX is electrically connected to the output terminal of the logic circuit. It is also preferable that the logic circuit is configured to output a signal to the output terminal of the logic circuit that turns switch SWX ON when the digital value input to wire DZ is "0", and to output a signal to the output terminal of the logic circuit that turns switch SWX OFF when the digital value input to wire DZ is anything other than "0". As a result, when the digital value input to wire DZ is "0", circuit ZCSa can output a potential corresponding to "0" (the potential supplied by wire VINIL2) to wire OL.

[0204] Furthermore, the analog-to-digital converter (ADC) can be considered as one of the function-based arithmetic circuits described above. Therefore, if a different function-based arithmetic circuit is to be used in the converter circuit ITRZ1, the analog-to-digital converter (ADC) can be replaced with the circuit that performs the desired function arithmetic. It is preferable that the circuit performing the function arithmetic has an analog voltage input and a digital voltage output.

[0205] Figure 3 shows the circuit configuration of region L1 of the arithmetic circuit 10A, but the circuit configuration of region L2 of the arithmetic circuit 10A in Figure 2 should take into account the individual circuit configurations of the arithmetic circuit 10A described in Figure 3. That is, for example, the circuit WCS in region L2 can have the same configuration as the circuit WCS in region L1, the circuit WSD in region L2 can have the same configuration as the circuit WSD in region L1, and the circuit ITS in region L2 can have the same configuration as the circuit ITS in region L1. In addition, the sub-arrays SAr_1 to Sar_p in region L2 can have the same configuration as the sub-array SAr in region L1.

[0206] Furthermore, the current output from the circuit ITS in region L1 is input to the wirings XCL[1]_1 to XCL[n]_1 and XCL[1]_p to XCL[n]_p, respectively, which extend to the cell array CA in region L2. In other words, in region L2, the calculation result sent from the circuit ITS in region L1 can be used as second data, and a sum-of-products operation can be performed between the first data sent from the circuit WCS in region L2 and the second data. In addition, the circuit ITS in region L2 can perform a function operation using the result of the sum-of-products operation as the input value and output it to the wirings OL[1] to OL[k].

[0207] <Example of operation of the arithmetic circuit 1> Next, we will explain an example of the operation of the arithmetic circuit 10A shown in Figure 3.

[0208] Figure 7 shows a timing chart of an example of the operation of the arithmetic circuit 10A in Figure 3. The timing chart in Figure 7 shows the potential fluctuations of wires SWL1, SWL2, WSL[i] (where i is an integer between 1 and m-1), WSL[i+1], XCL[i], XCL[i+1], node NN[i,j] (where j is an integer between 1 and n-1), node NN[i+1,j], node NNref[i], and node NNref[i+1] between time T11 and time T23, and in the vicinity of these times. Furthermore, the timing chart in Figure 7 also shows the current I flowing between the first and second terminals of transistor F2 contained in cell IM[i,j]. F2 [i,j] and the amount of current I flowing between the first and second terminals of transistor F2m contained in cell IMref[i]. F2m [i] and the current I flowing between the first and second terminals of transistor F2 contained in cell IM[i+1,j] F2 [i+1,j] and the current I flowing between the first and second terminals of transistor F2m contained in cell IMref[i+1]. F2m The variations of [i+1] and each of them are also shown.

[0209] Furthermore, the circuit WCS of the arithmetic circuit 10A shall be the circuit WCS shown in Figure 4A, and the circuit XCS of the arithmetic circuit 10A shall be the circuit XCS shown in Figure 4C. In addition, the circuit XCS may be configured without a switch SW5, that is, the wiring XCL and the circuit XCSa may be directly electrically connected. Alternatively, in this example of operation, the switch SW5 of the circuit XCS may always be in the ON state during operation.

[0210] In this example, the potential of wiring VE is set to ground potential GND. Also, before time T11, the initial settings assume that the potentials of nodes NN[i,j], NN[i+1,j], NNref[i], and NNref[i+1] are set to ground potential GND. Specifically, for example, by setting the initialization potential of wiring VINIL1 in Figure 4A to ground potential GND, and turning on switches SWW, SW3, and transistors F1 contained in cells IM[i,j] and IM[i+1,j], the potentials of nodes NN[i,j] and NN[i+1,j] can be set to ground potential GND. Furthermore, for example, by setting the initialization potential of wiring VINIL2 in Figure 4C to the ground potential GND, and turning on the switch SWX and the respective transistors F1m contained in cells IMref[i,j] and IMref[i+1,j], the potentials of nodes NNref[i,j] and NNref[i+1,j] can be set to the ground potential GND.

[0211] <<From time T11 to time T12>> Between time T11 and time T12, a high-level potential (labeled "High" in Figure 7) is applied to wiring SWL1, and a low-level potential (labeled "Low" in Figure 7) is applied to wiring SWL2. As a result, a high-level potential is applied to the control terminals of switches SW3[1] through SW3[n], causing each of switches SW3[1] through SW3[n] to be in the ON state, and a low-level potential is applied to the gates of switches SW4[1] through SW4[n], causing each of switches SW4[1] through SW4[n] to be in the OFF state.

[0212] Furthermore, between time T11 and time T12, a low-level potential is applied to wiring WSL[i] and wiring WSL[i+1]. As a result, a low-level potential is applied to the gates of transistors F1 contained in cells IM[i,1] through IM[i,n] in the i-th row of cell array CA, and to the gate of transistor F1m contained in cell IMref[i], causing transistors F1 and F1m to turn off. Additionally, a low-level potential is applied to the gates of transistors F1 contained in cells IM[i+1,1] through IM[i+1,n] in the i+1-th row of cell array CA, and to the gate of transistor F1m contained in cell IMref[i+1], causing transistors F1 and F1m to turn off.

[0213] Furthermore, between time T11 and time T12, the ground potential GND is applied to wiring XCL[i] and wiring XCL[i+1]. Specifically, for example, if the wiring XCL shown in Figure 4C is wiring XCL[i] and wiring XCL[i+1] respectively, the potential of wiring XCL[i] and wiring XCL[i+1] can be set to the ground potential GND by setting the initialization potential of wiring VINIL2 to the ground potential GND and turning on switch SWX.

[0214] Furthermore, between time T11 and time T12, in each of the circuits WCSa in Figure 4A, which are electrically connected to wiring WCL[1]_s to wiring WCL[n]_s via separate switches SW3, no first data is input to wiring DW[1] to wiring DW[K]. In this case, it is assumed that a low level potential is input to each of the wirings DW[1] to wiring DW[K] in the circuit WCSa in Figure 4A. Also, between time T11 and time T12, in each of the circuits XCSa in Figure 4C, which are electrically connected to wiring XCL[1] to wiring XCL[m], no second data is input to wiring DX[1] to wiring DX[L]. In this case, it is assumed that a low level potential is input to each of the wirings DX[1] to wiring DX[L] in the circuit XCSa in Figure 4C.

[0215] Furthermore, between time T11 and time T12, no current flows through wiring WCL[j]_s, wiring XCL[i], and wiring XCL[i+1]. Therefore, I F2 [i,j], I F2m [i], I F2 [i+1,j], I F2m [i+1] is 0.

[0216] <<From time T12 to time T13>> Between time T12 and time T13, a high-level potential is applied to wiring WSL[i]. This applies a high-level potential to the gates of transistors F1 in cells IM[i,1] through IM[i,n] of row i of cell array CA, and to the gate of transistor F1m in cell IMref[i], causing transistors F1 and F1m to turn ON. Also, between time T12 and time T13, a low-level potential is applied to wirings WSL[1] through WSL[m] other than wiring WSL[i], and transistors F1 in cells IM[1,1] through IM[m,n] other than row i of cell array CA, and transistors F1m in cells IMref[1] through IMref[m] other than row i are assumed to be in the OFF state.

[0217] Furthermore, the ground potential GND has been continuously applied to wiring XCL[1] through wiring XCL[m] since before time T12.

[0218] <<From time T13 to time T14>> Between time T13 and time T14, a current of amount I0[i,j] flows from circuit WCSa[j] to wiring WCL[j]_s via switch SW3[j] as the first data. Specifically, when wiring WCL shown in Figure 4A is wiring WCL[j]_s, a signal corresponding to the first data is input to each of wiring DW[1] to DW[K], causing a current of I0[i,j] to flow from circuit WCSa to the second terminal of switch SW3[j]. In other words, the value of the K-bit signal input as the first data is α[i,j] (α[i,j] is between 0 and 2). K When I0[i,j] = α[i,j] × I (i,j) is an integer less than or equal to -1, then I0[i,j] = α[i,j] × I Wut This is the result.

[0219] Note that when α[i,j] is 0, I0[i,j]=0, so strictly speaking, no current flows from circuit WCSa to cell array CA via switch SW3[j]. However, in this specification and other documents, it may be stated that "a current of I0[i,j]=0 flows."

[0220] Between time T13 and time T14, the first terminal of transistor F1 in cell IM[i,j] in row i of cell array CA and the wiring WCL[j]_s are conductive, and the first terminals of transistor F1 in cells IM[1,j] through IM[m,j] other than row i of cell array CA and the wiring WCL[j]_s are not conductive. Therefore, a current of I0[i,j] flows from wiring WCL[j] to cell IM[i,j].

[0221] By the way, when transistor F1 in cell IM[i,j] is turned ON, transistor F2 in cell IM[i,j] becomes a diode connection. Therefore, when current flows from wiring WCL[j]_s to cell IM[i,j], the potentials of the gate of transistor F2 and the second terminal of transistor F2 become approximately equal. This potential is determined by the amount of current flowing from wiring WCL[j] to cell IM[i,j] and the potential of the first terminal of transistor F2 (here, GND), etc. In this example of operation, when a current of amount I0[i,j] flows from wiring WCL[j] to cell IM[i,j], the potential of the gate of transistor F2 (node ​​NN[i,j]) becomes V g Let [i,j] be the case. That is, in transistor F2, the gate-source voltage is V g [i,j]-GND is established, and the current I0[i,j] is set as the current flowing between the first and second terminals of transistor F2.

[0222] Here, the threshold voltage of transistor F2 is V th When [i,j] is denoted as such, the current I0[i,j] when transistor F2 operates in the subthreshold region can be described by the following equation.

[0223]

number

[0224] Note I a is V g [i,j] is V th The drain current when [i,j], where J is a correction factor determined by temperature, device structure, etc.

[0225] Furthermore, between time T13 and time T14, current I is transmitted from circuit XCS to wiring XCL[i] as reference data. ref0A current of I flows. Specifically, when the wiring XCL shown in Figure 4(C) is wiring XCL[i], a high-level potential is input to wiring DX[1] and a low-level potential is input to each of the wirings DX[2] through DX[K], and a current I flows from circuit XCSa to wiring XCL[i]. ref0 It flows. In other words, I ref0 =I Xut This is the result.

[0226] Between time T13 and time T14, the first terminal of transistor F1m contained in cell IMref[i] and the wiring XCL[i] are in a conductive state, so a current I is supplied from wiring XCL[i] to cell IMref[i]. ref0 An electric current flows.

[0227] Similar to cell IM[i,j], when transistor F1m in cell IMref[i] is turned on, transistor F2m in cell IMref[i] becomes a diode-connected unit. Therefore, when current flows from wiring XCL[i] to cell IMref[i], the potentials of the gate of transistor F2m and the second terminal of transistor F2m become approximately equal. This potential is determined by the amount of current flowing from wiring XCL[i] to cell IMref[i] and the potential of the first terminal of transistor F2m (GND in this case). In this example of operation, the amount of current I flows from wiring XCL[i] to cell IMref[i]. ref0 As the current flows, the potential at the gate (node ​​NNref[i]) of transistor F2 is V gm [i] is assumed to be the case, and the potential of the wiring XCL[i] at this time is also V gm Let [i]. That is, in transistor F2m, the gate-source voltage is V gm [i]-GND, and the current flowing between the first and second terminals of transistor F2m is the current quantity I. ref0 This will be set.

[0228] Here, the threshold voltage of transistor F2m is V thm[i] When transistor F2m operates in the subthreshold region, the current I ref0 This can be written as follows:

[0229]

number

[0230] The correction coefficient J is assumed to be the same as that of transistor F2 included in cell IM[i,j]. For example, the device structure and size (channel length, channel width) of the transistors are assumed to be the same. Although the correction coefficient J of each transistor will vary due to manufacturing variations, it is assumed that the variations are suppressed to a degree that allows the discussion described later to hold true with sufficient accuracy for practical purposes.

[0231] Here, the first data point, the weight coefficient w[i,j], is defined as follows.

[0232]

number

[0233] Therefore, equations (1.2), (1.3), and I0[i,j]=α[i,j]×I Wut , and I ref0 =I Xut Using this, equation (1.1) can be rewritten as follows:

[0234]

number

[0235] Note that the current I output by the current source CS of the circuit WCSa in Figure 4A Wut And the current I output by the current source CS of the circuit XCSa in Figure 4C Xut If and are equal, then w[i,j]=α[i,j]. That is, I Wut And, I Xut If and are equal, then α[i,j] corresponds to the value of the first data, so I Wut And, IXut It is preferable that and are equal to each other.

[0236] <<From time T14 to time T15>> Between time T14 and time T15, a low-level potential is applied to wiring WSL[i]. This applies a low-level potential to the gates of transistors F1 in cells IM[i,1] through IM[i,n] of row i of cell array CA, and to the gate of transistor F1m in cell IMref[i], causing transistors F1 and F1m to turn off.

[0237] When transistor F1 in cell IM[i,j] turns off, capacitance C5 receives the difference between the potential of the gate of transistor F2 (node ​​NN[i,j]) and the potential of wiring XCL[i], which is V. g [i,j]-V gm [i] is maintained. Also, when transistor F1 contained in cell IMref[i] turns off, capacitance C5m maintains 0, which is the difference between the potential of the gate of transistor F2m (node ​​NNref[i]) and the potential of wiring XCL[i]. Note that the voltage held by capacitance C5m is a non-zero voltage (here, for example, V) depending on the transistor characteristics of one or both of transistors F1m and F2m during the operation from time T13 to time T14. ds In some cases, this may be the case. In this case, the potential of node NNref[i] is V ds It can be considered as the potential with added voltage.

[0238] <<From time T15 to time T16>> Between time T15 and time T16, GND is applied to wiring XCL[i]. Specifically, for example, if wiring XCL shown in Figure 4C is wiring XCL[i], the potential of wiring XCL[i] can be set to the ground potential GND by setting the initialization potential of wiring VINIL2 to the ground potential GND and turning on switch SWX.

[0239] Therefore, the potential of nodes NN[i,1] through NN[i,n] changes due to capacitive coupling by the capacitance C5 contained in each of the cells IM[i,1] through IM[i,n] in row i, and the potential of node NNref[i] changes due to capacitive coupling by the capacitance C5m contained in cell IMref[i].

[0240] The change in potential at nodes NN[i,1] through NN[i,n] is the potential obtained by multiplying the change in potential at wiring XCL[i] by a capacitive coupling coefficient determined by the configuration of each cell IM[i,1] through IM[i,n] contained in cell array CA. This capacitive coupling coefficient is calculated, for example, by the capacitance of capacitor C5, the gate capacitance of transistor F2, and the parasitic capacitance. In each of cells IM[i,1] through IM[i,n], when the capacitive coupling coefficient due to capacitor C5 is P, the potential at node NN[i,j] of cell IM[i,j] is calculated from the potential at the time between time T14 and time T15 by P(V gm [i]-GND) decreases

[0241] Similarly, a change in the potential of wiring XCL[i] causes a change in the potential of node NNref[i] due to capacitive coupling by capacitance C5m contained in cell IMref[i]. When the capacitive coupling coefficient by capacitance C5m is set to p, the same as for capacitance C5, the potential of node NNref[i] of cell IMref[i] is calculated from the potential between time T14 and time T15 as P(V). gm [i]-GND) decreases

[0242] Note that in the timing chart in Figure 7, P=1 is used as an example. Therefore, the potential of node NNref[i] between time T15 and time T16 is GND.

[0243] As a result, the potential of node NN[i,j] of cell IM[i,j] decreases, causing transistor F2 to turn off. Similarly, the potential of node NNref[i] of cell IMref[i] decreases, causing transistor F2m to turn off. Therefore, between time T15 and time T16, I F2 [i,j], I F2m Each of [i] is 0.

[0244] <<From time T16 to time T17>> Between time T16 and time T17, a high-level potential is applied to wiring WSL[i+1]_s. This applies a high-level potential to the gates of transistors F1 in cells IM[i+1,1] through IM[i+1,n] in the i+1th row of cell array CA, and to the gates of transistors F1m in cell IMref[i+1], causing transistors F1 and F1m to turn ON. Also, between time T16 and time T17, a low-level potential is applied to wirings WSL[1]_s through WSL[m]_s other than wiring WSL[i+1]_s, and transistors F1 in cells IM[1,1] through IM[m,n] other than the i+1th row of cell array CA, and transistors F1m in cells IMref[1] through IMref[m] other than the i+1th row are assumed to be OFF.

[0245] Furthermore, the ground potential GND has been continuously applied to wiring XCL[1] through wiring XCL[m] since before time T16.

[0246] <<From time T17 to time T18>> Between time T17 and time T18, a current of amount I0[i+1,j] flows from circuit WCS to cell array CA via switch SW3[j] as the first data. Specifically, when the wiring WCL shown in Figure 4A is wiring WCL[j]_s, a signal corresponding to the first data is input to each of the wirings DW[1] to DW[K], causing a current of amount I0[i+1,j] to flow from circuit WCSa to the second terminal of switch SW3[j]. In other words, the value of the K-bit signal input as the first data is α[i+1,j] (α[i+1,j] is between 0 and 2). K Let I0[i+1,j] = α[i+1,j] × I Wut This is the result.

[0247] Note that when α[i+1,j] is 0, I0[i+1,j]=0, so strictly speaking, no current flows from circuit WCSa to cell array CA via switch SW3[j]. However, in this specification and other documents, it is sometimes written as "a current of I0[i+1,j]=0 flows," similar to the case where I0[i,j]=0.

[0248] At this time, there is a conductive state between the first terminal of transistor F1 in cell IM[i+1,j] in the i+1 row of cell array CA and the wiring WCL[j]_s, and there is a non-conductive state between the first terminal of transistor F1 in cells IM[1,j] through IM[m,j] other than the i+1 row of cell array CA and the wiring WCL[j]_s. Therefore, a current of I0[i+1,j] flows from the wiring WCL[j]_s to cell IM[i+1,j].

[0249] Incidentally, when the transistor F1 included in the cell IM[i+1,j] is turned on, the transistor F2 included in the cell IM[i+1,j] has a diode-connected configuration. Therefore, when current flows from the wiring WCL[j]_s to the cell IM[i+1,j], the potentials of the gate of the transistor F2 and the second terminal of the transistor F2 become substantially equal. The said potential is determined by the amount of current flowing from the wiring WCL[j]_s to the cell IM[i+1,j], the potential of the first terminal of the transistor F2 (here GND), etc. In this operation example, when a current of current amount I0[i+1,j] flows from the wiring WCL[j] to the cell IM[i+1,j], the potential of the gate (node NN[i+1,j]) of the transistor F2 becomes V g [i+1,j]. That is, in the transistor F2, the gate-source voltage becomes V g [i+1,j] - GND, and the current amount I0[i+1,j] is set as the current flowing between the first terminal and the second terminal of the transistor F2.

[0250] Here, when the threshold voltage of the transistor F2 is V th [i+1,j], the current amount I0[i+1,j] when the transistor F2 operates in the subthreshold region can be described as follows.

[0251]

Equation

[0252] Note that the correction coefficient is the same J as that of the transistor F2 included in the cell IM[i,j] and the transistor F2m included in the cell IMref[i].

[0253] Also, between time T17 and time T18, from the circuit XCS, a current amount I as reference data is sent to the wiring XCL[i+1] ref0A current flows. Specifically, in the same manner as from time T13 to time T14, when the wiring XCL shown in FIG. 4C is the wiring XCL[i + 1], a high-level potential is input to the wiring DX[1], and low-level potentials are input to each of the wirings DX[2] to DX[K], and a current I ref0 =I Xut flows from the circuit XCSa to the wiring XCL[i + 1].

[0254] Between time T17 and time T18, since the connection between the first terminal of the transistor F1m included in the cell IMref[i + 1] and the wiring XCL[i + 1] becomes conductive, a current of amount I ref0 flows from the wiring XCL[i + 1] to the cell IMref[i + 1].

[0255] Similar to the cell IM[i + 1, j], when the transistor F1m included in the cell IMref[i + 1] is turned on, the transistor F2m included in the cell IMref[i + 1, j] is configured in a diode connection. Therefore, when a current flows from the wiring XCL[i + 1] to the cell IMref[i + 1], the potentials of the gate of the transistor F2m and the second terminal of the transistor F2m become substantially equal. The said potential is determined by the amount of current flowing from the wiring XCL[i + 1] to the cell IMref[i + 1] and the potential of the first terminal of the transistor F2m (here GND), etc. In this operation example, when a current of amount I ref0 flows from the wiring XCL[i + 1] to the cell IMref[i + 1], the gate (node NNref[i + 1]) of the transistor F2m becomes V gm [i + 1], and also the potential of the wiring XCL[i + 1] at this time is also V gm [i + 1]. That is, in the transistor F2m, the gate-source voltage becomes V gm [i + 1] - GND, and as the current flowing between the first terminal and the second terminal of the transistor F2m, a current of amount I ref0 is set.

[0256] Here, the threshold voltage of the transistor F2m is V thmWhen [i+1,j] is defined as the current I when transistor F2m operates in the subthreshold region, ref0 This can be written as follows:

[0257]

number

[0258] The correction coefficient J is assumed to be the same as that of transistor F2 included in cell IM[i+1,j].

[0259] Here, we define the first data point, the weight coefficient w[i+1,j], as follows.

[0260]

number

[0261] Therefore, equations (1.6), (1.7), and I0[i+1,j]=α[i+1,j]×I Wut , and I ref0 =I Xut Using this, equation (1.5) can be rewritten as follows:

[0262]

number

[0263] Note that the current I output by the current source CS of the circuit WCSa in Figure 4A Wut And the current I output by the current source CS of the circuit XCSa in Figure 4C Xut If and are equal, then w[i+1,j]=α[i+1,j]. That is, I Wut And, I Xut If and are equal, then α[i+1,j] corresponds to the value of the first data, so I Wut And, I Xut It is preferable that and are equal to each other.

[0264] <<From time T18 to time T19>> Between time T18 and time T19, a low-level potential is applied to wiring WSL[i+1]. This applies a low-level potential to the gates of transistors F1 in cells IM[i+1,1] through IM[i+1,n] in the i+1 row of cell array CA, and to the gate of transistor F1m in cell IMref[i+1], causing transistors F1 and F1m to turn off.

[0265] When transistor F1 in cell IM[i+1,j] turns off, capacitor C5 receives the difference between the potential of the gate of transistor F2 (node ​​NN[i+1,j]) and the potential of wiring XCL[i+1], which is V. g [i+1,j]-V gm [i+1] is maintained. Also, when transistor F1 contained in cell IMref[i+1] turns off, capacitance C5m maintains 0, which is the difference between the potential of the gate of transistor F2m (node ​​NNref[i+1]) and the potential of wiring XCL[i+1]. Note that the voltage held by capacitance C5m is a non-zero voltage (here, for example, V) depending on the transistor characteristics of one or both of transistors F1m and F2m during operation from time T18 to time T19. ds In some cases, this may be the case. In this case, the potential of node NNref[i+1] is V ds It can be considered as the potential with added voltage.

[0266] <<From time T19 to time T20>> Between time T19 and time T20, the ground potential GND is applied to wiring XCL[i+1]. Specifically, for example, if wiring XCL shown in Figure 4A is wiring XCL[i+1], the potential of wiring XCL[i+1] can be set to the ground potential GND by setting the initialization potential of wiring VINIL2 to the ground potential GND and turning on switch SWX.

[0267] Therefore, the potential of nodes NN[i,1] to NN[i+1,n] changes due to capacitive coupling by the capacitance C5 contained in each of the cells IM[i+1,1] to IM[i+1,n] in the i+1 row, and the potential of node NNref[i+1] changes due to capacitive coupling by the capacitance C5m contained in cell IMref[i+1].

[0268] The change in potential of nodes NN[i+1,1] to NN[i+1,n] is the potential obtained by multiplying the change in potential of wiring XCL[i+1] by the capacitive coupling coefficient determined by the configuration of each cell IM[i+1,1] to IM[i+1,n] contained in cell array CA. This capacitive coupling coefficient is calculated using the capacitance of capacitor C5, the gate capacitance of transistor F2, parasitic capacitance, etc. In each of cells IM[i+1,1] to IM[i+1,n], if the capacitive coupling coefficient due to capacitor C5 is P, which is the same as the capacitive coupling coefficient due to capacitor C5 in each of cells IM[i,1] to IM[i,n], then the potential of node NN[i+1,j] of cell IM[i+1,j] is calculated by taking the potential at the time between time T18 and time T19 and calculating P(V gm [i+1]-GND) decreases.

[0269] Similarly, a change in the potential of wiring XCL[i+1] causes a change in the potential of node NNref[i+1] due to capacitive coupling by capacitance C5m contained in cell IMref[i+1]. When the capacitive coupling coefficient for capacitance C5m is denoted as P, the same as for capacitance C5, the potential of node NNref[i+1] of cell IMref[i+1] is calculated as P(V) from the potential at the time between time T18 and time T19. gm [i+1]-GND) decreases.

[0270] Note that in the timing chart in Figure 7, P=1 is used as an example. Therefore, the potential of node NNref[i+1] between time T20 and time T21 is GND.

[0271] As a result, the potential at node NN[i+1,j] of cell IM[i+1,j] decreases, causing transistor F2 to turn off. Similarly, the potential at node NNref[i+1] of cell IMref[i+1] decreases, causing transistor F2m to turn off. Therefore, between time T19 and time T20, I F2 [i+1,j], I F2m Each of [i+1] is 0.

[0272] <<From time T20 to time T21>> Between time T20 and time T21, a low-level potential is applied to wiring SWL1. As a result, a low-level potential is applied to the control terminals of switches SW3[1] through SW3[n], causing each of switches SW3[1] through SW3[n] to turn off.

[0273] <<From time T21 to time T22>> Between time T21 and time T22, a high-level potential is applied to the wiring SWL2. As a result, a high-level potential is applied to the control terminals of switches SW4[1] through SW4[n], causing each of switches SW4[1] through SW4[n] to turn on.

[0274] <<From time T22 to time T23>> Between time T22 and time T23, the current quantity I is transferred from circuit XCS to wiring XCL[i] as the second data. ref0 x[i]I is x[i] times the original. ref0 A current flows. Specifically, for example, when the wiring XCL shown in Figure 4C is wiring XCL[i], a high-level potential or a low-level potential is input to each of the wirings DX[1] to DX[K] according to the value of x[i], and the current x[i]I flows from circuit XCSa to wiring XCL[i]. ref0 =x[i]I Xut The current flows. In this example, x[i] corresponds to the value of the second data. At this time, the potential of wiring XCL[i] is from 0 to V gmLet it change to [i] + ΔV[i].

[0275] A change in the potential of wiring XCL[i] causes a change in the potential of nodes NN[i,1] through NN[i,n] due to capacitive coupling by the capacitance C5 contained in each of the cells IM[i,1] through IM[i,n] in row i of cell array CA. Therefore, the potential of node NN[i,j] of cell IM[i,j] is V g [i,j]+PΔV[i]

[0276] Similarly, a change in the potential of wiring XCL[i] causes a change in the potential of node NNref[i] due to capacitive coupling by capacitance C5m contained in cell IMref[i]. Therefore, the potential of node NNref[i] of cell IMref[i] is V gm [i] + PΔV[i]

[0277] As a result, the current I1[i,j] flowing between the first and second terminals of transistor F2 and the current I ref1 [i,j] can be written as follows:

[0278]

number

[0279]

number

[0280] Note that x[i] is defined as follows:

[0281]

number

[0282] Therefore, equation (1.9) can be rewritten using equations (1.4) and (1.11) as follows:

[0283]

number

[0284] In other words, the amount of current flowing between the first and second terminals of transistor F2 contained in cell IM[i,j] is proportional to the product of the first data w[i,j] and the second data x[i].

[0285] Furthermore, between time T22 and time T23, the current quantity I is transferred from circuit XCS to wiring XCL[i+1] as the second data. ref0 x[i+1]I is x[i+1] times the original. ref0 A current of x[i+1]I flows. Specifically, for example, when the wiring XCL shown in Figure 4C is wiring XCL[i+1], a high-level potential or a low-level potential is input to each of the wirings DX[1] to DX[K] according to the value of x[i+1], and the current x[i+1]I flows from circuit XCSa to wiring XCL[i+1]. ref0 =x[i+1]I Xut The current flows. In this example, x[i+1] corresponds to the value of the second data. At this time, the potential of wiring XCL[i+1] is from 0 to V gm Let it change to [i+1] + ΔV[i+1].

[0286] A change in the potential of wiring XCL[i+1] causes a change in the potential of nodes NN[i+1,1] through NN[i+1,n] due to capacitive coupling by the capacitance C5 contained in each of the cells IM[i+1,1] through IM[i+1,n] in the i+1 row of cell array CA. Therefore, the potential of node NN[i+1,j] of cell IM[i+1,j] is V g The result is [i+1,j]+PΔV[i+1].

[0287] Similarly, a change in the potential of wiring XCL[i+1] causes a change in the potential of node NNref[i+1] due to capacitive coupling by capacitance C5m contained in cell IMref[i+1]. Therefore, the potential of node NNref[i+1] of cell IMref[i+1] is V gm The result is [i+1] + PΔV[i+1].

[0288] As a result, the current flowing between the first and second terminals of transistor F2, I1[i+1,j], and the current flowing between the first and second terminals of transistor F2m, I, are determined between time T22 and time T23. ref1 [i+1,j] can be written as follows:

[0289]

number

[0290]

number

[0291] Note that x[i+1] is defined as follows:

[0292]

number

[0293] Therefore, equation (1.13) can be rewritten using equations (1.8) and (1.15) as follows:

[0294]

number

[0295] In other words, the amount of current flowing between the first and second terminals of transistor F2 contained in cell IM[i+1,j] is proportional to the product of the first data, w[i+1,j], and the second data, x[i+1].

[0296] Here, we consider the sum of the currents flowing from the conversion circuit ITRZ[j] through the switch SW4[j] and the wiring WCL[j]_s to cells IM[i,j] and IM[i+1,j]. The sum of these currents is I S If we set it to [j], then I S [j] can be expressed by the following equation, from equations (1.12) and (1.16).

[0297]

number

[0298] Therefore, the amount of current output from the conversion circuit ITRZ[j] is proportional to the sum of the products of the first data, which are the weight coefficients w[i,j] and w[i+1,j], and the second data, which are the neuron signal values ​​x[i] and x[i+1].

[0299] In the above example, we dealt with the sum of the currents flowing through cell IM[i,j] and cell IM[i+1,j], but we may also deal with the sum of the currents flowing through each of the cells IM[1,j] through IM[m,j]. In this case, equation (1.17) can be rewritten as the following equation.

[0300]

number

[0301] Therefore, even in the case of an arithmetic circuit 10A having a cell array CA with three or more rows and multiple columns, the sum-of-accumulate operation can be performed as described above. In this case, the arithmetic circuit 10A uses one of the multiple columns as the current quantity I ref0 , and xI ref0 By using cells that hold this information, it becomes possible to simultaneously perform multiply-accumulate operations for the number of remaining columns among multiple columns. In other words, by increasing the number of columns in the memory cell array, it is possible to provide a semiconductor device that achieves high-speed multiply-accumulate operations.

[0302] <Configuration Example 3> Furthermore, the configurations of cell IM and cell IMref applicable to the arithmetic circuit 10A in Figure 2, as described in Configuration Example 2, are not limited to the cell IM and cell IMr shown in the arithmetic circuit 10A in Figure 3. The configuration of the semiconductor device in one aspect of the present invention may be modified depending on the circumstances, as long as it is within the scope of solving the problem.

[0303] For example, the cell IM and cell IMref of the arithmetic circuit 10A in Figure 2 may be configured with the cell IM and cell IMref shown in Figure 8. Figure 8 shows, as an example, subarray SAr and subarray SA_s included in the cell array CA of region L1. Also, similar to the arithmetic circuit 10A in Figure 3, subarray SAr has cells IMref[1] to IMref[m], and subarray SA_s has cells IM[1,1] to IM[m,n].

[0304] Each of the cells IM[1,1] to IM[m,n] in Figure 8 has a transistor F5 in addition to the circuit elements included in cells IM[1,1] to IM[m,n] in Figure 3. Furthermore, each of the cells IMref[1] to IMref[m] in Figure 8 has a transistor F5m in addition to the circuit elements included in cells IMref[1] to IMref[m] in Figure 3.

[0305] Furthermore, transistors F5 and F5m can each be replaced with transistors applicable to, for example, transistors F1, F2, F1m, or F2m. Therefore, the configurations of transistors F5 and F5m should be considered in reference to the descriptions of transistors F1, F2, F1m, and F2m mentioned above.

[0306] In each of cells IM[1,1] through IM[m,n] in Figure 8, the first terminal of transistor F1 is electrically connected to the gate of transistor F2. The first terminal of transistor F2 is electrically connected to wiring VE. The first terminal of capacitor C5 is electrically connected to the gate of transistor F2. Furthermore, the second terminal of transistor F2 is electrically connected to the first terminal of transistor F5. Furthermore, the second terminal of transistor F5 is electrically connected to the second terminal of transistor F1.

[0307] Furthermore, in each of cells IMref[1] to IMref[m] in Figure 8, the first terminal of transistor F1m is electrically connected to the gate of transistor F2m. The first terminal of transistor F2m is electrically connected to wiring VE. The first terminal of capacitor C5 is electrically connected to the gate of transistor F2m. Also, the second terminal of transistor F2m is electrically connected to the first terminal of transistor F5m. Also, the second terminal of transistor F5m is electrically connected to the second terminal of transistor F1m.

[0308] Furthermore, in cell IMref[1] and cells IM[1,1] through IM[1,n] located in the first row of cell array CA, the gates of transistor F5 and transistor F5m are electrically connected to wiring CLL[1]. Also, in cell IMref[m] and cells IM[m,1] through IM[m,n] located in the m row of cell array CA, the gates of transistor F5 and transistor F5m are electrically connected to wiring CLL[m].

[0309] Each of the wirings CCL[1] to CCL[m] functions, for example, as wiring that provides a constant potential. This constant potential can be, for example, a potential higher than 0V, a potential higher than the ground potential, and so on.

[0310] Incidentally, in the configuration of cell IM shown in Figure 3, transistor F2 is directly electrically connected to wiring WCL, so the potential of the second terminal of transistor F2 may change as the amount of current flowing through wiring WCL changes. Also, in the configuration of cell IMref shown in Figure 3, transistor F2m is directly electrically connected to wiring XCL, so the potential of the second terminal of transistor F2m may change as the amount of current flowing through wiring XCL changes. For this reason, the source-drain voltage of transistor F2 or transistor F2m may change, and the amount of current flowing through transistor F2 or transistor F2m may change.

[0311] Therefore, as shown in Figure 8, by providing transistor F5 in cell IM, the second terminal of transistor F2 becomes less susceptible to the direct influence of changes in the potential of wiring WCL. This prevents abrupt changes in the potential of the second terminal of transistor F2 due to changes in the potential of wiring WCL. Similarly, by providing transistor F5m in cell IM, the second terminal of transistor F2m becomes less susceptible to the direct influence of changes in the potential of wiring XCL. This prevents abrupt changes in the potential of the second terminal of transistor F2m due to changes in the potential of wiring XCL.

[0312] In other words, transistor F5 has the function of fixing the potential of the second terminal of transistor F2, or preventing abrupt changes in the potential of the second terminal of transistor F2. Similarly, transistor F5m has the function of fixing the potential of the second terminal of transistor F2m, or preventing abrupt changes in the potential of the second terminal of transistor F2m.

[0313] Therefore, by applying the cell IM and cell IMref shown in Figure 8 to the arithmetic circuit 10A in Figure 2, the operation of the arithmetic circuit 10A can be stabilized.

[0314] Although Figure 8 illustrates an example configuration of the cell array CA in region L1, the configuration of cell IM and cell IMref in Figure 8 may also be applied to cell IM and cell IMref included in the cell array CA of region L2.

[0315] <Configuration Example 4> Furthermore, the configuration of the arithmetic circuit 10A shown in Figure 2, as described in Configuration Example 2, may be modified depending on the circumstances.

[0316] For example, the configuration of the arithmetic circuit 10A shown in Figure 2 may be modified as shown in the configuration of the arithmetic circuit 10AA in Figure 9. The arithmetic circuit 10AA is configured in which the circuit ITS is not provided in the arithmetic circuit 10A. In other words, the arithmetic circuit 10AA in Figure 9 is configured such that each of the wirings WCL[1]_1 to WCL[n]_1 is directly electrically connected one-to-one to wirings OL[1]_1 to OL[n]_1, and each of the wirings WCL[1]_p to WCL[n]_p is directly electrically connected one-to-one to wirings OL[1]_p to OL[n]_p. Although not shown in Figure 9, when p is 3 or greater, each of the wirings WCL[1] to WCL[n] in sub-array SA other than sub-array SA_1 and sub-array SA_p is electrically connected to the corresponding wiring OL.

[0317] By configuring the arithmetic circuit 10AA shown in Figure 9, for example, the sum of the currents flowing from wiring WCL[1]_1 to wiring OL[1]_1, that is, the sum of the currents output from cells IM[1,1] to IM[m,1], can be directly passed to wiring XCL[1]_1 in region L2. Similarly, in region L1, wirings WCL other than wiring WCL[1]_1 can be considered.

[0318] The arithmetic circuit 10AA in Figure 9 does not have an ITS circuit, so its circuit area can be reduced compared to the arithmetic circuit 10A in Figure 2. In addition, the arithmetic circuit 10AA in Figure 9 can reduce the power consumption required to drive the ITS circuit compared to the arithmetic circuit 10A in Figure 2.

[0319] <Configuration Example 5> In the arithmetic circuit 10A of Configuration Example 2, an example of an arithmetic circuit configuration is shown that performs a sum of products on a first data that is positive or "0" and a second data that is positive or "0". However, by changing the circuit configuration of arithmetic circuit 10A, it is possible to configure an arithmetic circuit that can perform a sum of products on a first data that is positive, negative, or "0" and a second data that is positive or "0".

[0320] The arithmetic circuit 10B shown in Figure 10 is a modified example of the arithmetic circuit 10A shown in Figure 2, and differs from the arithmetic circuit 10A in that multiple cells IMr and multiple wiring WCLr are provided in each of the subarrays SA_1 to SA_p of region L1 and region L2, respectively.

[0321] In the subarrays SA_1 to SA_p of regions L1 and L2, for example, the cell IMr[i,j] (not shown) in the i-th row and j-th column is provided to be paired with the cell IM[i,j] (not shown). Therefore, in each of the subarrays SA_1 to SA_p, the calculation cells of cell IM and cell IMr are arranged in an m-row, 2-column matrix. In the calculation circuit 10B, it is assumed that one pair of cell IM[i,j] and cell IMr[i,j] can hold one first data.

[0322] Furthermore, in the subarrays SA_1 to SA_p of region L1 and region L2, for example, the j-th column wiring WCLr[j] (not shown) is provided in pairs with wiring WCL[j] (not shown). That is, for example, in subarray SA_1, wiring WCL[1]_1 to wiring WCL[n]_1 and wiring WCLr[1]_1 to wiring WCL[n]r_1 extend in the column direction, and in subarray SA_p, wiring WCL[1]_p to wiring WCL[n]_p and wiring WCLr[1]_p to wiring WCL[n]r_p extend in the column direction.

[0323] In the subarray SA_s of region L1, cell IMr[i,j] is electrically connected to wiring XCL[i] and wiring WSL[i]. Furthermore, cell IMr[i,j] is electrically connected to wiring WCLr[j]_s. Similarly, in the subarray SA_s of region L2, cell IMr[j,h] (where h is an integer between 1 and k) is electrically connected to wiring XCL[j]_s and wiring WSL[j]. Furthermore, cell IMr[j,h] is electrically connected to wiring WCLr[h]_s.

[0324] Furthermore, in region L2, wiring WCL[1]_1 is electrically connected to wiring WCL[1]_p, similar to the arithmetic circuit 10A in Figure 2. Although not shown, if p is 3 or greater, wiring WCL[1]_1 is electrically connected to each of the wirings WCL[1]_2 through WCL[1]_(p-1) that extend to the first column of each of the different sub-arrays SA. Also, wiring WCL[k]_1 is electrically connected to wiring WCL[k]_p. Although not shown, if p is 3 or greater, wiring WCL[k]_1 is electrically connected to each of the wirings WCL[k]_2 through WCL[k]_(p-1) that extend to the k column of each of the different sub-arrays SA.

[0325] Furthermore, in region L2, wiring WCLr[1]_1 is electrically connected to wiring WCLr[1]_p. Although not shown in the diagram, if p is 3 or greater, wiring WCLr[1]_1 is electrically connected to each of the wirings WCLr[1]_2 through WCLr[1]_(p-1) that extend to the first column of each of the different sub-arrays SA. Also, wiring WCLr[k]_1 is electrically connected to wiring WCLr[k]_p. Although not shown in the diagram, if p is 3 or greater, wiring WCLr[k]_1 is electrically connected to each of the wirings WCLr[k]_2 through WCLr[k]_(p-1) that extend to the k column of each of the different sub-arrays SA.

[0326] Furthermore, in the subarray SA_s of region L1, the circuit ITS has the function of acquiring the difference in the amount of current flowing through the wiring WCL[j]_s and the wiring WCLr[j]_s, and outputting information corresponding to that difference (for example, one or both of the current and voltage) to the wiring OL[j]_s. Furthermore, in region L2, the circuit ITS has the function of acquiring the sum of the amounts of current flowing through the wirings WCL[j]_1 to WCL[j]_p located in the j-th column of each subarray SA, and the sum of the amounts of current flowing through the wirings WCLr[j]_1 to WCLr[j]_p located in the j-th column of each subarray SA, and outputting information corresponding to that difference (for example, one or both of the current and voltage) to the wiring OL[j].

[0327] For example, cell IM can have a configuration similar to that of cell IM[1,1] to cell IM[m,n] included in the cell array CA of the arithmetic circuit 10A in Figure 2.

[0328] Next, we will describe examples of configurations such as cell IM, cell IMr, and cell IMref that can be applied to the arithmetic circuit 10B in Figure 10.

[0329] Figure 11 is a circuit diagram showing specific configuration examples of cells IM, IMr, IMref, circuit WCS, and circuit ITS of the arithmetic circuit 10B in Figure 10. Note that Figure 11 also shows sub-arrays SAr and SA_s. Furthermore, to show the electrical connection with cell array CA, Figure 11 also includes circuits WCS and WSD.

[0330] Furthermore, cell IMr can have the same configuration as cell IM. Cell IMr in Figure 11 is illustrated as an example with the same configuration as cell IM. In addition, to distinguish between the transistors and capacitances contained in cell IM and cell IMr, the designation "r" is added to the transistors and capacitances contained in cell IMr.

[0331] Specifically, cell IMr has transistor F1r, transistor F2r, and capacitor C5r. Transistor F1r corresponds to transistor F1 of cell IM, transistor F2r corresponds to transistor F2 of cell IM, and capacitor C5r corresponds to capacitor C5 of cell IM. Therefore, the electrical connection configuration of transistor F1r, transistor F2r, and capacitor C5r should be considered in the above-mentioned description of IM[1,1] to cell IM[m,n].

[0332] Furthermore, in cell IMr, the connection point between the first terminal of transistor F1r, the gate of transistor F2r, and the first terminal of capacitor C5r is defined as node NNr.

[0333] In cell IM[1,j], the second terminal of capacitor C5 is electrically connected to wiring XCL[1], the gate of transistor F1 is electrically connected to wiring WSL[1], and the second terminals of transistor F1 and transistor F2 are electrically connected to wiring WCL[j]_s. Also, in cell IMr[1,j], the second terminal of capacitor C5r is electrically connected to wiring XCL[1], the gate of transistor F1r is electrically connected to wiring WSL[1], and the second terminals of transistor F1r and transistor F2r are electrically connected to wiring WCLr[j]_s.

[0334] Similarly, in cell IM[m,j], the second terminal of capacitor C5 is electrically connected to wiring XCL[m], the gate of transistor F1 is electrically connected to wiring WSL[m], and the second terminals of transistor F1 and transistor F2 are electrically connected to wiring WCL[j]_s. Also, in cell IMr[m,j], the second terminal of capacitor C5r is electrically connected to wiring XCL[m], the gate of transistor F1r is electrically connected to wiring WSL[m], and the second terminals of transistor F1r and transistor F2r are electrically connected to wiring WCLr[j].

[0335] Each of the wirings WCL[j] and WCLr[j] functions, for example, as wiring that carries current from circuit WCS to cell IM and cell IMr, similar to wirings WCL[1] to WCL[n] in Figure 2. Alternatively, for example, they function as wiring that carries current from circuit ITS to cell IM and cell IMr.

[0336] Furthermore, in the calculation circuit 10B of Figure 11, circuit SWS1 includes switch SW3[j] and switch SW3r[j]. The first terminal of switch SW3[j] is electrically connected to wiring WCL[j], the second terminal of switch SW3[j] is electrically connected to circuit WCSa[j] included in circuit WCG_s (described later), and the control terminal of switch SW3[j] is electrically connected to wiring SWL1. Also, the first terminal of switch SW3r[j] is electrically connected to wiring WCLr[j], the second terminal of switch SW3r[j] is electrically connected to circuit WCSb[j] included in circuit WCG_s (described later), and the control terminal of switch SW3r[j] is electrically connected to wiring SWL1.

[0337] The circuit WCG_s of the circuit WCS shown in Figure 11 includes, as an example, the circuit WCSa[j] and the circuit WCSb[j]. For the configuration of the circuits WCSa[j] and WCSb[j] in Figure 11, for example, the circuit WCSa shown in Figure 4A or Figure 4B can be applied.

[0338] Furthermore, in the calculation circuit 10B of Figure 11, circuit SWS2 includes switch SW4[j] and switch SW4r[j]. The first terminal of switch SW4[j] is electrically connected to wiring WCL[j], the second terminal of switch SW4[j] is electrically connected to the conversion circuit ITRZA[j] described later, and the control terminal of switch SW4[j] is electrically connected to wiring SWL2. In addition, the first terminal of switch SW4r[j] is electrically connected to wiring WCLr[j], the second terminal of switch SW4r[j] is electrically connected to the conversion circuit ITRZA[j] described later, and the control terminal of switch SW4r[j] is electrically connected to wiring SWL2.

[0339] The circuit ITG_s of the circuit ITS shown in Figure 11 includes, as an example, a conversion circuit ITRZA[j]. The conversion circuit ITRZA[j] is a circuit corresponding to the conversion circuit ITRZ[j] in the calculation circuit 10A in Figure 2, and has the function of generating a voltage corresponding to the difference between the amount of current flowing from the conversion circuit ITRZA[j] to the wiring WCL[j] and the amount of current flowing from the conversion circuit ITRZA[j] to the wiring WCLr[j], and outputting it to the wiring OL[j]_s.

[0340] Figure 12A shows a specific example of the configuration of the conversion circuit ITRZA[j]. The conversion circuit ITRZA1 shown in Figure 12A is an example of a circuit that can be applied to the conversion circuit ITRZA[j] in Figure 11. In addition, Figure 12A also shows circuit SWS2, wiring WCL, wiring WCLr, wiring SWL2, switch SW4, and switch SW4r to show the electrical connections with the surrounding circuits of the conversion circuit ITRZA1. Furthermore, wiring WCL and wiring WCLr can be, for example, wiring WCL[j] and wiring WCLr[j] included in the calculation circuit 10B in Figure 11, and switches SW4 and SW4r can be, for example, switches SW4[j] and switch SW4r[j] included in the calculation circuit 10B in Figure 11.

[0341] The conversion circuit ITRZA1 in Figure 12A is electrically connected to wiring WCL via switch SW4. Furthermore, the conversion circuit ITRZA1 is electrically connected to wiring WCLr via switch SW4r. Also, the conversion circuit ITRZA1 is electrically connected to wiring OL. The conversion circuit ITRZA1 has the function of acquiring the difference current between either the amount of current flowing from the conversion circuit ITRZA1 to wiring WCL via switch SW4, or the amount of current flowing from wiring WCL to the conversion circuit ITRZA1 via switch SW4, and either the amount of current flowing from the conversion circuit ITRZA1 to wiring WCLr via switch SW4r, or the amount of current flowing from wiring WCLr to the conversion circuit ITRZA1 via switch SW4r. It also has the function of flowing this difference current between the conversion circuit ITRZA1 and wiring OL.

[0342] The conversion circuit ITRZA1 in Figure 12A includes, as an example, a transistor F6, a current source CI, a current source CIr, and a current mirror circuit CM.

[0343] The second terminal of switch SW4 is electrically connected to the first terminal of current mirror circuit CM and the output terminal of current source CI. The second terminal of switch SW4r is electrically connected to the second terminal of current mirror circuit CM, the output terminal of current source CIr, and the first terminal of transistor F6. The input terminal of current source CI is electrically connected to wiring VHE, and the input terminal of current source CIr is electrically connected to wiring VHE. The third terminal of current mirror circuit CM is electrically connected to wiring VSE, and the fourth terminal of current mirror circuit CM is electrically connected to wiring VSE.

[0344] The second terminal of transistor F6 is electrically connected to wiring OL, and the gate of transistor F6 is electrically connected to wiring SWL3.

[0345] For example, the current mirror circuit CM has the function of flowing a current corresponding to the potential of the first terminal of the current mirror circuit CM between the first and third terminals of the current mirror circuit CM, and between the second and fourth terminals of the current mirror circuit CM.

[0346] Wiring VHE functions, for example, as wiring that provides a constant voltage. Specifically, this constant voltage can be, for example, a high-level potential.

[0347] The VSE wiring functions, for example, as wiring that provides a constant voltage. Specifically, this constant voltage can be, for example, a low-level potential or ground potential.

[0348] Wiring SWL3 functions, for example, as wiring for transmitting a signal to switch transistor F6 to the ON or OFF state. Specifically, for example, a high-level potential or a low-level potential can be input to wiring SWL3.

[0349] Current source CI has the function of supplying a constant current between its input terminal and output terminal. Similarly, current source CIr has the function of supplying a constant current between its input terminal and output terminal. In the conversion circuit ITRZA1 shown in Figure 12A, it is preferable that the magnitude of the current supplied by current source CI and the magnitude of the current supplied by current source CIr are equal.

[0350] Here, we will explain an example of the operation of the conversion circuit ITRZA1 shown in Figure 12A.

[0351] First, the amount of current flowing from the conversion circuit ITRZA1 through switch SW4 to the wiring WCL is I S The amount of current flowing from the conversion circuit ITRZA1 to the wiring WCLr via switch SW4r is I Sr Let's assume that I0 is the amount of current supplied by current source CI and current source CIr, respectively.

[0352] I S In the calculation circuit 10B of Figure 11, this is the sum of the currents flowing through cells IM[1,j] to IM[m,j] located in the j-th column. Sr In the calculation circuit 10B of Figure 11, this is the sum of the currents flowing through cells IMr[1,j] to IMr[m,j] located in the j-th column.

[0353] When a high-level potential is input to wiring SWL2, switches SW4 and SW4r are turned ON. Therefore, the amount of current flowing from the first terminal to the third terminal of the current mirror circuit CM is I0 - I S This is the result. Also, the current mirror circuit CM transmits I0-I from the second terminal of the current mirror circuit CM to the second terminal. S A certain amount of current flows.

[0354] Next, a high-level potential is input to wiring SWL3, and transistor F6 turns on. At this time, the amount of current flowing through wiring OL is I out Therefore, I out =I0-(I0-IS )-I Sr =I S -I Sr This is the result.

[0355] Here, we will explain the case where the arithmetic circuit 10B in Figure 11 performs a sum-of-products operation on a first data (positive, negative, or "0") and a second data (positive, or "0"). Regarding the storage of the first data in cell IM, please refer to the example of storing the first data described above.

[0356] When cells IM[i,j] and IMr[i,j] hold positive first data, the current flowing through cell IM[i,j] is set to be such that a current corresponding to the absolute value of the positive first data flows between the first and second terminals of transistor F2 of cell IM[i,j], and the current flowing through cell IMr[i,j] is set to be such that no current flows between the first and second terminals of transistor F2r of cell IMr[i,j]. Furthermore, when circuit CES[i,j] holds negative first data, the current flowing through cell IM[i,j] is set to be such that no current flows between the first and second terminals of transistor F2 of cell IM[i,j], and the current flowing through cell IMr[i,j] is set to be such that a current corresponding to the absolute value of the negative first data flows between the first and second terminals of transistor F2r of cell IMr[i,j]. Furthermore, when the circuit CES[i,j] holds the first data of "0", the cell IM[i,j] is set so that no current flows between the first and second terminals of transistor F2 of cell IM[i,j], and the cell IMr[i,j] is set so that no current flows between the first and second terminals of transistor F2r of cell IMr[i,j].

[0357] Here, when the second data is input to each of the wirings XCL[1] to XCL[m] of the arithmetic circuit 10B in Figure 11, the amount of current flowing between the first and second terminals of transistor F2 in cell IM[i,j] and the amount of current flowing between the first and second terminals of transistor F2 in cell IMr[i,j] are proportional to the second data.

[0358] I SThis is the sum of the currents flowing through cells IM[1,j] through IM[m,j] located in column j. Therefore, I S This can be expressed, for example, by the equation (2.1) below. That is, I S This corresponds to the result of the sum-of-products operation between the absolute value of the first positive data and the second data. Also, I Sr This is the sum of the currents flowing through cells IMr[1,j] through IMr[m,j] located in column j. Therefore, I Sr This represents the total amount of current flowing through cell IMr, and can be expressed similarly to, for example, equation (2.2) below. That is, I Sr This corresponds to the result of the sum-of-products operation between the absolute value of the negative first data point and the second data point.

[0359]

number

[0360] Therefore, the amount of current I flowing through wiring OL out =I S -I Sr This corresponds to the difference between the sum of products of the absolute value of the first positive data and the second data, and the sum of products of the absolute value of the first negative data and the second data. In other words, I out =I S -I Sr This corresponds to the result of a sum-of-products operation between the negative, "0", or positive first data held in cells IM[1,j] to IM[m,j] and IMr[1,j] to IMr[m,j], and the second data input to each of the wiring XCL[1] to wiring XCL[m].

[0361] By the way, when the sum of the currents flowing through cells IM[1,j] to IM[m,j] is greater than the sum of the currents flowing through cells IMR[1,j] to IMMR[m,j], that is, I S I Sr When it is greater than I outThe current becomes greater than 0 and flows from the conversion circuit ITRZA1 to the wiring OL. On the other hand, when the sum of the currents flowing through cells IM[1,j] to IM[m,j] is less than the sum of the currents flowing through cells IMR[1,j] to IMR[m,j], that is, I S I Sr When it is smaller than I, current may not flow from wiring OL to conversion circuit ITRZA1. S I Sr When it is smaller than I out This can be approximately 0. Therefore, the conversion circuit ITRZA1 can be considered to act, for example, as a ReLU function.

[0362] Furthermore, hierarchical neural networks will be described later in Embodiment 5.

[0363] Furthermore, as the conversion circuit ITRZA of the arithmetic circuit 10 in Figure 11, for example, the conversion circuit ITRZA2 shown in Figure 12B may be applied. The conversion circuit ITRZA2 has a circuit configuration that combines the conversion circuit ITRZA1 in Figure 12A and the conversion circuit ITRZ1 in Figure 6. As a result, the amount of current flowing between the first and second terminals of transistor F6, corresponding to the result of the sum-of-products operation between the first data and the second data, is converted to an analog voltage by a current-voltage conversion circuit consisting of a load LE and an operational amplifier OP1. This analog voltage is then converted to a digital voltage by an analog-to-digital conversion circuit, and this digital voltage is converted to an analog current by circuit ZCSa. As a result, unlike the conversion circuit ITRZA1, the conversion circuit ITRZA2 performs current-to-voltage conversion, analog-to-digital conversion, and analog current, so the error in the amount of current output to wiring OL can be made smaller than that of the conversion circuit ITRZA1.

[0364] <Configuration Example 6> Furthermore, the arithmetic circuit 10A in Figure 2, described in Configuration Example 2, may be modified to the configuration of the arithmetic circuit 10C shown in Figure 13. The arithmetic circuit 10C in Figure 13 differs from the arithmetic circuit 10A in that it has a circuit XCS in region L2.

[0365] In region L2, circuit XCS is electrically connected to wiring XCL[1]_1 through XCL[n]_1 and wiring XCL[1]_p through XCL[n]_p.

[0366] In the arithmetic circuit 10C, the circuit XCS in region L2, for example, when writing the first data to cell IM of cell array CA, generates a current I in the wiring XCL. ref0 It outputs the following: In other words, at times T13 to T15, T17 to T19, etc. in the timing chart of Figure 7, circuit XCS outputs current I to wiring XCL. ref0 Output the voltage and set the potential of wiring XCL to V gm I'll do that.

[0367] Furthermore, in the calculation circuit 10C, circuit XCS in region L2 stops outputting current to wiring XCL when calculations are performed by the cell array CA, for example. Specifically, in circuit XCS in Figure 4C, switch SW5 is turned off. Instead, wiring XCL receives current corresponding to the result calculated by the cell array CA in region L1. In other words, at times T22 to T23 in the timing chart of Figure 7, wiring XCL in region L2 is supplied with current from circuit ITS in region L1.

[0368] As described above, by configuring the arithmetic circuit 10C, when the first data is written to the cell array CA in region L2, the circuit XCS in region L2 can supply a reference current to the wiring XCL. By supplying a reference current to the wiring XCL when the first data is written, when a current corresponding to the result calculated by the cell array CA in region L1 is input to the wiring XCL, the calculation of the first and second data can be performed with high accuracy.

[0369] In addition, while the above-described arithmetic circuits 10, 10A, 10B, and 10C are configured to have a circuit WCS for writing first data to region L1 and region L2 respectively, it is also possible to use the circuit WCS in region L1 to write first data to cells IM included in the cell array CA in region L2. In other words, the above-described arithmetic circuits 10, 10A, 10B, and 10C may be configured without a circuit WCS in region L2, and instead be electrically connected to the circuit WCS in region L1 and to a plurality of wirings WCL extending to the cell array CA in region L2.

[0370] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., can be appropriately combined with other configuration examples or drawings, etc., at least in part.

[0371] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0372] (Embodiment 2) This embodiment describes an example of a display device configuration combining a semiconductor device according to one aspect of the present invention and a display unit.

[0373] <Configuration Example 1> Figure 14 shows an example configuration of a display device combining the semiconductor device and display unit described in the above embodiment. The display device 100A shown in Figure 14 includes, as an example, a display unit DSP and a circuit unit SIC. Although Figure 14 shows a sensor PDA, the sensor PDA may be located inside or outside the display device 100A.

[0374] In Figure 14, thicker wires are indicated as multiple wires or bus wires.

[0375] In Figure 14, the display unit DSP has, as an example, multiple pixel circuits PX arranged in a matrix. The pixel circuits PX can be, for example, pixels using a liquid crystal display device, a light-emitting device containing organic EL material, or a light-emitting device containing a light-emitting diode such as a micro-LED. In this embodiment, the pixel circuits PX of the display unit DSP are described as being made using a light-emitting device containing organic EL material. In particular, the brightness of the light emitted from a light-emitting device capable of high-brightness emission is, for example, 500 cd / m². 2 Preferably 1000 cd / m² 2 More than 10000cd / m 2 More preferably, 2000 cd / m² 2 More than 5000cd / m 2 The following is possible. Circuits applicable to the display unit DSP, pixel circuit PX, etc., will be described in detail in Embodiment 4.

[0376] Furthermore, in Figure 14, the circuit section SIC includes the peripheral circuit DRV and the functional circuit MFNC.

[0377] The peripheral circuit DRV functions, for example, as a peripheral circuit for driving the display unit DSP. Specifically, the peripheral circuit DRV includes, for example, a source driver circuit 11, a digital-to-analog conversion circuit 12, a gate driver circuit 13, and a level shifter 14.

[0378] Furthermore, the functional circuit MFNC may include, for example, a storage device for storing image data to be displayed on the display unit DSP, a decoder for restoring encoded image data, a GPU (Graphics Processing Unit) for processing image data, a power supply circuit, a correction circuit, and a CPU. In Figure 14, the functional circuit MFNC may include, for example, a storage device 21, a GPU (AI accelerator) 22, an EL correction circuit 23, a timing controller 24, a CPU (NoffCPU®) 25, a sensor controller 26, and a power supply circuit 27.

[0379] Furthermore, in the display device 100A shown in Figure 14, the bus wiring BSL is electrically connected to each of the circuits included in the peripheral circuit DRV and the circuits included in the functional circuit MFNC, as an example.

[0380] The source driver circuit 11, for example, has the function of transmitting image data to the pixel circuit PX included in the display unit DSP. Therefore, the source driver circuit 11 is electrically connected to the pixel circuit PX via wiring SL.

[0381] The digital-to-analog conversion circuit 12, for example, has the function of converting digitally processed image data, such as that processed by a GPU and correction circuit (described later), into analog data. The image data converted to analog data is transmitted to the display unit DSP via the source driver circuit 11. The digital-to-analog conversion circuit 12 may be included in the source driver circuit 11, or the image data may be transmitted in the order of source driver circuit 11, digital-to-analog conversion circuit 12, and then the display unit DSP.

[0382] The gate driver circuit 13, for example, has the function of selecting the pixel circuit PX to which the image data will be transmitted in the display unit DSP. Therefore, the gate driver circuit 13 is electrically connected to the pixel circuit PX via wiring GL.

[0383] The level shifter 14, for example, has the function of converting the signals input to the source driver circuit 11, the digital-to-analog conversion circuit 12, the gate driver circuit 13, etc., to an appropriate level.

[0384] The storage device 21, for example, has the function of storing image data to be displayed on the display unit DSP. The storage device 21 can be configured to store image data as either digital or analog data.

[0385] Furthermore, when saving image data to the storage device 21, it is preferable that the storage device 21 be a non-volatile memory. In this case, for example, a NAND type memory can be used as the storage device 21.

[0386] Furthermore, when storing temporary data generated by the GPU 22, EL correction circuit 23, CPU 25, etc., in the storage device 21, it is preferable to use volatile memory as the storage device 21. In this case, for example, SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory) can be used as the storage device 21.

[0387] For example, the GPU22 has the function of processing image data read from the storage device 21 for rendering on the display unit DSP. In particular, because the GPU22 is configured to perform parallel pipeline processing, it can process image data to be displayed on the display unit DSP at high speed. The GPU22 can also function as a decoder for restoring encoded images.

[0388] Furthermore, the functional circuit MFNC may include multiple circuits that can improve the display quality of the display unit DSP. For example, such circuits may include correction circuits (color tuning, brightness adjustment) that detect color unevenness in the image displayed on the display unit DSP and correct the color unevenness to create an optimal image. Also, if the pixels of the display unit DSP use light-emitting devices (sometimes called organic EL elements) made of organic EL material, the functional circuit MFNC may include an EL correction circuit that corrects variations in the brightness of the light emitted by multiple organic EL elements. In this embodiment, since the pixel circuit PX of the display unit DSP is described as being made of light-emitting devices containing organic EL material, the functional circuit MFNC includes an EL correction circuit 23 as an example.

[0389] Furthermore, artificial intelligence may be used for the image correction described above. For example, the current flowing through the display device provided in the pixel (or the voltage applied to the display device) may be monitored and acquired, the image displayed on the display unit DSP may be acquired by an image sensor, and the current (or voltage) and the image may be treated as input data for an artificial intelligence calculation (for example, an artificial neural network calculation), and the output result may be used to determine whether or not the image has been corrected.

[0390] Furthermore, artificial intelligence calculations can be applied not only to image correction but also to image data upconversion (downconversion). This allows for upconversion (downconversion) of low-resolution image data to match the resolution of the display unit's DSP, enabling the display of high-quality images on the display unit's DSP.

[0391] Furthermore, the artificial intelligence calculations described above can be performed using the GPU22 included in the functional circuit MFNC. In other words, various correction calculations can be performed using the GPU22. Examples of various correction calculations include color uniformity correction and upconversion (downconversion) processing. In addition, the GPU22 may be configured to have a circuit 22a for correcting color uniformity and a circuit 22b for performing upconversion (downconversion), as shown in Figure 14.

[0392] In this specification, the GPU that performs artificial intelligence calculations will be referred to as the AI ​​accelerator. In other words, in this specification, the GPU provided in the functional circuit MFNC may be described as the AI ​​accelerator.

[0393] Furthermore, as the arithmetic circuits included in the AI ​​accelerator, for example, the arithmetic circuits 10, 10A, and 10B, which are semiconductor devices of the embodiment described above, can be applied.

[0394] The timing controller 24 has, for example, a function to arbitrarily set the frame rate at which images are displayed on the display unit DSP. For example, when displaying a still image on the display unit DSP, the display device 100A can be driven at a reduced frame rate by the timing controller 24. Conversely, when displaying a video on the display unit DSP, the display device 100A can be driven at a higher frame rate by the timing controller 24. In other words, by providing the timing controller 24 to the display device 100A, the frame rate can be changed according to whether it is a still image or a video. In particular, when displaying a still image on the display unit DSP, the frame rate can be reduced, thereby reducing the power consumption of the display device 100A.

[0395] The CPU 25 has the function of performing general-purpose processing such as executing the operating system, controlling data, performing various calculations, and executing programs. In the display device 100A, the CPU 25 has the role of issuing commands such as writing or reading image data from the storage device 21, correcting image data, and operating sensors described later. In addition, the CPU 25 may have the function of transmitting control signals to at least one of the circuits included in the functional circuit MFNC, such as the storage device, the GPU, the correction circuit, the timing controller, and the high-frequency circuit.

[0396] Furthermore, the CPU 25 may have a circuit for temporarily backing up data (hereinafter referred to as the backup circuit). Preferably, the backup circuit can retain the data even if, for example, the power supply voltage is stopped. For example, when a still image is displayed by the display unit DSP, the CPU 25 can stop functioning until it displays an image different from the current still image. Therefore, by temporarily saving the data being processed by the CPU 25 to the backup circuit, and then stopping the power supply voltage to the CPU 25 to shut down the CPU 25, the dynamic power consumption of the CPU 25 can be reduced. In this specification, a CPU having a backup circuit is referred to as a NoffCPU.

[0397] The sensor controller 26, for example, has the function of controlling the sensor PDA. Figure 14 also illustrates the wiring SNCL as the wiring for electrically connecting the sensor PDA and the sensor controller 26.

[0398] The sensor PDA can be, for example, a touch sensor that can be installed above, below, or inside the display unit DSP.

[0399] Alternatively, the sensor PDA can be, for example, an illuminance sensor. In particular, by acquiring the intensity of ambient light illuminating the display unit DSP using the illuminance sensor, the brightness (luminance) of the image displayed on the display unit DSP can be changed according to the ambient light. For example, if the ambient light is bright, the luminance of the image displayed on the display unit DSP can be increased to improve the visibility of the image. Conversely, if the ambient light is dim, the luminance of the image displayed on the display unit DSP can be decreased to reduce power consumption.

[0400] Alternatively, the sensor PDA can be, for example, an image sensor. For instance, by acquiring an image using the image sensor, the image can be displayed on the DSP display unit.

[0401] The power supply circuit 27 has the function of generating voltage to supply to circuits included in the peripheral circuit DRV, circuits included in the functional circuit MFNC, pixels included in the display unit DSP, etc. The power supply circuit 27 may also have the function of selecting the circuits to which voltage is supplied. For example, the power supply circuit 27 can reduce the overall power consumption of the display device 100A by stopping the voltage supply to the CPU 25, GPU 22, etc., during the period when a still image is displayed on the display unit DSP.

[0402] <Configuration Example 2> Here, we will describe an example configuration in the display device 100A described above, in which the sensor PDA is used as an image sensor to acquire images of the user's eyes and / or their surroundings when viewing the display image of the display device 100A. The user's eyes refer to, for example, the eyeball and / or the pupil, and the surroundings of the user's eyes refer to, for example, one or more selected from the eyelids, glabella, inner corner of the eye, and outer corner of the eye.

[0403] The sensor PDA can, for example, capture images of the user's eyes and / or their surroundings as they view the display image on the display device 100A. The images of the user's eyes and / or their surroundings captured by the sensor PDA are then transmitted to the GPU 22 (AI accelerator). The GPU 22 can then perform inference processing based on the transmitted images using an artificial neural network.

[0404] Figure 15 shows an example of operation in which the sensor PDA captures images of the user's eye and / or its surroundings, and then performs neural network inference processing based on the captured images. Specifically, Figure 15 shows an example in which the user's eye ME and its surroundings are captured by multiple photodetectors PD included in the sensor PDA, and the captured images are transmitted to the GPU 22.

[0405] For example, the light-receiving element PD shown in Figure 28A or Figure 28B, which will be described later in Embodiment 4, can be used as the sensor PDA shown in Figure 15.

[0406] As described above, GPU22 performs inference processing based on an artificial neural network. Specifically, GPU22 performs sum-of-products operations on the captured image and pre-trained weight coefficients, and then calculates an activation function using the results of the sum-of-products operation, thereby enabling inference processing based on an artificial neural network. As a result, the output data D obtained by GPU22 is... OUT For example, "whether or not the user blinks," "degree of eye opening," and "body temperature" can be inferred from the user's eye ME and surrounding area.

[0407] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0408] (Embodiment 3) This embodiment describes a hierarchical neural network. The computation of the hierarchical neural network can be performed using the semiconductor device described in the above embodiment.

[0409] <Hierarchical Neural Network> A hierarchical neural network, for example, has one input layer, one or more hidden layers, and one output layer, and is composed of a total of three or more layers. The hierarchical neural network ANN shown in Figure 16A is an example, and the neural network ANN has layers 1 through R (where R can be an integer of 4 or greater). In particular, layer 1 corresponds to the input layer, layer R corresponds to the output layer, and the other layers correspond to hidden layers. Note that in Figure 16A, layers (k-1) and k (where k is an integer between 3 and R-1) are shown as hidden layers, and the other hidden layers are omitted from the illustration.

[0410] Each layer of the neural network ANN has one or more neurons. In Figure 16A, the first layer is neuron N1 (1) Neuron N p (1) (Here, p is an integer greater than or equal to 1.) The (k-1)th layer has neuron N1 (k-1) Neuron N m (k-1) (Here, m is an integer greater than or equal to 1.) The k-th layer has neurons N1 (k) Neuron N n (k) (where n is an integer greater than or equal to 1.) The R layer has neurons N1 (R) Neuron N q (R) (where q is an integer greater than or equal to 1.)

[0411] Note that Figure 16A shows neuron N1 (1) , Neuron N p (1) , neuron N1 (k-1) , Neuron N m (k-1) , neuron N1 (k) , Neuron N n (k) , neuron N1 (R) , Neuron N q (R) In addition, the (k-1) layer neurons N i (k-1) (Here, i is an integer between 1 and m, inclusive.) Neuron N of layer k j (k) (Here, j is an integer between 1 and n, inclusive.) is also illustrated, while the other neurons are not shown in the diagram.

[0412] Next, we will explain the transmission of signals from neurons in the previous layer to neurons in the next layer, and the signals that are input and output in each neuron. Note that in this explanation, we will assume that the neurons in layer k are N j (k) Let's focus on that.

[0413] Figure 16B shows the neurons N in layer k. j (k) And, neuron N j (k) The signal input to and neuron N j (k) This shows the signal output from and .

[0414] Specifically, the (k-1) neuron N1 (k-1) Neuron N m (k-1) z1 is the output signal of each of the following: (k-1) ~z m (k-1) However, neuron N j (k) It is outputting towards neuron N. j (k) is z1 (k-1)~z m (k-1) z j (k) Generate z j (k) This is output as an output signal to each neuron in the (k+1)th layer (not shown).

[0415] The degree to which signals are transmitted from neurons in the previous layer to neurons in the next layer is determined by the strength of the synaptic connections (hereinafter referred to as weight coefficients) between those neurons. In a neural network (ANN), the signal output from a neuron in the previous layer is multiplied by the corresponding weight coefficient and input to the neuron in the next layer. Let i be an integer between 1 and m, and the (k-1)th neuron N i (k-1) and the k-th layer of neurons N j (k) The weight coefficient of the synapse between w i (k-1) j (k) When this is the case, the neurons N in layer k j (k) The signal input to the device can be expressed by equation (3.1).

[0416]

number

[0417] In other words, the (k-1)th layer neuron N1 (k-1) Neuron N m (k-1) From each of these, the k-th layer neurons N j (k) When a signal is transmitted to z1, the signal in question is z1 (k-1) ~z m (k-1) This includes weight coefficients (w1) corresponding to each signal. (k-1) j (k) Or maybe lol m (k-1) j (k) ) is multiplied. And the neuron N in layer kj (k) w1 (k-1) j (k) ·z1 (k-1) Or maybe lol m (k-1) j (k) ·z m (k-1) This is input. At this time, the neuron N in layer k j (k) The sum of the signals input to u j (k) This is given by equation (3.2).

[0418]

number

[0419] Also, the weight coefficient w1 (k-1) j (k) Or maybe lol m (k-1) j (k) And the neuron's signal z1 (k-1) ~z m (k-1) A bias may be introduced as a skew into the result of the sum of products of and. When the bias is denoted as b, equation (3.2) can be rewritten as follows:

[0420]

number

[0421] Neuron N j (k) , u j (k) Depending on the output signal z j (k) This generates neuron N. j (k) Output signal z from j (k) We define it by the following formula.

[0422]

number

[0423] function f(u j (k) The activation function in a hierarchical neural network can be a step function, linear ramp function, sigmoid function, etc. The activation function may be the same for all neurons, or it may be different for all neurons. Furthermore, the activation functions of neurons may be the same or different for each layer.

[0424] Incidentally, the signals, weight coefficients w, or bias b output by neurons in each layer may be analog values ​​or digital values. As digital values, they may be binary, ternary, or even have a larger number of bits. For example, in the case of analog values, activation functions such as a linear ramp function or a sigmoid function may be used. In the case of binary digital values, for example, a step function that outputs -1 or 1, or 0 or 1 may be used. Furthermore, the signals output by neurons in each layer may have three or more values, in which case a ternary activation function may be used, for example, a step function that outputs -1, 0, or 1, or a step function that outputs 0, 1, or 2. Alternatively, for example, a step function that outputs 5 values, such as -2, -1, 0, 1, or 2, may be used. By using digital values ​​for at least one of the signals, weight coefficients w, or bias b output by neurons in each layer, it is possible to reduce the circuit size, reduce power consumption, or increase the processing speed. Furthermore, the accuracy of the calculation can be improved by using analog values ​​for at least one of the signals output by neurons in each layer, the weight coefficient w, or the bias b.

[0425] The neural network ANN, upon receiving an input signal at its first layer (input layer), sequentially generates an output signal at each layer from the first layer (input layer) to the last layer (output layer) based on the signal input from the previous layer, using equations (3.1), (3.2) (or (3.3)), and (3.4), and outputs this output signal to the next layer. The signal output from the last layer (output layer) corresponds to the result calculated by the neural network ANN.

[0426] When the circuit included in region L1 of the arithmetic circuit 10 described in Embodiment 1 is applied as the hidden layer described above, the weight coefficient w s[k-1] (k-1) s[k] (k) (where s[k-1] is an integer between 1 and m, and s[k] is an integer between 1 and n) is used as the first data, and the current amount corresponding to the first data is sequentially stored in each cell IM of the same column, so that the neurons N of the (k-1) layer s[k-1] (k-1) Output signal z from s[k-1] (k-1) Using this as the second data, the amount of current corresponding to the second data is passed from circuit XCS to the wiring XCL of each row, thereby inputting the current I to the conversion circuit ITRZ. S From this, the sum of products of the first data and the second data can be calculated. In addition, by using the value of this sum of products to determine the value of the activation function, the value of the activation function can be used as a signal for the neuron N in layer k. s[k] (k) Output signal z s[k] (k) It can be done this way.

[0427] Furthermore, when the circuit included in region L2 of the arithmetic circuit 10 described in Embodiment 1 is applied as the output layer described above, the weight coefficient w s[R-1] (R-1) s[R] (R) (where s[R-1] is an integer greater than or equal to 1, and s[R] is an integer between 1 and q) is used as the first data, and the current amount corresponding to the first data is sequentially stored in each cell IM of the same column, so that the neurons N of the (R-1) layer s[R-1] (R-1)Output signal z from s[R-1] (R-1) Using this as the second data, the amount of current corresponding to the second data is passed from circuit XCS to the wiring XCL of each row, thereby inputting the current I to the conversion circuit ITRZ. S From this, the sum of products of the first data and the second data can be calculated. In addition, by using the value of this sum of products to determine the value of the activation function, the value of the activation function can be used as a signal for the neuron N in layer R. s[R] (R) Output signal z s[R] (R) It can be done this way.

[0428] Furthermore, the input layer described in this embodiment may also function as a buffer circuit that outputs the input signal to the second layer.

[0429] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0430] (Embodiment 4) This embodiment describes a display device that can be provided in an electronic device according to one aspect of the present invention. The display unit DSP described in the above embodiment can be replaced with the display device described in this embodiment.

[0431] <Example of display device configuration> Figure 17 is a cross-sectional view showing an example of a display device according to one aspect of the present invention. The display device 100 shown in Figure 17 has, as an example, a configuration in which a pixel circuit, a driving circuit, and the like are provided on a substrate 310.

[0432] Specifically, the display device 100 includes, for example, a circuit layer SICL, a wiring layer LINL, and a pixel layer PXAL. The circuit layer SICL includes, for example, a substrate 310, on which a transistor 300 is formed. Above the transistor 300, a wiring layer LINL is provided, and the wiring layer LINL is provided with wiring that electrically connects to the transistor 300, the transistor 200 (described later), the light-emitting device 150a (described later), the light-emitting device 150b (described later), etc. Above the wiring layer LINL, a pixel layer PXAL is provided, for example, the transistor 200 and the light-emitting device 150 (in Figure 17, light-emitting device 150a and light-emitting device 150b), etc.

[0433] For example, the substrate 310 can be a semiconductor substrate (e.g., a single-crystal substrate) made of silicon or germanium. In addition to semiconductor substrates, the substrate 310 can also be, for example, an SOI (Silicon On Insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate with stainless steel foil, a tungsten substrate, a substrate with tungsten foil, a flexible substrate, a laminated film, paper containing fibrous material, or a base film. Examples of glass substrates include barium borosilicate glass, aluminobosilicate glass, or soda-lime glass. Examples of flexible substrates, laminated films, and base films include the following: For example, plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Alternatively, synthetic resins such as acrylic resin can be used as an example. Alternatively, examples include polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride. Alternatively, examples include polyamide, polyimide, aramid, epoxy resin, inorganic vapor-deposited film, or paper. If the manufacturing process of the display device 100 includes heat treatment, it is preferable to select a material with high heat resistance for the substrate 310.

[0434] In this embodiment, the substrate 310 is described as a semiconductor substrate having silicon as its material.

[0435] The transistor 300 is provided on a substrate 310 and has an element isolation layer 312, a conductor 316, an insulator 315, an insulator 317, a semiconductor region 313 consisting of a part of the substrate 310, a low-resistance region 314a that functions as a source region or a drain region, and a low-resistance region 314b. For this reason, the transistor 300 is a Si transistor. In Figure 17, one of the source or drain of the transistor 300 is shown to be electrically connected to the conductors 330, 356, and 366, which will be described later, via the conductor 328, which will be described later. However, the electrical connection configuration of the semiconductor device in one aspect of the present invention is not limited to this. In one aspect of the present invention, for example, the gate of the transistor 300 may be electrically connected to the conductors 330, 356, and 366, which will be described later, via the conductor 328.

[0436] The transistor 300 can be made into a Fin type by, for example, configuring the top surface and the side surface in the channel width direction of the semiconductor region 313 to be covered by a conductor 316 via an insulator 315 that functions as a gate insulating film. By making the transistor 300 a Fin type, the effective channel width can be increased, and the on-characteristics of the transistor 300 can be improved. In addition, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-characteristics of the transistor 300.

[0437] The transistor 300 may be either a p-channel or an n-channel type. Alternatively, multiple transistors 300 may be provided, using both p-channel and n-channel types.

[0438] In the low-resistance region 314a and low-resistance region 314b, which are the channel-forming region of the semiconductor region 313, the region near it, the source region, or the drain region, it is preferable that a silicon-based semiconductor is included, and it is particularly preferable that single-crystal silicon is included. Alternatively, each of the above-mentioned regions may be formed from a material having germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), aluminum gallium arsenide (GaAlAs), gallium nitride (GaN), etc. Furthermore, each of the above-mentioned regions may be constructed using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) using, for example, gallium arsenide and aluminum gallium arsenide.

[0439] The conductor 316, which functions as the gate electrode, can be made of a conductive material such as silicon, a semiconductor material, a metallic material, an alloy material, or a metal oxide material containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0440] Furthermore, since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use titanium nitride and tantalum nitride, or both, as the conductor. In addition, in order to achieve both conductivity and embedding properties, it is preferable to use tungsten and aluminum, or both, as laminated materials for the conductor, and using tungsten is particularly preferable in terms of heat resistance.

[0441] The element isolation layer 312 is provided to separate multiple transistors formed on the substrate 310. The element isolation layer can be formed using, for example, the LOCOS (Local Oxidation of Silicon) method, the STI (Shallow Trench Isolation) method, or the mesa isolation method.

[0442] Note that the transistor 300 shown in Figure 17 is just one example, and its structure is not limited to this example. Any suitable transistor can be used depending on the circuit configuration, driving method, etc. For example, the transistor 300 may have a planar structure instead of a fin type.

[0443] In the transistor 300 shown in Figure 17, insulators 320, 322, 324, and 326 are stacked in order from the substrate 310 side.

[0444] For insulators 320, 322, 324, and 326, one or more selected from silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum oxide nitride, and aluminum nitride may be used.

[0445] The insulator 322 may also function as a planarizing film that flattens steps caused by the insulator 320 and the transistor 300 covered by the insulator 322. For example, the upper surface of the insulator 322 may be planarized by a planarizing treatment using a chemical mechanical polishing (CMP) method or the like to improve its flatness.

[0446] Furthermore, it is preferable to use a barrier insulating film for the insulator 324 that prevents the diffusion of impurities such as water and hydrogen from the substrate 310 or the transistor 300 to the region above the insulator 324 (for example, the region where the transistor 200, light-emitting device 150a, light-emitting device 150b, etc. are provided). Therefore, it is preferable to use an insulating material for the insulator 324 that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, and water molecules (i.e., the above impurities do not easily permeate it). Also, depending on the situation, it is preferable to use an insulating material for the insulator 324 that has the function of suppressing the diffusion of impurities such as nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (i.e., the above impurities do not easily permeate it). Alternatively, it is preferable to have the function of suppressing the diffusion of oxygen (for example, oxygen atoms and / or oxygen molecules).

[0447] As an example of a film with hydrogen barrier properties, silicon nitride formed by the CVD (Chemical Vapor Deposition) method can be used.

[0448] The amount of hydrogen desorption can be analyzed, for example, using a thermal desorption gas analysis (TDS) method. For example, in TDS analysis, the amount of hydrogen desorption from insulator 324, when the film surface temperature is in the range of 50°C to 500°C, is calculated as 10 × 10¹⁶ hydrogen atoms per unit area of ​​insulator 324. 15 atoms / cm 2 The following is preferably 5 × 10 15 atoms / cm 2 The following is acceptable.

[0449] Furthermore, it is preferable that the dielectric constant of the insulator 326 is lower than that of the insulator 324. For example, the relative permittivity of the insulator 326 is preferably less than 4, and more preferably less than 3. Also, for example, the relative permittivity of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, than that of the relative permittivity of the insulator 324. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance occurring between wiring can be reduced.

[0450] Furthermore, insulators 320, 322, 324, and 326 have conductors 328 and 330 embedded in them, which connect to light-emitting devices and the like that are provided above insulator 326. Conductors 328 and 330 have the function of a plug or wiring. Conductors that have the function of a plug or wiring may be grouped together and given the same reference numeral. Also, in this specification, the wiring and the plug that connects to the wiring may be an integrated unit. That is, there may be cases where a part of the conductor functions as wiring, and cases where a part of the conductor functions as a plug.

[0451] The plugs and wiring (conductor 328 and conductor 330) can be made from one or more conductive materials selected from metal materials, alloy materials, metal nitride materials, and metal oxide materials, either in a single layer or in a laminated form. It is preferable to use high-melting-point materials such as tungsten or molybdenum, which offer both heat resistance and conductivity, with tungsten being preferred. Alternatively, it is preferable to form them from low-resistance conductive materials such as aluminum or copper. Using low-resistance conductive materials can reduce wiring resistance.

[0452] Wiring layers may be provided on the insulator 326 and the conductor 330. For example, in Figure 17, insulators 350, 352, and 354 are sequentially stacked on top of insulators 326 and conductor 330. Conductors 356 are formed on insulators 350, 352, and 354. Conductors 356 function as plugs or wiring for connecting to transistor 300. Conductors 356 can be provided using the same material as conductors 328 and 330.

[0453] For example, it is preferable that insulator 350, like insulator 324, is an insulator that has barrier properties against hydrogen, oxygen, and water. Also, as insulators 352 and 354, it is preferable to use insulators with relatively low dielectric constants in order to reduce parasitic capacitance between wiring, similar to insulator 326. Furthermore, insulators 362 and 364 have the functions of an interlayer insulating film and a planarizing film. In addition, it is preferable that conductor 356 contains a conductor that has barrier properties against hydrogen, oxygen, and water.

[0454] For example, tantalum nitride can be used as the conductor that has barrier properties against hydrogen. Furthermore, by laminating tantalum nitride with highly conductive tungsten, it is possible to suppress the diffusion of hydrogen from the transistor 300 while maintaining conductivity as wiring. In this case, it is preferable that the tantalum nitride layer, which has barrier properties against hydrogen, is in contact with the insulator 350, which also has barrier properties against hydrogen.

[0455] Furthermore, insulator 360, insulator 362, and insulator 364 are stacked in order on insulator 354 and conductor 356.

[0456] It is preferable that the insulator 360, like the insulator 324, is an insulator that has barrier properties against impurities such as water and hydrogen. Therefore, as the insulator 360, for example, a material that can be used for the insulator 324 can be used.

[0457] Insulators 362 and 364 function as interlayer insulating films and planarizing films, respectively. Furthermore, it is preferable that insulators 362 and 364, like insulator 324, be insulators that have barrier properties against impurities such as water and hydrogen. Therefore, one or both of insulators 362 and 364 can be made from materials applicable to insulator 324.

[0458] Furthermore, openings are formed in the regions of insulators 360, 362, and 364 that overlap with a portion of the conductor 356, and the conductor 366 is provided to fill these openings. The conductor 366 is also formed on insulator 362. The conductor 366 functions, for example, as a plug or wiring for connecting to transistor 300. The conductor 366 can be provided using the same material as conductors 328 and 330.

[0459] Insulator 370 and insulator 372 are stacked in order on insulator 364 and conductor 366, respectively.

[0460] It is preferable that the insulator 370, like the insulator 324, is an insulator that has barrier properties against impurities such as water and hydrogen. Therefore, as the insulator 370, for example, a material that can be used for the insulator 324 can be used.

[0461] The insulator 372 functions as an interlayer insulating film and a planarizing film. Furthermore, it is preferable to use an insulator 372 that, like the insulator 324, has barrier properties against impurities such as water and hydrogen. Therefore, the insulator 372 can be made from a material applicable to the insulator 324.

[0462] Furthermore, openings are formed in the regions of the insulator 370 and the insulator 372 that overlap with a portion of the conductor 366, and the conductor 376 is provided to fill these openings. The conductor 376 is also formed on the insulator 372. Subsequently, the conductor 376 is patterned into the shape of wiring, terminals, or pads by etching or other processes.

[0463] For example, the conductor 376 can be copper, aluminum, tin, zinc, tungsten, silver, platinum, or gold. Preferably, the conductor 376 is composed of the same components as the material used in the conductor 216 contained in the pixel layer PXAL, which will be described later.

[0464] Next, an insulator 380 is formed to cover the insulator 372 and the conductor 376, and then a planarization process using chemical mechanical polishing (CMP) or the like is performed until the conductor 376 is exposed. This allows the conductor 376 to be formed on the substrate 310 as wiring, terminals, or pads.

[0465] As the insulator 380, it is preferable to use a film that has barrier properties to prevent the diffusion of impurities such as water and hydrogen, similar to the insulator 324. In other words, it is preferable to use a material for the insulator 380 that is applicable to the insulator 324. Alternatively, as the insulator 380, it is also possible to use an insulator with a relatively low dielectric constant, similar to the insulator 326, in order to reduce parasitic capacitance between the wires. In other words, it is also possible to use a material for the insulator 380 that is applicable to the insulator 326.

[0466] The pixel layer PXAL includes, as an example, a substrate 210, a transistor 200, a light-emitting device 150 (light-emitting device 150a and light-emitting device 150b in Figure 17), and a substrate 102. The pixel layer PXAL also includes, as an example, an insulator 220, an insulator 222, an insulator 226, an insulator 250, an insulator 111a, an insulator 111b, an insulator 112, an insulator 113, an insulator 162, and a resin layer 163. The pixel layer PXAL also includes, as an example, a conductor 216, a conductor 228, a conductor 230, a conductor 121 (conductor 121a and conductor 121b in Figure 17), a conductor 122, and a conductor 123.

[0467] In Figure 17, for example, the insulator 202 functions as a bonding layer together with the insulator 380. Preferably, the insulator 202 is composed of the same components as the material used in the insulator 380.

[0468] A substrate 210 is provided above the insulator 202. In other words, the insulator 202 is formed on the lower surface of the substrate 210. It is preferable to use a substrate 210 that is applicable to substrate 310, for example. In the display device 100 shown in Figure 17, substrate 310 is described as a semiconductor substrate made of silicon.

[0469] A transistor 200, for example, is formed on the substrate 210. Since the transistor 200 is formed on the substrate 210, which is a semiconductor substrate made of silicon, it functions as a Si transistor. For details on the configuration of transistor 200, please refer to the description of transistor 300.

[0470] An insulator 220 and an insulator 222 are provided above the transistor 200. Insulator 220 functions as an interlayer insulating film and a planarizing film, similar to insulator 320, for example. Similarly, insulator 222 functions as an interlayer insulating film and a planarizing film, similar to insulator 322, for example.

[0471] Furthermore, the insulators 220 and 222 are provided with multiple openings. These openings are formed in regions superimposed on the source and drain of the transistor 200, and in regions superimposed on the conductor 376. Of the multiple openings, the conductor 228 is formed in the openings superimposed on the source and drain of the transistor 200. Of the remaining openings, the insulator 214 is formed on the side surface of the openings superimposed on the conductor 376, and the conductor 216 is formed in the remaining openings. In particular, the conductor 216 is sometimes called a TSV (Through Silicon Via).

[0472] For example, the conductor 216 or conductor 228 can be made of a material that can be used for conductor 328. In particular, it is preferable that conductor 216 is made of the same material as conductor 376.

[0473] The insulator 214 has the function of electrically insulating the substrate 210 from the conductor 216, for example. It is preferable to use a material as the insulator 214 that is applicable to the insulators 320 and 324.

[0474] The insulator 380 and conductor 376 formed on the substrate 310 and the insulator 202 and conductor 216 formed on the substrate 210 are joined together, for example, by a bonding process.

[0475] As a preliminary step before the bonding process, for example, a planarization process is performed on the substrate 310 side to make the surface heights of the insulator 380 and the conductor 376 the same. Similarly, a planarization process is performed on the substrate 210 side to make the surface heights of the insulator 202 and the conductor 216 the same.

[0476] In the bonding process, when joining insulator 380 and insulator 202, that is, joining insulating layers, a hydrophilic bonding method can be used. This method involves first providing high flatness through polishing, then bringing the surfaces that have been hydrophilically treated with oxygen plasma or the like into contact for temporary bonding, followed by dehydration through heat treatment to perform the final bonding. Since the hydrophilic bonding method also involves bonding at the atomic level, a mechanically superior bond can be obtained.

[0477] Furthermore, when joining conductor 376 and conductor 216, that is, joining conductors to conductors, a surface activation bonding method can be used, in which the oxide film and adsorbed impurity layer on the surface are removed by sputtering or other methods, and the cleaned and activated surfaces are brought into contact for bonding. Alternatively, a diffusion bonding method can be used, which uses a combination of temperature and pressure to bond the surfaces. In both cases, bonding occurs at the atomic level, resulting in a bond that is excellent not only electrically but also mechanically.

[0478] By performing the bonding process described above, the conductor 376 on the substrate 310 can be electrically connected to the conductor 216 on the substrate 210. Furthermore, a mechanically strong connection can be obtained between the insulator 380 on the substrate 310 and the insulator 202 on the substrate 210.

[0479] When bonding substrate 310 and substrate 210, insulating layers and metal layers are present on each bonding surface. For example, a combination of surface activation bonding and hydrophilic bonding methods can be used. For instance, a method can be used in which the surface is cleaned after polishing, an anti-oxidation treatment is applied to the surface of the metal layer, and then a hydrophilic treatment is performed before bonding. Alternatively, the surface of the metal layer may be made of a metal that is difficult to oxidize, such as gold, and then a hydrophilic treatment may be performed.

[0480] Furthermore, a bonding method other than the one described above may be used to bond substrate 310 and substrate 210. For example, flip-chip bonding may be used as a method for bonding substrate 310 and substrate 210. When using flip-chip bonding, connection terminals such as bumps may be provided above the conductor 376 on substrate 310, or below the conductor 216 on substrate 210. Examples of flip-chip bonding include a method in which a resin containing anisotropic conductive particles is injected between insulator 380 and insulator 202, and between conductor 376 and conductor 216 to bond them, and a method using silver-tin solder to bond them. Alternatively, if the bumps and the conductors connected to the bumps are made of gold, ultrasonic bonding can be used. In addition, in order to reduce physical stress such as impact and thermal stress, an underfill agent may be injected between insulator 380 and insulator 202, and between conductor 376 and conductor 216, in addition to the flip-chip bonding method described above. Alternatively, for example, a die bonding film may be used to bond substrate 310 and substrate 210.

[0481] Insulator 224 and insulator 226 are stacked in order on insulator 222, insulator 214, conductor 216, and conductor 228, respectively.

[0482] The insulator 224, like the insulator 324, is preferably a barrier insulating film that prevents impurities such as water and hydrogen from diffusing into the region above the insulator 224. Therefore, it is preferable to use a material for the insulator 224 that can be used for the insulator 324.

[0483] The insulator 226 is preferably an interlayer film with a low dielectric constant, similar to the insulator 326. Therefore, it is preferable to use a material for the insulator 226 that can be used for the insulator 326, for example.

[0484] Furthermore, insulators 224 and 226 have a conductor 230 embedded in them that is electrically connected to the transistor 200, light-emitting device 150, etc. The conductor 230 functions as a plug or wiring. For example, the conductor 230 can be made of a material that can be applied to conductors 328, conductor 330, etc.

[0485] Insulator 250, insulator 111a, and insulator 111b are stacked in that order on insulator 224 and insulator 226.

[0486] It is preferable that the insulator 250, like the insulator 324, is an insulator that has barrier properties against impurities such as water and hydrogen. Therefore, as the insulator 250, for example, a material that can be applied to the insulator 324 can be used.

[0487] Various inorganic insulating films such as oxide insulating films, nitride insulating films, oxidative nitride insulating films, and nitride oxide insulating films can be suitably used as insulators 111a and 111b, respectively. For example, it is preferable to use an oxide insulating film or oxidative nitride insulating film such as a silicon oxide film, a silicon oxidative nitride film, or an aluminum oxide film for insulator 111a. For example, it is preferable to use a nitride insulating film such as a silicon nitride film or a silicon nitride oxide film for insulator 111b. Also, for example, it is preferable to use a nitride oxide insulating film for insulator 111b. More specifically, it is preferable to use a silicon oxide film as insulator 111a and a silicon nitride film as insulator 111b. It is preferable that insulator 111b has the function of an etching protective film. Alternatively, a nitride insulating film or nitride oxide insulating film may be used as insulator 111a and an oxide insulating film or oxidative nitride insulating film may be used as insulator 111b. In this embodiment, an example is shown in which a recess is provided in insulator 111b, but it is not necessary for insulator 111b to have a recess.

[0488] Furthermore, openings are formed in the regions of the insulator 250, insulator 111a, and insulator 111b that overlap with a portion of the conductor 230, and the conductor 121 is provided to fill these openings. In this specification, the conductors 121a and 121b shown in Figure 17 are collectively referred to as conductor 121. The conductor 121 can be provided using the same material as conductors 328 and 330.

[0489] Furthermore, the pixel electrode described in this embodiment includes, for example, a material that reflects visible light, and the counter electrode includes a material that transmits visible light.

[0490] The display device 100 is a top-emission type. The light emitted by the light-emitting device is emitted towards the substrate 102. It is preferable to use a material with high transparency to visible light for the substrate 102.

[0491] A light-emitting device 150a is provided above the conductor 121a, and a light-emitting device 150b is provided above the conductor 121b.

[0492] Here, we will describe the light-emitting device 150a and the light-emitting device 150b.

[0493] The light-emitting device described in this embodiment refers to a self-emissive light-emitting device such as an organic light-emitting element (also called an OLED (Organic Light Emitting Diode)). The light-emitting device electrically connected to the pixel circuit can be a self-emissive light-emitting device such as an LED (Light Emitting Diode), microLED, QLED (Quantum-dot Light Emitting Diode), or semiconductor laser.

[0494] Conductors 122a and 122b can be formed, for example, by depositing a conductive film on an insulator 111b, a conductor 121a, or a conductor 121b, and then applying photolithography or electron beam lithography to the conductive film.

[0495] Each of the conductors 122a and 122b functions, for example, as an anode for the light-emitting devices 150a and 150b provided by the display device 100.

[0496] For example, indium tin oxide (sometimes called ITO) can be used as the conductor 122a and conductor 122b.

[0497] Furthermore, the conductor 122a and conductor 122b may each be a laminated structure of two or more layers, rather than a single layer. For example, the first layer of the conductor may be a conductor with high reflectivity to visible light, and the top layer of the conductor may be a conductor with high light transmittance. Examples of conductors with high reflectivity to visible light include silver, aluminum, or an alloy film of silver (Ag), palladium (Pd), and copper (Cu) (Ag-Pd-Cu(APC) film). Examples of conductors with high light transmittance include the indium tin oxide mentioned above. In addition, for conductors 122a and conductor 122b, for example, a laminated film of aluminum sandwiched between a pair of titanium (a laminated film in the order of Ti, Al, Ti), or a laminated film of silver sandwiched between a pair of indium tin oxide (a laminated film in the order of ITO, Ag, ITO) may be used.

[0498] An EL layer 141a is provided on the conductor 122a. Furthermore, an EL layer 141b is provided on the conductor 122b.

[0499] By the way, it is preferable that each of the EL layers 141a and 141b has an emissive layer that emits light of a different color. For example, EL layer 141a may have an emissive layer that emits light of one of the following colors: red (R), green (G), and blue (B), and EL layer 141b may have an emissive layer that emits light of one of the remaining two colors. Also, although not shown in Figure 17, if an EL layer different from EL layers 141a and 141b is provided, this EL layer may have an emissive layer that emits light of the remaining color. Thus, the display device 100 may have a structure (SBS structure) in which different emissive layers for each color are formed on a plurality of pixel electrodes (conductors 121a and 121b in Figure 17).

[0500] The combination of colors emitted by the light-emitting layers contained in the EL layer 141a and the EL layer 141b is not limited to those described above; for example, cyan, magenta, and yellow may also be used. Furthermore, although the above example shows three colors, the number of colors emitted by the light-emitting device 150 in the display device 100 may be two, three, or four or more.

[0501] Each EL layer 141a and EL layer 141b may have, in addition to a layer containing a light-emitting organic compound (light-emitting layer), one or more of the following: an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.

[0502] Furthermore, the EL layer 141a and EL layer 141b can be formed by methods such as vapor deposition (vacuum deposition, etc.), coating (e.g., dip coating, die coating, bar coating, spin coating, and spray coating), and printing (e.g., inkjet printing, screen printing, offset printing, flexographic printing, gravure printing, and microcontact printing).

[0503] Furthermore, when applying the above coating method and printing method as the film formation method, the material to be formed can be, for example, a polymer compound (e.g., oligomers, dendrimers, and polymers), a medium-molecular-weight compound (a compound in the intermediate region between low-molecular-weight and high-molecular-weight compounds: molecular weight 400 to 4000), or an inorganic compound (e.g., a quantum dot material). Furthermore, the quantum dot material can be a colloidal quantum dot material, an alloy-type quantum dot material, a core-shell type quantum dot material, or a core-type quantum dot material.

[0504] For example, the light-emitting devices 150a and 150b in Figure 17 can be composed of multiple layers, such as a light-emitting layer 4411 and a layer 4430, as shown in the light-emitting device 150 in Figure 18A.

[0505] Layer 4420 may include, for example, a layer containing a material with high electron injection properties (electron injection layer) and a layer containing a material with high electron transport properties (electron transport layer). The light-emitting layer 4411 may include, for example, a light-emitting compound. Layer 4430 may include, for example, a layer containing a material with high hole injection properties (hole injection layer) and a layer containing a material with high hole transport properties (hole transport layer).

[0506] A configuration having a layer 4420, a light-emitting layer 4411, and a layer 4430 provided between a pair of electrodes (conductor 121 and conductor 122, which will be described later) can function as a single light-emitting unit, and in this specification, the configuration shown in Figure 18A is referred to as a single structure.

[0507] Furthermore, Figure 18B shows a modified example of the EL layer 141 of the light-emitting device 150 shown in Figure 18A. Specifically, the light-emitting device 150 shown in Figure 18B has a layer 4430-1 on a conductor 121, a layer 4430-2 on layer 4430-1, a light-emitting layer 4411 on layer 4430-2, a layer 4420-1 on the light-emitting layer 4411, a layer 4420-2 on layer 4420-1, and a conductor 122 on layer 4420-2. For example, when the conductor 121 is the anode and the conductor 122 is the cathode, layer 4430-1 functions as a hole injection layer, layer 4430-2 functions as a hole transport layer, layer 4420-1 functions as an electron transport layer, and layer 4420-2 functions as an electron injection layer. Alternatively, when conductor 121 is used as the cathode and conductor 122 as the anode, layer 4430-1 functions as an electron injection layer, layer 4430-2 functions as an electron transport layer, layer 4420-1 functions as a hole transport layer, and layer 4420-2 functions as a hole injection layer. By using such a layer structure, it is possible to efficiently inject carriers into the light-emitting layer 4411 and increase the efficiency of carrier recombination within the light-emitting layer 4411.

[0508] Furthermore, as shown in Figure 18C, a configuration in which multiple light-emitting layers (light-emitting layer 4411, light-emitting layer 4412, and light-emitting layer 4413) are provided between layer 4420 and layer 4430 is also a variation of the single structure.

[0509] Furthermore, a laminate having multiple layers such as layer 4420, light-emitting layer 4411, and layer 4430 may be referred to as a light-emitting unit. Multiple light-emitting units can be connected in series via an intermediate layer (charge generation layer). Specifically, as shown in Figure 18D, multiple light-emitting units, such as light-emitting unit 4400a and light-emitting unit 4400b, can be connected in series via an intermediate layer (charge generation layer) 4440. In this specification, such a structure is referred to as a tandem structure. In this specification and elsewhere, a tandem structure may also be referred to as a stack structure, for example. By using a tandem structure for a light-emitting device, a high-brightness light-emitting device can be created. Furthermore, using a tandem structure for a light-emitting device can be expected to improve the luminous efficiency and lifespan of the light-emitting device. When the light-emitting device 150 of the display device 100 in Figure 17 is in a tandem structure, the EL layer 141 can be configured to include, for example, layer 4420, light-emitting layer 4411 and layer 4430 of the light-emitting unit 4400a, an intermediate layer 4440, and layer 4420, light-emitting layer 4412 and layer 4430 of the light-emitting unit 4400b.

[0510] Furthermore, when displaying white light, the SBS structure described earlier can consume less power than the single and tandem structures mentioned above. Therefore, if you want to keep power consumption low, the SBS structure is preferable. On the other hand, the single and tandem structures are preferable because their manufacturing process is simpler than that of the SBS structure, which can lower manufacturing costs or increase manufacturing yield.

[0511] The light-emitting color of the light-emitting device 150 can be red, green, blue, cyan, magenta, yellow, or white, depending on the material constituting the EL layer 141. Furthermore, the color purity can be further enhanced by adding a microcavity structure to the light-emitting device 150.

[0512] A light-emitting device that emits white light preferably has a configuration that includes two or more types of light-emitting materials in the light-emitting layer. To obtain white light emission, for example, two light-emitting materials can be selected such that the light emitted by each of the two materials is complementary in color. Alternatively, to obtain white light emission, for example, one light-emitting color selected from three or more light-emitting materials can be selected such that the combined light-emitting color of the remaining light-emitting materials is complementary in color.

[0513] The light-emitting layer preferably contains two or more types of light-emitting materials that emit light such as R (red), G (green), B (blue), Y (yellow), and O (orange). Alternatively, it is preferable to have two or more types of light-emitting materials, and for each light-emitting material, the emission of light contains spectral components of two or more colors from R, G, and B.

[0514] Furthermore, as shown in Figure 17, a gap is provided between the two EL layers in adjacent light-emitting devices. Specifically, in Figure 17, a recess is formed between adjacent light-emitting devices, and an insulator 112 is provided to cover the sides of the recess (the sides of conductor 121a, conductor 122a, and EL layer 141a, and the sides of conductor 121b, conductor 122b, and EL layer 141b) and the bottom surface (a part of the insulator 111b). In addition, an insulator 162 is formed on the insulator 112 so as to fill the recess. In this way, it is preferable that the EL layers 141a and 141b are provided so as not to be in contact with each other. This effectively prevents current (also called lateral leakage current or side leakage current) from flowing through the two adjacent EL layers and causing unintended light emission (also called crosstalk). As a result, contrast can be increased, and a display device with high display quality can be realized. Furthermore, for example, by creating a configuration with extremely low lateral leakage current between light-emitting devices, the black display performed by the display device can be made to be a display with virtually no light leakage (also known as a true black display).

[0515] One method for forming the EL layer 141a and EL layer 141b is to use photolithography. For example, an EL film that will become the EL layer 141a and EL layer 141b can be deposited on the conductor 122, and then the EL film can be patterned using photolithography to form the EL layer 141a and EL layer 141b. This also makes it possible to create a gap between the two EL layers in adjacent light-emitting devices.

[0516] The insulator 112 can be an insulating layer having an inorganic material. For example, inorganic insulating films such as oxide insulating films, nitride insulating films, oxidative nitride insulating films, or nitride oxide insulating films can be used for the insulator 112. The insulator 112 may be a single layer or a multilayer structure. Examples of oxide insulating films include silicon oxide films, aluminum oxide films, magnesium oxide films, indium gallium zinc oxide films, gallium oxide films, germanium oxide films, yttrium oxide films, zirconium oxide films, lanthanum oxide films, neodymium oxide films, hafnium oxide films, and tantalum oxide films. Examples of nitride insulating films include silicon nitride films and aluminum nitride films. Examples of oxidative nitride insulating films include silicon oxidative nitride films and aluminum oxidative nitride films. Examples of nitride oxide insulating films include silicon nitride film and aluminum nitride film. In particular, aluminum oxide films are preferred because they have a high selectivity ratio with the EL layer in the etching process and have the function of protecting the EL layer in the formation of the insulator 162 described later. In particular, by applying an inorganic insulating film such as an aluminum oxide film, a hafnium oxide film, or a silicon oxide film formed by the ALD (Atomic Layer Deposition) method to the insulator 112, it is possible to form an insulator 112 with fewer pinholes and excellent function in protecting the EL layer.

[0517] In this specification, the term "oxide-nitride" refers to a material in which the oxygen content is greater than the nitrogen content, and the term "nitride oxide" refers to a material in which the nitrogen content is greater than the oxygen content. For example, when "silicon oxynitride" is written, it refers to a material in which the oxygen content is greater than the nitrogen content, and when "silicon nitride oxide" is written, it refers to a material in which the nitrogen content is greater than the oxygen content.

[0518] The insulator 112 can be formed using sputtering, CVD, PLD, or ALD. It is preferable to form the insulator 112 using the ALD method, which provides good coverage.

[0519] The insulator 162 provided on the insulator 112 has the function of flattening the recess in the insulator 112 formed between adjacent light-emitting devices. In other words, the presence of the insulator 162 has the effect of improving the flatness of the surface on which the conductor 123, described later, is formed. The insulator 162 can preferably be an insulating layer having an organic material. For example, the insulator 162 can be made of acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimidoamide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins. Alternatively, the insulator 162 may be made of organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin. Furthermore, the insulator 162 can be made of, for example, a photosensitive resin. For example, a photoresist may be used as the photosensitive resin. For the photosensitive resin, for example, a positive-type material or a negative-type material can be used.

[0520] The difference between the height of the upper surface of the insulator 162 and the height of the upper surface of the EL layer 141a or EL layer 141b is preferably 0.5 times or less the thickness of the insulator 162, and more preferably 0.3 times or less. Alternatively, the insulator 162 may be provided such that the upper surface of the EL layer 141a or EL layer 141b is higher than the upper surface of the insulator 162. Alternatively, the insulator 162 may be provided such that the upper surface of the insulator 162 is higher than the upper surface of the light-emitting layer of the EL layer 141a or EL layer 141b.

[0521] Conductors 123 are provided on the EL layer 141a, the EL layer 141b, the insulator 112, and the insulator 162. In addition, insulators 113 are provided on the light-emitting device 150a and the light-emitting device 150b, respectively.

[0522] The conductor 123 functions, for example, as a common electrode for the light-emitting device 150a and the light-emitting device 150b. Furthermore, in order to emit light from the light-emitting device 150 upwards onto the display device 100, it is preferable that the conductor 122 be made of a light-transmitting conductive material.

[0523] The conductor 123 is preferably a material that has high conductivity and is also translucent and reflective (sometimes called a semi-transparent / semi-reflective electrode). For the conductor 122, for example, an alloy of silver and magnesium or indium tin oxide can be used.

[0524] The insulator 113 may be referred to as a protective layer, and by providing the insulator 113 above the light-emitting devices 150a and 150b, the reliability of the light-emitting devices can be improved. In other words, the insulator 113 functions as a passivation film that protects the light-emitting devices 150a and 150b. Therefore, it is preferable that the insulator 113 is made of a material that prevents the ingress of water and other substances. For example, the insulator 113 can be made of a material that is applicable to the insulator 111a or the insulator 111b. Specifically, for example, the insulator 113 can be made of aluminum oxide, silicon nitride, or silicon oxide nitride.

[0525] A resin layer 163 is provided on the insulator 113. A substrate 102 is provided on the resin layer 163.

[0526] For the substrate 102, it is preferable to use a translucent substrate, for example. By using a translucent substrate for the substrate 102, the light emitted by the light-emitting devices 150a and 150b can be emitted upwards from the substrate 102.

[0527] It should be noted that the display device according to one aspect of the present invention is not limited to the configuration of the display device 100 shown in Figure 17. The configuration of the display device according to one aspect of the present invention may be modified as appropriate, as long as it is within the scope of solving the problem.

[0528] For example, the transistor 200 included in the pixel layer PXAL of the display device 100 in Figure 17 may be a transistor having a metal oxide in the channel formation region (hereinafter referred to as an OS transistor). The display device 100 shown in Figure 19 has a configuration in which a transistor 500 (OS transistor) that replaces transistor 200 and a light-emitting device 150 are provided above the circuit layer SICL and wiring layer LINL of the display device 100 in Figure 17.

[0529] In Figure 19, the transistor 500 is provided on the insulator 512. The insulator 512 is provided above the insulator 364 and the conductor 366, and it is preferable to use a material that has barrier properties against oxygen and hydrogen for the insulator 512. Specifically, for example, silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum oxide nitride, or aluminum nitride may be used for the insulator 512.

[0530] As an example of a film having barrier properties against hydrogen, silicon nitride formed by the CVD method can be used. However, when hydrogen diffuses into a semiconductor element having an oxide semiconductor, such as transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between transistor 500 and transistor 300. Specifically, a film that suppresses hydrogen diffusion is a film that has a low rate of hydrogen desorption.

[0531] Furthermore, for example, the same material as the insulator 320 can be used for the insulator 512. Also, by applying materials with relatively low dielectric constants to these insulators, parasitic capacitance between wiring can be reduced. For example, a silicon oxide film or a silicon oxynitride film can be used for the insulator 512.

[0532] Furthermore, an insulator 514 is provided on the insulator 512, and a transistor 500 is provided on the insulator 514. In addition, an insulator 576 is formed on the insulator 512 so as to cover the transistor 500. Above the insulator 576, an insulator 581 is provided to cover the insulator 576.

[0533] It is preferable to use a film for the insulator 514 that has barrier properties to prevent the diffusion of impurities such as water and hydrogen from the substrate 310 or the region below the insulator 512 where circuit elements are provided, to the region where the transistor 500 is provided. Therefore, for example, silicon nitride formed by the CVD method can be used for the insulator 514.

[0534] As described above, the transistor 500 shown in Figure 19 is an OS transistor that includes a metal oxide in its channel formation region. Examples of metal oxides that can be used include In-M-Zn oxide (where element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium) containing indium, element M, and zinc. Specifically, for example, an oxide containing indium, gallium, and zinc (sometimes referred to as IGZO) may be used as the metal oxide. Alternatively, for example, an oxide containing indium, aluminum, and zinc (sometimes referred to as IAZO) may be used as the metal oxide. Furthermore, for example, an oxide containing indium, aluminum, gallium, and zinc (sometimes referred to as IAGZO) may be used as the metal oxide. In addition to the above, metal oxides such as In-Ga oxide, In-Zn oxide, and indium oxide may also be used.

[0535] In particular, it is preferable to use a metal oxide that functions as a semiconductor and has a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a large band gap in this way, the off-current of the transistor can be reduced.

[0536] In particular, it is preferable to use an OS transistor, for example, an OS transistor, as the drive transistor included in the pixel circuit, which has a sufficiently small off-current even when the source-drain voltage is large. By using an OS transistor as the drive transistor, the amount of off-current flowing to the light-emitting device when the drive transistor is in the off state can be reduced, so that the brightness of the light emitted by the light-emitting device through which the off-current flows can be sufficiently low. Therefore, when comparing a drive transistor with a large off-current and a drive transistor with a small off-current, when black is displayed in the pixel circuit, the light emission brightness of the pixel circuit with a drive transistor with a small off-current can be lower than that of the pixel circuit with a drive transistor with a large off-current. In other words, by using an OS transistor, black level distortion when black is displayed in the pixel circuit can be suppressed.

[0537] Furthermore, the off-current value of an OS transistor per 1 μm channel width at room temperature is 1 aA (1 × 10⁻¹⁰). -18 A) Below, 1zA(1×10 -21 A) Less than or equal to 1yA(1×10 -24 A) It can be less than or equal to the following. Note that the off-current value of a Si transistor per 1 μm of channel width at room temperature is 1 fA (1 × 10⁻¹⁰). -15 A) More than 1pA (1×10 -12 A) The answer is as follows. Therefore, it can be said that the off-current of an OS transistor is about 10 orders of magnitude lower than that of a Si transistor.

[0538] Furthermore, to increase the luminescence brightness of the light-emitting device included in the pixel circuit, it is necessary to increase the amount of current flowing through the light-emitting device. In addition, to achieve this, it is necessary to increase the source-drain voltage of the drive transistor included in the pixel circuit. Compared to Si transistors, OS transistors have higher breakdown voltage between the source and drain, so a high voltage can be applied to the source-drain of an OS transistor. As a result, by using an OS transistor as the drive transistor included in the pixel circuit, a high voltage can be applied to the source-drain of the OS transistor, thereby increasing the amount of current flowing through the light-emitting device and increasing the luminescence brightness of the light-emitting device.

[0539] Furthermore, when the transistor operates in the saturation region, OS transistors exhibit smaller changes in source-drain current in response to changes in gate-source voltage compared to Si transistors. Therefore, by using OS transistors as driving transistors in the pixel circuit, the current flowing between the source and drain can be precisely controlled by changes in gate-source voltage, allowing for precise control of the current flowing to the light-emitting device. This enables precise control of the light-emitting brightness (allowing for greater gradation in the pixel circuit).

[0540] Furthermore, in terms of the saturation characteristics of the current flowing when a transistor operates in the saturation region, OS transistors can supply a more stable constant current (saturation current) than Si transistors, even as the source-drain voltage gradually increases. Therefore, by using OS transistors as driving transistors, for example, even if there are variations in the current-voltage characteristics of a light-emitting device containing EL material, a stable constant current can be supplied to the light-emitting device. In other words, when operating in the saturation region, the source-drain current remains almost unchanged even when the source-drain voltage is increased, thus stabilizing the luminescence brightness of the light-emitting device.

[0541] As described above, by using OS transistors in the drive transistors included in the pixel circuit, it is possible to achieve "suppression of black level floating," "increase in luminescence brightness," "multi-gradation," and "suppression of variations in light-emitting devices." As a result, the display device including the pixel circuit can display clear and smooth images, and as a result, one or more of the following can be observed: image sharpness and / or a high contrast ratio. Note that image sharpness may refer to the suppression of motion blur and / or the suppression of black level floating. Furthermore, by configuring the drive transistors included in the pixel circuit to have an extremely low off-current, the black display performed by the display device can be a display with minimal light leakage (true black display).

[0542] It is preferable that one or both of insulator 576 and insulator 581 function as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from above to transistor 500. Therefore, it is preferable that at least one of insulator 576 and insulator 581 is made of an insulating material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (i.e., the above impurities do not easily permeate it). Alternatively, it is preferable to use an insulating material that has the function of suppressing the diffusion of oxygen (e.g., one or both of oxygen atoms and oxygen molecules) (i.e., the above oxygen does not easily permeate it).

[0543] Preferably, one or both of insulators 576 and 581 are insulators that have the function of suppressing the diffusion of impurities such as water and hydrogen, as well as oxygen. For example, one or more selected from aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium-gallium-zinc oxide, silicon nitride, and silicon nitride oxide can be used.

[0544] Furthermore, the insulator 581, the insulator 576, and one of the source or drain electrodes of the transistor 500 are provided with openings for forming a plug or wiring. In addition, a conductor 540 that functions as a plug or wiring is formed at the meeting portion.

[0545] Furthermore, it is preferable that the insulator 581 functions as an interlayer film and a planarization film, for example.

[0546] Insulator 224 and insulator 226 are formed above insulator 581 and conductor 540. For details regarding insulators, conductors, and circuit elements located above insulator 224, including insulator 224, please refer to the description of the display device 100 in Figure 17.

[0547] Figure 17 shows a display device constructed by bonding a semiconductor substrate on which a light-emitting device 150 and pixel circuits are formed with a semiconductor substrate on which a drive circuit is formed, and Figure 19 shows a display device on which a light-emitting device 150 and pixel circuits are formed on a semiconductor substrate on which a drive circuit is formed. However, a display device according to one embodiment of the present invention is not limited to Figure 17 or Figure 19. A display device according to one embodiment of the present invention may, for example, have a structure in which only one layer of transistors is formed, rather than a layer structure in which two or more layers of transistors are stacked.

[0548] Specifically, for example, a display device according to one aspect of the present invention may have a configuration including a circuit with a transistor 200 formed on a substrate 210 and a light-emitting device 150 provided above the transistor 200, as shown in the display device 100 in Figure 20A. Alternatively, for example, as shown in the display device 100 in Figure 20B, the display device may have a configuration including an insulator 512 formed on a substrate 501, a transistor 500 provided on the insulator 512, and a light-emitting device 150 provided above the transistor 500. As the substrate 501, for example, a substrate applicable to the substrate 310 can be used, and a glass substrate is particularly preferred.

[0549] A display device according to one aspect of the present invention may have a configuration in which only one layer of transistors is formed and a light-emitting device 150 is provided above the transistors, as shown in the display device 100 in Figures 20A and 20B, respectively. Although not shown, a display device according to one aspect of the present invention may have a layer structure in which three or more layers of transistors are formed.

[0550] <Example of sealing structure for display device> Next, we will describe the sealing structure of the light-emitting device 150 that can be applied to the display device 100 in Figure 17.

[0551] Figure 21A is a cross-sectional view showing an example of a sealing structure applicable to the display device 100 of Figure 17. Specifically, Figure 21A illustrates the end of the display device 100 of Figure 17 and the material provided around that end. Figure 21A also shows an excerpt of only a part of the pixel layer PXAL of the display device 100. Specifically, each part of Figure 21A illustrates an insulator 250, an insulator located above the insulator 250, a conductor, and a light-emitting device 150a.

[0552] Furthermore, an opening is provided in the region 123CM shown in Figure 21A, for example. A conductor 121CM is provided in this opening, for example. The conductor 123 is electrically connected to the wiring located below the insulator 250 via the conductor 121CM. This allows the conductor 123, which functions as a common electrode, to be supplied with potential (for example, the anode potential and cathode potential in the light-emitting device 150a, etc.). Note that the conductor included in region 123CM and / or the conductors surrounding region 123CM may be referred to as connecting electrodes.

[0553] Furthermore, as the conductor 121CM, for example, any material applicable to the conductor 121 can be used.

[0554] In the display device 100 shown in Figure 21A, an adhesive layer 164 is provided at or around the edge of the resin layer 163. Specifically, the display device 100 is configured such that the insulator 113 and the substrate 102 are bonded together via the adhesive layer 164.

[0555] The adhesive layer 164 is preferably made of a material that suppresses the permeation of impurities such as components of the outside air and moisture. Using such a material for the adhesive layer 164 can improve the reliability of the display device 100.

[0556] A structure in which an insulator 113 and a substrate 102 are bonded together via a resin layer 164 using an adhesive layer 164 is sometimes called a solid encapsulation structure. Furthermore, in a solid encapsulation structure, if the resin layer 163 has the same function as the adhesive layer 164 in bonding the insulator 113 and the substrate 102, the adhesive layer 164 does not necessarily need to be provided.

[0557] On the other hand, a structure in which an insulator 113 and a substrate 102 are bonded together using an adhesive layer 164, with an inert gas filling the resin layer 163 instead, is sometimes called a hollow-sealed structure (not shown). Examples of inert gases include nitrogen and argon.

[0558] Furthermore, in the sealing structure of the display device 100 shown in Figure 21A, two or more adhesive layers may be used in stacks. For example, as shown in Figure 21B, an additional adhesive layer 165 may be provided inside the adhesive layer 164 (between the adhesive layer 164 and the resin layer 163). By stacking two or more adhesive layers, the permeation of impurities such as moisture can be further suppressed, thereby increasing the reliability of the display device 100.

[0559] Furthermore, a desiccant may be mixed into the adhesive layer 165. This allows the moisture contained in the resin layer 163, insulator, conductor, and EL layer formed inside the adhesive layer 164 and adhesive layer 165 to be adsorbed by the desiccant, thereby improving the reliability of the display device 100.

[0560] Furthermore, although the display device 100 in Figure 21B shows a solid encapsulation structure, a hollow encapsulation structure may also be used.

[0561] Furthermore, in the sealing structure of the display device 100 shown in Figures 21A and 21B, an inert liquid may be filled instead of the resin layer 163. Examples of inert liquids include fluorine-based inert liquids.

[0562] Incidentally, one aspect of the present invention is not limited to the configuration described above, and the configuration can be appropriately modified depending on the situation. Below, examples of modifications to the display device 100 of Figure 17 will be explained using Figures 22A to 23B. Note that Figures 22A to 23B show only a portion of the pixel layer PXAL of the display device 100. Specifically, Figures 22A to 23B each show the insulator 250, the insulator 111a, and the insulator, conductor, light-emitting device 150a, and light-emitting device 150b located above the insulator 111a. In particular, Figures 22A to 23B also show the light-emitting device 150c, conductor 121c, conductor 122c, and EL layer 141c.

[0563] For example, the color of light emitted by the EL layer 141c may differ from the color of light emitted by the EL layers 141a and 141b. Also, for example, the configuration of the display device 100 may be such that the number of colors emitted by the light-emitting devices 150a to 150c is two. Also, for example, the configuration of the display device 100 may be such that the number of light-emitting devices 150 is increased so that the number of colors emitted by multiple light-emitting devices is four or more (not shown).

[0564] Furthermore, for example, the display device 100 may be configured such that an EL layer 142 is formed on EL layer 141a to EL layer 141c, as shown in Figure 22A. Specifically, for example, in Figure 18A, if EL layers 141a to EL layers 141c include layer 4430 and light-emitting layer 4411, then EL layer 142 may include layer 4420. In this case, layer 4420 included in EL layer 142 functions as a common layer for each of the light-emitting devices 150a to 150c. Similarly, for example, in Figure 18C, if EL layers 141a to EL layers 141c include layer 4430, light-emitting layer 4411, light-emitting layer 4412, and light-emitting layer 4413, then by configuring EL layer 142 to include layer 4420, layer 4420 included in EL layer 142 functions as a common layer for each of the light-emitting devices 150a to 150c. Furthermore, for example, in Figure 18D, if the EL layers 141a to 141c are configured to include layer 4430, light-emitting layer 4412, and layer 4420 of the light-emitting unit 4400b, an intermediate layer 4440, and layer 4430 and light-emitting layer 4411 of the light-emitting unit 4400a, then by configuring the EL layer 142 to include layer 4420 of the light-emitting unit 4400b, layer 4420 of the light-emitting unit 4400a included in the EL layer 142 functions as a common layer in each of the light-emitting devices 150a to 150c.

[0565] Furthermore, for example, the insulator 113 of the display device 100 may be a multilayer structure of two or more layers, rather than a single layer. The insulator 113 may be a three-layer multilayer structure, for example, with an inorganic insulator as the first layer, an organic insulator as the second layer, and an inorganic insulator as the third layer. Figure 22(B) shows a cross-sectional view of a part of the display device 100 in which the insulator 113, including insulators 113a, 113b, and 113c, is a multilayer structure, with insulator 113a being an inorganic insulator, insulator 113b being an organic insulator, and insulator 113c being an inorganic insulator.

[0566] Furthermore, for example, the configuration of the display device 100 may include a microcavity structure (micro-resonator structure) in each of the EL layers 141a to 141c. A microcavity structure refers to a structure in which, for example, a conductive material having light-transmitting and light-reflecting properties is used as the conductor 122 which is the upper electrode (common electrode), and a conductive material having light-reflecting properties is used as the conductor 121 which is the lower electrode (pixel electrode), and the distance between the lower surface of the light-emitting layer and the upper surface of the lower electrode, that is, the thickness of the layer 4430 in Figure 18A, is set to a thickness corresponding to the wavelength of the color of light emitted by the light-emitting layer contained in the EL layer 141.

[0567] For example, the light reflected back by the lower electrode (reflected light) interferes significantly with the light that directly enters the upper electrode from the light-emitting layer (incident light). Therefore, it is preferable to adjust the optical distance between the lower electrode and the light-emitting layer to (2n-1)λ / 4 (where n is a natural number greater than or equal to 1, and λ is the wavelength of the light emission to be amplified). By adjusting this optical distance, the phases of the reflected light and the incident light of wavelength λ can be matched, and the light emission from the light-emitting layer can be further amplified. On the other hand, if the reflected light and the incident light have wavelengths other than λ, the phases will not match, and the light will attenuate without resonance.

[0568] In the above configuration, the EL layer may have a structure with multiple light-emitting layers or a structure with a single light-emitting layer. Furthermore, for example, the configuration of the tandem-type light-emitting device described above may be combined with a microcavity structure.

[0569] By incorporating a microcavity structure, it becomes possible to enhance the emission intensity in the front direction at specific wavelengths, thereby reducing power consumption. In particular, in the case of XR devices such as VR and AR, the light from the front direction of the light-emitting device often enters the eyes of the user wearing the device, so it is preferable to provide a microcavity structure in the display device of an XR device. Furthermore, in the case of a display device that displays images using four sub-pixels of red, yellow, green, and blue, in addition to the brightness enhancement effect of yellow emission, it is possible to apply a microcavity structure matched to the wavelength of each color to all sub-pixels, resulting in a display device with excellent characteristics.

[0570] Figure 23A shows a partial cross-sectional view of the display device 100 when a microcavity structure is provided as an example. Furthermore, if the light-emitting device 150a has a light-emitting layer that emits blue (B) light, the light-emitting device 150b has a light-emitting layer that emits green (G) light, and the light-emitting device 150c has a light-emitting layer that emits red (R) light, it is preferable to increase the film thickness in the order of EL layer 141a, EL layer 141b, and EL layer 141c, as shown in Figure 23A. Specifically, the film thickness of the layer 4430 contained in each of the EL layers 141a, EL layer 141b, and EL layer 141c should be determined according to the color of light emitted by each light-emitting layer. In this case, the layer 4430 contained in EL layer 141a will be the thinnest, and the layer 4430 contained in EL layer 141c will be the thickest.

[0571] Furthermore, the configuration of the display device 100 may include, for example, a colored layer (color filter). Figure 23B shows, as an example, a configuration in which a colored layer 166a, a colored layer 166b, and a colored layer 166c are included between the resin layer 163 and the substrate 102. The colored layers 166a to 166c can be formed on the substrate 102, for example. Also, if the light-emitting device 150a has a light-emitting layer that emits blue (B) light, the light-emitting device 150b has a light-emitting layer that emits green (G) light, and the light-emitting device 150c has a light-emitting layer that emits red (R) light, then the colored layer 166a is blue, the colored layer 166b is green, and the colored layer 166c is red.

[0572] The display device 100 shown in Figure 23B can be constructed by bonding a substrate 102, on which colored layers 166a to 166c are provided, to a substrate 310 on which light-emitting devices 150a to 150c are formed, via a resin layer 163. In this case, it is preferable to bond the substrates so that light-emitting device 150a and colored layer 166a overlap, light-emitting device 150b and colored layer 166b overlap, and light-emitting device 150c and colored layer 166c overlap. By providing colored layers 166a to 166c in the display device 100, for example, the light emitted by light-emitting device 150b is not emitted upwards on the substrate 102 via colored layer 166a or colored layer 166c, but is emitted upwards on the substrate 102 via colored layer 166b. In other words, since it is possible to block light from the light-emitting device 150 of the display device 100 in an oblique direction (the direction of the elevation angle when the upper surface of the substrate 102 is considered a horizontal plane), the dependence of the display device 100 on the viewing angle can be reduced, and a decrease in the display quality of the image displayed on the display device 100 when viewed from an oblique angle can be prevented.

[0573] Furthermore, the colored layers 166a to 166c formed on the substrate 102 may be covered with a resin called an overcoat layer. Specifically, the display device 100 may be laminated in the following order: resin layer 163, the overcoat layer, colored layers 166a to 166c, and substrate 102 (not shown). Examples of resins used for the overcoat layer include translucent thermosetting materials based on acrylic resin or epoxy resin.

[0574] Furthermore, for example, the configuration of the display device 100 may include a black matrix in addition to the colored layers (not shown). By providing a black matrix between the colored layers 166a and 166b, between the colored layers 166b and 166c, and between the colored layers 166c and 166a, it is possible to better block light from the light-emitting device 150 of the display device 100 in the oblique direction (the direction of the elevation angle when the upper surface of the substrate 102 is considered a horizontal plane), thereby better preventing a decrease in the display quality of the image displayed on the display device 100 when viewed from an oblique angle.

[0575] Furthermore, as shown in Figure 23B, if the display device has a colored layer, the light-emitting devices 150a to 150c provided in the display device may all be light-emitting devices that emit white light (not shown). In addition, the light-emitting devices can be, for example, a single structure or a tandem structure.

[0576] Furthermore, although the above-described configuration of the display device 100 uses conductors 121a to 121c as anodes and conductor 122 as a cathode, the display device 100 may also be configured with conductors 121a to 121c as cathodes and conductor 122 as an anode. In other words, in the manufacturing process described above, the stacking order of the hole injection layer, hole transport layer, light-emitting layer, electron transport layer, and electron injection layer contained in EL layers 141a to 141c and EL layer 142 may be reversed.

[0577] <Example of the structure of insulator 162> Next, the cross-sectional structure of the region including the insulator 162 and its surroundings in the display device 100 is shown.

[0578] Figure 24A shows an example where the thicknesses of EL layer 141a and EL layer 141b are different. The height of the upper surface of insulator 112 is the same as or approximately the same as the height of the upper surface of EL layer 141a on the EL layer 141a side, and the height of the upper surface of EL layer 141b on the EL layer 141b side. Furthermore, the upper surface of insulator 112 has a gentle slope, with the EL layer 141a side being higher and the EL layer 141b side being lower. Thus, it is preferable that the heights of insulator 112 and insulator 162 are the same as the heights of the upper surfaces of adjacent EL layers. Alternatively, the upper surface may have a flat portion, with the height being the same as the height of the upper surface of either of the adjacent EL layers.

[0579] In Figure 24B, the upper surface of the insulator 162 has a region that is higher than the upper surfaces of the EL layer 141a and the EL layer 141b. Furthermore, the upper surface of the insulator 162 has a shape that is convex and gently bulges towards the center.

[0580] In Figure 24C, the upper surface of the insulator 112 has a region that is higher than the upper surfaces of the EL layer 141a and the EL layer 141b. In addition, in the region including the insulator 162 and its periphery, the display device 100 has a first region located above at least one of the sacrificial layer 118 and the sacrificial layer 119. The first region is higher than the upper surfaces of the EL layer 141a and the EL layer 141b, and a portion of the insulator 162 is formed in the first region. In addition, in the region including the insulator 162 and its periphery, the display device 100 has a second region located above at least one of the sacrificial layer 118 and the sacrificial layer 119. The second region is higher than the upper surfaces of the EL layer 141a and the EL layer 141b, and a portion of the insulator 162 is formed in the second region.

[0581] In Figure 24D, the upper surface of the insulator 162 has a region that is lower than the upper surfaces of the EL layer 141a and the EL layer 141b. Furthermore, the upper surface of the insulator 162 has a gently concave shape that slopes toward the center.

[0582] In Figure 24E, the upper surface of the insulator 112 has a region that is higher than the upper surfaces of the EL layer 141a and the EL layer 141b. That is, on the surface where the EL layer 141 is formed, the insulator 112 protrudes, forming a convex portion.

[0583] In forming the insulator 112, for example, if the insulator 112 is formed to match or approximately match the height of the sacrificial layer, a protruding shape of the insulator 112 may be formed, as shown in Figure 24E.

[0584] In Figure 24F, the upper surface of the insulator 112 has a region that is lower than the upper surfaces of the EL layer 141a and the EL layer 141b. That is, the insulator 112 forms a recess on the surface on which the EL layer 141 is formed.

[0585] Thus, the insulators 112 and 162 can be made into various shapes.

[0586] <Example of pixel circuit configuration> Here, we will describe an example of a pixel circuit configuration that can be provided in the pixel layer PXAL.

[0587] Figures 25A and 25B show examples of pixel circuit configurations that can be provided in the pixel layer PXAL, and light-emitting devices 150 connected to the pixel circuit. Figure 25A is a diagram showing the connections of each circuit element included in the pixel circuit 400 provided in the pixel layer PXAL, and Figure 25B is a diagram schematically showing the hierarchical relationship of the circuit layer SICL, which includes the drive circuit 30, the layer OSL, which includes multiple transistors of the pixel circuit, and the layer EML, which includes the light-emitting device 150. The pixel layer PXAL of the display device 100 shown in Figure 25B includes, as an example, the layer OSL and the layer EML. Transistors 500A, 500B, and 500C included in the layer OSL shown in Figure 25B correspond to transistor 200 in Figure 17. The light-emitting device 150 included in the layer EML shown in Figure 25B corresponds to light-emitting device 150a or light-emitting device 150b in Figure 17.

[0588] The pixel circuit 400 shown as an example in Figures 25A and 25B comprises transistors 500A, 500B, 500C, and capacitor 600. Transistors 500A, 500B, and 500C can be transistors applicable to the transistor 200 described above, for example. That is, transistors 500A, 500B, and 500C can be Si transistors. Alternatively, transistors 500A, 500B, and 500C can be transistors applicable to the transistor 500 described above, for example. That is, transistors 500A, 500B, and 500C can be OS transistors. In particular, when transistors 500A, 500B, and 500C are OS transistors, it is preferable that each of transistors 500A, 500B, and 500C is equipped with a back gate electrode. In this case, the back gate electrode can be configured to receive the same signal as the gate electrode, or to receive a different signal from the gate electrode. Although Figures 25A and 25B show back gate electrodes for transistors 500A, 500B, and 500C, transistors 500A, 500B, and 500C may be configured without back gate electrodes.

[0589] Transistor 500B comprises a gate electrode electrically connected to transistor 500A, a first electrode electrically connected to light-emitting device 150, and a second electrode electrically connected to wiring ANO. Wiring ANO is a wire that provides a potential for supplying current to light-emitting device 150.

[0590] Transistor 500A comprises a first terminal electrically connected to the gate electrode of transistor 500B, a second terminal electrically connected to wiring SL which functions as a source line, and a gate electrode that has the function of controlling a conduction state or a non-conduction state based on the potential of wiring GL1 which functions as a gate line.

[0591] Transistor 500C comprises a first terminal electrically connected to wiring V0, a ​​second terminal electrically connected to the light-emitting device 150, and a gate electrode that has the function of controlling a conduction or non-conduction state based on the potential of wiring GL2 which functions as a gate wire. Wiring V0 is a wiring for supplying a reference potential and a wiring for outputting the current flowing through the pixel circuit 400 to the drive circuit 30.

[0592] Capacitor 600 comprises a conductive film electrically connected to the gate electrode of transistor 500B and a conductive film electrically connected to the second electrode of transistor 500C.

[0593] The light-emitting device 150 includes a first electrode electrically connected to the first electrode of the transistor 500B, and a second electrode electrically connected to the wiring VCOM. The wiring VCOM is a wire that provides a potential for supplying current to the light-emitting device 150.

[0594] This allows the intensity of light emitted by the light-emitting device 150 to be controlled in accordance with the image signal applied to the gate electrode of transistor 500B. Furthermore, variations in the gate-source voltage of transistor 500B can be suppressed by the reference potential of the wiring V0 provided via transistor 500C.

[0595] Furthermore, the wiring V0 can output a current that can be used to set pixel parameters. More specifically, wiring V0 can function as a monitor line to output the current flowing through transistor 500B or the current flowing through light-emitting device 150 to the outside. The current output to wiring V0 is converted into a voltage by a source follower circuit or the like and output to the outside. Alternatively, it can be converted into a digital signal by an AD converter or the like and output to the arithmetic circuit 10 or the like described in the above embodiment.

[0596] In the configuration shown as an example in Figure 25B, the wiring electrically connecting the pixel circuit 400 and the drive circuit 30 can be shortened, thereby reducing the wiring resistance. As a result, data can be written at high speed, and the display device 100 can be driven at high speed. This allows for a sufficient frame duration even with a large number of pixel circuits 400 in the display device 100, thus increasing the pixel density of the display device 100. Furthermore, increasing the pixel density of the display device 100 improves the resolution of the image displayed by the display device 100. For example, the pixel density of the display device 100 can be set to 1000 ppi or more, or 5000 ppi or more, or 7000 ppi or more. Therefore, the display device 100 can be used as a display device for AR or VR, and can be suitably applied to electronic devices where the distance between the display unit and the user is close, such as HMDs.

[0597] Figures 25A and 25B show a pixel circuit 400 having a total of three transistors as an example, but the pixel circuit relating to one embodiment of the present invention is not limited to this. Below, we will describe examples of pixel circuit configurations applicable to the pixel circuit 400.

[0598] The pixel circuit 400A shown in Figure 26A illustrates transistors 500A and 500B, and capacitor 600. Figure 26A also illustrates the light-emitting device 150 connected to the pixel circuit 400A. Furthermore, wirings SL, GL, ANO, and VCOM are electrically connected to the pixel circuit 400A.

[0599] Transistor 500A's gate is electrically connected to wiring GL, and one of its source and drain is electrically connected to wiring SL, the other of which is connected to the gate of transistor 500B and one of the electrodes of capacitor 600. Transistor 500B's source and drain are electrically connected to wiring ANO, and the other of which is connected to the anode of light-emitting device 150. Capacitor 600's other electrode is electrically connected to the anode of light-emitting device 150. Light-emitting device 150's cathode is electrically connected to wiring VCOM.

[0600] The pixel circuit 400B shown in Figure 26B is a configuration in which transistor 500C is added to the pixel circuit 400A. Furthermore, wiring V0 is electrically connected to the pixel circuit 400B.

[0601] The pixel circuit 400C shown in Figure 26C is an example in which transistors 500A and 500B of the pixel circuit 400A are replaced with transistors in which the gate and back gate are electrically connected. Similarly, the pixel circuit 400D shown in Figure 26D is an example in which the same transistor is replaced with the pixel circuit 400B. This increases the current that the transistor can supply. Here, all transistors used are those with a pair of electrically connected gates, but this is not the only option. Alternatively, transistors with a pair of gates that are electrically connected to different wirings may be used. For example, reliability can be improved by using a transistor in which one of the gates and the source are electrically connected.

[0602] The pixel circuit 400E shown in Figure 27A is a configuration in which a transistor 500D is added to the above-mentioned pixel circuit 400B. In addition, three wires (wires GL1, GL2, and GL3) that function as gate wires are electrically connected to the pixel circuit 400E.

[0603] Transistor 500D has its gate electrically connected to wiring GL3, and one of its source and drain is electrically connected to the gate of transistor 500B, while the other is electrically connected to wiring V0. Also, the gate of transistor 500A is electrically connected to wiring GL1, and the gate of transistor 500C is electrically connected to wiring GL2.

[0604] By simultaneously making transistors 500C and 500D conduct, the source and gate of transistor 500B become at the same potential, making transistor 500B non-conductive. This allows the current flowing to the light-emitting device 150 to be forcibly interrupted. Such a pixel circuit is suitable for use in display methods that alternate between display periods and off periods.

[0605] The pixel circuit 400F shown in Figure 27B is an example of the pixel circuit 400E with a capacitance of 600A added. The capacitance of 600A functions as a holding capacitance.

[0606] The pixel circuit 400G shown in Figure 27C and the pixel circuit 400H shown in Figure 27D are examples of applying transistors with electrically connected gates to the above-mentioned pixel circuit 400E or pixel circuit 400F, respectively. Transistors 500A, 500C, and 500D are transistors with electrically connected gates and back gates, while transistor 500B is a transistor with its gate electrically connected to its source.

[0607] <Plan view schematic and cross-sectional view schematic of a light-emitting device> Figure 28A is a schematic plan view showing an example configuration of a display device 100 according to one embodiment of the present invention, in which a light-emitting device and a light-receiving device are arranged within a single pixel. The display device 100 has multiple light-emitting devices 150R that emit red light, multiple light-emitting devices 150G that emit green light, multiple light-emitting devices 150B that emit blue light, and multiple light-receiving devices 160. In Figure 28A, the labels R, G, and B are added to the light-emitting area of ​​each light-emitting device 150 to simplify the distinction between them. The label PD is added to the light-receiving area of ​​each light-receiving device 160.

[0608] The light-emitting devices 150R, 150G, 150B, and 160 are each arranged in a matrix. Figure 28A shows an example in which the light-emitting devices 150R, 150G, and 150B are arranged in the X direction, with the 160 being arranged below them. Figure 28A also shows an example configuration in which light-emitting devices 150 emitting light of the same color are arranged in the Y direction intersecting the X direction. In the display device 100 shown in Figure 28A, for example, a pixel 80 can be composed of subpixels having light-emitting devices 150R, subpixels having light-emitting devices 150G, and subpixels having light-emitting devices 150B arranged in the X direction, and subpixels having 160 being provided below these subpixels.

[0609] It is preferable to use EL elements such as OLED (Organic Light Emitting Diode) or QLED (Quantum-dot Light Emitting Diode) for light-emitting devices 150R, 150G, and 150B. Examples of light-emitting materials for EL elements include fluorescent materials, phosphorescent materials, inorganic compounds (such as quantum dot materials), and thermally activated delayed fluorescence (TADF) materials. For TADF materials, materials in thermal equilibrium between the singlet excited state and the triplet excited state may be used. Such TADF materials have a shorter emission lifetime (excitation lifetime), which can suppress efficiency degradation in the high-brightness region of the light-emitting element.

[0610] For example, a pn-type or pin-type photodiode can be used for the light-receiving device 160. The light-receiving device 160 functions as a photoelectric conversion element that detects light incident on it and generates an electric charge. The amount of charge generated is determined based on the amount of incident light.

[0611] In particular, it is preferable to use an organic photodiode having a layer containing an organic compound for the light-receiving device 160. Organic photodiodes can be easily made thinner, lighter, and larger in area, and because they offer a high degree of freedom in shape and design, they can be applied to various display devices.

[0612] In one embodiment of the present invention, an organic EL element is used as the light-emitting device 150, and an organic photodiode is used as the light-receiving device 160. The organic EL element and the organic photodiode can be formed on the same substrate. Therefore, an organic photodiode can be incorporated into a display device using an organic EL element. It is preferable to separate the organic EL elements and the organic photodiode by photolithography. This makes it possible to reduce the spacing between light-emitting devices, between organic photodiodes, and between light-emitting devices and organic photodiodes, thereby enabling a display device with a higher aperture ratio compared to the case where a shadow mask such as a metal mask is used.

[0613] Figure 28A shows a conductor 123 that functions as a common electrode and a conductor 121CM that functions as a connecting electrode. Here, the conductor 121CM is electrically connected to the conductor 123. The conductor 121CM is located outside the display section where the light-emitting device 150 and the light-receiving device 160 are arranged. Figure 28A also shows the area of ​​the conductor 123 that overlaps with the light-emitting device 150, the light-receiving device 160, and the conductor 121CM with a dashed line.

[0614] The conductor 121CM can be provided along the outer periphery of the display unit. For example, it may be provided along one side of the outer periphery of the display unit, or it may be provided across two or more sides of the outer periphery of the display unit. That is, if the top surface shape of the display unit is rectangular, the top surface shape of the conductor 121CM can be strip-shaped, L-shaped, U-shaped (angle bracket-shaped), or square, etc.

[0615] Figure 28B is a schematic plan view showing an example configuration of the display device 100, and is a modified version of the display device 100 shown in Figure 28A. The display device 100 shown in Figure 28B differs from the display device 100 shown in Figure 28A in that it has a light-emitting device 150IR that emits infrared light. The light-emitting device 150IR can emit, for example, near-infrared light (light with a wavelength of 750 nm to 1300 nm).

[0616] In the example shown in Figure 28B, light-emitting devices 150R, 150G, and 150B are arranged in the X direction, along with light-emitting device 150IR, and a light-receiving device 160 is arranged below them. The light-receiving device 160 has the function of detecting infrared light.

[0617] Figure 29A is a cross-sectional view corresponding to the dashed line A1-A2 in Figure 28A, and Figure 29B is a cross-sectional view corresponding to the dashed line B1-B2 in Figure 28A. Furthermore, Figure 29C is a cross-sectional view corresponding to the dashed line C1-C2 in Figure 28A, and Figure 29D is a cross-sectional view corresponding to the dashed line D1-D2 in Figure 28A. The light-emitting devices 150R, 150G, 150B, and 160 are provided on the insulator 111. In addition, if the display device 100 has a light-emitting device 150IR, the light-emitting device 150IR is provided on the insulator 111.

[0618] In this specification, for example, when we refer to "B on A" or "B below A," it is not necessarily required that A and B have areas in contact.

[0619] Figure 29A shows an example of the cross-sectional configuration of the light-emitting devices 150R, 150G, and 150B as shown in Figure 28A. Figure 29B also shows an example of the cross-sectional configuration of the light-receiving device 160 as shown in Figure 28A.

[0620] Light-emitting device 150R has a conductor 121R that functions as a pixel electrode, a hole injection layer 85R, a hole transport layer 86R, a light-emitting layer 87R, an electron transport layer 88R, a common layer 89, and a conductor 123. Light-emitting device 150G has a ...

Claims

[Claim 1] It comprises a first cell array, a second cell array, and a first conversion circuit. The first cell array comprises a first cell and a second cell located in the same row as the first cell. The second cell array comprises a third cell and a fourth cell located in the same row as the third cell. The first conversion circuit has a plurality of input terminals and a plurality of output terminals, The first cell is electrically connected to the first wiring and the second wiring. The second cell is electrically connected to the first wiring and the third wiring. Each of the multiple input terminals of the first conversion circuit is electrically connected to the second wiring and the third wiring. Each of the multiple output terminals of the first conversion circuit is electrically connected to the fourth wiring and the fifth wiring. The third cell is electrically connected to the fourth wiring and the sixth wiring. The fourth cell is electrically connected to the fifth wiring and the seventh wiring. The first cell has the function of supplying a first current to the second wiring in an amount corresponding to the product of the first data held in the first cell and the second data input to the first cell from the first wiring. The second cell has the function of supplying a second current to the third wiring in an amount corresponding to the product of the third data held in the second cell and the fourth data input to the second cell from the first wiring. The first conversion circuit has the function of sending a fifth data corresponding to the total amount of current flowing from the second wiring to the fourth wiring, and the function of sending a sixth data corresponding to the total amount of current flowing from the third wiring to the fifth wiring, The third cell has the function of supplying a third current to the sixth wiring in an amount corresponding to the product of the seventh data held in the third cell and the fifth data input to the third cell from the fourth wiring. The fourth cell has the function of supplying a fourth current to the seventh wiring in an amount corresponding to the product of the eighth data held in the fourth cell and the sixth data input to the fourth cell from the fifth wiring. The sixth wiring is electrically connected to the seventh wiring. Semiconductor equipment.

Images