Methods, programs, and computers for timing semiconductor integrated circuits.
By incorporating dummy cells with multiple dummy metals in semiconductor integrated circuits, the method addresses the issue of increased layout data size and improves timing adjustment efficiency and TAT.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- RENESAS ELECTRONICS CORP
- Filing Date
- 2024-12-11
- Publication Date
- 2026-06-23
AI Technical Summary
The existing techniques for semiconductor integrated circuits result in an increase in layout data size due to the arrangement information of dummy metals.
A timing adjustment method that involves adding dummy cells containing multiple dummy metals to the layout data, connecting them to signal wirings to adjust timing, and managing them as a single entity to reduce data size and suppress variations in metal density.
This approach effectively suppresses the increase in layout data size and improves timing adjustment efficiency by accurately setting delay times and reducing rework, thereby enhancing Turn Around Time (TAT).
Smart Images
Figure 2026101750000001_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a timing adjustment method, program, and computer for semiconductor integrated circuits.
Background Art
[0002] Patent Document 1 discloses a technique of connecting a signal wiring to a dummy metal in layout data when the delay time of the signal wiring in the layout data represents a hold error.
Prior Art Documents
Patent Documents
[0003]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0004] The technique described in Patent Document 1 has a problem that the size of the layout data increases due to the arrangement information of the dummy metal.
[0005] This disclosure has been made to solve such problems, and an object thereof is to realize a timing adjustment method, program, and computer for a semiconductor integrated circuit that suppresses an increase in the size of layout data.
[0006] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.
Means for Solving the Problems
[0007] A timing adjustment method for a semiconductor integrated circuit according to an embodiment includes: a step of adding a dummy cell including a plurality of dummy metals to layout data of the semiconductor integrated circuit; If the delay time of the signal wiring included in the layout data represents a hold error, the process includes selecting a dummy cell to connect to the signal wiring, The steps include connecting one or more dummy metals from the plurality of dummy metals included in the selected dummy cell to the signal wiring, Includes.
[0008] In a program according to one embodiment, On the computer, The process of adding dummy cells containing multiple dummy metals to the layout data of a semiconductor integrated circuit, If the delay time of the signal wiring included in the layout data represents a hold error, the process of selecting a dummy cell to connect to the signal wiring is performed. The process of connecting one or more dummy metals from the plurality of dummy metals included in the selected dummy cell to the signal wiring, Make it run.
[0009] A computer according to one embodiment is, The process of adding dummy cells containing multiple dummy metals to the layout data of a semiconductor integrated circuit, If the delay time of the signal wiring included in the layout data represents a hold error, the process of selecting a dummy cell to connect to the signal wiring is performed. The process of connecting one or more dummy metals from the plurality of dummy metals included in the selected dummy cell to the signal wiring, Execute this. [Effects of the Invention]
[0010] According to the above embodiment, it is possible to provide a timing adjustment method, program, and computer for semiconductor integrated circuits that suppress the increase in the size of layout data. [Brief explanation of the drawing]
[0011] [Figure 1]It is a schematic diagram illustrating the layout of a semiconductor integrated circuit after configuration wiring. [Figure 2] It is a schematic diagram showing an example of the arrangement of conventional dummy metals. [Figure 3] It is a schematic diagram showing an overview of an embodiment. [Figure 4] It is a block diagram showing the configuration of a system to which the timing adjustment method according to Embodiment 1 is applied. [Figure 5] It is a flowchart showing the timing adjustment method of the semiconductor integrated circuit according to Embodiment 1. [Figure 6] It is a schematic diagram exemplifying a dummy cell according to Embodiment 1. [Figure 7] It is a schematic diagram showing a dummy metal connected to a signal wiring. [Figure 8] It is a schematic diagram showing a dummy metal connected to a signal wiring. [Figure 9] It is a schematic diagram exemplifying a dummy cell according to Embodiment 2. [Figure 10] It is a schematic diagram showing a dummy metal connected to a signal wiring. [Figure 11] It is a flowchart showing the timing adjustment method of the semiconductor integrated circuit according to Embodiment 4.
Modes for Carrying Out the Invention
[0012] For the sake of clarity of explanation, the following descriptions and drawings are appropriately omitted and simplified. In each drawing, the same reference numerals are assigned to the same elements, and redundant explanations are omitted as necessary. Also, each element described in the drawings as a functional block performing various processes can be composed of a CPU (Central Processing Unit), memory, and other circuits in terms of hardware, and can be realized by a program loaded into the memory or the like in terms of software. Therefore, it is understood by those skilled in the art that these functional blocks can be realized in various forms by hardware, software operating on the hardware, or combinations thereof, and are not limited to any of them.
[0013] Summary of Embodiment FIG. 1 illustrates the layout of a semiconductor integrated circuit after placement and routing. In the placement and routing process, the path of the signal wiring 12 connecting a plurality of standard cells 11 is determined. The standard cell 11 constitutes an AND circuit, an OR circuit, or the like. Conventionally, as shown in FIG. 2, in order to suppress the variation in the metal density in the wiring layer where the signal wiring 12 is provided, dummy metals 13 are added to the empty regions of the wiring layer where the signal wiring 12 is provided. The plurality of dummy metals 13 may have different shapes from each other. Since data representing the position and shape of each dummy metal 13 is added to the layout data, the data size of the layout data increases.
[0014] In the embodiment, as shown in FIG. 3, instead of the dummy metal 13, dummy cells 14 are arranged in the empty regions of the wiring layer where the signal wiring 12 is provided. Each of the dummy cells 141 and 142 is an example of the dummy cell 14. The dummy cell 141 is surrounded by a dotted line, and the dummy cell 142 is surrounded by a solid line. The size of the dummy cell 141 is smaller than the size of the dummy cell 142. In FIG. 3, two types of dummy cells 14 are added to the layout, but one type of dummy cell 14 may be added to the layout.
[0015] Multiple dummy metals 20 are arranged in dummy cell 14. For example, six square-shaped dummy metals 21 are arranged in dummy cell 141. Four rectangular-shaped dummy metals 22 are arranged in dummy cell 142. The metal density of dummy metals 21 and dummy metals 22 are different.
[0016] The dummy cell 14 is positioned to avoid the signal wiring 12. The dummy cell 14 and the standard cell 11 may overlap as long as the positions of the pins of the standard cell 11 and the positions of the dummy metal 20 satisfy the DRC (Design Rule Check).
[0017] The embodiment increases the delay time of the signal wiring 12 by connecting the signal wiring 12 to the dummy metal 20. Since multiple dummy metals 20 are grouped into a single dummy cell 14, the embodiment can reduce the data size of the layout data. For example, if there are six dummy metals 20 placed in the dummy cell 14, conventionally, data representing the position and shape of each of the six dummy metals 20 would be added to the layout data. However, according to the embodiment, multiple dummy metals 20 are treated as a single dummy cell 14. Therefore, only data representing the position and shape of the dummy cell 14 needs to be added to the layout data, so the size of the data related to the dummy metals 20 can be compressed to 1 / 6 of the size of the data representing the position and shape of each of the six dummy metals 20. If the dummy metals 20 in the dummy cell 14 have the same shape as each other, the amount of increase in the delay time of the signal wiring 12 can be set with high accuracy based on the number of dummy metals 20 connected to the signal wiring 12.
[0018] Embodiment 1 Figure 4 is a block diagram showing the configuration of a system to which the semiconductor integrated circuit timing adjustment method according to Embodiment 1 is applied. The system shown in Figure 4 comprises a computer 31, an input device 32, and an output device 33. The input device 32 and the output device 33 are connected to the computer 31. The output device 33 may include a display device and a printing device. Layout data 45 may be generated in response to input to the input device 32.
[0019] The computer 31 comprises a CPU 311 and a storage unit 312. The storage unit 312 stores the computer program 341. The CPU 311 executes the computer program 341.
[0020] The system shown in Figure 4 includes a design tool 34, which is software. The design tool 34 is installed in the storage unit 312. The design tool 34 includes a computer program 341 and a file 342. The file 342 includes layout data 45. The layout data 45 represents the position of each component to be placed in the integrated circuit. The components may include standard cells, signal lines, and dummy cells. The position may be the coordinates of each component placed in a predetermined coordinate region. The computer program 341 includes a wiring path determination unit 41, a dummy cell addition unit 42, a timing verification unit 43, and a dummy metal connection unit 44, which will be described later.
[0021] Figure 5 is a flowchart showing a timing adjustment method for a semiconductor integrated circuit according to Embodiment 1.
[0022] First, the wiring path determination unit 41 determines the path of the signal wiring 12 that connects the standard cells 11 to each other (step S101). Next, the dummy cell addition unit 42 adds dummy cells 14 containing multiple dummy metals 20 to the layout data 45. The dummy cell addition unit 42 places the dummy cells 14 in the empty areas of the wiring layers of the signal wiring 12 that are arranged along the path determined in step S101 (step S102).
[0023] Figure 6 is a schematic diagram illustrating an example of a dummy cell 14. Six dummy metals 20 are placed inside the dummy cell 14. The six dummy metals 20 are arranged in a 2x3 grid. Each dummy metal 20 has a square shape. The distance between adjacent dummy metals 20 may be constant. The placement of the dummy cell 14 helps to suppress variations in metal density.
[0024] Note that in Figure 6, only dummy cells 14 having the same dummy metal layout pattern are arranged, but this is not limited to this. As shown in Figure 3, the dummy cell addition section 42 may select appropriate dummy cells from dummy cells 14 having dummy metal layout patterns with different metal densities while satisfying the metal density constraints, and add them to the layout.
[0025] Referring again to Figure 5, the timing verification unit 43 then performs timing verification for the path determined in step S101 (step S103). If the delay time of the signal wiring 12 in the layout data 45 represents a hold error, the timing verification unit 43 calculates a negative slack value for the signal wiring 12 where the hold error occurred. The slack value represents the value obtained by subtracting the constraint value from the delay time in the signal wiring 12. The negative slack value is the slack value when the slack value is negative, indicating that the delay time in the signal wiring 12 does not satisfy the constraint condition. The absolute value of the slack value when the slack value is negative may also be called the negative slack value.
[0026] Next, the dummy metal connection unit 44 determines the number of dummy metals 20 required to satisfy the constraint value from the negative slack value (step S104). The dummy metal connection unit 44 may determine the number of dummy metals 20 by referring to a table that associates the number of dummy metals 20 with the delay time. Alternatively, the dummy metal connection unit 44 may determine the number of dummy metals 20 by dividing the negative slack value by the delay time per dummy metal 20.
[0027] The dummy metal connection section 44 may calculate a delay time corresponding to the distance between the dummy metal 20 closest to the signal wiring 12 where the hold error occurred and the signal wiring 12, based on the resistance and capacitance values of the wiring. The dummy metal connection section 44 may then subtract the calculated delay time from the negative slack value and determine the number of dummy metals 20 from the result of the subtraction.
[0028] Next, the dummy metal connector 44 searches for and selects the dummy cell 14 closest to the signal wiring 12 where the hold error occurred (step S105). If the number of dummy metals 20 determined in step S104 exceeds the number of dummy metals 20 contained in one dummy cell 14, the dummy metal connector 44 may search for and select multiple dummy cells 14.
[0029] Next, the dummy metal connector 44 selects a dummy metal 20 corresponding to the start point and a dummy metal 20 corresponding to the end point from among the dummy metals 20 included in the dummy cell 14 selected in step S105 (step S106).
[0030] Next, the dummy metal connection section 44 connects the signal wiring 12 where the hold error occurred to the dummy metal 20 corresponding to the start point selected in step S106, and connects adjacent dummy metals 20 between the start and end points to each other (step S107). In this way, the dummy metals 20 contained in the dummy cells 14, which are arranged to suppress variations in metal density, are used for timing adjustment.
[0031] Referring to Figure 7, if four dummy metals 20 are required, the dummy metal connector 44 connects the signal wiring 12 to a dummy wiring 15 containing four dummy metals 20. Increasing the wiring capacitance can increase the delay time of the signal wiring 12. Alternatively, as described in Patent Document 1, the dummy metal connector 44 may further connect a dummy metal 20 corresponding to the endpoint selected in step S106 to the signal wiring 12, and increase the length of the signal wiring 12 and thus increase the delay time by cutting the section between the point on the signal wiring 12 connected to the starting point selected in step S106 and the point on the signal wiring 12 connected to the endpoint selected in step S106.
[0032] The dummy metal 20 may be used for purposes other than increasing the delay time of the signal wiring 12. For example, if the netlist is updated to connect signal wiring 12 and signal wiring 16 from the layout in which they were originally arranged, as shown in the upper diagram of Figure 8, the dummy metal connector 44 may connect signal wiring 12 to signal wiring 16 via dummy wiring 15, as shown in the lower diagram of Figure 8. The dummy metal 20 is used as part of the dummy wiring 15.
[0033] Referring again to Figure 5, if hold errors occur for multiple signal lines 12 in step S103, steps S104 to S107 may be executed multiple times. In addition, the layout data of the dummy cell 14 may have flag information indicating whether or not it is connected to a signal line 12, in addition to information indicating its position and shape. In this case, after step S107, the dummy metal connection unit 44 writes information indicating that it is used to the flag information of the dummy cell 14, including the dummy metal 20 connected to the signal line 12. In step S105, the dummy metal connection unit 44 may search for a dummy cell 14 that is close to a signal line 12 among the dummy cells 14 that have flag information indicating that they are not connected to any signal lines.
[0034] The timing verification unit 43 performs timing verification again after step S107 (step S108). If the timing verification fails (NG in step S108), the dummy metal connection unit 44 increases the number of dummy metals 20 connected to the signal wiring 12 (step S104) and executes steps S105 to S108 again. If the timing verification fails in step S108 and it is necessary to connect another dummy cell 14, the unit may refer to the flag information mentioned above to find an additional dummy cell 14 to connect. If the timing verification is successful (OK in step S108), the timing verification unit 43 may output that the timing constraints have been met (step S109). An example that does not include step S104 may also be included in Embodiment 1. For example, the number of dummy metals 20 connected to the signal wiring 12 may be increased one by one until the timing verification in step S108 is successful.
[0035] In Embodiment 1, the layout data 45 includes data for a dummy cell 14 containing multiple dummy metals 20, rather than data for each dummy metal 20, thus preventing an increase in data size.
[0036] When multiple dummy metals 20 have the same shape, the delay time of the signal wiring 12 can be accurately set based on the number of dummy metals 20 connected to the signal wiring 12. Furthermore, conventionally, when dummy metals 20 with various shapes were connected to the signal wiring 12, it was necessary to calculate the delay time individually, resulting in significant rework if the added delay time was insufficient. Embodiment 1 reduces rework and improves the Turn Around Time (TAT).
[0037] Embodiment 2 In Embodiment 2, each dummy metal 20 has a rectangular shape. A dummy metal layout pattern representing the shape and position of the dummy metal 20 in each dummy cell 14 is selected from a plurality of dummy metal layout patterns. Descriptions that overlap with Embodiment 1 are omitted.
[0038] Referring to Figure 9, each of the dummy metals 23 and 24 is an example of a dummy metal 20. Dummy cell 143 has a first dummy metal layout pattern, and dummy cell 144 has a second dummy metal layout pattern. In dummy cell 143 with the first dummy metal layout pattern, three dummy metals 23 are arranged in a 1x3 arrangement. In dummy cell 144 with the second dummy metal layout pattern, two dummy metals 24 are arranged in a 2x1 arrangement. In dummy cell 141 shown in Figure 3, one of the two directions along the long side of the dummy metal 21 is the same as the direction along the long side of the dummy metal 22 in dummy cell 142, but the direction along the long side of the dummy metal 23 is perpendicular to the direction along the long side of the dummy metal 24. The directions along the long sides of the dummy metals 20 may be the same among multiple dummy metal layout patterns.
[0039] Referring to Figure 5, in step S102, the dummy cell addition unit 42 selects a dummy metal layout pattern for the dummy cells 14 to be placed in the empty areas of the signal wiring layers of the signal wiring 12, based on the arrangement of the signal wiring 12 determined in step S101. Based on the arrangement of the signal wiring 12, the dummy cell addition unit 42 places dummy cells having appropriate dummy metal layout patterns to satisfy the metal density constraints.
[0040] Embodiment 2 can satisfy the metal density constraint by adding dummy cells 14 with an appropriate dummy metal layout pattern, regardless of the direction along the long side of the dummy metal.
[0041] Embodiment 3 In Embodiment 3, a single dummy cell 14 is used to adjust the timing of multiple signal lines 12. Explanations that overlap with Embodiment 1 are omitted.
[0042] Referring to Figure 10, in Embodiment 3, the dummy metals 20 contained within the dummy cell 14 include dummy metals 20 connected to signal wiring 12A and dummy metals 20 connected to signal wiring 12B. The dummy metal connection section 44 connects, for example, two dummy metals 20 to signal wiring 12A and four dummy metals 20 to signal wiring 12B. This allows for efficient use of the dummy metals 20.
[0043] For example, the dummy metal connector 44 may, after connecting two dummy metals 20 to the signal wiring 12A, write information indicating that they have been used to the flag information of the two dummy metals 20. The flag information may be held in a library that manages the information of the dummy cell 14. The dummy metal connector 44 selects the dummy metal 20 to be connected to the signal wiring 12B from among the dummy metals 20 that have flag information that does not have information indicating that they have been used written to them.
[0044] Embodiment 3 can improve the efficiency of using the dummy metal 20.
[0045] Embodiment 4 Embodiment 4 is a specific example of Embodiment 1. Descriptions that overlap with Embodiment 1 are omitted.
[0046] Figure 11 is a flowchart showing the flow of the timing adjustment method according to Embodiment 4. Comparing Figure 5 and Figure 11, the input and output data are more clearly shown in Figure 11, and some steps are omitted from the illustration.
[0047] In step S102, the dummy cell addition unit 42 takes the netlist 51 and the Design Exchange Format (DEF) file 52 as input and adds the dummy cell 14 to the layout data 45 by referring to the pattern information 53. The netlist 51 shows the connection relationships of the standard cells 11. The DEF file 52 contains the position, wiring, and connection information of the standard cells 11. The pattern information 53 shows the shape and position of the dummy metal 20 in each dummy metal layout pattern of the dummy cell 14.
[0048] In step S103, the timing verification unit 43 takes the library 54 as input and performs timing verification. The library 54 may include information indicating the delay time in each standard cell 11 and the delay time in each signal line 12.
[0049] In step S104, the dummy metal connector 44 determines the required number of dummy metals 20 by referring to the dummy metal list 55. The dummy metal list 55 holds information regarding the delay time for each number of dummy metals 20, and whether or not each dummy metal 20 is used.
[0050] In step S107, the dummy metal connector 44 connects the signal wiring 12 to the dummy metal 20. The dummy metal connector 44 updates the dummy metal list 55 by registering in the dummy metal list 55 that the dummy metal 20 connected to the signal wiring 12 has been used.
[0051] Embodiment 4 can accommodate various dummy metal layout patterns and can update information indicating available dummy metals.
[0052] The present invention has been described in detail above based on embodiments, but it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence. Furthermore, the above embodiments can be combined in any way. For example, some or all of Embodiments 1 to 4 can be combined to realize the invention.
[0053] The program described above includes, when loaded into a computer, a set of instructions (or software code) for causing the computer to perform one or more of the functions described in the embodiments. The program may be stored in a non-temporary computer-readable medium or a physical storage medium. Examples, but not limited to, include RAM (Random-Access Memory), ROM (Read-Only Memory), flash memory, SSD (Solid-State Drive), or other memory technologies, CD-ROM, DVD (Digital Versatile Disc), Blu-ray® disc, or other optical disc storage, magnetic cassette, magnetic tape, magnetic disk storage, or other magnetic storage devices. The program may be transmitted over a temporary computer-readable medium or a communication medium. Examples, but not limited to, include temporary computer-readable medium or a communication medium that includes electrically, optically, acoustically, or otherwise propagating signals. [Explanation of symbols]
[0054] 31 Computer 311 CPU 312 Storage section 32 Input devices 33 Output device 34 Design Tools 341 Computer Programs 41 Wiring Route Determination Section 42 Dummy cell addition section 43 Timing Verification Unit 44 Dummy metal connector 342 files 45 Layout data 13, 20, 21, 22, 23, 24 Dummy metal 14, 141, 142, 143, 144 Dummy Cells 11 Standard Cells 12, 12A, 12B, 16 signal wiring 15 Dummy Wiring 45 Layout data 51 Netlist 52 DEF files 53 Pattern Information 54 Libraries
Claims
1. A process of adding dummy cells containing multiple dummy metals to the layout data of a semiconductor integrated circuit, If the delay time of the signal wiring included in the layout data represents a hold error, the process includes selecting a dummy cell to connect to the signal wiring, The steps include connecting one or more dummy metals from the plurality of dummy metals included in the selected dummy cell to the signal wiring, A method for timing semiconductor integrated circuits, including the components mentioned above.
2. The aforementioned dummy metals have the same shape as each other. The timing adjustment method includes a step of determining the number of dummy metals connected to the signal wiring from a negative slack value corresponding to the delay time. A method for adjusting the timing of a semiconductor integrated circuit according to claim 1.
3. Each dummy metal has a square shape. A method for adjusting the timing of a semiconductor integrated circuit according to claim 2.
4. The distance between adjacent dummy metals is constant. A method for adjusting the timing of a semiconductor integrated circuit according to claim 2.
5. Some of the aforementioned dummy metals are used to connect two signal lines to each other. A method for adjusting the timing of a semiconductor integrated circuit according to claim 1.
6. In the aforementioned addition step, select the dummy cell to be added from a plurality of dummy cells having different dummy metal layout patterns. A method for adjusting the timing of a semiconductor integrated circuit according to claim 1.
7. The plurality of dummy cells include a first dummy cell containing dummy metal whose direction along the longer side is a first direction, and a second dummy cell containing dummy metal whose direction along the longer side is a second direction perpendicular to the first direction. A method for adjusting the timing of a semiconductor integrated circuit according to claim 6.
8. The plurality of dummy metals in the dummy cell include a first dummy metal connected to a first signal wiring and a second dummy metal connected to a second signal wiring different from the first signal wiring. A method for adjusting the timing of a semiconductor integrated circuit according to claim 1.
9. On the computer, The process of adding dummy cells containing multiple dummy metals to the layout data of a semiconductor integrated circuit, If the delay time of the signal wiring included in the layout data represents a hold error, the process of selecting a dummy cell to connect to the signal wiring is performed. The process of connecting one or more dummy metals from the plurality of dummy metals included in the selected dummy cell to the signal wiring, A program that executes the command.
10. The process of adding dummy cells containing multiple dummy metals to the layout data of a semiconductor integrated circuit, If the delay time of the signal wiring included in the layout data represents a hold error, a process is performed to select a dummy cell to connect to the signal wiring. The process of connecting one or more dummy metals from the plurality of dummy metals included in the selected dummy cell to the signal wiring, The computer that runs it.