Semiconductor device and method for manufacturing the same
By employing a delay circuit with selectable paths and a selector circuit, the semiconductor manufacturing process achieves precise delay adjustments, mitigating timing violations and electro-migration errors, thus reducing rework and design man-hours.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- RENESAS ELECTRONICS CORP
- Filing Date
- 2024-12-11
- Publication Date
- 2026-06-23
AI Technical Summary
Existing semiconductor manufacturing processes face challenges in managing circuit concentration and wiring delays, leading to electro-migration errors and frequent rework due to timing violations, especially with miniaturization and reduced power supply voltages.
The implementation of a delay circuit with multiple selectable paths and a selector circuit to adjust delay values, allowing for precise design of anticipated delays and reducing manual corrections, thereby minimizing rework and electro-migration errors.
This approach enables high-precision design with reduced man-hours and fewer design errors, addressing timing violations proactively and reducing the need for frequent rework.
Smart Images
Figure 2026101847000001_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device configured to arrange a plurality of circuits on a plane and connect wirings to each of them, and a method for manufacturing the same.
Background Art
[0002] In semiconductor devices, miniaturization of the manufacturing process and reduction of the operating power supply voltage are progressing. As miniaturization and voltage reduction progress, the influence of poor clock timing due to wiring delay in semiconductor devices becomes greater.
[0003] The timing between a semiconductor device and an external device is called AC timing (Analog Current Timing). As verification of AC timing, it may be necessary to verify signals via an external device. Therefore, when verifying the operation, it is necessary to consider the delay of signals via the external device.
[0004] As the manufacturing process is miniaturized, the operating frequency of semiconductor devices is increasing, and a difference in operating speed with external devices is emerging. As a method for reducing the delay difference between a semiconductor device and an external device, a method of inserting a delay value for delaying signal transfer in advance can be cited. The delay value is on the order of several tens of ns at maximum.
[0005] Patent Document 1 discloses a semiconductor device that eliminates poor clock timing by inserting a buffer circuit for adjusting the delay time. Patent Document 1 also discloses providing a cell occupancy check unit that calculates the layout congestion degree of a predetermined region so that buffer circuits do not locally concentrate.
Prior Art Documents
Patent Documents
[0006]
Patent Document 1
[0007] When using a tool that automatically corrects timing violations to insert delay values, as mentioned above, circuits can become concentrated in certain areas. Since localized concentration of circuits and wiring can cause EM errors (Electro Migration Errors), circuits are manually inserted to resolve the delays.
[0008] To manually resolve the delay, it would be necessary to sequentially correct the AC timing errors in the initially laid-out circuit diagram. Since power analysis needs to be performed each time the layout is changed, this presents a challenge due to frequent rework.
[0009] Other challenges and novel features will become apparent from the description and accompanying drawings in this specification. [Means for solving the problem]
[0010] According to one embodiment, the method for manufacturing a semiconductor device of the present disclosure involves arranging a delay circuit capable of selecting one of a plurality of delay paths by a selection signal, connecting the output of the delay circuit to become the timing signal of a digital circuit, connecting a predetermined voltage as the selection signal to select one of the plurality of delay paths, and selecting the amount of delay so that the input / output timing of the digital circuit matches predetermined conditions. Other features will be described in detail below. [Effects of the Invention]
[0011] This disclosure provides a semiconductor device and a method for manufacturing the same that enable the design of anticipated delays with high precision using fewer man-hours. [Brief explanation of the drawing]
[0012] [Figure 1]Figure 1 shows the layout of the semiconductor device of this disclosure, the configuration diagram of the delay HM, and a plan view of the semiconductor device layout. [Figure 2] Figure 2 is a flowchart showing the method for manufacturing the semiconductor device according to the present disclosure. [Figure 3] Figure 3 illustrates the adjustment of the delay of the semiconductor device of this disclosure. [Figure 4] Figure 4 illustrates the adjustment of the delay of the semiconductor device of this disclosure. [Figure 5] Figure 5 illustrates the switching of delay values in the semiconductor device of this disclosure. [Figure 6] Figure 6 illustrates the switching of delay values in the semiconductor device of this disclosure. [Figure 7] Figure 7 illustrates the switching of the delay HM of the semiconductor device of this disclosure. [Figure 8] Figure 8 is a layout diagram of the related semiconductor device. [Figure 9] Figure 9 is a layout diagram of the related semiconductor device. [Modes for carrying out the invention]
[0013] The embodiments of this disclosure will be described in detail below with reference to the drawings. In the specification and drawings, the same or corresponding components are denoted by the same reference numerals, and redundant descriptions are omitted. In the drawings, components may be omitted or simplified for the sake of clarity. Furthermore, at least a portion of each embodiment may be combined with one another as desired.
[0014] <Embodiment 1> FIG. 1(a) is a diagram showing the layout of the semiconductor device 10 of the present disclosure before inserting a delay HM (Hard Macro) which is a delay circuit. As shown in FIG. 1(a), the semiconductor device 10 is connected to an external device 21 located upstream and an external device 22 located downstream. The semiconductor device 10 includes a plurality of circuits inside. In the configuration example of the semiconductor device 10 shown in FIG. 1(a), two flip-flop circuits FF_A and FF_B which are digital circuits are provided.
[0015] In the method of manufacturing the semiconductor device of the present disclosure, a plurality of circuits are arranged on a plane and wirings are connected to each of them. Therefore, by using the delay HM which is a circuit block incorporated as hardware, the defect of AC timing (Analog Current Timing) is eliminated. In the semiconductor device of the present disclosure, the delay HM shown in FIG. 1(b) is mounted on an IP (Intellectual Property) which is circuit design data for which it is predicted that the convergence of AC timing is difficult.
[0016] FIG. 1(b) is a diagram showing the configuration of the delay HM provided in the semiconductor device 10. A timing signal for adding a delay is input as an input signal to an input terminal ck_in. The input signal is output to a second circuit 112 and / or a fifth circuit 115 via a first circuit 111. The first circuit 111 includes a plurality of inverter circuits 121. The second circuit 112 includes a plurality of inverter circuits 122. Therefore, the delay HM includes a plurality of signal paths. Each of the first circuit 111 and the second circuit 112 implements a delay value corresponding to the number of stages of the inverter circuit. A buffer circuit is also referred to as a delay element.
[0017] Furthermore, the semiconductor device 10 includes a fourth circuit 114 that outputs a selection signal and a fifth circuit 115 that is a selector circuit that operates based on the timing signal. The fifth circuit 115 receives the selection signal and the timing signal output from the first circuit 111 and adjusts the delay determined by the signal path. The selector circuit can switch the delay value with a selector.
[0018] For example, if 0 is input to the selection signal in the selector circuit, it switches to the D0 path that does not pass through the second circuit 112, and if 1 is input to the selection signal in the selector circuit, it switches to the D1 path that passes through the second circuit 112. Since the delay value is determined by the number of connection stages of the delay elements, for example, in the case of the D0 path, it can be delayed by the number of stages of the delay elements included in the first circuit 111. Also, in the case of the D1 path, it can be delayed by the number of stages of the delay elements included in the first circuit 111 and the second circuit 112.
[0019] Therefore, the delay HM has a plurality of delay paths with different input-output delay amounts, and is configured such that one of the plurality of delay paths can be selected by a selection signal. Also, a plurality of delay HMs, which are delay circuits, may be arranged. The signal paths in each delay circuit may be individually set with the voltages connected as selection signals.
[0020] The signal output from the fifth circuit 115 is output from the output terminal ck_out via the sixth circuit 116. The flip-flop circuit FF_B, which is a digital circuit, operates at a timing based on the delay signal and outputs an output signal to the external device 22.
[0021] FIG. 1(c) is a plan view of the layout of the semiconductor device 10. The first circuit 111 to the sixth circuit 116 are configured by blocks having a rectangular shape in a plan view. For example, the first circuit 111 and the second circuit 112 can arbitrarily change the connection according to the number of inverter circuit stages required. Also, the positions of the input terminal ck_in and the output terminal ck_out are fixed on the block. The input terminal ck_in and the output terminal ck_out are arranged on the same line parallel to an arbitrary side of the rectangular shape.
[0022] FIG. 2 is a flowchart showing a manufacturing method of the semiconductor device 10 of the present disclosure. First, the layout of the semiconductor device 10 is designed using the delay HM (S101). The layout design includes at least an arrangement process of arranging the delay HM.
[0023] After the layout design is complete, a power analysis (S102) to determine if the power requirements are met and a verification (S103) to determine if the layout rules are met are performed in parallel. If the layout rules are not met, the layout design is redone. If the layout rules are met, the process proceeds to the next step.
[0024] First, it is verified whether the timing conditions are met (S104). If the timing conditions are met, the process proceeds to the next step. If the timing conditions are not met, the delay value is switched to a level that will satisfy the timing conditions (S105). Specifically, a wiring process is performed to connect the output of the delay circuit so that it becomes the timing signal of the digital circuit. After that, a delay adjustment process is performed to select one of several delay paths by connecting a predetermined voltage as a selection signal and to select the amount of delay so that the input / output timing of the digital circuit matches the predetermined conditions. The switching of delay values at timing violation points may be done automatically using a tool, or it may be done manually by creating a command.
[0025] If the timing conditions are met, the verification conditions for EM errors (Electro Migration Error) are checked (S106). If the EM verification conditions are not met, the type of delay HM is switched to meet the EM verification conditions (S107). That is, a characteristic adjustment process is performed to change the number of semiconductor elements constituting the delay path while maintaining the delay amount of the delay circuit in order to meet the predetermined EM characteristics. The switching of the delay HM type at the EM verification violation point may be done automatically using a tool, or it may be done manually by creating a command. If the EM verification conditions are met, the process is completed.
[0026] In the manufacturing methods of semiconductor devices in related technological fields, rework was frequent due to the need for successive design changes caused by timing violations. On the other hand, the semiconductor device manufacturing method of this disclosure uses a delayed HM design, which allows for proactive measures to be taken against the problem. Therefore, by using a delayed HM, the problem is mitigated, and furthermore, rework is reduced, thus reducing design man-hours.
[0027] Figures 3(a) to 3(d) illustrate the adjustment of delay when outputting a signal to an external device 22 located downstream. In this case, timing violations occur in the clock line of the external output and in the signal from the flip-flop FF_B to the external output.
[0028] To address timing violations in the clock line of the external output, a layout is prepared in advance in which delays HM131 and 132 are placed in parallel upstream of FF_B, as shown in Figure 3(b). The configurations of delays HM131 and 132 are as shown in Figure 2(b). The delay values in the second circuit 112 of delays HM131 and 132 are inserted into the clock line. This eliminates timing violations in the clock line of the external output.
[0029] To address timing violations in the signal from the flip-flop FF_B to the external output, a layout is pre-created in which delays HM131 and 132 are placed in parallel downstream of FF_B, as shown in Figure 3(c). The delay values within the second circuit 112 of delays HM131 and 132 are inserted into the data line. This eliminates timing violations in the signal from the flip-flop FF_B to the external output.
[0030] Furthermore, the delays HM131 and 132 are composed of rectangular blocks and are arranged on the same line parallel to any side of the rectangle. Therefore, as shown in Figure 3(d), the pin heights can be aligned by arranging the delays HM131 and 132 in parallel.
[0031] Figures 4(a) to 4(d) illustrate the adjustment of delay when a signal is input from an upstream external device 21. In this case, timing violations occur in the clock line of the external input and in the signal from the external device 21 to the flip-flop FF_A.
[0032] To address timing violations in the external input clock line, a layout is pre-created in which delays HM131 and 132 are placed in parallel upstream of FF_A in the clock line, as shown in Figure 4(b). The configurations of delays HM131 and 132 are as shown in Figure 2(b). The delay values in the second circuit 112 of delays HM131 and 132 are inserted into the clock line. This eliminates timing violations in the external input clock line.
[0033] To address timing violations in the signal from external device 21 to flip-flop FF_A, a layout is pre-created in which delays HM131 and 132 are placed in parallel upstream of FF_A on the data line, as shown in Figure 4(c). The delay values within the second circuit 112 of delays HM131 and 132 are inserted into the data line. This eliminates timing violations in the signal from external device 21 to flip-flop FF_A.
[0034] Furthermore, the delays HM131 and 132 are composed of rectangular blocks and are arranged on the same line parallel to any side of the rectangle. Therefore, as shown in Figure 4(d), the pin heights can be aligned by arranging the delays HM131 and 132 in parallel.
[0035] As a comparative example, we will consider the case where a buffer circuit BUF is inserted into a semiconductor device 20 whose layout has already been determined, using Figures 8(a) to (c) and Figures 9(a) to (c). Figures 8(a) and 9(a) show a semiconductor device 20 having four flip-flops FF_A to FF_D. If a delay of several tens of nanoseconds is introduced into this semiconductor device 20 after the wiring process, the wiring to bypass the existing circuit becomes complicated, and there is a risk that the delay value will exceed the intended delay (see Figures 8(b) and (c)).
[0036] Furthermore, process miniaturization reduces the delay value per element, leading to a massive increase in the number of buffer circuits (BUFs) that need to be inserted. Consequently, this results in an increase in the number of elements required to achieve the desired delay value, as well as an increase in the amount of work involved during the design phase.
[0037] Furthermore, consider the case where a buffer circuit BUF can be inserted into the clock line of the flip-flop FF_D after the wiring process. As shown by the dotted line in Figure 9(b), a design rule violation may occur between the newly inserted buffer circuit BUF and its wiring and the existing wiring. Even if the clock line of the flip-flop FF_D is rewired to resolve the design rule violation in Figure 9(b), the delay value may increase, causing errors in sections where the timing was previously met.
[0038] Furthermore, since power analysis is performed in parallel with timing design during backend design, the analysis cannot be performed with correct values until the number and type of cells to be used are determined. Consequently, there is a problem in that it is difficult to estimate the amount of leakage due to delayed insertion. In addition, the concentration of delayed insertions can lead to a problem in which EM errors are more likely to occur.
[0039] The semiconductor device and method for manufacturing the same described herein can overcome the above-mentioned challenges and problems.
[0040] Next, the method for setting fixed values in the fifth circuit 115, which is a digital circuit, will be explained using Figures 5 and 6. Note that the explanation of the parts of the delay HM configuration shown in Figures 5 and 6 that overlap with those in Figures 1(b) and (c) will be omitted. The delay HM shown in Figure 5(a) is supplied with power supply voltage and ground voltage. The selection of the delay path may be performed by connecting either the power supply voltage or the ground voltage as a selection signal (see Figures 5(b) and (c)). That is, the delay value is switched by switching from the power supply voltage to the ground voltage, or from the ground voltage to the power supply voltage. As shown in Figures 6(a) and (b), the delay value can be switched by simply changing from the state where it is connected to VDD to the state where it is connected to VSS, so the impact on resolving timing violations is small.
[0041] Alternatively, the signal value can be switched using elements (Tie-High, Tie-Low) to fix it to High or Low. Furthermore, it is possible to automate the switching process by using EDA (Electronic Design Automation) tools to recognize the delayed HM, obtain timing verification results, and perform the switching.
[0042] As described above, countermeasures against EM errors are taken using a delayed HM. However, countermeasures for EM errors caused by other factors in the semiconductor device 10 will be explained using Figures 7(a) to 7(e). Note that explanations of the delayed HM configuration shown in Figures 7(a) to 7(e) that overlap with Figure 1(b) will be omitted.
[0043] Figure 7(a) is a typical delay HM of the present disclosure shown in Figure 1(b). Figure 7(b) is a delay HM for which the second circuit 112 and the fourth circuit 114 that outputs a selection signal are to be removed. Figure 7(c) is a delay HM for which the path from the first circuit 111 directly to the fifth circuit and the fourth circuit 114 that outputs a selection signal are to be removed. Figure 7(d) is a delay HM with the second circuit 112, the fourth circuit 114 that outputs a selection signal, and the fifth circuit 115 removed at the layout design stage. Figure 7(e) is a delay HM with the path from the first circuit 111 directly to the fifth circuit, and the fourth circuit 114 and the fifth circuit 115 that output a selection signal removed at the layout design stage.
[0044] By providing multiple types of delayed HMs in this way, it is possible to replace them with selector-less delayed HMs with fewer cells (see Figures 7(d) and (e)), thereby eliminating EM errors.
[0045] The present inventors have described the invention in detail based on embodiments, but it goes without saying that this disclosure is not limited to the embodiments already described, and various modifications are possible without departing from the spirit of the invention. [Explanation of symbols]
[0046] 10, 20 Semiconductor equipment 21, 22 External devices 111 1st circuit 112 2nd circuit 113 3rd circuit 114 4th circuit 115 5th circuit 116 6th circuit 121, 122 Inverter Circuit 131, 132 Delayed HM
Claims
1. A method for manufacturing a semiconductor device in which multiple circuits are arranged on a plane and wiring is connected to each of them, A placement step involves arranging a digital circuit that operates based on a timing signal, and a delay circuit that has multiple delay paths with different input / output delay amounts, and is configured so that one of the multiple delay paths can be selected by a selection signal. A wiring step of connecting the output of the delay circuit to the timing signal of the digital circuit, The device includes a delay adjustment step of selecting one of the plurality of delay paths by connecting a predetermined voltage as the selection signal, and selecting the delay amount so that the input / output timing of the digital circuit matches predetermined conditions. A method for manufacturing a semiconductor device.
2. The delay circuit is supplied with a power supply voltage and a ground voltage, and the selection of the delay path is performed by connecting either the power supply voltage or the ground voltage as the selection signal. A method for manufacturing a semiconductor device according to claim 1.
3. Multiple delay circuits are arranged, and the signal path in each delay circuit has a voltage that is individually set to be connected as the selection signal. A method for manufacturing a semiconductor device according to claim 1.
4. The semiconductor device further comprises a characteristic adjustment step of changing the number of semiconductor elements constituting the delay path while maintaining the delay amount of the delay circuit, so that the semiconductor device satisfies predetermined EM (Electro Migration) characteristics. A method for manufacturing a semiconductor device according to claim 1.
5. The digital circuit and the delay circuit are composed of blocks that form a rectangular shape in a plan view during the arrangement process. The positions of the input and output terminals of the delay circuit are fixed on the block. A method for manufacturing a semiconductor device according to claim 1.
6. The input and output terminals of the delay circuit are arranged in the block on the same line parallel to any side of the rectangular shape. The method for manufacturing a semiconductor device according to claim 5.
7. A delay circuit that takes an input signal as input, adds a predetermined delay, and outputs it as a delayed signal. The system includes a digital circuit that operates at a timing based on the aforementioned delay signal and outputs an output signal, The delay circuit is composed of multiple delay elements and has a selector circuit that allows selection of one of multiple signal paths with different numbers of connection stages of the delay elements. The output timing of the output signal of the digital circuit is adjusted by the delay determined by the signal path selected by the selector circuit. Semiconductor equipment.
8. The delay circuit is supplied with a power supply voltage and a ground voltage, and the selection by the selector circuit is performed by connecting either the power supply voltage or the ground voltage as a selection signal. The semiconductor device according to claim 7.
9. Multiple delay circuits are arranged, and the signal path in each delay circuit has a voltage that is individually set to be connected as the selection signal. The semiconductor device according to claim 8.