Semiconductor equipment

Abstract

It is preferable to ensure the electrical characteristics of the edge termination structure. [Solution] A semiconductor device is provided comprising: a semiconductor substrate having an upper surface and a lower surface and provided with a drift region of a first conductivity type; an active portion provided on the semiconductor substrate; and an edge termination structure provided on the semiconductor substrate and provided between the active portion and the edge of the semiconductor substrate on the upper surface of the semiconductor substrate, wherein the edge termination structure has an interlayer insulating film provided on the upper surface of the semiconductor substrate and a guard ring of a second conductivity type provided on the semiconductor substrate and at least a portion of which is in contact with the interlayer insulating film on the upper surface of the semiconductor substrate, wherein in a first cross section parallel to both a first direction toward the edge of the semiconductor substrate from the active portion and the depth direction of the semiconductor substrate, the guard ring has at least one side surface, and the side surface has one or more inflection points.

Description

[Technical Field]

[0001] This invention relates to a semiconductor device. [Background technology]

[0002] Conventionally, semiconductor devices having a termination structure are known (see, for example, Patent Document 1). Patent Document 1, International Publication No. 2024 / 100926 [Overview of the project] [Problems that the invention aims to solve]

[0003] It is preferable to ensure the electrical characteristics of the edge termination structure. [Means for solving the problem]

[0004] To solve the above problems, a first embodiment of the present invention provides a semiconductor device comprising: a semiconductor substrate having an upper surface and a lower surface and provided with a drift region of a first conductivity type; an active portion provided on the semiconductor substrate; and an edge termination structure provided on the semiconductor substrate and located between the active portion and the edge of the semiconductor substrate on the upper surface of the semiconductor substrate. In the above semiconductor device, the edge termination structure may have an interlayer insulating film provided on the upper surface of the semiconductor substrate. In the above semiconductor device, the edge termination structure may have a guard ring of a second conductivity type provided on the semiconductor substrate and having at least a portion of it in contact with the interlayer insulating film on the upper surface of the semiconductor substrate. In any of the above semiconductor devices, in a first cross-section parallel to both a first direction toward the edge of the semiconductor substrate from the active portion and the depth direction of the semiconductor substrate, the guard ring has at least one side surface, and the side surface may have one or more inflection points.

[0005] In the first direction of any of the semiconductor devices described above, the portion of the guard ring between the inflection point closest to the interlayer insulating film and the interlayer insulating film may be wider than the portion between the inflection point and the lower end of the guard ring.

[0006] In the first cross-section of any of the semiconductor devices described above, the guard ring may have a lower end and a first side surface that is closer to the active portion than the lower end. In the first cross-section of any of the semiconductor devices described above, the guard ring may have a second side surface that is closer to the edge of the semiconductor substrate than the lower end. In any of the semiconductor devices described above, each of the first side surface and the second side surface may have one or more inflection points.

[0007] In any of the above semiconductor devices, there may be at least one inflection point located on the upper surface side of the semiconductor substrate, rather than the center of the guard ring in the depth direction.

[0008] In any of the above semiconductor devices, the side surface of the guard ring may have a curved edge that is convex toward the upper surface of the semiconductor substrate toward the interlayer insulating film. In any of the above semiconductor devices, the curved edge may be in contact with the interlayer insulating film.

[0009] To solve the above problems, a second embodiment of the present invention provides a semiconductor device comprising: a semiconductor substrate having an upper surface and a lower surface and provided with a drift region of a first conductivity type; an active portion provided on the semiconductor substrate; and an edge termination structure provided on the semiconductor substrate and located between the active portion and the edge of the semiconductor substrate on the upper surface of the semiconductor substrate. In the above semiconductor device, the edge termination structure may include an interlayer insulating film provided on the upper surface of the semiconductor substrate and a guard ring of a second conductivity type provided on the semiconductor substrate, with at least a portion of it in contact with the interlayer insulating film on the upper surface of the semiconductor substrate. Any of the above semiconductor devices may include a well region of a second conductivity type between the active portion and the edge termination structure. In any of the above semiconductor devices, the depth of the guard ring may be greater than the depth of the well region. In any of the above semiconductor devices, the guard ring may have a first end which is the end of the guard ring on the active portion side, a lower end which is the deepest position of the guard ring, and a second end which is the outer peripheral end of the guard ring on the semiconductor substrate side. In any of the semiconductor devices described above, the distance between the lower end and the second end in a top view of the semiconductor substrate may be greater than the distance between the lower end and the first end.

[0010] In any of the semiconductor devices described above, the interface between the guard ring and the drift region may have a shape that is convex towards the upper surface between the position of the lower end and the position of the second end.

[0011] In any of the semiconductor devices described above, the guard ring may have the shape of an envelope formed by the overlapping of a plurality of individual guard rings.

[0012] In any of the above-described semiconductor devices, the semiconductor substrate may contain antimony as a bulk dopant.

[0013] In any of the above-described semiconductor devices, the interlayer insulating film may include the bulk dopant.

[0014] In any of the above semiconductor devices, the concentration of the bulk dopant in the interlayer insulating film at the first position contacting the upper surface of the semiconductor substrate may be higher than the chemical concentration of the bulk dopant in the interlayer insulating film at the second position farther from the upper surface of the semiconductor substrate than the first position.

[0015] In the semiconductor substrate of any of the above semiconductor devices, the chemical concentration of the bulk dopant in the drift region may be higher than the chemical concentration of the bulk dopant at the position contacting the interlayer insulating film.

[0016] In any of the above semiconductor devices, the active portion may be provided on the upper surface side of the semiconductor substrate and may include a gate trench portion having a gate conductive portion provided inside the semiconductor substrate and a gate insulating film insulating the gate conductive portion and the semiconductor substrate. In any of the above semiconductor devices, the active portion may include an adjacent trench portion arranged side by side with the gate trench portion in the arrangement direction. In any of the above semiconductor devices, the active portion may include a base region of the second conductivity type provided in a mesa portion which is a region sandwiched between the gate trench portion and the adjacent trench portion. In any of the above semiconductor devices, a first end which is the lower end of the base region at a portion contacting the gate insulating film may be arranged at a position deeper than a second end which is the lower end of the base region at the center in the arrangement direction of the mesa portion.

[0017] In any of the above semiconductor devices, the shape of the lower surface of the base region in the arrangement direction may be a convex curved surface shape on the upper surface side of the semiconductor substrate.

[0018] Any of the semiconductor devices described above may include a trench bottom region of a second conductivity type that is provided apart from the base region and contacts the lower end of the gate trench portion. In any of the semiconductor devices described above, the upper end of the trench bottom region in the portion contacting the gate insulating film may be located closer to the upper surface side of the semiconductor substrate than the upper end of the central trench bottom region in the arrangement direction of the mesa portion. In any of the semiconductor devices described above, the upper end of the trench bottom region may include a first curved surface that is convex toward the lower surface side of the semiconductor substrate toward the gate insulating film in the arrangement direction.

[0019] The above summary of the invention does not list all the necessary features of the present invention. Also, sub - combinations of these feature groups can also be inventions.

Brief Description of the Drawings

[0020] [Figure 1] It is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. [Figure 2] It is an enlarged view of region D in FIG. 1. [Figure 3] It is a view showing an example of the e - e cross - section in FIG. 2. [Figure 4] It is an enlarged view of the mesa portion 60 in FIG. 3. [Figure 5A] It is a view showing the doping concentration distribution in the depth direction of the mesa portion 60. [Figure 5B] It is a view showing another example of the doping concentration distribution in the depth direction of the mesa portion 60. [Figure 6] It is an enlarged view showing another example of the mesa portion 60. [Figure 7] It is a view showing the concentration distribution of bulk donors on the h - h' line in FIG. 6. [Figure 8] It is a view showing a first modification example of the mesa portion 60. [Figure 9A] It is a view showing the doping concentration distribution in the depth direction of the mesa portion 60. [Figure 9B] It is a view showing another example in the first modification example of the mesa portion 60. [Figure 9C] This figure shows another example of the doping concentration distribution in the depth direction of the mesa section 60. [Figure 9D] This figure shows another example of the first modified form of the mesa section 60. [Figure 9E] This figure shows another example of the doping concentration distribution in the depth direction of the mesa section 60. [Figure 10] This figure shows a second modified example of the mesa section 60. [Figure 11] This figure shows a third modified example of the mesa section 60. [Figure 12] This figure shows a fourth modified example of the mesa section 60. [Figure 13] This figure shows an example of the manufacturing process for semiconductor device 100. [Figure 14A] This diagram illustrates the trench formation process S1010. [Figure 14B] This diagram illustrates the injection process S1020 for the trench bottom region 109. [Figure 14C] This is a diagram illustrating the injection process S1030 for the storage area 16. [Figure 14D] This is a diagram illustrating the injection process S1040 for the base region 14. [Figure 14E] This is a diagram illustrating the annealing process S1050. [Figure 15A] This figure illustrates another example of the injection process S1040 for the base region 14. [Figure 15B] This is a diagram illustrating another example of the annealing process S1050. [Figure 16] This figure shows another example of the manufacturing process for semiconductor device 100. [Figure 17A] Figure 16 illustrates the injection process S1050 for the storage area 16. [Figure 17B] This figure illustrates the second annealing process S1060 in Figure 16. [Figure 18A] Figure 16 illustrates another example of the injection process S1050 for the storage region 16. [Figure 18B]This figure illustrates another example of the second annealing process S1060 in Figure 16. [Figure 19] Figure 1 shows an example of a cross-section of bb. [Figure 20] This is an enlarged view of the semiconductor substrate 10 near the well region 17 and guard ring 92 in Figure 19. [Figure 21] This figure shows another example of Guard Ring 92. [Figure 22] This figure shows another example of Guard Ring 92. [Figure 23] This figure shows the concentration distribution of bulk donors along the i-i' line in Figure 22. [Figure 24] This figure shows the guard ring 92 in the comparative example. [Figure 25] This figure shows an example of the manufacturing process for the edge termination structure 90. [Figure 26A] This is a diagram illustrating the injection process S2010 for the guard ring 92. [Figure 26B] This is a diagram illustrating the annealing process S2020. [Figure 27A] This figure illustrates another example of the injection process S2010 for the guard ring 92. [Figure 27B] This is a diagram illustrating another example of the annealing process S2020. [Modes for carrying out the invention]

[0021] The present invention will be described below through embodiments, but these embodiments are not intended to limit the scope of the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0022] In this specification, one side of a semiconductor substrate parallel to its depth direction is referred to as "top," and the other side as "bottom." Of the two main surfaces of a substrate, layer, or other component, one surface is referred to as the top surface, and the other surface as the bottom surface. The directions of "top" and "bottom" are not limited to the direction of gravity or the direction in which the semiconductor device is mounted.

[0023] In this specification, technical matters may be described using the Cartesian coordinate axes, the X, Y, and Z axes. The Cartesian coordinate axes merely specify the relative positions of components and do not limit any particular direction. For example, the Z axis does not limit the direction to height relative to the ground. Note that the +Z axis direction and the -Z axis direction are opposite directions. When the sign is not specified and only the Z axis direction is written, it means the direction parallel to the +Z and -Z axes.

[0024] In this specification, the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are defined as the X and Y axes. The axis perpendicular to the top and bottom surfaces of the semiconductor substrate is defined as the Z axis. In this specification, the direction of the Z axis may be referred to as the depth direction. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X and Y axes, may be referred to as the horizontal direction.

[0025] The region from the center of the semiconductor substrate in the depth direction to the top surface of the semiconductor substrate is sometimes referred to as the top surface. Similarly, the region from the center of the semiconductor substrate in the depth direction to the bottom surface of the semiconductor substrate is sometimes referred to as the bottom surface.

[0026] In this specification, the terms "identical" or "equal" may include cases where there are errors due to manufacturing variations, etc. Such errors are, for example, within 10%.

[0027] In this specification, the conductivity type of a doped region containing impurities is described as either P-type or N-type. In this specification, impurities may specifically refer to either N-type donors or P-type acceptors, and may be referred to as dopants. In this specification, doping means introducing donors or acceptors into a semiconductor substrate to make it a semiconductor exhibiting either an N-type conductivity or a P-type conductivity.

[0028] In this specification, doping concentration means the concentration of the donor or acceptor at thermal equilibrium. In this specification, net doping concentration means the net concentration obtained by adding up the charge polarity, with the donor concentration being the concentration of positive ions and the acceptor concentration being the concentration of negative ions. As an example, the donor concentration is N D , the acceptor concentration is N A Therefore, the net doping concentration at any given position is N D -N A In this specification, net doping concentration may be simply referred to as doping concentration.

[0029] Donors have the function of supplying electrons to a semiconductor. Acceptors have the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to impurities themselves. For example, a VOH defect in a semiconductor, where a vacancy (V), oxygen (O), and hydrogen (H) are bonded, functions as an electron-supplying donor. A hydrogen donor may be a donor in which at least a vacancy (V) and hydrogen (H) are bonded. Alternatively, interstitial Si-H, where interstitial silicon (Si-i) and hydrogen are bonded in a silicon semiconductor, and CiOi-H, where interstitial carbon (Ci) and interstitial oxygen (Oi) and hydrogen are bonded, also function as electron-supplying donors. In this specification, VOH defects, CiOi-H, or interstitial Si-H may be referred to as hydrogen donors.

[0030] In this specification, the semiconductor substrate has N-type bulk donors uniformly distributed throughout. The bulk donors are donors formed by dopants that were substantially uniformly contained in the ingot from which the semiconductor substrate originated during the production of the ingot. The bulk donors in this example are elements other than hydrogen. The dopants of the bulk donors are, for example, phosphorus, antimony, arsenic, selenium, or sulfur, but are not limited thereto. The bulk donors are also included in the P-type regions. The semiconductor substrate may be a wafer cut from a semiconductor ingot, or may be a chip obtained by singulating the wafer. The semiconductor ingot may be manufactured by any of the Czochralski method (CZ method), the magnetic field applied Czochralski method (MCZ method), or the float zone method (FZ method). The ingot in this example is manufactured by the MCZ method. The oxygen concentration contained in the substrate manufactured by the MCZ method is 1×10 17 ~7×10 17 / cm 3 . The oxygen concentration contained in the substrate manufactured by the FZ method is 1×10 15 ~5×10 16 / cm 3 . A higher oxygen concentration tends to more easily generate hydrogen donors. The bulk donor concentration may be the chemical concentration of the bulk donors distributed throughout the semiconductor substrate, and may be a value between 90% and 100% of the chemical concentration. Also, a non-doped substrate that does not contain dopants such as phosphorus may be used as the semiconductor substrate. In that case, the bulk donor concentration (D0) of the non-doping substrate is, for example, 1×10 10 / cm 3 or more and 5×10 12 / cm 3 or less. The bulk donor concentration (D0) of the non-doping substrate is preferably 1×10 11 / cm 3 or more. The bulk donor concentration (D0) of the non-doping substrate is preferably 5×10 12 / cm 3 or less. Incidentally, each concentration in the present invention may be a value at room temperature. The value at room temperature may be, for example, the value at 300 K (Kelvin) (about 26.9 °C).

[0031] In this specification, when P+ type or N+ type is mentioned, it means a higher doping concentration than P type or N type, and when P- type or N- type is mentioned, it means a lower doping concentration than P type or N type. Furthermore, when P++ type or N++ type is mentioned in this specification, it means a higher doping concentration than P+ type or N+ type. Unless otherwise specified, the units used in this specification are SI units. Although units of length may be expressed in cm, calculations may be performed after converting to meters (m).

[0032] In this specification, chemical concentration refers to the atomic density of impurities measured independently of the electrical activation state. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration described above can be measured by voltage-capacitance (CV) spectroscopy. Alternatively, the carrier concentration measured by broadened resistance (SR) spectroscopy may be used as the net doping concentration. The carrier concentration measured by CV or SR spectroscopy may be the value at thermal equilibrium. Furthermore, in the N-type region, since the donor concentration is sufficiently larger than the acceptor concentration, the carrier concentration in that region may be used as the donor concentration. Similarly, in the P-type region, the carrier concentration in that region may be used as the acceptor concentration. In this specification, the doping concentration in the N-type region may be referred to as the donor concentration, and the doping concentration in the P-type region may be referred to as the acceptor concentration.

[0033] If the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value may be used as the concentration of the donor, acceptor, or net doping in that region. If the concentrations of the donor, acceptor, or net doping are nearly uniform, the average value of the concentrations of the donor, acceptor, or net doping in that region may be used as the concentration of the donor, acceptor, or net doping. In this specification, concentrations per unit volume are expressed as atoms / cm³. 3 , or / cm 3This unit is used for donor or acceptor concentrations in semiconductor substrates, or for chemical concentrations. The atom notation may be omitted.

[0034] The carrier concentration measured by the SR method may be lower than the donor or acceptor concentration. When measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value for the crystalline state in the range where current flows. The decrease in carrier mobility occurs because carriers are scattered due to disorder in the crystal structure caused by lattice defects, etc.

[0035] The donor or acceptor concentrations calculated from carrier concentrations measured by the CV method or SR method may be lower than the chemical concentrations of the elements exhibiting donor or acceptor properties. For example, in silicon semiconductors, the donor concentrations of phosphorus or arsenic, or the acceptor concentrations of boron, are approximately 99% of their respective chemical concentrations. On the other hand, the donor concentration of hydrogen in silicon semiconductors is approximately 0.1% to 10% of the hydrogen chemical concentration. The semiconductor substrate may be silicon, silicon carbide, gallium nitride, diamond, or gallium oxide.

[0036] Figure 1 is a top view showing an example of a semiconductor device 100 according to one embodiment of the present invention. In Figure 1, the positions of each component projected onto the upper surface of the semiconductor substrate 10 are shown. In Figure 1, only some components of the semiconductor device 100 are shown, and some components are omitted.

[0037] The semiconductor device 100 comprises a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has edges 162 when viewed from above. In this specification, when simply referred to as "top view," it means viewing from the top side of the semiconductor substrate 10. In this example, the semiconductor substrate 10 has two pairs of edges 162 that face each other when viewed from above. In Figure 1, the X and Y axes are parallel to either edge 162. The Z axis is perpendicular to the top surface of the semiconductor substrate 10.

[0038] The semiconductor substrate 10 is provided with an active area 160. The active area 160 is a region in which the main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is operating. An emitter electrode is provided above the active area 160, but it is omitted in Figure 1. The active area 160 may refer to the region that overlaps with the emitter electrode when viewed from above. The active area 160 may refer to the region in which the emitter electrode and the semiconductor substrate 10 are in periodic contact when viewed from above. In addition, the region sandwiched between the active areas 160 when viewed from above may also be included in the active area 160. For example, if the emitter electrode is separated into two, the region between the two emitter electrodes when viewed from above may also be included in the active area 160.

[0039] The active section 160 is provided with a diode section 80 including a diode element such as a freewheeling diode (FWD). The active section 160 may further be provided with a transistor section 70 including a transistor element such as an IGBT (Insulated Gate Bipolar Transistor). In the example shown in Figure 1, the transistor section 70 and the diode section 80 are arranged alternately along a predetermined arrangement direction (in this example, the X-axis direction) on the upper surface of the semiconductor substrate 10. The semiconductor device 100 in this example is a reverse-conducting IGBT (RC-IGBT). The transistor section 70 and the diode section 80 are connected in antiparallel to each other. That is, the emitter of the transistor section 70 and the anode of the diode section 80 are electrically connected, and the collector of the transistor section 70 and the cathode of the diode section 80 are electrically connected.

[0040] In Figure 1, the region where the transistor section 70 is located is denoted by the symbol "I," and the region where the diode section 80 is located is denoted by the symbol "F." In this specification, the direction perpendicular to the arrangement direction in a top view may be referred to as the extension direction (Y-axis direction in Figure 1). The transistor section 70 and the diode section 80 may each have their longitudinal length in the extension direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section described later.

[0041] The diode portion 80 has an N+ type cathode region in the area in contact with the lower surface of the semiconductor substrate 10. The region where the cathode region is located in a top view may be the diode portion 80. A P type collector region may be provided in the area of ​​the lower surface of the semiconductor substrate 10 other than the diode portion 80.

[0042] The transistor section 70 has a P-type collector region in the area in contact with the lower surface of the semiconductor substrate 10. Furthermore, the transistor section 70 has a gate structure periodically arranged on the upper surface side of the semiconductor substrate 10, which includes an N-type emitter region, a P-type base region, a gate conductive portion, and a gate insulating film.

[0043] The semiconductor device 100 may have one or more pads on the semiconductor substrate 10. In this example, the semiconductor device 100 has a gate pad 164. The semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current sensing pad. Each pad is located near the edge 162. The vicinity of the edge 162 refers to the area between the edge 162 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as wires.

[0044] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to the conductive portion of the gate trench of the active portion 160. The semiconductor device 100 is provided with gate wiring that connects the gate pad 164 to the gate trench. In Figure 1, the gate wiring is shown with diagonal hatching.

[0045] The gate wiring in this example has an outer gate wiring 130 and an active gate wiring 131. The outer gate wiring 130 is positioned between the active portion 160 and the edge 162 of the semiconductor substrate 10 in a top view. In this example, the outer gate wiring 130 surrounds the active portion 160 in a top view. The area surrounded by the outer gate wiring 130 in a top view may be considered the active portion 160. Furthermore, a well region is formed below the gate wiring. The well region is a P-type region with a higher density than the base region, which will be described later, and is formed from the top surface of the semiconductor substrate 10 to a position deeper than the base region. The area surrounded by the well region in a top view may be considered the active portion 160.

[0046] The outer perimeter gate wiring 130 is connected to the gate pad 164. The outer perimeter gate wiring 130 is located above the semiconductor substrate 10. The outer perimeter gate wiring 130 may be a metal wiring containing aluminum or the like.

[0047] The active gate wiring 131 is provided in the active section 160. By providing the active gate wiring 131 in the active section 160, variations in the wiring length from the gate pad 164 can be reduced for each region of the semiconductor substrate 10.

[0048] The outer periphery gate wiring 130 and the active side gate wiring 131 are connected to the gate trench portion of the active portion 160. The outer periphery gate wiring 130 and the active side gate wiring 131 are positioned above the semiconductor substrate 10. The outer periphery gate wiring 130 and the active side gate wiring 131 may be wiring formed from a semiconductor such as polysilicon doped with impurities, or metal wiring containing aluminum, or both.

[0049] The active gate wiring 131 may be connected to the outer gate wiring 130. In this example, the active gate wiring 131 extends in the X-axis direction from one outer gate wiring 130 to the other outer gate wiring 130 that sandwiches the active section 160, crossing the active section 160 approximately in the center in the Y-axis direction. When the active section 160 is divided by the active gate wiring 131, the transistor section 70 and the diode section 80 may be arranged alternately in the X-axis direction in each divided region.

[0050] The semiconductor device 100 may include a temperature sensing unit (not shown) which is a PN junction diode made of polysilicon or the like, and a current detection unit (not shown) which simulates the operation of a transistor unit provided in the active unit 160.

[0051] In this example, the semiconductor device 100 includes an edge termination structure 90 between the active portion 160 and the edge 162 when viewed from above. In this example, the edge termination structure 90 is positioned between the outer peripheral gate wiring 130 and the edge 162. The edge termination structure 90 mitigates electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 90 may include at least one of a guard ring, a field plate, and a resurf arranged in an annular shape around the active portion 160. Figure 1 shows a plurality of guard rings 92 arranged in an annular shape around the active portion 160.

[0052] Figure 2 is an enlarged view of region D in Figure 1. Region D is the region including the transistor section 70, the diode section 80, and the active-side gate wiring 131. The semiconductor device 100 in this example includes a gate trench section 40, a dummy trench section 30, a well section 17, an emitter section 12, a base section 14, and a contact section 15, which are provided inside the upper surface of the semiconductor substrate 10. The gate trench section 40 and the dummy trench section 30 are examples of trench sections. The semiconductor device 100 in this example also includes an emitter electrode 52 and an active-side gate wiring 131, which are provided above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the active-side gate wiring 131 are provided separately from each other.

[0053] An interlayer insulating film is provided between the emitter electrode 52 and the active gate wiring 131 and the upper surface of the semiconductor substrate 10, but this is omitted in Figure 2. In this example, contact holes 54 are provided in the interlayer insulating film, penetrating the film. In Figure 2, each contact hole 54 is hatched with diagonal lines.

[0054] The emitter electrode 52 is provided above the gate trench 40, dummy trench 30, well region 17, emitter region 12, base region 14, and contact region 15. The emitter electrode 52 contacts the emitter region 12, contact region 15, and base region 14 on the upper surface of the semiconductor substrate 10 through a contact hole 54. The emitter electrode 52 is also connected to a dummy conductive part in the dummy trench 30 through a contact hole provided in the interlayer insulating film. The emitter electrode 52 may be connected to a dummy conductive part of the dummy trench 30 at its tip in the Y-axis direction. The dummy conductive part of the dummy trench 30 does not need to be connected to the emitter electrode 52 and the gate conductive part, and may be controlled to a potential different from the potential of the emitter electrode 52 and the gate conductive part.

[0055] The active gate wiring 131 connects to the gate trench portion 40 through a contact hole provided in the interlayer insulating film. The active gate wiring 131 may be connected to the gate conductive portion of the gate trench portion 40 at the tip portion 41 of the gate trench portion 40 in the Y-axis direction. The active gate wiring 131 is not connected to the dummy conductive portion in the dummy trench portion 30.

[0056] The emitter electrode 52 is formed from a material containing metal. Figure 2 shows the area in which the emitter electrode 52 is provided. For example, at least a portion of the emitter electrode 52 is formed from aluminum or an aluminum-silicon alloy, such as AlSi or AlSiCu. The emitter electrode 52 may have a barrier metal formed from titanium or a titanium compound in the layer below the region formed from aluminum or the like. Furthermore, it may have a plug formed by embedding tungsten or the like in the contact hole so as to be in contact with the barrier metal and the aluminum or the like. The emitter electrode 52 may be the electrode with the largest surface area when viewed from above.

[0057] The well region 17 is provided overlapping with the active gate wiring 131. The well region 17 also extends to a predetermined width in areas that do not overlap with the active gate wiring 131. In this example, the well region 17 is provided away from the Y-axis end of the contact hole 54 towards the active gate wiring 131. The well region 17 is a second conductivity type region with a higher doping concentration than the base region 14. In this example, the base region 14 is P-type, and the well region 17 is P+-type.

[0058] Each of the transistor section 70 and the diode section 80 has multiple trench sections arranged in the direction of arrangement. In this example, the transistor section 70 has one or more gate trench sections 40 and one or more dummy trench sections 30 alternately provided along the direction of arrangement. In this example, the diode section 80 has multiple dummy trench sections 30 provided along the direction of arrangement. In this example, the diode section 80 does not have gate trench sections 40.

[0059] The gate trench portion 40 in this example may have two linear portions 39 (the trench portion which is linear along the extension direction) that extend along the extension direction perpendicular to the alignment direction, and a tip portion 41 that connects the two linear portions 39. In Figure 2, the extension direction is the Y-axis direction.

[0060] Preferably, at least a portion of the tip portion 41 is provided in a curved shape when viewed from above. By connecting the ends of the two straight portions 39 in the Y-axis direction with the tip portion 41, electric field concentration at the ends of the straight portions 39 can be mitigated.

[0061] In the transistor section 70, the dummy trench section 30 is provided between each of the straight sections 39 of the gate trench section 40. There may be one dummy trench section 30 between each of the straight sections 39, or there may be multiple dummy trench sections 30. The dummy trench section 30 may have a straight shape extending in the extension direction, and like the gate trench section 40, it may have a straight section 29 and a tip section 31. The semiconductor device 100 shown in Figure 2 includes both a dummy trench section 30 with a straight shape without a tip section 31 and a dummy trench section 30 with a tip section 31.

[0062] The diffusion depth of the well region 17 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. The Y-axis ends of the gate trench portion 40 and the dummy trench portion 30 are located in the well region 17 when viewed from above. In other words, at the Y-axis end of each trench portion, the bottom in the depth direction of each trench portion is covered by the well region 17. This makes it possible to mitigate electric field concentration at the bottom of each trench portion.

[0063] In the arrangement direction, mesa portions are provided between each trench portion. A mesa portion refers to a region within the semiconductor substrate 10 that is sandwiched between trench portions. For example, the upper end of a mesa portion is the upper surface of the semiconductor substrate 10. The depth position of the lower end of a mesa portion is the same as the depth position of the lower end of a trench portion. In this example, the mesa portion is provided on the upper surface of the semiconductor substrate 10, extending along the trench in the extension direction (Y-axis direction). In this example, a mesa portion 60 is provided in the transistor portion 70, and a mesa portion 61 is provided in the diode portion 80. In this specification, when simply referred to as a mesa portion, it refers to mesa portion 60 and mesa portion 61, respectively.

[0064] Each mesa portion is provided with a base region 14. Of the base regions 14 exposed on the upper surface of the semiconductor substrate 10 in the mesa portion, the region closest to the active gate wiring 131 is defined as base region 14-e. Figure 2 shows the base region 14-e located at one end of each mesa portion in the extending direction, but a base region 14-e is also located at the other end of each mesa portion. In each mesa portion, at least one of a first conductivity type emitter region 12 and a second conductivity type contact region 15 may be provided in the region sandwiched between the base regions 14-e in a top view. In this example, the emitter region 12 is N+ type and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 may be provided in the depth direction between the base region 14 and the upper surface of the semiconductor substrate 10.

[0065] The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 60 in contact with the gate trench portion 40 may be provided with a contact region 15 exposed on the upper surface of the semiconductor substrate 10.

[0066] Each of the contact region 15 and emitter region 12 in the mesa portion 60 extends from one trench portion to the other in the X-axis direction. As an example, the contact region 15 and emitter region 12 of the mesa portion 60 are arranged alternately along the extension direction (Y-axis direction) of the trench portion.

[0067] In other examples, the contact region 15 and emitter region 12 of the mesa portion 60 may be arranged in a stripe pattern along the extension direction (Y-axis direction) of the trench portion. For example, the emitter region 12 may be provided in the region in contact with the trench portion, and the contact region 15 may be provided in the region sandwiched between the emitter regions 12.

[0068] The mesa portion 61 of the diode portion 80 does not have an emitter region 12. A base region 14 and a contact region 15 may be provided on the upper surface of the mesa portion 61. In the region on the upper surface of the mesa portion 61 sandwiched between the base regions 14-e, a contact region 15 may be provided in contact with each base region 14-e. In the region on the upper surface of the mesa portion 61 sandwiched between the contact regions 15, a base region 14 may be provided. The base region 14 may be arranged in the entire region sandwiched between the contact regions 15.

[0069] A contact hole 54 is provided above each mesa portion. The contact hole 54 is located in the region sandwiched between the base region 14-e. In this example, the contact hole 54 is provided above the contact region 15, the base region 14, and the emitter region 12. In the diode portion 80, the contact region 15 may not be provided. The contact hole 54 is not provided in the region corresponding to the base region 14-e and the well region 17. The contact hole 54 may be located in the center in the arrangement direction (X-axis direction) of the mesa portion 60.

[0070] In the diode section 80, a cathode region 82 is provided in the region adjacent to the lower surface of the semiconductor substrate 10. In the region of the lower surface of the semiconductor substrate 10 where the cathode region 82 is not provided, a P-type collector region 22 may be provided. The cathode region 82 and the collector region 22 are provided between the lower surface 23 of the semiconductor substrate 10 and the buffer region 20. The cathode region 82 and the collector region 22 may be in contact with the lower surface 23 of the semiconductor substrate 10. In Figure 2, the boundary between the cathode region 82 and the collector region 22 is shown by a dotted line.

[0071] The cathode region 82 is positioned away from the well region 17 in the Y-axis direction. This ensures a distance between the P-type region (well region 17), which has a relatively high doping concentration and is formed to a deep position, and the N+-type cathode region 82, thereby improving pressure resistance. In this example, the Y-axis end of the cathode region 82 is positioned further from the well region 17 than the Y-axis end of the contact hole 54. In other examples, the Y-axis end of the cathode region 82 may be positioned between the well region 17 and the contact hole 54.

[0072] Figure 3 shows an example of the ee cross-section in Figure 2. The ee cross-section is the XZ plane passing through the emitter region 12 and the cathode region 82. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in this cross-section.

[0073] The interlayer insulating film 38 is provided on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film that includes at least one layer of insulating film such as silicate glass with impurities such as boron or phosphorus added, a thermal oxide film, and other insulating films. The interlayer insulating film 38 is provided with contact holes 54 as described in Figure 2.

[0074] The emitter electrode 52 is located above the interlayer insulating film 38. The emitter electrode 52 is in contact with the upper surface 21 of the semiconductor substrate 10 through a contact hole 54 in the interlayer insulating film 38. The collector electrode 24 is located on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are made of a metallic material such as aluminum. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (Z-axis direction) is referred to as the depth direction.

[0075] The semiconductor substrate 10 has an N-type or N-type drift region 18. The drift region 18 is provided in both the transistor section 70 and the diode section 80.

[0076] The mesa portion 60 of the transistor portion 70 has an N+ type emitter region 12 and a P type base region 14, which are provided in order from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An N type storage region 16 may also be provided in the mesa portion 60. The storage region 16 is located between the base region 14 and the drift region 18. However, the storage region 16 is not required.

[0077] In the mesa portion 60, the emitter region 12 is provided between the base region 14 and the upper surface 21 of the semiconductor substrate 10. The emitter region 12 is exposed to the upper surface 21 of the semiconductor substrate 10 and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The doping concentration of the emitter region 12 is higher than that of the drift region 18.

[0078] The base region 14 is located below the emitter region 12. In this example, the base region 14 is located in contact with the emitter region 12. The base region 14 may be in contact with the trenches on both sides of the mesa region 60. However, the shape of the base region near the trenches will be described later.

[0079] The storage region 16 is located below the base region 14. The storage region 16 is an N-type region with a higher doping concentration than the drift region 18. That is, the donor concentration in the storage region 16 is higher than that in the drift region 18. By providing a high-concentration storage region 16 between the drift region 18 and the base region 14, the carrier injection promotion effect (IE effect) can be enhanced and the on-voltage can be reduced. The storage region 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60. In the storage region 16 shown in Figure 3, it is provided only on the upper surface 21 side of the lower end of the trench portion, but in other examples, the storage region 16 may be provided from the upper surface 21 side to the lower surface 23 side of the lower end of the trench portion.

[0080] A P-shaped base region 14 is provided in the mesa region 61 of the diode region 80, in contact with the upper surface 21 of the semiconductor substrate 10. The base region 14 of the diode region 80 functions as the anode region of the diode region 80. A drift region 18 is provided below the base region 14. In the mesa region 61, a storage region 16 may be provided below the base region 14.

[0081] In both the transistor section 70 and the diode section 80, an N+ type buffer section 20 may be provided below the drift section 18. The doping concentration in the buffer section 20 is higher than the doping concentration in the drift section 18. The buffer section 20 may have a concentration peak with a higher doping concentration than the drift section 18. The doping concentration of the concentration peak refers to the doping concentration at the peak of the concentration peak. Furthermore, the doping concentration of the drift section 18 may be the average value of the doping concentration in a region where the doping concentration distribution is nearly flat.

[0082] The buffer region 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The concentration peaks of the buffer region 20 may be located at the same depth as, for example, the chemical concentration peaks of hydrogen (proton) or phosphorus. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower end of the base region 14 from reaching the collector region 22 and the cathode region 82.

[0083] In the transistor section 70, a P+ type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than that of the base region 14. The collector region 22 may contain the same acceptors as the base region 14, or it may contain different acceptors. The acceptors of the collector region 22 are, for example, boron.

[0084] In the diode section 80, an N+ type cathode section 82 is provided below the buffer section 20. The donor concentration of the cathode section 82 is higher than that of the drift section 18. The donor of the cathode section 82 is, for example, arsenic, hydrogen, or phosphorus. The position where the collector section 22 and the cathode section 82 are in contact may be the boundary between the transistor section 70 and the diode section 80 in the X-axis direction.

[0085] The collector region 22 and the cathode region 82 are exposed to the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed from a metallic material such as aluminum.

[0086] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the upper surface 21 of the semiconductor substrate 10. Each trench extends from the upper surface 21 of the semiconductor substrate 10, through the base region 14, and down to below the base region 14. In regions where at least one of the emitter region 12, contact region 15, and storage region 16 is provided, each trench also penetrates these doping regions. The statement that a trench penetrates a doping region is not limited to manufacturing in the order of forming the doping region before forming the trench. Manufacturing in which doping regions are formed between the trenches after the trenches have been formed is also included in the statement that a trench penetrates a doping region.

[0087] As described above, the transistor section 70 is provided with a gate trench section 40 and a dummy trench section 30. The diode section 80 is provided with a dummy trench section 30, but not with a gate trench section 40.

[0088] The gate trench portion 40 is provided on the upper surface 21 side of the semiconductor substrate 10. The gate trench portion 40 in this example has a gate trench, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided covering the inner wall of the gate trench. The gate insulating film 42 may be an oxide film formed by oxidizing the semiconductor on the inner wall of the gate trench, or a nitride film formed by nitriding. For example, if the semiconductor substrate 10 is a silicon substrate, the gate insulating film 42 may be a silicon oxide film.

[0089] The gate conductive portion 44 is provided inside the semiconductor substrate 10 and is located inside the gate trench, further inward than the gate insulating film 42. Being provided inside the semiconductor substrate 10 means that it is located between the upper surface 21 and the lower surface 23 of the semiconductor substrate 10 in the depth direction. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0090] The gate conductive portion 44 may be longer than the base region 14 in the depth direction. The gate trench portion 40 in this cross-section is covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed on the surface layer of the interface of the base region 14 that is in contact with the gate trench portion 40.

[0091] An interlayer insulating film 48 may be provided between the interlayer insulating film 38 and the gate conductive portion 44 in the depth direction. The interlayer insulating film 48 may be provided on the side of the upper surface 21 of the semiconductor substrate 10. In this example, the interlayer insulating film 48 is provided between the gate insulating films 42 in the X-axis direction. The position where the interlayer insulating film 48 and the gate insulating film 42 are in contact may be on the upper surface 21 side of the upper end of the base region 14. The interlayer insulating film 48 may be formed from the same material as the interlayer insulating film 38 and may be formed in the same process. Alternatively, the interlayer insulating film 48 may be formed from a different material than the interlayer insulating film 38 and may be formed in a different process. In other examples, the interlayer insulating film 48 may not be provided, and the upper surface of the gate conductive portion 44 may be aligned with the upper surface 21 of the semiconductor substrate 10.

[0092] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the xz cross-section of Figure 3. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 is provided covering the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction. Furthermore, an interlayer insulating film 48 may also be provided between the dummy conductive part 34 and the interlayer insulating film 38.

[0093] In this example, the gate trench portion 40 and the dummy trench portion 30 are covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The bottom portions of the dummy trench portion 30 and the gate trench portion 40 may be curved (curved in cross-section) with a downward convex shape.

[0094] Figure 4 is an enlarged view of the mesa portion 60 in Figure 3. In Figure 4, one of the trench portions flanking the mesa portion 60 is the gate trench portion 40. In this specification, a trench portion arranged alongside the gate trench portion 40 in the arrangement direction may be referred to as an adjacent trench portion 150. In this example, the arrangement direction is the X-axis direction, and the adjacent trench portion 150 is a dummy trench portion 30. However, the adjacent trench portion 150 may also be the gate trench portion 40. In this example, the mesa portion 60 is the region sandwiched between the gate trench portion 40 and the adjacent trench portion 150.

[0095] In this example, the emitter region 12, base region 14, and storage region 16 are in contact with the sidewall portion of the gate insulating film 42. The lower end of the base region 14 in contact with the gate insulating film 42 is defined as the first end m1. The lower end of the central base region 14 in the alignment direction of the mesa portion 60 is defined as the second end m2.

[0096] In this example, the first end portion m1 is positioned deeper than the second end portion m2. In this specification, the depth of the structure provided on the upper surface 21 is the distance in the Z-axis direction relative to the upper surface 21. That is, the distance between the first end portion m1 and the upper surface 21 is greater than the distance between the second end portion m2 and the upper surface 21. The depth of the structure provided on the lower surface 23 is the distance in the Z-axis direction relative to the lower surface 23. The gate-collector capacitance of the transistor section 70 varies depending on the area of ​​the impurity region in contact with the gate insulating film 42. In this example, the gate-collector capacitance varies depending on the area in contact with the storage region 16 of the gate insulating film 42. The region where the gate insulating film 42 and the base region 14 are in contact may be referred to as the channel region 152. The channel region 152 may be the region where an inversion layer is formed when a voltage above the gate threshold is applied to the gate electrode electrically connected to the gate conductive part 44. If the area of ​​the channel region 152 increases, the area in contact with the storage region 16 of the gate insulating film 42 decreases, and consequently the gate-collector capacitance decreases. By positioning the first end m1 deeper than the second end m2, the gate-collector capacitance can be reduced, and the turn-on characteristics can be improved. Furthermore, since the second end m2 is positioned shallower than the first end m1, the influence of variations in the doping concentration of the storage region 16 on the doping concentration distribution of the base region 14, particularly the portion in contact with the side wall of the gate trench 40, can be suppressed. As a result, variations in the gate threshold voltage can be suppressed. Even if the storage region 16 is not provided, and the portion of the storage region 16 in Figure 4 is the drift region 18, the positioning of the second end m2 shallower than the first end m1 reduces the contact area of ​​the gate insulating film 42 with the drift region 18, thereby reducing the gate-collector capacitance and suppressing variations in the gate threshold voltage. On the other hand, as the area of ​​the channel region 152 increases, the gate-emitter capacitance increases and the transconductance gm decreases. This also reduces the saturation current value during a short circuit, making it easier to ensure short-circuit withstand capability. The shape of this base region 14 can be formed by adjusting the position of ion implantation, as will be described later.

[0097] The distance d1 in the depth direction between the first end m1 and the second end m2 may be 0.1 μm or more. The larger the distance d1, the larger the area of ​​the channel region 152 described above can be. The distance d1 may be 0.2 μm or more, 0.3 μm or more, 0.4 μm or more, or 0.5 μm or more.

[0098] The distance d1 in the depth direction between the first end m1 and the second end m2 may be 1.0 μm or less. The distance d1 may be 0.9 μm or less, 0.8 μm or less, 0.7 μm or less, or 0.6 μm or less.

[0099] Let m3 be the lower end of the emitter region 12. The lower end m3 of the emitter region 12 may be flat in the X-axis direction. That is, the thickness of the emitter region 12 in the depth direction may be constant regardless of the position in the X-axis direction. A flat lower end m3 of the emitter region 12 means that the variation in the thickness of the emitter region 12 may be 10% or less, 5% or less, or 1% or less of the average thickness of the emitter region 12. Let d3 be the distance from the lower end m3 of the emitter region 12 in contact with the gate insulating film 42 to the first end m1. Also, let d2 be the distance from the lower end m3 of the central emitter region 12 in the arrangement direction of the mesa portion 60 to the second end m2. In this example, distance d3 is greater than distance d2. Distances d3 and d2 may be the length in the depth direction (Z-axis direction) of the base region 14 at their respective X-axis positions.

[0100] In the mesa portion 60, even in the portion in contact with the adjacent trench portion 150, the base region 14, the storage region 16, and the emitter region 12 may have the same shape as the portion in contact with the gate trench portion 40. When the adjacent trench portion 150 is the gate trench portion 40, the gate-collector capacitance can be reduced in the adjacent trench portion 150 as described above. The shape of the base region 14 in the XZ cross section may be symmetrical with respect to a line that crosses the center of the mesa portion 60 in the X-axis direction in the depth direction. Furthermore, in other mesa portions 60 where at least one of the trench portions sandwiching the mesa portion 60 is the gate trench portion 40, the shape shown in Figure 4 may be provided.

[0101] The shape of the lower surface of the base region 14 in the alignment direction may include a curved surface 28 that is convex toward the upper surface 21 of the semiconductor substrate 10. Figure 4 shows a curve corresponding to the curved surface 28 on the lower surface of the base region 14. The curve on the lower surface of the base region 14 may have an inflection point 98. An inflection point is a point where the sign of the second derivative f''(x) of the function changes when the curve is considered as a function of z=f(x) in the XZ coordinate system. In this example, the lower surface of the base region 14 has one inflection point 98 between the position where it is in contact with the gate insulating film 42 in the alignment direction and the center of the mesa portion 60. It also has one inflection point 98 between the center of the mesa portion 60 in the alignment direction and the adjacent trench portion 150. In this example, the curved surface 28 is the portion of the lower surface of the base region 14 in the XZ cross section between the inflection point 98 and the center of the mesa portion 60 in the alignment direction. As shown in Figure 4, if the base region 14 has a shape that is symmetrical with respect to a line that crosses the center of the mesa portion 60 in the X-axis direction in the depth direction, the curved surface 28 is the portion between the two inflection points 98 on the lower surface of the base region 14 in the XZ cross section.

[0102] Figure 5A shows the doping concentration distribution in the depth direction of the mesa region 60. In Figure 5A, the doping concentrations of the f-f' and g-g' lines in Figure 4 are shown. The f-f' line is a line that crosses the emitter region 12, base region 14, and storage region 16 in the depth direction at the center of the alignment direction of the mesa region 60 and extends to the drift region 18. The g-g' line is a line that crosses the emitter region 12, base region 14, and storage region 16 in the depth direction at the position in contact with the gate insulating film 42 and extends to the drift region 18. In Figure 5A, the horizontal axis shows the position in the depth direction, and the vertical axis shows the doping concentration. In Figure 5A, the doping concentration of the bulk donor is denoted as Dd.

[0103] Each region may have a doping concentration peak. Let D1 be the doping concentration at the peak position of the emitter region 12 on the f-f' line. Similarly, let D2 be the doping concentration at the peak position of the base region 14 on the f-f' line, and let D3 be the doping concentration at the peak position of the accumulation region 16. Also, let D1' be the doping concentration at the peak position of the emitter region 12 on the g-g' line. Similarly, let D2' be the doping concentration at the peak position of the base region 14 on the g-g' line, and let D3' be the doping concentration at the peak position of the accumulation region 16.

[0104] Doping concentrations D1 and D1' may be equal. Doping concentrations D2 and D2' may be equal. Doping concentrations D3 and D3' may be equal. For example, doping concentration D1 is 1 × 10⁻⁶. 20 / cm 3 Therefore, the doping concentration D2 is 2 × 10⁻⁶ 17 / cm 3 Therefore, the doping concentration D3 is 2 × 10 16 / cm 3 The relationship between doping concentrations may be D1 > D2 > D3, and D1' > D2' > D3'. Note that doping concentration D2' may be less than doping concentration D2. In this case, the gate threshold may be determined by doping concentration D2'.

[0105] The peak position of the emitter region 12 on the f-f' line may be the same as the peak position of the emitter region 12 on the g-g' line. The peak position of the base region 14 on the f-f' line may be the same as the peak position of the base region 14 on the g-g' line. The peak position of the storage region 16 on the f-f' line may be the same as the peak position of the storage region 16 on the g-g' line. However, at least one peak position may differ between the f-f' line and the g-g' line.

[0106] The position of the first end m1 may be the position of the PN junction between the base region 14 and the storage region 16 in the g-g' line. The position of the second end m2 may be the position of the PN junction between the base region 14 and the storage region 16 in the f-f' line. If the storage region 16 is not provided, the position of the PN junction between the base region 14 and the drift region 18 may be the position of the first end m1 or the second end m2. The position of the lower end m3 may be the position of the PN junction between the emitter region 12 and the base region 14 in the f-f' line or the g-g' line. The integrated value of the doping concentration of the base region 14 in the g-g' line may be greater than or equal to the integrated value of the doping concentration of the base region 14 in the f-f' line. The integrated value of the doping concentration of the storage region 16 in the g-g' line may be less than or equal to the integrated value of the doping concentration of the storage region 16 in the f-f' line.

[0107] Figure 5B shows another example of the doping concentration distribution in the depth direction of the mesa 60. In Figure 5B, the doping concentration distribution of the base region 14 in the depth direction differs from the example in Figure 5A. Other features of Figure 5B may be the same as those of Figure 5A. The base region 14 at the g-g' line may have more doping concentration peaks in the depth direction than the base region 14 at the f-f' line. For example, in the example shown in Figure 5B, the base region 14 may have a peak smaller than the doping concentration D2' at a position deeper than the peak of doping concentration D2'. This makes it easier to increase the thickness of the base region 14 at the f-f' line compared to the thickness of the base region 14 at the g-g' line. In this case, additional dopants may be injected into the base region 14 near the g-g' line.

[0108] Figure 6 is an enlarged view showing another example of the mesa portion 60. In this example of the mesa portion 60, the shape of the lower surface of the base region 14 differs from that of the base region 14 in Figure 4. Other aspects may be the same as in the example in Figure 4.

[0109] In this example, the shape of the lower surface of the base region 14 is a curved surface that is convex toward the upper surface 21 of the semiconductor substrate 10 in the alignment direction. In other words, the lower surface of the base region 14 in this example does not have an inflection point 98. To put it another way, in the XZ cross section, the curved surface 28 is from the position on the lower surface of the base region 14 that is in contact with the gate insulating film 42 to the center of the mesa portion 60 in the alignment direction. Even with such a shape, the area of ​​the storage region 16 in contact with the gate insulating film 42 becomes small. Therefore, the above-mentioned effects can be achieved, such as reducing the gate-collector capacitance.

[0110] When forming the gate insulating film 42 by oxidizing or nitriding the semiconductor substrate 10, or by depositing an oxide film or the like, or by heating after formation, bulk donors around the gate insulating film 42 are incorporated into the gate insulating film 42. Depending on the type of bulk donor and the annealing conditions when forming the base region 14, etc., the way in which bulk donors are incorporated from the mesa region 60 into the gate insulating film 42 will differ.

[0111] Under typical annealing conditions for the base region 14 of an IGBT, if the bulk donor is phosphorus, it is easily incorporated into the gate insulating film 42, and the phosphorus concentration in the portion in contact with the gate insulating film 42 increases. On the other hand, if the bulk donor is antimony, it is not easily incorporated into the gate insulating film 42. In that case, the gate insulating film 42 contains antimony, and the antimony concentration in the portion in contact with the gate insulating film 42 remains low. In the mesa region 60, the antimony concentration may decrease as it approaches the gate insulating film 42. In the base region 14, the antimony concentration may decrease as it approaches the gate insulating film 42. In the storage region 16, the antimony concentration may decrease as it approaches the gate insulating film 42.

[0112] If the bulk donor concentration in the portion in contact with the gate insulating film 42 is low, the junction with the base region 14 may be shaped to be further away from the base region 14. In the portion in contact with the gate insulating film 42, the donor concentration of N-type bulk donor is low, so the doping concentration of the base region 14 near the junction may be relatively low. The doping concentration is the value obtained by subtracting the acceptor concentration from the donor concentration at a certain location. The semiconductor substrate 10 in this example contains antimony as a bulk donor. Therefore, the base region 14 has the shape shown in Figure 6. If the semiconductor substrate 10 contains multiple types of bulk donors, the antimony concentration may be the highest.

[0113] The shape shown in Figure 6 may be formed by adjusting the depth and position of ion implantation. For example, it can be formed by implanting the dopant in the base region 14 deeper as it approaches the gate insulating film 42. The doping concentrations in the f-f' and g-g' lines may be the same as those in Figure 5A or Figure 5B.

[0114] Figure 7 shows the chemical concentration distribution of the bulk donor dopant along the h-h' line in Figure 6. The h-h' line is a line that crosses the gate insulating film 42 in the alignment direction and extends to the base region 14 of the semiconductor substrate 10. In Figure 7, the horizontal axis shows the position in the alignment direction, and the vertical axis shows the chemical concentration of the bulk donor dopant. As described above, the gate insulating film 42 in this example contains the bulk donor dopant (antimony). Hereafter, the bulk donor dopant may be referred to as the bulk dopant.

[0115] Position x0 in Figure 7 is the boundary between the gate insulating film 42 and the gate conductive portion 44. The first position x1 is the position where the gate insulating film 42 and the semiconductor substrate 10 are in contact. Let y1 be the chemical concentration of the bulk dopant at the first position x1. The second position x2 is a position in the gate insulating film 42 that is further from the semiconductor substrate 10 than the first position x1. The second position x2 may be the center of the gate insulating film 42 in the alignment direction, and may be equal to position x0. Let y2 be the chemical concentration of the bulk dopant at the second position x2.

[0116] Concentration y1 may be higher than concentration y2. As described above, the gate insulating film 42 incorporates bulk dopant from the semiconductor substrate 10, so the chemical concentration of bulk dopant at the position in contact with the semiconductor substrate 10 becomes higher. Concentration y1 may be 1.2 times or more, 1.5 times or more, 2 times or more, 5 times or more, or 10 times or more than concentration y2. Concentration y1 may be the maximum value of the bulk dopant chemical concentration of the gate insulating film 42. The chemical concentration of bulk dopant in the gate insulating film 42 may decrease monotonically from the first position x1 to position x0.

[0117] Let y3 be the chemical concentration of the bulk dopant in the base region 14 at the first position x1. Concentration y3 may be lower than concentration y1. As described above, the bulk dopant around the gate insulating film 42 is incorporated into the gate insulating film 42, so concentration y3 becomes lower. Concentration y3 may be lower than concentration y2. Concentration y3 may be lower than the minimum chemical concentration of the bulk dopant in the gate insulating film 42.

[0118] In the semiconductor substrate 10, the chemical concentration of the bulk dopant in the drift region 18 may be higher than the chemical concentration of the bulk dopant at the location in contact with the gate insulating film 42. The chemical concentration of the bulk dopant in the drift region 18 may be the average value of the drift region 18. The location in contact with the gate insulating film 42 may be the location in the base region 14 that is in contact with the gate insulating film 42 (first location x1). In that case, the concentration of the bulk donor will be y3. The above difference in concentration may be 1.5 times or more, 2 times or more, 5 times or more, or 10 times or more.

[0119] Figure 8 shows a first modified example of the mesa portion 60. The semiconductor device 100 in this example has a second conductivity type trench bottom region 109 in addition to the mesa portion 60 shown in Figure 6. The trench bottom region 109 is provided separately from the base region 14. A storage region 16 is provided between the trench bottom region 109 and the base region 14 in this example. That is, the trench bottom region 109 is a floating region that is not electrically connected to the base region 14.

[0120] The trench bottom region 109 is in contact with the lower end of the gate trench section 40. By providing the trench bottom region 109, the electric field at the lower end of the gate trench section 40 can be mitigated. Part of the trench bottom region 109 is located on the upper surface 21 side of the lower end of the gate trench section 40, and the other part is located on the lower surface 23 side of the lower end of the gate trench section 40. The trench bottom region 109 may be in contact with the lower end of the adjacent trench section 150. The trench bottom region 109 may be provided continuously in the arrangement direction from the gate trench section 40 to the adjacent trench section 150.

[0121] Let m4 be the upper end of the trench bottom region 109 in contact with the gate insulating film 42. Let m5 be the upper end of the central trench bottom region 109 in the alignment direction of the mesa portion 60. The upper end m4 may be located closer to the upper surface 21 of the semiconductor substrate 10 than the upper end m5. For the same reasons as the base region 14 described above, the dopant in the trench bottom region 109 diffuses easily near the gate insulating film 42, resulting in the shape shown in Figure 8. This further increases the area of ​​the trench bottom region 109 in contact with the gate insulating film 42. Therefore, the gate-collector capacitance can be further reduced, and the turn-on characteristics can be further improved. Note that even if the storage region 16 is not provided and the portion of the storage region 16 in Figure 8 is the drift region 18, the gate-collector capacitance can still be reduced. The upper end m4 may be located furthest towards the upper surface 21 of the trench bottom region 109. The bulk dopant in this example is also antimony.

[0122] The distance d6 in the depth direction between the upper end m4 and the upper end m5 may be 0.1 μm or more. The larger the distance d6, the smaller the contact area between the gate insulating film 42 and the storage region 16, which can produce the effects described above, such as reducing the gate-collector capacitance. The distance d6 may be 0.2 μm or more, 0.3 μm or more, 0.4 μm or more, or 0.5 μm or more.

[0123] The distance d6 in the depth direction between the upper end m4 and the upper end m5 may be 1.0 μm or less. The distance d1 may be 0.9 μm or less, 0.8 μm or less, 0.7 μm or less, or 0.6 μm or less. The reason why the upper end m5 is recessed towards the lower surface 23 is that, as will be described later, a trench bottom region 109 is formed by injecting a dopant from the bottom of the trench and allowing it to diffuse. However, the upper end m5 does not have to be recessed towards the lower surface 23. In the trench bottom region 109, the antimony concentration may decrease as it approaches the gate insulating film 42. Also, the portion of the gate insulating film 42 in contact with the trench bottom region 109 may contain antimony.

[0124] Let d4 be the thickness of the trench bottom region 109 in contact with the gate insulating film 42. In this example, thickness d4 is the distance between the upper end m4 and the lower end m7 of the trench bottom region 109 at the horizontal position of the upper end m4. Let d5 be the thickness of the central trench bottom region 109 in the direction of arrangement of the mesa portion 60. In this example, thickness d5 is the distance between the upper end m5 and the lower end m6 of the central trench bottom region 109 in the direction of arrangement of the mesa portion 60. Thickness d4 may be greater than thickness d5. The lower end m6 may or may not be recessed towards the upper surface 21 for the same reasons as the upper end m5.

[0125] The upper end of the trench bottom region 109 may include a first curved surface c1 that is convex toward the lower surface 23 of the semiconductor substrate 10 toward the gate insulating film 42 in the alignment direction. Since Figure 8 is a cross-sectional view, the first curved surface c1 is represented by a curve existing on the first curved surface c1. A curved surface being convex downwards means that the line segment connecting two points on the curve existing on the curved surface is always above the curve. In this case, the point between these two points does not necessarily have to include a point where the first derivative is zero. As described above, the bulk dopant is incorporated into the gate insulating film 42 as it approaches it. Therefore, the dopant in the trench bottom region 109 becomes more easily diffused. As a result, it takes the shape shown in Figure 8. The first curved surface c1 of the trench bottom region 109 may be in contact with the gate insulating film 42.

[0126] The upper end of the trench bottom region 109 may include a second curved surface c2 that is convex toward the upper surface 21 of the semiconductor substrate 10 in the alignment direction. Since Figure 8 is a cross-section, the second curved surface c2 is represented by a curve that exists on the second curved surface c2. A curved surface is convex upward if the line segment connecting two points on the curve that exists on the curved surface is always below the curve. In this case, the point where the first derivative is zero does not necessarily have to be included between the two points. In this example, the second curved surface c2 is located closer to the center of the mesa portion 60 in the alignment direction than the first curved surface c1.

[0127] The upper end of the trench bottom region 109 may include a third curved surface c3 that is convex toward the lower surface 23 of the semiconductor substrate 10 in the alignment direction. Since Figure 8 is a cross-section, the third curved surface c3 is represented by a curve on the third curved surface c3. The third curved surface c3 may be located closer to the center of the mesa portion 60 in the alignment direction than the second curved surface c2. In this example, the third curved surface c3 is formed in the center of the mesa portion 60 in the alignment direction.

[0128] The upper end of the trench bottom region 109 may have a first curved surface c1, a second curved surface c2, and a third curved surface c3 in the direction of arrangement, from the gate insulating film 42 toward the adjacent trench portion 150. Since Figure 8 is a cross-section, the upper end of the trench bottom region 109 has a first curved surface c1, a second curved surface c2, and a third curved surface c3 in the direction of arrangement, from the gate insulating film 42 toward the adjacent trench portion 150. Inflection points may be provided between the curves on each of the curved surfaces.

[0129] In the mesa portion 60, the trench bottom region 109 may have the same shape as the portion in contact with the adjacent trench portion 40, even in the portion in contact with the adjacent trench portion 150. When the adjacent trench portion 150 is the gate trench portion 40, the gate-collector capacitance can also be reduced in the adjacent trench portion 150. The shape of the trench bottom region 109 in the XZ cross section may be symmetrical with respect to a line that crosses the center of the mesa portion 60 in the X-axis direction in the depth direction. Furthermore, in other mesa portions 60 where at least one of the trench portions sandwiching the mesa portion 60 is the gate trench portion 40, the shape shown in Figure 8 or the like may be provided.

[0130] Figure 9A shows the doping concentration distribution in the depth direction of the mesa 60. In Figure 9A, the doping concentrations of the f-f' and g-g' lines in Figure 8 are shown. The positions of the f-f' and g-g' lines are the same as in Figure 4. However, in this example, the f-f' and g-g' lines also cross the trench bottom region 109. The emitter region 12, base region 14, and storage region 16 are the same as in Figure 5A, so their explanation is omitted.

[0131] The trench bottom region 109 may have a doping concentration peak. Let D4 be the doping concentration at the peak position of the trench bottom region 109 on the f-f' line. Also, let D4' be the doping concentration at the peak position of the trench bottom region 109 on the g-g' line. Doping concentrations D4 and D4' may be equal. Doping concentration D4 may be less than doping concentration D2 and less than doping concentration D3. As an example, doping concentration D4 may be 1 × 10⁻⁶. 16 / cm 3 In other cases, doping concentration D4 may be higher than doping concentration D3.

[0132] The peak position of the trench bottom region 109 on the f-f' line and the peak position of the trench bottom region 109 on the g-g' line may be equal or different. The position of the upper end m4 may be the position of the PN junction between the accumulation region 16 and the trench bottom region 109 on the g-g' line. The position of the upper end m5 may be the position of the PN junction between the accumulation region 16 and the trench bottom region 109 on the f-f' line. If the accumulation region 16 is not provided, the position of the PN junction between the trench bottom region 109 and the drift region 18 may be the position of the upper end m4 or the upper end m5.

[0133] The position of the lower end m6 may be the position of the PN junction between the trench bottom region 109 and the drift region 18 on the f-f' line. The position of the lower end m7 may be the position of the PN junction between the trench bottom region 109 and the drift region 18 on the g-g' line. The integrated value of the doping concentration in the trench bottom region 109 on the g-g' line may be greater than the integrated value of the doping concentration in the trench bottom region 109 on the f-f' line. Also, if the bulk dopant is antimony, the doping concentration Dd in the drift region 18 may be 95% or more and 100% or less of the antimony chemical concentration.

[0134] Figure 9B shows another example of the first modification of the mesa section 60. In this example, the mesa section 60 has a drift region 18 between the accumulation region 16 and the trench bottom region 109. In other words, the accumulation region 16 and the trench bottom region 109 are not in contact. Other aspects are the same as the modification shown in Figure 8.

[0135] Figure 9C shows another example of the doping concentration distribution in the depth direction of the mesa 60. In Figure 9C, the doping concentrations of the f-f' and g-g' lines in Figure 9B are shown. This example differs from the example shown in Figure 9A in that the high-concentration areas in the accumulation region 16 do not reach the trench bottom region 109, and the trench bottom region 109 forms a PN junction with the drift region 18. That is, this distribution can be formed by performing ion implantation to form the accumulation region 16 at a shallower depth, or by not allowing dopant diffusion to reach deep depths. There may be a position between the accumulation region 16 and the trench bottom region 109 where the doping concentration is equal to the bulk donor doping concentration Dd. In such cases, the positional relationships of each junction, as explained using Figure 9A, still hold.

[0136] Figure 9D shows another example of the first modified form of the mesa section 60. In this example, the mesa section 60 does not have an accumulation region 16. A drift region 18 is provided in the region where the accumulation region 16 was provided in Figure 8. Other aspects are the same as the modified form shown in Figure 8.

[0137] Figure 9E shows another example of the doping concentration distribution in the depth direction of the mesa 60. This example differs from the examples shown in Figures 9A and 9C in that there is no accumulation region 16, and the base region 14 and trench bottom region 109 form PN junctions with the drift region 18. In other words, this distribution can be formed by not performing ion implantation to form the accumulation region 16. Even in this case, the positional relationships of each junction, as explained using Figures 9A and 9C, hold true. Note that even if the trench bottom region 109 is not provided, the relationship of the junction positions between the base region 14 and the drift region 18 may be as in this example.

[0138] Figure 10 shows a second modified example of the mesa portion 60. In this example, the mesa portion 60 has an emitter region 12, a base region 14, a storage region 16, and a trench bottom region 109. The bulk dopant in this example is phosphorus. As described above, under typical IGBT annealing conditions, phosphorus is easily incorporated into the gate insulating film 42, and the phosphorus concentration in the portion in contact with the gate insulating film 42 increases. Therefore, the dopant of the base region 14 and the dopant of the trench bottom region 109 become less likely to diffuse near the gate insulating film 42. As a result, in this example, the lower end of the base region 14 in contact with the gate insulating film 42 is positioned shallower than the lower end of the center of the mesa portion 60. Also, in this example, the upper end of the trench bottom region 109 decreases toward the gate insulating film 42. In other words, the upper end is in contact with the gate insulating film 42 in an upwardly convex curved portion. Therefore, the area of ​​the N-type storage region 16 in contact with the gate insulating film 42 becomes larger. As a result, the gate-collector capacitance increases, leading to a decrease in turn-on characteristics compared to the first modified example shown in Figure 8, or the aforementioned effects becoming insufficient.

[0139] Figure 11 shows a third modified example of the mesa portion 60. The lower end of the base region 14 in this example has the shape shown in Figure 4. The upper end of the trench bottom region 109 in this example has the shape shown in Figure 10. That is, although the bulk dopant in this example is phosphorus, the first end m1 of the base region 14 is made deeper by adjusting the ion implantation of the base region 14. In this example as well, the area of ​​the N-type storage region 16 in contact with the gate insulating film 42 is reduced. As a result, the gate-collector capacitance can be reduced, and compared to the second modified example shown in Figure 10, the turn-on characteristics can be improved and the effects described above can be achieved.

[0140] Figure 12 shows a fourth modified example of the mesa portion 60. The lower end of the base region 14 in this example has the shape shown in Figure 4. The upper end of the trench bottom region 109 in this example has the shape shown in Figure 8. That is, the bulk dopant in this example is antimony, and the first end m1 of the base region 14 is made deeper by adjusting the ion implantation of the base region 14. In this example, the area of ​​the N-type storage region 16 in contact with the gate insulating film 42 is further reduced. Therefore, the gate-collector capacitance can be reduced, and compared to the second modified example shown in Figure 10, the turn-on characteristics can be improved and the above-mentioned effects can be achieved.

[0141] Figure 13 is a diagram showing an example of the manufacturing process for a semiconductor device 100. Figure 13 shows a part of the manufacturing process. The manufacturing process in this example includes a trench formation step S1010, an injection step S1020 for the trench bottom region 109, an injection step S1030 for the storage region 16, an injection step S1040 for the base region 14, and an annealing step S1050.

[0142] Figure 14A is a diagram illustrating the trench formation process S1010. In the trench formation process S1010, a mask with a predetermined pattern is provided on the upper surface 21 of the semiconductor substrate 10, and trenches 46 are formed by etching the semiconductor substrate 10. The bulk dopant of the semiconductor substrate 10 in this example is antimony. From here on, up to the example in Figure 18B, the bulk dopant is antimony unless otherwise specified.

[0143] Figure 14B illustrates the injection process S1020 for the trench bottom region 109. In the injection process S1020 for the trench bottom region 109, the dopant for the trench bottom region 109 is injected into the semiconductor substrate 10 from the bottom of the trench 46. In this example, the dopant is boron.

[0144] Figure 14C illustrates the injection process S1030 for the storage region 16. In the injection process S1030 for the storage region 16, the dopant for the storage region 16 is injected to a predetermined depth from the upper surface 21 of the semiconductor substrate 10. In this example, the dopant is phosphorus.

[0145] Figure 14D illustrates the injection process S1040 for the base region 14. In the injection process S1040 for the base region 14, the dopant for the base region 14 is injected to a predetermined depth from the upper surface 21 of the semiconductor substrate 10. In this example, the depth position of the dopant injected near the trench 46 is deeper than the depth position of the dopant injected into the center of the mesa. In another example, the dose amount of the dopant injected near the trench 46 may be greater than the dose amount of the dopant injected into the center of the mesa. Alternatively, both the depth position and the dose amount may be varied. Furthermore, the process of injecting the dopant into the center of the mesa and the process of injecting the dopant near the trench 46 may be performed separately, including the patterning of the resist, or they may be performed simultaneously. In this example, the dopant is boron.

[0146] Figure 14E illustrates the annealing process S1050. In the annealing process S1050, the gate insulating film 42 and the base region 14, storage region 16, and trench bottom region 109 are formed. In this example, the semiconductor substrate 10 is heated and oxidized to form an oxide film 155 on the top surface 21 and the surface inside the trench 46. The oxide film 155 inside the trench 46 becomes the gate insulating film 42 or dummy insulating film 32. At this time, antimony (bulk dopant) from the surrounding semiconductor substrate 10 is also incorporated into the gate insulating film 42.

[0147] The annealing temperature is, for example, 1100°C or below, or 1050°C or below, or 900°C or above, or 950°C or above. In this case, antimony is less easily incorporated into the gate insulating film 42 compared to phosphorus. Therefore, the concentration of antimony near the gate insulating film 42 is lower compared to the center of the mesa portion 60, etc.

[0148] Meanwhile, annealing the semiconductor substrate 10 diffuses and activates the dopant, forming the base region 14, the storage region 16, and the trench bottom region 109. Because the antimony concentration near the gate insulating film 42 is low, the dopant in the trench bottom region 109 can easily diffuse near the gate insulating film 42. As a result, the upper end of the trench bottom region 109 moves closer to the upper surface 21 as it approaches the gate insulating film 42.

[0149] Because the depth of the dopant injected into the vicinity of the trench 46 is increased in the base region 14, the lower end is formed deeply near the gate insulating film 42. Also, due to the antimony effect described above, the lower end of the base region 14 may be closer to the bottom surface 23 near the gate insulating film 42. The shape of the lower end of the base region 14 and the trench bottom region 109 shown in Figure 14E may be the same as in Figure 12.

[0150] In other cases, the lower end of the base region 14 and the shape of the trench bottom region 109 shown in Figure 11 may be formed. For example, when phosphorus is used as the dopant for the storage region 16 and it is formed at a high concentration, the shape of the boundary with the trench bottom region 109 may be as shown in Figure 11. Also, the bulk dopant of the semiconductor substrate 10 is not limited to antimony. For example, the bulk dopant may be phosphorus. The lower end of the base region 14 is formed deeply near the gate insulating film 42 because the depth position of the dopant injected near the trench 46 is increased. In this case as well, the lower end of the base region 14 and the shape of the trench bottom region 109 shown in Figure 11 may be formed.

[0151] Figure 15A illustrates another example of the injection process S1040 for the base region 14. In this example, the dopant is injected uniformly in the direction of the arrangement of the mesa portions 60.

[0152] Figure 15B illustrates another example of the annealing process S1050. In this example of the annealing process S1050, a semiconductor substrate 10, in which the dopant in the base region 14 of Figure 15A has been uniformly injected, is annealed. The bulk dopant in this example is also antimony. Therefore, the dopant in the base region 14 tends to diffuse near the gate insulating film 42. As a result, the upper end of the base region 14 moves closer to the lower surface 23 as it approaches the gate insulating film 42. The shape of the lower end of the base region 14 and the trench bottom region 109 shown in Figure 15B may be the same as in Figure 8. In other cases, for example, depending on the concentration, element, or location of the accumulation region 16, either the lower end of the base region 14 or the trench bottom region 109 may be formed in the shape shown in Figure 10.

[0153] Figure 16 shows another example of the manufacturing process for the semiconductor device 100. This example differs from the manufacturing process shown in Figure 13 in that the injection process for the storage region 16 (S1050) and the second annealing process (S1060) are performed after the first annealing process (S1040). The first annealing process (S1040) in this example corresponds to the annealing process (S1050) in Figure 13. In other words, it is the same as in Figure 13 except that the dopant injection and formation of the storage region 16 do not occur up to the first annealing process (S1040).

[0154] Figure 17A is a diagram illustrating the implantation process S1050 for the storage region 16 in Figure 16. The base region 14 and the trench bottom region 109 have been formed by the time of the implantation process S1050 for the storage region 16. The shapes of the base region 14 and the trench bottom region 109 in this example are as shown in Figure 12. In the implantation process S1050 for the storage region 16, the dopant for the storage region 16 is implanted from the upper surface 21 of the semiconductor substrate 10 to the depth between the base region 14 and the trench bottom region 109. Note that the oxide film on the upper surface 21 of the mesa portion 60 may be removed before ion implantation.

[0155] Figure 17B is a diagram illustrating the second annealing step S1060 in Figure 16. In the second annealing step S1060, the dopant in the accumulation region 16 is diffused and activated to form the accumulation region 16. The annealing temperature of the second annealing step S1060 is, for example, 1000°C or less. The annealing temperature of the second annealing step S1060 may be lower than the annealing temperature of the first annealing step S1040. The semiconductor device 100 of the embodiment can also be manufactured by this method. The shape of the lower end of the base region 14 and the trench bottom region 109 shown in Figure 17B may be the same as in Figure 12. Alternatively, they may be the same as in Figure 11.

[0156] Figure 18A illustrates another example of the injection process S1050 for the storage region 16 in Figure 16. The shapes of the base region 14 and the trench bottom region 109 in this example are the same as those shown in Figure 8. Other aspects are the same as the example shown in Figure 17A.

[0157] Figure 18B illustrates another example of the second annealing step S1060 in Figure 16. In the second annealing step S1060 of this example, the dopants in the storage region 16 are diffused and activated in the semiconductor substrate 10 of Figure 18A to form the storage region 16. The semiconductor device 100 of the embodiment can also be manufactured by this method. The shape of the lower end of the base region 14 and the trench bottom region 109 shown in Figure 18B may be the same as in Figure 8. In other cases, either the lower end of the base region 14 or the trench bottom region 109 may be formed in the shape shown in Figure 10.

[0158] In each example of the manufacturing method, the adjacent trench portion 150 side (the dummy insulating film 32 side in each example) may have the same shape as the gate insulating film 42 side. That is, the shapes of the base region 14 and the trench bottom region 109 may be symmetrical with respect to a line extending in the depth direction through the center of the mesa portion 60. Note that the trench bottom region 109 may not be formed in any of the examples. Also, the storage region 16 may not be formed.

[0159] In each example of the manufacturing method, it is not essential that the formation of the gate insulating film 42 and the diffusion of the dopant occur in the same annealing step. The gate insulating film 42 may be formed first, and the dopant may be diffused in a later step. Also, when adjusting the ion implantation of the dopant in the base region 14 as shown in Figure 14D, the gate insulating film 42 may be formed after the annealing step of the base region 14. For example, the trench 46 may be formed after the base region 14 is formed, and then the gate insulating film 42 may be formed. The inside of the trench 46 or the top surface 21 may be covered with an oxide film 155 during the ion implantation of each dopant, and this oxide film 155 may become the gate insulating film 42 as is, or it may be removed once during the manufacturing process. The gate conductive portion 44 and interlayer insulating films 38, 48 may be formed inside the trench 46 before or simultaneously with the diffusion of each dopant.

[0160] Figure 19 shows an example of the bb cross-section in Figure 1. The bb cross-section is the XZ plane passing through the edge termination structure 90, the transistor section 70, and the diode section 80. The structures of the transistor section 70 and the diode section 80 are the same as those described in Figures 2 and 3. In Figure 19, the structures of the gate trench section 40, the dummy trench section 30, and the mesa section 60 are shown in a simplified manner.

[0161] In the semiconductor substrate 10, a well region 17 is provided between the edge termination structure 90 and the transistor portion 70. The well region 17 is a P+ type region in contact with the upper surface 21 of the semiconductor substrate 10. The well region 17 may extend to a position deeper than the lower ends of the gate trench portion 40 and the dummy trench portion 30. Parts of the gate trench portion 40 and the dummy trench portion 30 may be located inside the well region 17.

[0162] An interlayer insulating film 38 covering the well region 17 may be provided on the upper surface 21 of the semiconductor substrate 10. Above the interlayer insulating film 38, electrodes and wiring such as an emitter electrode 52 and outer peripheral gate wiring 130 are provided. The emitter electrode 52 extends from above the active portion 160 to above the well region 17. The emitter electrode 52 may be connected to the well region 17 via a contact hole provided in the interlayer insulating film 38.

[0163] The outer gate wiring 130 is positioned between the emitter electrode 52 and the edge termination structure 90. Although the emitter electrode 52 and the outer gate wiring 130 are positioned separately from each other, the gap between the emitter electrode 52 and the outer gate wiring 130 is omitted in Figure 4. The outer gate wiring 130 is electrically insulated from the well region 17 by the interlayer insulating film 38.

[0164] The edge termination structure 90 is provided on the upper surface 21 of the semiconductor substrate 10 between the active portion 160 and the edge of the semiconductor substrate 10. The edge may be any of the edges 162 of the semiconductor substrate 10 in Figure 1. In this specification, the direction from the active portion 160 toward the edge of the semiconductor substrate 10 may be referred to as the first direction. In Figure 19, the positive direction of the X axis is the first direction. However, in other cross-sections, the negative direction of the X axis, the positive direction of the Y axis, or the negative direction of the Y axis may be the first direction.

[0165] The edge termination structure 90 is provided with a plurality of guard rings 92, a plurality of field plates 94, a channel stopper 174, and an interlayer insulating film 38. In the edge termination structure 90, an N-type drift region 18 is provided inside the semiconductor substrate 10. In addition, a P+-type collector region 22 may be provided in the region in contact with the lower surface 23. An N+-type buffer region 20 may be provided between the collector region 22 and the drift region 18.

[0166] The interlayer insulating film 38 is provided on the upper surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 may be made of the same material as the interlayer insulating film 38 of the active portion 160, and may be an oxide film formed by oxidizing the semiconductor substrate 10, or a nitride film formed by nitriding. In this example, the interlayer insulating film 38 covers a part of the adjacent guard rings 92 and the drift region 18 between the guard rings 92.

[0167] Each guard ring 92 may be provided on the upper surface 21 so as to surround the active portion 160. Multiple guard rings 92 may have the function of spreading the depletion layer generated in the active portion 160 to the outside of the semiconductor substrate 10. This prevents electric field concentration inside the semiconductor substrate 10 and improves the breakdown voltage of the semiconductor device 100.

[0168] In this example, the guard ring 92 is a P+ type semiconductor region formed by ion implantation near the upper surface 21. The depth of the bottom of the guard ring 92 may be deeper than the depth of the bottom of the gate trench 40 and the dummy trench 30. The depth of the bottom of the guard ring 92 may be the same as or different from the depth of the bottom of the well region 17.

[0169] The guard ring 92 may be exposed on the upper surface 21 of the semiconductor substrate 10. At least a portion of the guard ring 92 may be in contact with the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. In this example, the upper surface of the guard ring 92 is covered by the interlayer insulating film 38. The shape of the guard ring 92 will be described later.

[0170] The field plate 94 is formed of a metal such as aluminum or a conductive material such as polysilicon. The field plate 94 may also be formed of an aluminum-silicon alloy, such as AlSi or AlSiCu. The field plate 94 may be formed of the same material as the outer gate wiring 130 or the emitter electrode 52. The field plate 94 is provided on the interlayer insulating film 38. In this example, the field plate 94 is connected to the guard ring 92 through through holes provided in the interlayer insulating film 38.

[0171] The channel stopper 174 is provided exposed on the upper surface 21 and side wall near the edge 162 of the semiconductor substrate 10. The channel stopper 174 is an N+ type or P+ type region with a higher doping concentration than the drift region 18. The channel stopper 174 has the function of terminating the depletion layer generated in the active region 160 near the edge 162 of the semiconductor substrate 10.

[0172] In Figure 19, the interlayer insulating film 38 of the transistor section 70, diode section 80, and edge termination structure section 90 is depicted with the same thickness, but the thickness may differ, and the formation process may differ, resulting in different compositions. At least a portion of the field plate 94, outer gate wiring 130, and emitter electrode 52 is covered with a protective film such as polyimide or nitride film, but the protective film is omitted in the drawings of this specification.

[0173] Figure 20 is an enlarged view of the semiconductor substrate 10 near the well region 17 and guard ring 92 in Figure 19. In Figure 20, the field plate 94 and the lower surface 23 of the semiconductor substrate 10 are omitted.

[0174] The first cross-section is defined as a cross-section parallel to both the first direction and the depth direction of the semiconductor substrate 10. Cross-section bb, i.e., the cross-sections in Figures 19 and 20, is an example of the first cross-section. The guard ring 92 has at least one side surface in the first cross-section. In this example, the guard ring 92 has a lower end 120, a first side surface 121, and a second side surface 122 in the first cross-section. The first side surface 121 is the side surface closer to the active part 160 than the lower end 120, and the second side surface 122 is the side surface closer to the edge of the semiconductor substrate 10 than the lower end 120. Since Figure 20 is a cross-section, the side surfaces are shown as curves. The lower end 120 may be the deepest position of the guard ring 92 (a position farther from the upper surface 21).

[0175] The side surface of the guard ring 92 may have one or more inflection points 98 in the first cross-section. An inflection point is a point where the sign of the second derivative of the function changes when the curve is considered as a function of z=f(x) in the XZ coordinate system. The first side surface 121 and the second side surface 122 may each have one or more inflection points 98. In the guard ring 92 of this example, the first side surface 121 and the second side surface 122 each have two inflection points 98. The side surface of the guard ring 92 may be the interface between the guard ring 92 and the drift region 18.

[0176] Let w1 be the width in the first direction of the portion of the guard ring 92 between the inflection point 98 closest to the interlayer insulating film 38 and the interlayer insulating film 38. Also, let w2 be the width of the portion between the inflection point 98 and the lower end 120 of the guard ring 92. If there are multiple inflection points 98, any of the inflection points 98 can be used to define the width w2. The width w1 may be wider than the width w2.

[0177] The area between the guard rings 92 may be an N-type region. In this example, a drift region 18 is provided between the guard rings 92. When the width w1 is wider than the width w2, the difference between the width of the drift region 18 between the guard rings 92 on the upper surface 21 and the width of the drift region 18 at the depth position of the lower end 120 of the guard ring 92 becomes larger. As a result, the electric field distribution near the lower end 120 of the guard ring 92 is further relaxed. Figure 20 schematically shows equipotential lines 262. Guard rings 92 of this shape can be formed by performing multiple ion implantations with different implantation depths and doses.

[0178] The presence of an inflection point 98 in the guard ring 92 makes it easier to increase the width w1. The width w1 may be 1.2 times or more, 1.5 times or more, or 2 times or more than the width w2. The width w1 may be the width of the guard ring 92 at the position of the upper surface 21. The width w2 may be the width of the guard ring 92 on the lower surface 23 side of the center in the depth direction of the guard ring 92. In Figure 20, the position of the lower end 120 in the depth direction of the guard ring 92 is denoted as j1, and the central position in the depth direction of the guard ring 92 is denoted as j2.

[0179] At least one inflection point 98 may be located on the upper surface 21 side of the semiconductor substrate 10 relative to the central position j2 in the depth direction of the guard ring 92. Two or more inflection points 98 may be located on the upper surface 21 side of the central position j2, and three or more inflection points 98 may be located on the upper surface 21 side of the central position j2. In this example, all inflection points 98 are located on the upper surface 21 side of the central position j2.

[0180] Let k1 be the distance from the upper surface 21 to the lower end 120 of the guard ring 92. The inflection point 98 may be located within one-third or one-quarter of the distance k1 in the depth direction from the upper surface 21. Two or more inflection points 98 may be located within one-third or one-quarter of the distance k1 in the depth direction from the upper surface 21. Three or more inflection points 98 may be located within one-third or one-quarter of the distance k1 in the depth direction from the upper surface 21. These relationships of inflection points 98 may hold for each of the multiple guard rings 92. Furthermore, the shape of the guard ring 92 may be symmetrical with respect to a line parallel to the depth direction passing through the lower end 120.

[0181] Figure 21 shows another example of the guard ring 92. The guard ring 92 in this example is formed to a greater depth than the guard ring 92 shown in Figure 20. The guard ring 92 may be formed to a greater depth than the well region 17. Also, its width in the first direction is wider than that of the guard ring 92 shown in Figure 20. The guard ring 92 in this example also has an inflection point 98. Furthermore, the relationship between width w1 and width w2 described above also holds in this example.

[0182] In this example, the guard ring 92 has a first side surface 121 and a second side surface 122 that are arranged asymmetrically. In this example, the second side surface 122 is longer in the first direction than the first side surface 121. Therefore, the inflection point 98 of the first side surface 121 and the inflection point of the second side surface 122 are located at different depth positions.

[0183] The end of the guard ring 92 on the active portion 160 side is designated as the first end 201. In this example, the end of the guard ring 92 on the negative X-axis side is the first end 201. The end of the guard ring 92 on the edge 162 side of the semiconductor substrate 10 is designated as the second end 202. In other words, the second end is the outer peripheral end of the guard ring 92 on the semiconductor substrate 10 side. In this example, the end of the guard ring 92 on the positive X-axis side is the second end 202.

[0184] Let d11 be the distance between the lower end 120 and the first end 201 in a top view. Let d12 be the distance between the lower end 120 and the second end 202 in a top view. In Figure 21, distances d11 and d12 are distances in the X-axis direction. In this example, distance d12 is greater than distance d11. Distance d12 may be 1.2 times or more, 1.5 times or more, 2 times or more, or 5 times or more than distance d11. Distance d12 may be 10 times or less of distance d11.

[0185] In this example, the guard ring 92 is formed by multiple individual guard rings 922, each formed by performing multiple ion implantations with different implantation depths and doses, overlapping in the X-axis direction to form an aggregate, with the envelope of these aggregates forming a single guard ring 92. In Figure 21, the multiple individual guard rings 922 formed by each ion implantation are shown by dotted lines. The guard ring 92 shown in Figure 21 has the shape of an envelope formed by the overlapping of these individual guard rings 922 (VLD: Variable Lateral Doping). A similar shape may be formed by changing the implantation depth in a single ion implantation using a gradient resist, or by changing the density of the resist openings in a single ion implantation and then diffusing and connecting the formed regions. In addition, a high-concentration N+ type region 104 may be provided between a part of the guard ring 92 and the upper surface 21. This ensures resistance to pressure fluctuations due to external charges.

[0186] The guard ring 92 may have an edge curved surface 102. In this example, the side surface of the guard ring 92 has an edge curve between the lower end 120 and the second end 202. In this example, the side surface of the guard ring 92 has an edge curve between the lower end 120 and the first end 201. The edge curved surface 102 will be described later.

[0187] Figure 22 shows another example of the guard ring 92. The side surface of the guard ring 92 in this example also has an inflection point 98. In addition, the side surface of the guard ring 92 in this example has an edge surface 102. The edge surface 102 is a curved surface that is convex toward the upper surface 21 of the semiconductor substrate 10 toward the interlayer insulating film 38. A curved surface being convex upward means that the line segment connecting two points on the curve on the curved surface is always on the lower side of the curve. In this case, the point where the first derivative is zero does not necessarily have to be included between the two points. In the first cross section, the edge surface 102 is represented as a curve on the edge surface 102. In this example, the edge surface 102 is located between the upper surface 21 and the inflection point 98.

[0188] In this example, the side surface of the guard ring 92 between the inflection points 98 is a curved surface that is convex downwards. A curved surface is convex downwards if the line segment connecting two points on the curve that exist on the curved surface is always above the curve. In this case, the point between those two points does not necessarily have to be one where the first derivative is zero.

[0189] The edge surface 102 of the guard ring 92 may be in contact with the interlayer insulating film 38. In the first cross-section of Figure 22, the curve on the edge surface 102 is in contact with the interlayer insulating film 38. In other words, the edge surface 102 may be exposed on the upper surface of the semiconductor substrate 10. The edge surface 102 allows the width w2 to be larger than the width w1, and the electric field distribution near the lower end 120 of the guard ring 92 is further mitigated.

[0190] The position of the inflection point 98 in the depth direction in this example may be the same as the position described in Figure 20. Also, both the first side surface 121 and the second side surface 122 may have an edge surface 102. Multiple guard rings 92 may have edge surfaces 102. Also, the side surface of the well region 17 may have an inflection point 98 and may have an edge surface 102. Furthermore, the guard ring 92 in this example may be symmetrical with respect to a line parallel to the depth direction passing through the lower end 120.

[0191] Figure 23 shows the chemical concentration distribution of the bulk dopant along the i-i' line in Figure 22. The i-i' line crosses the interlayer insulating film 38 in the depth direction and extends to the guard ring 92 of the semiconductor substrate 10. In Figure 23, the horizontal axis indicates the position in the depth direction, and the vertical axis indicates the chemical concentration of the bulk dopant. In this example, the bulk dopant is antimony.

[0192] As explained in the section 60, the incorporation of bulk dopant into the gate insulating film 42 also occurs in the edge termination structure 90. That is, when the semiconductor substrate 10 is oxidized or nitrided to form the interlayer insulating film 38, the bulk dopant around the interlayer insulating film 38 is incorporated into the interlayer insulating film 38. At that time, the way in which the bulk dopant is incorporated into the interlayer insulating film 38 differs depending on the type of bulk dopant and the annealing conditions.

[0193] Under typical annealing conditions for the guard ring 92 of an IGBT, if the bulk dopant is phosphorus, it is easily incorporated into the interlayer insulating film 38, and the phosphorus concentration in the portion in contact with the interlayer insulating film 38 increases. On the other hand, if the bulk dopant is antimony, it is not easily incorporated into the gate insulating film 42. As a result, the antimony concentration decreases near the interlayer insulating film 38. In the region where the antimony concentration has decreased, the dopant of the guard ring 92 diffuses easily, and a guard ring 92 with the shape shown in Figure 22 is formed.

[0194] The semiconductor substrate 10 in this example contains antimony as a bulk dopant. The antimony concentration may decrease as it approaches the interlayer insulating film 38. However, the guard ring 92 with the shape shown in Figure 22 may be formed by adjusting the depth position and dose amount when ion implanting the dopant into the guard ring 92.

[0195] The interlayer insulating film 38 may contain a bulk dopant. In this example, the interlayer insulating film 38 contains antimony. Position x0 in Figure 23 is the end of the interlayer insulating film 38 opposite to the upper surface 21. The first position x1 is the position where the interlayer insulating film 38 and the upper surface 21 of the semiconductor substrate 10 are in contact. Let y1 be the chemical concentration of the bulk dopant in the interlayer insulating film 38 at the first position x1. The second position x2 is a position in the interlayer insulating film 38 that is further from the upper surface 21 of the semiconductor substrate 10 than the first position x1. The second position x2 may be the center of the interlayer insulating film 38 in the depth direction, and may be equal to position x0. Let y2 be the chemical concentration of the bulk dopant at the second position x2.

[0196] Concentration y1 may be higher than concentration y2. As described above, the interlayer insulating film 38 incorporates bulk dopant from the semiconductor substrate 10, so the chemical concentration of bulk dopant at the position in contact with the semiconductor substrate 10 becomes higher. Concentration y1 may be 1.2 times or more, 1.5 times or more, 2 times or more, 5 times or more, or 10 times or more than concentration y2. Concentration y1 may be the maximum value of the bulk dopant chemical concentration of the interlayer insulating film 38. The chemical concentration of bulk dopant in the interlayer insulating film 38 may decrease as it moves away from the upper surface 21 of the semiconductor substrate 10.

[0197] Let y3 be the chemical concentration of the bulk dopant in the guard ring 92 at the first position x1. Concentration y3 may be lower than concentration y1. As described above, the bulk dopant around the interlayer insulating film 38 is incorporated into the interlayer insulating film 38, so concentration y3 is lower. Concentration y3 may be lower than concentration y2. Concentration y3 may be lower than the minimum chemical concentration of the bulk dopant in the interlayer insulating film 38.

[0198] In the semiconductor substrate 10, the chemical concentration of the bulk dopant in the drift region 18 may be higher than the chemical concentration of the bulk dopant at the location in contact with the interlayer insulating film 38. The drift region 18 may be the drift region 18 of the edge termination structure 90. The chemical concentration of the bulk dopant in the drift region 18 may be the average value of the drift region 18. The location in contact with the interlayer insulating film 38 may be the location where the guard ring 92 contacts the gate insulating film 42 (first location x1). In that case, the chemical concentration of the bulk dopant will be y3. The difference in concentration may be 1.5 times or more, 2 times or more, 5 times or more, or 10 times or more.

[0199] Figure 24 shows the guard ring 92 in the comparative example. The bulk dopant in the comparative example is phosphorus. As described above, under general IGBT annealing conditions, the phosphorus of the bulk dopant is not incorporated into the interlayer insulating film 38 at the same chemical concentration as the bulk dopant in the semiconductor substrate 10, and the phosphorus concentration in the portion in contact with the interlayer insulating film 38 increases. Therefore, near the interlayer insulating film 38, the bond with the guard ring 92 is formed on the side closer to the guard ring 92. As a result, the width of the guard ring 92 on the upper surface 21 of the comparative example becomes narrower. Therefore, compared to the example, the difference between the width of the drift region 18 between the guard rings 92 on the upper surface 21 and the width of the drift region 18 at the depth position of the lower end 120 of the guard ring 92 becomes smaller. As a result, the electric field distribution near the lower end 120 of the guard ring 92 is less likely to be relaxed.

[0200] Furthermore, the embodiments of the active portion 160 described in Figures 4 to 12 and the embodiments of the guard ring 92 of the edge termination structure 90 described in Figures 20 to 23 may be combined in any way. In other words, the semiconductor device 100 may have any of the active portion 160 described in Figures 4 to 12 and any of the edge termination structure 90 described in Figures 20 to 23. This makes it possible to improve the turn-on characteristics while mitigating the electric field distribution.

[0201] Figure 25 shows an example of the manufacturing process for the edge termination structure 90. Figure 25 shows a part of the manufacturing process. The manufacturing process in this example includes an injection process S2010 for the guard ring 92 and an annealing process S2020.

[0202] Figure 26A illustrates the injection process S2010 for the guard ring 92. In this example, an interlayer insulating film 38 is formed on the upper surface 21 of the semiconductor substrate 10 prior to the injection process S2010 for the guard ring 92, and an opening is formed in the interlayer insulating film 38. However, the interlayer insulating film 38 may be formed simultaneously with the formation of the guard ring 92, or in a later process than the formation of the guard ring 92.

[0203] In the guard ring 92 injection process S2010, the guard ring 92 dopant is injected into a predetermined position on the semiconductor substrate 10. In this example, the dopant is boron. In Figure 26A, the injection depth is divided into three stages depending on the position in the first direction. In other examples, the dose amount may be varied depending on the position in the first direction, and the injection depth and dose amount may be varied. The type of bulk dopant in this example is not particularly limited. It may be phosphorus or antimony.

[0204] Figure 26B illustrates the annealing process S2020. In the annealing process S2020, the dopant is diffused and activated to form a guard ring 92. In this example, a portion of the dopant diffuses to below the interlayer insulating film 38. The shape of the formed guard ring 92 changes depending on the injection depth and other factors. As a result, the side surface of the guard ring 92 has an inflection point 98.

[0205] The shape of the guard ring 92 shown in Figure 26B may be the same as that in Figure 20. The annealing temperature is, for example, 1100°C or less. In this example, the guard ring 92 does not have an edge curved surface 102, but a guard ring with an edge curved surface 102 may be formed by adjusting the dopant injection depth and dose amount.

[0206] Figure 27A illustrates another example of the injection process S2010 for the guard ring 92. In this example, the injection depth of the dopant in the guard ring 92 injection process S2010 is constant regardless of the position in the first direction. The bulk dopant in this example is antimony. In addition, the interlayer insulating film 38 in this example is formed by oxidizing or nitriding the upper surface 21 of the semiconductor substrate 10.

[0207] Figure 27B illustrates another example of the annealing process S2020. In this example of the annealing process S2020, the semiconductor substrate 10 shown in Figure 27A is annealed. As described above, the antimony concentration is low near the interlayer insulating film 38, so the junction between the guard ring 92 and the drift region 18 is formed far from the guard ring 92. As a result, an inflection point 98 and an edge surface 102 are formed on the side surface of the guard ring 92. The shape of the guard ring 92 shown in Figure 27B may be the same as that in Figure 22. Furthermore, the interlayer insulating film 38 may be formed simultaneously with the formation of the guard ring 92.

[0208] In this example, the interlayer insulating film 38 may be partially or completely removed before ion implantation of the guard ring 92, or partially or completely removed after the formation of the guard ring 92. As a result, the guard ring 92 does not need to be in contact with the interlayer insulating film 38. Even if the interlayer insulating film 38 is removed, the chemical concentration of the bulk dopant in the semiconductor substrate 10 does not change, so a guard ring 92 with the same shape as in Figure 22 is formed. Even if an n-type region different from the drift region 18 is formed adjacent to the guard ring 92 by ion implantation, the guard ring 92 may have the same shape as in Figure 22. The formation of the n-type region may be, for example, by antimony ion implantation.

[0209] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0210] It should be noted that the execution order of operations, procedures, steps, and stages in the apparatus, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be implemented in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, it does not mean that it is essential to perform the operations in that order. [Explanation of symbols]

[0211] 10...Semiconductor substrate, 12...Emitter region, 14...Base region, 15...Contact region, 16...Storage region, 17...Well region, 18...Drift region, 20...Buffer region, 21...Top surface, 22...Collector region, 23...Bottom surface, 24...Collector electrode, 28...Curved surface, 29...Straight section, 30...Dummy trench section, 3 1...Tip section, 32...Dummy insulating film, 34...Dummy conductive section, 38...Interlayer insulating film, 39...Straight section, 40...Gate trench section, 41...Tip section, 42...Gate insulating film, 44...Gate conductive section, 46...Trench, 48...Interlayer insulating film, 52...Emitter electrode, 54...Contact hole, 60...Mesa section, 61...Mesa section, 70...Transistor section, 80...Diode section, 82...Cathode region, 90...Edge termination structure section, 92...Guard ring, 94...Field plate, 98...Inflection point, 100...Semiconductor device, 102...Edge curved surface, 104...High-density region, 109...Trench bottom region, 120...Lower end, 121...First side surface, 122... Second side, 130... Outer periphery gate wiring, 131... Active side gate wiring, 150... Adjacent trench area, 152... Channel area, 155... Oxide film, 160... Active area, 162... Edge, 164... Gate pad, 174... Channel stopper, 201... First end, 202... Second end, 262... Equipotential lines, 922... Individual guard rings

Claims

1. A semiconductor substrate having an upper surface and a lower surface, and provided with a first conductivity type drift region, The semiconductor substrate has an active portion provided on it, An edge termination structure is provided on the semiconductor substrate, between the active portion and the edge of the semiconductor substrate on the upper surface of the semiconductor substrate. Equipped with, The aforementioned edge termination structure is An interlayer insulating film provided on the upper surface of the semiconductor substrate, A second conductive type guard ring is provided on the semiconductor substrate, and at least a portion of it is in contact with the interlayer insulating film on the upper surface of the semiconductor substrate. It has, In a first cross-section parallel to both the first direction from the active portion toward the edge of the semiconductor substrate and the depth direction of the semiconductor substrate, the guard ring has at least one side surface, and the side surface has one or more inflection points. Semiconductor equipment.

2. In the first direction, the portion of the guard ring between the inflection point closest to the interlayer insulating film and the interlayer insulating film is wider than the portion between the inflection point and the lower end of the guard ring. The semiconductor device according to claim 1.

3. In the first cross-section, the guard ring is The bottom edge and The first side surface on the side of the active portion that is closer to the lower end, The second side surface on the edge side of the semiconductor substrate, which is closer to the end than the lower end It has, Each of the first and second surfaces has one or more of the inflection points. The semiconductor device according to claim 1.

4. There is at least one inflection point located on the upper surface side of the semiconductor substrate, rather than the center of the guard ring in the depth direction. The semiconductor device according to claim 1.

5. The side surface of the guard ring has a curved edge that is convex toward the upper surface of the semiconductor substrate toward the interlayer insulating film, The edge curved surface is in contact with the interlayer insulating film. The semiconductor device according to claim 1.

6. A semiconductor substrate having an upper surface and a lower surface, and provided with a first conductivity type drift region, The semiconductor substrate has an active portion provided on it, An edge termination structure is provided on the semiconductor substrate, between the active portion and the edge of the semiconductor substrate on the upper surface of the semiconductor substrate. Equipped with, The aforementioned edge termination structure is An interlayer insulating film provided on the upper surface of the semiconductor substrate, A second conductive type guard ring is provided on the semiconductor substrate, and at least a portion of it is in contact with the interlayer insulating film on the upper surface of the semiconductor substrate. It has, A second conductivity type well region is provided between the active portion and the edge termination structure. The depth of the guard ring is greater than the depth of the well region. The aforementioned guard ring is The first end of the guard ring, which is the end on the active part side, The lower end, which is the deepest position of the guard ring, The guard ring has a second end which is the outer peripheral end of the semiconductor substrate, The distance between the lower end and the second end in a top view of the semiconductor substrate is greater than the distance between the lower end and the first end. Semiconductor equipment.

7. The interface between the guard ring and the drift region has a shape that is convex towards the upper surface between the lower end and the second end. The semiconductor device according to claim 6.

8. The guard ring has the shape of an envelope formed by the overlapping of multiple individual guard rings. The semiconductor device according to claim 6.

9. The semiconductor substrate contains antimony as a bulk dopant. The semiconductor device according to any one of claims 1 to 7.

10. The interlayer insulating film includes the bulk dopant. The semiconductor device according to claim 9.

11. The chemical concentration of the bulk dopant in the interlayer insulating film at a first position in contact with the upper surface of the semiconductor substrate is higher than the chemical concentration of the bulk dopant in the interlayer insulating film at a second position further from the upper surface of the semiconductor substrate than the first position. The semiconductor device according to claim 10.

12. In the semiconductor substrate, the chemical concentration of the bulk dopant in the drift region is higher than the chemical concentration of the bulk dopant at the location in contact with the interlayer insulating film. The semiconductor device according to claim 10.

13. The active portion is A gate trench portion having a gate conductive portion provided on the upper surface side of the semiconductor substrate and located inside the semiconductor substrate, and a gate insulating film that insulates the gate conductive portion and the semiconductor substrate, Adjacent trench portions arranged alongside the gate trench portion in the direction of arrangement, A second conductive base region is provided in the mesa region, which is the region sandwiched between the gate trench and the adjacent trench, It has, The first end, which is the lower end of the base region in contact with the gate insulating film, is positioned deeper than the second end, which is the lower end of the central base region in the arrangement direction of the mesa portion. The semiconductor device according to any one of claims 1 to 8.

14. The shape of the lower surface of the base region in the aforementioned arrangement direction is a curved surface that is convex toward the upper surface of the semiconductor substrate. The semiconductor device according to claim 13.

15. It comprises a second conductive trench bottom region provided separately from the base region and in contact with the lower end of the gate trench portion, The upper end of the trench bottom region in contact with the gate insulating film is located on the upper surface side of the semiconductor substrate, more so than the upper end of the central trench bottom region in the arrangement direction of the mesa portion. The semiconductor device according to claim 13.

16. The upper end of the trench bottom region includes a first curved surface that is convex toward the lower surface side of the semiconductor substrate toward the gate insulating film in the arrangement direction. The semiconductor device according to claim 15.

Images