Semiconductor equipment

Abstract

To reduce the circuit size of semiconductor devices or to improve the driving capability of semiconductor devices. [Solution] A transistor in which the channel region is formed by an oxide semiconductor is used as a pull-down transistor. The oxide semiconductor has a band gap of 2.0 eV or more, preferably 2.5 eV or more, and more preferably 3.0 eV or more. Therefore, hot carrier degradation in the transistor can be suppressed. As a result, the circuit size of the semiconductor device having the pull-down transistor can be reduced. In addition, the gate of the pull-up transistor is made to a floating state by the switching of the transistor. Furthermore, by increasing the purity of the oxide semiconductor, the off-current of the transistor can be reduced to 1 aA / μm (1 × 10⁻¹⁶). -18 It is possible to achieve a value of A / μm or less. As a result, the driving capability of semiconductor devices can be improved.

Claims

1. It has first to ninth transistors, Either the source or the drain of the first transistor is always in contact with the gate signal line. The source or drain of the first transistor is always in contact with the clock signal line. Either the source or the drain of the second transistor is always in contact with the gate signal line. The source or drain of the second transistor is always in electrical contact with the power line. Either the source or the drain of the third transistor is always in contact with the gate signal line. The source or drain of the third transistor, the other of which is always in electrical contact with the power line, The gate of the third transistor is always in contact with the first signal line. Either the source or drain of the fourth transistor is always in contact with the gate of the first transistor. The source or drain of the fourth transistor, the other of which is always in electrical contact with the power line, The gate of the fourth transistor is always in electrical contact with the gate of the second transistor. Either the source or drain of the fifth transistor is always in contact with the gate of the first transistor. The source or drain of the fifth transistor, the other of which is always in contact with the second signal line, The gate of the fifth transistor is always in conductivity with the second signal line. Either the source or drain of the sixth transistor is always in contact with the gate of the first transistor. The source or drain of the sixth transistor is always in electrical contact with the power line. The gate of the sixth transistor is always in conductivity with the first signal line. Either the source or the drain of the seventh transistor is always in electrical contact with the first wiring. The source or drain of the seventh transistor is always in contact with the gate of the second transistor. The gate of the seventh transistor is always in electrical contact with the first wiring. Either the source or the drain of the eighth transistor is always in contact with the gate of the second transistor. The source or drain of the eighth transistor is always in electrical contact with the power line. The gate of the eighth transistor is always in electrical contact with the gate of the first transistor. Either the source or drain of the ninth transistor is always in contact with the gate of the second transistor. The source or drain of the ninth transistor is always in electrical contact with the power line. The gate of the ninth transistor is always in electrical contact with the second signal line in the semiconductor device.

2. It has first to ninth transistors, Either the source or the drain of the first transistor is always in contact with the gate signal line. The source or drain of the first transistor is always in contact with the clock signal line. Either the source or the drain of the second transistor is always in contact with the gate signal line. The source or drain of the second transistor is always in electrical contact with the power line. Either the source or the drain of the third transistor is always in contact with the gate signal line. The source or drain of the third transistor, the other of which is always in electrical contact with the power line, The gate of the third transistor is always in contact with the first signal line. Either the source or drain of the fourth transistor is always in contact with the gate of the first transistor. The source or drain of the fourth transistor, the other of which is always in electrical contact with the power line, The gate of the fourth transistor is always in electrical contact with the gate of the second transistor. Either the source or drain of the fifth transistor is always in contact with the gate of the first transistor. The source or drain of the fifth transistor, the other of which is always in contact with the second signal line, The gate of the fifth transistor is always in conductivity with the second signal line. Either the source or drain of the sixth transistor is always in contact with the gate of the first transistor. The source or drain of the sixth transistor is always in electrical contact with the power line. The gate of the sixth transistor is always in conductivity with the first signal line. Either the source or the drain of the seventh transistor is always in electrical contact with the first wiring. The source or drain of the seventh transistor is always in contact with the gate of the second transistor. The gate of the seventh transistor is always in electrical contact with the first wiring. Either the source or the drain of the eighth transistor is always in contact with the gate of the second transistor. The source or drain of the eighth transistor is always in electrical contact with the power line. The gate of the eighth transistor is always in electrical contact with the gate of the first transistor. Either the source or drain of the ninth transistor is always in contact with the gate of the second transistor. The source or drain of the ninth transistor is always in electrical contact with the power line. The gate of the ninth transistor is always in contact with the second signal line. The W (W is the channel width) / L (L is the channel length) ratio of the first transistor is greater than the W / L ratio of the second transistor. The W / L ratio of the first transistor is greater than the W / L ratio of the fourth transistor. The W / L ratio of the first transistor is greater than the W / L ratio of the fifth transistor. A semiconductor device in which the W / L ratio of the first transistor is greater than the W / L ratio of the sixth transistor.

3. It has first to ninth transistors, Either the source or the drain of the first transistor is always in contact with the gate signal line. The source or drain of the first transistor is always in contact with the clock signal line. Either the source or the drain of the second transistor is always in contact with the gate signal line. The source or drain of the second transistor is always in electrical contact with the power line. Either the source or the drain of the third transistor is always in contact with the gate signal line. The source or drain of the third transistor, the other of which is always in electrical contact with the power line, The gate of the third transistor is always in contact with the first signal line. Either the source or drain of the fourth transistor is always in contact with the gate of the first transistor. The source or drain of the fourth transistor, the other of which is always in electrical contact with the power line, The gate of the fourth transistor is always in electrical contact with the gate of the second transistor. Either the source or drain of the fifth transistor is always in contact with the gate of the first transistor. The source or drain of the fifth transistor, the other of which is always in contact with the second signal line, The gate of the fifth transistor is always in conductivity with the second signal line. Either the source or drain of the sixth transistor is always in contact with the gate of the first transistor. The source or drain of the sixth transistor is always in electrical contact with the power line. The gate of the sixth transistor is always in conductivity with the first signal line. Either the source or the drain of the seventh transistor is always in electrical contact with the first wiring. The source or drain of the seventh transistor is always in contact with the gate of the second transistor. The gate of the seventh transistor is always in electrical contact with the first wiring. Either the source or the drain of the eighth transistor is always in contact with the gate of the second transistor. The source or drain of the eighth transistor is always in electrical contact with the power line. The gate of the eighth transistor is always in electrical contact with the gate of the first transistor. Either the source or drain of the ninth transistor is always in contact with the gate of the second transistor. The source or drain of the ninth transistor is always in electrical contact with the power line. The gate of the ninth transistor is always in contact with the second signal line. The clock signal line has a region with a wiring width smaller than the channel width of the first transistor. The clock signal line is a semiconductor device having a region with a wiring width smaller than the channel width of the fifth transistor.

4. It has first to ninth transistors, Either the source or the drain of the first transistor is always in contact with the gate signal line. The source or drain of the first transistor is always in contact with the clock signal line. Either the source or the drain of the second transistor is always in contact with the gate signal line. The source or drain of the second transistor is always in electrical contact with the power line. Either the source or the drain of the third transistor is always in contact with the gate signal line. The source or drain of the third transistor, the other of which is always in electrical contact with the power line, The gate of the third transistor is always in contact with the first signal line. Either the source or drain of the fourth transistor is always in contact with the gate of the first transistor. The source or drain of the fourth transistor, the other of which is always in electrical contact with the power line, The gate of the fourth transistor is always in electrical contact with the gate of the second transistor. Either the source or drain of the fifth transistor is always in contact with the gate of the first transistor. The source or drain of the fifth transistor, the other of which is always in contact with the second signal line, The gate of the fifth transistor is always in conductivity with the second signal line. Either the source or drain of the sixth transistor is always in contact with the gate of the first transistor. The source or drain of the sixth transistor is always in electrical contact with the power line. The gate of the sixth transistor is always in conductivity with the first signal line. Either the source or the drain of the seventh transistor is always in electrical contact with the first wiring. The source or drain of the seventh transistor is always in contact with the gate of the second transistor. The gate of the seventh transistor is always in electrical contact with the first wiring. Either the source or the drain of the eighth transistor is always in contact with the gate of the second transistor. The source or drain of the eighth transistor is always in electrical contact with the power line. The gate of the eighth transistor is always in electrical contact with the gate of the first transistor. Either the source or drain of the ninth transistor is always in contact with the gate of the second transistor. The source or drain of the ninth transistor is always in electrical contact with the power line. The gate of the ninth transistor is always in contact with the second signal line. The W (W is the channel width) / L (L is the channel length) ratio of the first transistor is greater than the W / L ratio of the second transistor. The W / L ratio of the first transistor is greater than the W / L ratio of the fourth transistor. The W / L ratio of the first transistor is greater than the W / L ratio of the fifth transistor. The W / L ratio of the first transistor is greater than the W / L ratio of the sixth transistor. The clock signal line has a region with a wiring width smaller than the channel width of the first transistor. The clock signal line is a semiconductor device having a region with a wiring width smaller than the channel width of the fifth transistor.

5. It has first to ninth transistors, Either the source or the drain of the first transistor is always in contact with the gate signal line. The source or drain of the first transistor is always in contact with the clock signal line. Either the source or the drain of the second transistor is always in contact with the gate signal line. The source or drain of the second transistor is always in electrical contact with the power line. Either the source or the drain of the third transistor is always in contact with the gate signal line. The source or drain of the third transistor, the other of which is always in electrical contact with the power line, The gate of the third transistor is always in contact with the first signal line. Either the source or drain of the fourth transistor is always in contact with the gate of the first transistor. The source or drain of the fourth transistor, the other of which is always in electrical contact with the power line, The gate of the fourth transistor is always in electrical contact with the gate of the second transistor. Either the source or drain of the fifth transistor is always in contact with the gate of the first transistor. The source or drain of the fifth transistor, the other of which is always in contact with the second signal line, The gate of the fifth transistor is always in conductivity with the second signal line. Either the source or drain of the sixth transistor is always in contact with the gate of the first transistor. The source or drain of the sixth transistor is always in electrical contact with the power line. The gate of the sixth transistor is always in conductivity with the first signal line. Either the source or the drain of the seventh transistor is always in electrical contact with the first wiring. The source or drain of the seventh transistor is always in contact with the gate of the second transistor. The gate of the seventh transistor is always in electrical contact with the first wiring. Either the source or the drain of the eighth transistor is always in contact with the gate of the second transistor. The source or drain of the eighth transistor is always in electrical contact with the power line. The gate of the eighth transistor is always in electrical contact with the gate of the first transistor. Either the source or drain of the ninth transistor is always in contact with the gate of the second transistor. The source or drain of the ninth transistor is always in electrical contact with the power line. The gate of the ninth transistor is always in contact with the second signal line. At least one of the first to ninth transistors is a semiconductor device having an oxide semiconductor in its channel-forming region.

6. It has first to ninth transistors, Either the source or the drain of the first transistor is always in contact with the gate signal line. The source or drain of the first transistor is always in contact with the clock signal line. Either the source or the drain of the second transistor is always in contact with the gate signal line. The source or drain of the second transistor is always in electrical contact with the power line. Either the source or the drain of the third transistor is always in contact with the gate signal line. The source or drain of the third transistor, the other of which is always in electrical contact with the power line, The gate of the third transistor is always in contact with the first signal line. Either the source or drain of the fourth transistor is always in contact with the gate of the first transistor. The source or drain of the fourth transistor, the other of which is always in electrical contact with the power line, The gate of the fourth transistor is always in electrical contact with the gate of the second transistor. Either the source or drain of the fifth transistor is always in contact with the gate of the first transistor. The source or drain of the fifth transistor, the other of which is always in contact with the second signal line, The gate of the fifth transistor is always in conductivity with the second signal line. Either the source or drain of the sixth transistor is always in contact with the gate of the first transistor. The source or drain of the sixth transistor is always in electrical contact with the power line. The gate of the sixth transistor is always in conductivity with the first signal line. Either the source or the drain of the seventh transistor is always in electrical contact with the first wiring. The source or drain of the seventh transistor is always in contact with the gate of the second transistor. The gate of the seventh transistor is always in electrical contact with the first wiring. Either the source or the drain of the eighth transistor is always in contact with the gate of the second transistor. The source or drain of the eighth transistor is always in electrical contact with the power line. The gate of the eighth transistor is always in electrical contact with the gate of the first transistor. Either the source or drain of the ninth transistor is always in contact with the gate of the second transistor. The source or drain of the ninth transistor is always in electrical contact with the power line. The gate of the ninth transistor is always in contact with the second signal line. The W (W is the channel width) / L (L is the channel length) ratio of the first transistor is greater than the W / L ratio of the second transistor. The W / L ratio of the first transistor is greater than the W / L ratio of the fourth transistor. The W / L ratio of the first transistor is greater than the W / L ratio of the fifth transistor. The W / L ratio of the first transistor is greater than the W / L ratio of the sixth transistor. At least one of the first to ninth transistors is a semiconductor device having an oxide semiconductor in its channel-forming region.

7. It has first to ninth transistors, Either the source or the drain of the first transistor is always in contact with the gate signal line. The source or drain of the first transistor is always in contact with the clock signal line. Either the source or the drain of the second transistor is always in contact with the gate signal line. The source or drain of the second transistor is always in electrical contact with the power line. Either the source or the drain of the third transistor is always in contact with the gate signal line. The source or drain of the third transistor, the other of which is always in electrical contact with the power line, The gate of the third transistor is always in contact with the first signal line. Either the source or drain of the fourth transistor is always in contact with the gate of the first transistor. The source or drain of the fourth transistor, the other of which is always in electrical contact with the power line, The gate of the fourth transistor is always in electrical contact with the gate of the second transistor. Either the source or drain of the fifth transistor is always in contact with the gate of the first transistor. The source or drain of the fifth transistor, the other of which is always in contact with the second signal line, The gate of the fifth transistor is always in conductivity with the second signal line. Either the source or drain of the sixth transistor is always in contact with the gate of the first transistor. The source or drain of the sixth transistor is always in electrical contact with the power line. The gate of the sixth transistor is always in conductivity with the first signal line. Either the source or the drain of the seventh transistor is always in electrical contact with the first wiring. The source or drain of the seventh transistor is always in contact with the gate of the second transistor. The gate of the seventh transistor is always in electrical contact with the first wiring. Either the source or the drain of the eighth transistor is always in contact with the gate of the second transistor. The source or drain of the eighth transistor is always in electrical contact with the power line. The gate of the eighth transistor is always in electrical contact with the gate of the first transistor. Either the source or drain of the ninth transistor is always in contact with the gate of the second transistor. The source or drain of the ninth transistor is always in electrical contact with the power line. The gate of the ninth transistor is always in contact with the second signal line. The clock signal line has a region with a wiring width smaller than the channel width of the first transistor. The clock signal line has a region with a wiring width smaller than the channel width of the fifth transistor. At least one of the first to ninth transistors is a semiconductor device having an oxide semiconductor in its channel-forming region.

8. It has first to ninth transistors, Either the source or the drain of the first transistor is always in contact with the gate signal line. The source or drain of the first transistor is always in contact with the clock signal line. Either the source or the drain of the second transistor is always in contact with the gate signal line. The source or drain of the second transistor is always in electrical contact with the power line. Either the source or the drain of the third transistor is always in contact with the gate signal line. The source or drain of the third transistor, the other of which is always in electrical contact with the power line, The gate of the third transistor is always in contact with the first signal line. Either the source or drain of the fourth transistor is always in contact with the gate of the first transistor. The source or drain of the fourth transistor, the other of which is always in electrical contact with the power line, The gate of the fourth transistor is always in electrical contact with the gate of the second transistor. Either the source or drain of the fifth transistor is always in contact with the gate of the first transistor. The source or drain of the fifth transistor, the other of which is always in contact with the second signal line, The gate of the fifth transistor is always in conductivity with the second signal line. Either the source or drain of the sixth transistor is always in contact with the gate of the first transistor. The source or drain of the sixth transistor is always in electrical contact with the power line. The gate of the sixth transistor is always in conductivity with the first signal line. Either the source or the drain of the seventh transistor is always in electrical contact with the first wiring. The source or drain of the seventh transistor is always in contact with the gate of the second transistor. The gate of the seventh transistor is always in electrical contact with the first wiring. Either the source or the drain of the eighth transistor is always in contact with the gate of the second transistor. The source or drain of the eighth transistor is always in electrical contact with the power line. The gate of the eighth transistor is always in electrical contact with the gate of the first transistor. Either the source or drain of the ninth transistor is always in contact with the gate of the second transistor. The source or drain of the ninth transistor is always in electrical contact with the power line. The gate of the ninth transistor is always in contact with the second signal line. The W (W is the channel width) / L (L is the channel length) ratio of the first transistor is greater than the W / L ratio of the second transistor. The W / L ratio of the first transistor is greater than the W / L ratio of the fourth transistor. The W / L ratio of the first transistor is greater than the W / L ratio of the fifth transistor. The W / L ratio of the first transistor is greater than the W / L ratio of the sixth transistor. The clock signal line has a region with a wiring width smaller than the channel width of the first transistor. The clock signal line has a region with a wiring width smaller than the channel width of the fifth transistor. At least one of the first to ninth transistors is a semiconductor device having an oxide semiconductor in its channel-forming region.

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