LED array

Abstract

This provides a novel method for growing and subsequently fabricating μLED arrays. [Solution] A method for manufacturing a light-emitting diode (LED) array comprises the steps of forming a semiconductor layer 100 of a group III nitride material, and forming a dielectric mask layer 104 covering the semiconductor layer, wherein the dielectric mask layer comprises the steps of forming an array of holes penetrating the dielectric mask layer, each exposing a region of the semiconductor layer, and growing an LED structure (108) in each of the holes.

Description

Technical Field

[0001] The present invention relates to a light emitting diode (LED) and a method of manufacturing an LED array. The present invention has specific applications to an array of LEDs on the micrometer scale.

Background Art

[0002] There is a significantly increasing demand for the development of micro-sized LEDs, or even more specifically, III-nitride light emitting diodes (LEDs) on the micrometer scale, also referred to as micro LEDs (μLEDs). Micro LEDs are a major component for new generation displays and visible light communication (VLC) applications. III-nitride μLEDs exhibit several unique characteristics for display applications compared to organic light emitting diodes (OLEDs) and liquid crystal displays (LCDs). Unlike LCDs, III-nitride microdisplays with μLEDs as the main component are self-emissive. Monochrome displays using μLEDs exhibit high resolution, high efficiency, and high contrast ratios. OLEDs are typically operated at current densities several orders of magnitude lower than semiconductor LEDs in order to maintain a reasonable lifespan. As a result, the luminance of OLEDs is relatively low, typically 3000 cd / m 2 for full-color displays, while III-nitride μLEDs exhibit a luminance higher than 10 5 cd / m 2 . Naturally, III-nitride μLEDs inherently exhibit a long operating lifespan and chemical robustness in comparison to OLEDs. Therefore, III-nitride μLEDs are expected to potentially replace LCDs and OLEDs for high-resolution and high-brightness displays in a wide range of applications in the near future, such as smartphones. In addition to display applications, μLEDs exhibit a significantly reduced junction capacitance as a result of their reduced dimensions compared to area LEDs, thus potentially leading to high-speed transmission with GHz modulation bandwidth in VLC applications.

[0003] Currently, III nitride μLEDs are fabricated exclusively by a combination of standard photolithography and subsequent dry etching processes on standard III nitride LED wafers, similar to the fabrication of conventional wide-area LEDs with typical device areas of 300 μm × 300 μm or larger (ZYFan, JYLin, and HXJiang, J.Phys.D:Appl.Phys.41, 094001 (2008); HXJiang and JYLin, Optical Express 21, A476 (2013)). The only major difference in device fabrication between wide-area LEDs and μLEDs is device dimensions. Typically, the diameter of a μLED ranges from 50 μm to several micrometers.

[0004] III. There are several fundamental problems with current methods for fabricating nitride μLEDs. Firstly, dry etching processes such as inductively coupled plasma (ICP) dry etching have been widely used in the semiconductor industry to define both broad-area LED mesas and μLED mesas. Therefore, surface and sidewall damage introduced by the dry etching process significantly increases the non-radioactive recombination rate (F. Olivier, A. Daami, C. Licitra, and F. Templier, Appl. Phys. Lett. 111, 022104 (2017); SSKonoplev, KA Bulashevich, and SY Karpov, Phys. Status Solidi A 215, 1700508 (2017); W. Chen, G. Hu, J. Lin, J. Jiang, M. Liu, Y. Yang, G. Hu, Y. Lin, Z. Wu, Y. Liu, and B. Zhang, Appl. Phys. Express 8, 032102 (2015); C.-M. Yang, D.-S. Kim, YSPark, J.-H.Lee, YSLee, and J.-H.Lee, Opt. Photonics J.2, 185 (2012); Y. Zhang, E. Guo, Z. Li, T. Wei, J. Li, X. Ye, and G. Wang, IEEE Photonics Technol. Lett. 24, 243 (2012); P. Zuo, B. Zhao, S. Yan, G. Yue, H. Yang, Y. Li, H. Wu, Y. Jiang, H. Jia, J. Zhou, and H. Chen, Opt. Quantum Electron. 48, 1 (2016). This problem is more serious in LEDs with reduced dimensions, and especially in μLEDs with a large surface area-to-bulk volume ratio. To date, all reports have shown that the peak external quantum efficiency (EQE) decreases as the size of the μLED decreases (D. Hwang, A. Mughal, CD Pynn, S. Nakamura, and SPDen Baars, Appl. Phys. Express 10, 032101 (2017); P. Zuo, B. Zhao, S. Yan, G. Yue, H. Yang, Y. Li, H. Wu, Y. Jiang, H. Jia, J. Zhou, and H. Chen, Opt. Quantum Electron.48, 1(2016);F.Olivier, S.Tirano, L.Dupre', B.Aventurier, C.Largeron, and F.Templier, J.Lumin.191, 112(2017);P.Tia n, JJDMcKendry, J.Herrnsdorf, S.Watson, R.Ferreira, IMWatson, E.Gu, AEKelly, and MDDawson, Appl.Phys.Lett.105, 171107 (2014)).

[0005] This reduction is attributed to mesa sidewall damage from dry etching, which creates sidewall defects for surface recombination and non-radioactive recombination. Sidewall passivation using dielectric materials can reduce the effects of plasma-induced damage in LEDs to some extent, but the improvement is minimal, even when advanced atomic layer deposition (ALD) is used for surface passivation instead of standard plasma-enhanced chemical vapor deposition (PECVD).

[0006] Secondly, current methods, which inevitably involve the use of a combination of standard photolithography and subsequent dry etching processes, typically lead to enormous waste of epiwafer material. For example, to fabricate a μLED array with a diameter of 12 μm and a pitch distance of 15 μm (reducing the pitch distance further with current photolithography methods is extremely difficult), 50% of the epiwafer material needs to be removed by etching, which means that 50% of the epiwafer is wasted.

[0007] Thirdly, future smart displays, including microdisplays, and VLCs, will need to operate with ultra-high response speeds. Therefore, ultra-fast electrical channels are required for the interconnection between the LED driver transistors and the individual LED components.

[0008] Current μLED arrays are electrically connected by n-GaN in III nitride LED wafers, in which case the typical fabrication procedure for a μLED array is to use a dry etching process to etch the LED wafer down to the n-GaN, which is the sole electrical channel for connecting all the μLEDs. [Overview of the project] [Problems that the invention aims to solve]

[0009] Therefore, to address these issues, it is desirable to develop different methods for growing and subsequently fabricating μLED arrays. To meet the demands of industry, any new methods must be built on a scalable foundation. [Means for solving the problem]

[0010] The present invention provides a method for manufacturing a light-emitting diode (LED) array, comprising the steps of: forming a semiconductor layer of a group III nitride material; forming a dielectric mask layer covering the semiconductor layer, wherein the dielectric mask layer has an array of holes penetrating the dielectric mask layer, each exposing a region of the semiconductor layer; and growing an LED structure in each of the holes.

[0011] LED structures can be grown on exposed areas of the semiconductor layer. Growth is generally upward because growth does not occur from the dielectric sidewalls of the holes. Upward growth of LED structures within holes can therefore result in layered LED structures, each of which is generally flat or planar and of substantially constant thickness.

[0012] The semiconductor layer may be formed on a substrate of, for example, a group III nitride such as GaN, or on a substrate of sapphire, silicon (Si) silicon carbide (SiC), or glass.

[0013] The step of growing an LED structure within each pore may include the step of growing an n-type layer, at least one active layer, and a p-type layer within each pore. The at least one active layer may be between the n-type layer and the p-type layer. The at least one active layer may include at least one quantum well layer, and may include multiple quantum well layers. These may be formed from, for example, InGaN, or another suitable group III nitride material. The n-type and p-type layers may further consist of group III nitride materials such as GaN, InGaN, or AlGaN.

[0014] At least one active layer may have an upper surface that is below the upper surface of the dielectric layer. If only one quantum well layer is present, the upper surface is the upper surface of that quantum well layer. If multiple quantum well layers are present, the upper surface is the upper surface of the uppermost quantum well layer. The upward direction can be defined as the direction of growth of the semiconductor layer and / or the LED structure.

[0015] The steps of forming a dielectric mask layer may include growing a layer of dielectric material, forming a mask to cover the dielectric mask layer, for example using photolithography, and etching an array of holes into the layer of dielectric material using the mask. Alternatively, the dielectric layer may be grown around areas where holes will later be formed, for example by a mask formed by photolithography with subsequent growth and / or etching, during the growth of the dielectric layer.

[0016] The method may further include the step of etching each of the exposed areas of the semiconductor layer before the step of growing the LED structure in each of the holes.

[0017] The semiconductor layer can provide a common contact for all aspects of the LED structure.

[0018] The semiconductor layer can be doped. For example, the semiconductor layer may include a single layer of n-type or p-type group III nitride material. Alternatively, the semiconductor layer may include a first sublayer and a second sublayer, and the heterointerface between the first and second sublayers is configured to form a two-dimensional charge carrier gas at the heterointerface. The sublayers may form buffer and barrier layers. The two-dimensional charge carrier gas may be, for example, a two-dimensional electron gas (2DEG). A two-dimensional hole gas (2DHG) may also be used, but typically these have lower charge carrier density and / or mobility. For example, a heterostructure including a GaN layer and an AlGaN or InGaN layer, or more generally, two layers of AlGaN with different Al content, or two layers of InGaN with different In content, is two layers. It is well known that a 2DEG can be formed at the interface between the two layers, and that the electron density within the 2DEG varies depending on several factors, including the Al content of the AlGaN layer or the In content of the InGaN layer. Other group III nitride heterointerfaces can be used with the same effect.

[0019] The method may further include the step of forming one or more contact layer areas covering an LED structure. The contact layer areas, or each of them, may extend beyond at least one of the LED structures to be in electrical contact with at least one of the LED structures. The contact layer areas may be electrically insulated from each other.

[0020] The holes, and therefore the LED structures, can be arranged in a regular array. The array may be a square array, or it may be a rectangular or hexagonal array. The array may have a pitch of 4 μm to 500 μm, i.e., the distance between the centers of each nearest pair of holes or LEDs. The holes, and therefore the LED structures, may have a maximum diameter of 1 to 500 μm, or 5 to 500 μm.

[0021] The present invention further provides for manufacturing an LED display including an LED array according to the present invention.

[0022] The present invention further provides an LED array including a semiconductor layer, a dielectric layer having an array of holes extending beyond and through the semiconductor layer, and LED devices formed in each of the holes.

[0023] The present invention further provides an LED display including the LED array according to the present invention.

Brief Description of the Drawings

[0024] [Figure 1] FIG. 1a is a diagram showing an as-grown template formed in the process according to the first embodiment of the present invention. FIG. 1b is a diagram showing the template of FIG. 1a with a masking pattern formed in the mask layer of the template. FIG. 1c is a diagram showing the template of FIG. 1a with micro-LEDs grown in the holes within the mask layer. FIG. 1d is a diagram showing the template of FIG. 1c with electrical contacts formed on the template. [Figure 2] FIG. 2a is a diagram showing an as-grown template formed in the process according to the second embodiment of the present invention. FIG. 2b is a diagram showing the template of FIG. 2a with a masking pattern formed in the mask layer of the template. FIG. 2c is a diagram showing the template of FIG. 2a with micro-LEDs grown in the holes within the mask layer. FIG. 2d is a diagram showing the template of FIG. 2c with electrical contacts formed on the template. [Figure 3] FIG. 22 is a cross-sectional view through the LED structure of the template of FIG. 2d. [Figure 4] FIG. 25 is a diagram of a scanning electron microscope image of an LED array according to an embodiment of the present invention. [Figure 5]This figure shows the electroluminescence spectrum of an LED array according to an embodiment of the present invention. [Figure 6] This figure shows the variation in the internal quantum efficiency of the embodiment of the present invention as a function of the LED diameter. [Modes for carrying out the invention]

[0025] Referring to Figure 1a, in the first embodiment of the present invention, a semiconductor layer, for example, a standard An n-type GaN (n-GaN) layer 100 is initially grown on a substrate 102. The substrate 102 may be a GaN substrate, or any other heterogeneous substrate such as sapphire, silicon (Si), silicon carbide (SiC), or even glass. The GaN layer 100 can be grown by any standard GaN growth method, using either metal-organic vapor phase epitaxial (MOVPE) or molecular beam epitaxial (MBE), or any other suitable growth method. The resulting "grown n-GaN template" may have a thickness greater than 10 μm, but typically the thickness is in the range of 500 nm to 10 μm. Subsequently, a dielectric layer 104, such as silicon dioxide (SiO2) or silicon nitride (SiN), or any other suitable dielectric material, is deposited on the n-GaN layer 100 by PECVD or any other suitable deposition method. The thickness of the dielectric layer may be in the range of 20 nm to 500 μm.

[0026] Referring to Figure 1b, an array of holes 106 is then formed within the dielectric layer 104. The holes 106 are typically on a micrometer scale and are therefore referred to as microholes. This can be done by means of photolithography and then an etching process (which may be dry etching or wet etching). The use of photolithography is advantageous because it allows the holes, and therefore the LEDs formed within them, to be formed precisely with the desired position, shape, and size. In forming the microholes 106, the dielectric layer 104 is etched through its entire thickness to the upper surface of the n-GaN layer 100. The microhole diameter can be 1 μm to 500 μm, or 3 μm to 500 μm, and the pitch distance, i.e., the distance between the centers of the closest adjacent microholes, can be, for example, 4 μm to 500 μm. Further etching of the n-GaN layer 100, only within the micro-hole areas, can be performed using the remaining dielectric layer 104 as a mask. The n-GaN etching depth can range from zero (meaning no GaN etching) to 10 μm, depending on the n-GaN layer thickness. Typically, the optimal etching method or conditions will differ for the n-GaN layer compared to the dielectric layer. For example, SF6 etching can be used to etch the dielectric layer 104 but not the n-GaN layer 100. Therefore, etching all paths through the dielectric layer 104 and stopping at the upper surface of the semiconductor layer 100 is relatively easy to achieve. This also has advantages for the quality of the LED structure grown within the holes 106.

[0027] In the shown embodiment, the hole 106 has a rounded, specifically circular cross-section, but other cross-sections, such as oval or square, may be used.

[0028] Next, referring to Figure 1c, a standard III nitride LED structure is grown on the exposed area of ​​the GaN layer 100. However, since only discrete areas of the GaN layer 100 are exposed by the dielectric layer or micropores 106 in the mask, the LED structure is formed as an array of discrete LEDs 108 separated by the remaining portions of the dielectric layer 104 between the micropores 106. The LED structure 108 is grown by either MOVPE or MBE, or any other suitable growth method. Growth occurs upward from the exposed area of ​​the GaN (or other semiconductor) layer and not from the sidewalls of the holes 106. Therefore, a layered LED structure can be built up inside each of the holes 106, and each layer is substantially flat or planar. The LED structure may include an n-GaN layer 110, an active region 112, and then a final p-doped GaN layer 114. The active region 112 may include an InGaN prelayer, an InGaN-based multiple quantum well (MQW), and a thin p-type AlGaN layer (not shown) as a blocking layer. An example of an LED structure is described in more detail below with reference to Figure 3. As mentioned above, due to the dielectric mask 104, the LED structure forms a μLED array as shown in Figure 1c. As shown, it can only be grown in the micropores 106.

[0029] It is important that the uppermost layer of InGaN MQW112 does not extend above the upper surface of the dielectric layer 104, as this can cause a short-circuit effect after the template is fabricated as the final μLED array. It is also important that the overgrown n-GaN 110 within each micro-pore region is in direct contact with the n-GaN layer 100 in the unetched portion of the template below the dielectric mask 104, so that all individual μLEDs are electrically connected to one another by the n-GaN layer 100 in the unetched portion below the dielectric mask 104.

[0030] Referring to Figure 1d, once the LED array structure is completed, further device fabrication is carried out, including the formation of electrical contacts for the array. For example, an upper contact layer 116 may be formed above the dielectric mask layer 104 and above the upper p-GaN layer of each individual micro-LED device 108. The upper contact layer 116 therefore forms a common p-contact for all of the LED devices 108. The upper contact layer 116 may be formed from ITO or a Ni / Au alloy. An anode 118 may then be formed on the p-contact layer 116. For example, a portion of the dielectric layer 104 may be removed by etching, and then a portion of the LED structure on the etched dielectric layer section may be further etched down to the n-GaN, thereby exposing a region 120 of the n-GaN 100, and a cathode 122 may be formed on that exposed region 120 of the n-GaN.

[0031] When an LED array is used in a display, a continuous contact layer 116 can be replaced by several separate contact layer areas, each covering a different group of LED structures 108. Each group may contain only one LED structure 108, or it may contain multiple LED structures, for example, two, three, or four. The contact layer areas are electrically isolated from each other, for example, by being spaced apart. This allows each group of LED structures to be addressable, i.e., to be switched on and off independently of others. Specifically, each contact layer area may be connected to a switching device such that each LED or group of LEDs forms a display that forms pixels. Precise control of the location, size, and shape of the LED structures provided by photolithography is important in ensuring that the contact layer areas are correctly aligned with the LED structures so that those LED structures can be individually addressed.

[0032] Since overgrowth of the LED structure occurs only within the microporous region 106, it was found that the growth rate during the formation of the LED device is significantly increased, approximately four times faster in some cases, compared to growth on a planar template without any patterning features under the same conditions.

[0033] It will be recognized that various modifications are possible to the embodiments described above. For example, in one modification, the structure is reversed, and the p-GaN layer is grown on the substrate and covered with a dielectric layer, and then the p-GaN layer of the LED device 108 is formed first, followed by a multiple quantum well layer, and then the n-GaN layer. The n-contact layer is then formed above the upper surface of the dielectric layer in place of the p-contact layer, and the positions of the anode and cathode are reversed.

[0034] In the configurations shown in Figures 1a to 1d, the overgrown n-GaN 110 within the micropores 106 allows all individual μLEDs 108 to interact with each other through the n-GaN layer 100. To be electrically connected, the unetched portion of the n-GaN layer 100 below the dielectric mask 104 must coincide with the n-GaN. Instead of using the unetched portion of the n-GaN 100 below the dielectric mask 104 as an electrically connected channel, in a further embodiment, a group III nitride heterostructure with a two-dimensional electron gas (2DEG) in the heterojunction is used as the semiconductor layer instead of the n-GaN layer. In this embodiment, a standard AlGaN / GaN HEMT structure is used. The electron gas (2DEG) with high sheet carried density and high electron mobility, formed at the interface between the AlGaN barrier and the GaN buffer of the HEMT structure, is used as an electrically connected channel.

[0035] Referring to Figures 2a to 2d, to manufacture such a device, a standard AlGaN / GaN HEMT structure is first grown on GaN, a substrate, or any dissimilar substrate such as sapphire, Si, SiC, or even glass, by any standard GaN growth method, using either MOVPE or MBE or any other epitaxial method. Specifically, in this embodiment, a GaN layer 200 forming a buffer layer is grown on a substrate 202, and then an AlGaN layer 201 forming a barrier layer is grown on the GaN layer 200. This structure is referred to herein as the “grown HEMT template”. Subsequently, a dielectric layer 204, such as SiO2 or SiN, or any other dielectric material, with a thickness ranging from 2 nm to 500 μm, is deposited on the grown HEMT template by PECVD or any other suitable deposition method. Subsequently, by means of photolithography and then an etching process (which may be dry etching or wet etching), the dielectric layer 204 is etched down to the surface of the HEMT structure to form a micro-hole array 206 within the dielectric layer 204, in which case the micro-hole diameter may range from a few μm to 500 μm, and the pitch distance between adjacent hole centers may range from 10 μm to 500 μm. Further etching of the grown HEMT within the micro-hole area may be performed using the remaining area of ​​the dielectric layer 204 as a mask. The etching depth of the grown HEMT may range from zero (meaning no etching at all) to 10 μm, depending on the AlGaN barrier position of the grown HEMT template. However, generally, the etching will extend downward to at least as far as the heterointerface between the two layers 200, 201 of the grown HEMT structure, so as to give good electrical contact between each of the LED structures and 2DEG.

[0036] Next, a standard III nitride LED structure is grown on a patterned HEMT template with a dielectric mask characterized by micropores, by either the MOVPE or MBE method, or any other epitaxial method. This may include, for example, growing an n-GaN layer, an InGaN prelayer, an InGaN-based MQW as the active region, and then a thin p-type AlGaN as a blocking layer, and then the final p-doped GaN. Due to the dielectric mask, the LED structure grows only within the micropores 206, forming discrete micro-LED devices 208 within the micropores, as shown in Figure 2c.

[0037] Similar to the embodiments shown in Figures 1a to 1d, the important point is that the upper surface of the InGaN MQW212 should be below the upper surface of the dielectric layer 204 to avoid short-circuit effects after it has been fabricated as the final μLED array.

[0038] Referring to Figure 3, the LED structures in the LED arrays in Figures 1a to 1d and 2a to 2d can have any suitable structure, but in one example, those LED structures The structure may include an n-GaN layer 310, an InGaN prelayer 316 formed above the n-GaN layer 310, several InGaN quantum well layers 312 formed above the prelayer 316, a p-doped blocking layer 318, for example, p-AlGaN, and then a p-GaN layer 314. It will be recognized that this structure can be varied in several ways. As noted above, it is preferable that the upper surface of the uppermost of the quantum well layers 312 is below the upper surface of the dielectric layer. It is even more preferable that the upper surface of the blocking layer 318 is below the upper surface of the dielectric layer.

[0039] Another important point is that the overgrown n-GaN in the micro-pore area directly contacts the interface between the AlGaN barrier and GaN buffer of the initially grown HEMT structure in the unetched portion below the dielectric mask 204, so that all individual μLEDs are electrically connected by a 2DEG formed at the interface between the AlGaN barrier and GaN buffer of the HEMT structure (i.e., the unetched portion) below the dielectric mask. Once the LED structure is complete, any suitable standard device fabrication can be carried out as in the embodiments of Figures 1a to 1d, each device containing several individual μLED components as shown in Figure 2d, in which case all individual μLEDs 208, separated by the remaining dielectric mask 204 to eliminate short circuits in each device, share a common p-contact 216.

[0040] In the embodiments shown in Figures 2a to 2d, it should be noted that selective etching of the dielectric mask 204 may be required prior to any standard LED fabrication step in order to expose a portion of the surface of the HEMT structure, in which case the cathode contact 222 is fabricated on the exposed HEMT surface, as shown in Figure 2d. The selective etching may be dry etching or wet etching.

[0041] As an example, Figure 4 shows a typical scanning microscope image of a μLED array epiwafer manufactured as described above, where each μLED has a diameter of 40 μm.

[0042] As an example, Figure 5 shows the electroluminescence spectrum of a μLED with a diameter of 40 μm as a function of the injection current.

[0043] Figure 6 shows the internal quantum efficiency (IQE) of a μLED formed as described above, measured as a function of the μLED diameter. This figure shows that the IQE of the LED increases by decreasing the diameter of the μLED. The result differs from the results of all previous μLEDs fabricated using conventional methods. This suggests that the method described above avoids dry etching-induced sidewall damage, which typically occurs during conventional fabrication processes.

Claims

1. A method for manufacturing a light-emitting diode (LED) array, comprising the steps of: forming a semiconductor layer of a group III nitride material; forming a dielectric mask layer covering the semiconductor layer, wherein the dielectric mask layer has an array of holes penetrating the dielectric mask layer, each exposing a portion of the semiconductor layer; and growing an LED structure in each of the holes.

2. The method according to claim 1, wherein the step of growing an LED structure in each of the holes includes the step of growing an n-type layer, at least one active layer, and a p-type layer in each of the holes.

3. The method according to claim 1 or 2, wherein the at least one active layer has an upper surface that is below the upper surface of the dielectric layer.

4. The method according to any one of claims 1 to 3, wherein the step of forming the dielectric mask layer includes the steps of growing a layer of dielectric material and etching the array of holes into the layer of dielectric material.

5. The method according to any one of claims 1 to 4, further comprising the step of etching each of the exposed areas of the semiconductor layer before the step of growing the LED structure in each of the holes.

6. The method according to any one of claims 1 to 5, wherein the semiconductor layer provides common contact to all of the LED structure.

7. The method according to any one of claims 1 to 6, wherein the semiconductor layer is doped.

8. The method according to any one of claims 1 to 6, wherein the semiconductor layer comprises a first sublayer and a second sublayer, and the heterointerface between the first sublayer and the second sublayer is configured to form a two-dimensional charge carrier gas.

9. The method according to any one of claims 1 to 8, wherein the LED structure is a microLED structure, and the array is a regular array having a pitch of 4 μm to 500 μm.

10. The method according to any one of claims 1 to 9, further comprising the step of forming a plurality of contact layer regions covering the LED structure, wherein each of the contact layer regions makes electrical contact with each group of the LED structure.

11. A method for manufacturing an LED display, comprising the steps of: manufacturing an LED array including the mask layer and the LED structure by the method according to any one of claims 1 to 10; and manufacturing an LED display including the LED array.

12. An LED array comprising a semiconductor layer, a dielectric layer having an array of holes extending above the semiconductor layer and penetrating the dielectric layer, and an LED device formed in each of the holes.

13. The LED array according to claim 12, wherein each of the LED devices includes an n-type layer, at least one active layer, and a p-type layer.

14. The LED array according to claim 12 or 13, wherein the at least one active layer has an upper surface that is below the upper surface of the dielectric layer.

15. The LED array according to any one of claims 12 to 14, wherein the semiconductor layer provides common contact to all of the LED structures.

16. The LED array according to any one of claims 12 to 15, wherein the semiconductor layer is doped.

17. The LED array according to any one of claims 12 to 15, wherein the semiconductor layer comprises a first sublayer and a second sublayer, and the heterointerface between the first sublayer and the second sublayer is configured to form a two-dimensional charge carrier gas.

18. The LED array according to any one of claims 12 to 17, wherein the LED structure is a microLED structure, and the array is a regular array having a pitch of 4 μm to 500 μm.

19. The LED array according to any one of claims 12 to 18, further comprising a plurality of contact layer regions extending beyond the LED structure, each of which contact layer regions is in electrical contact with each group of the LED structures.

20. An LED display comprising an LED array according to any one of claims 12 to 19.

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