Charge / discharge control circuit, charge / discharge control device, and battery device

Abstract

Suppresses current consumption during over-discharge. [Solution] The charge / discharge control circuit 30 comprises a positive power input terminal C1 connected to the positive terminal of the battery 11, a negative power input terminal C2 connected to the negative terminal of the battery 11, a reference voltage source 71 that supplies a reference voltage, an over-discharge detection ladder circuit A11 connected between the positive power input terminal C1 and the negative power input terminal C2, an over-discharge detection comparator circuit 61 that incorporates at least a part of the reference voltage source that supplies the same voltage as the reference voltage and detects the over-discharge state based on the output from the over-discharge detection ladder circuit A11, and a logic circuit 62 that controls the on / off state of the internal circuit and the discharge control FET 21 in accordance with the over-discharge detection signal output from the over-discharge detection comparator circuit 61.

Description

Technical Field

[0001] The present disclosure relates to a charge-discharge control circuit, a charge-discharge control device, and a battery device.

Background Art

[0002] A charge-discharge control circuit for controlling the charge and discharge of a battery is known (see, for example, Patent Document 1). In the charge-discharge control circuit, over-discharge control and over-charge control are performed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the conventional circuit as described above, there is a problem that the current consumption in the over-discharge state of the charge-discharge control circuit is large. For example, in the conventional circuit, after transitioning to the over-discharge state, in order to reduce the current consumption, circuits that are not used in the over-discharge state, such as an over-charge detection circuit and an over-current detection circuit, are turned off (OFF), but some circuits such as a bias circuit and a reference voltage circuit (Vref circuit) are on (ON) and operating. Therefore, when the battery pack is stored, the battery is consumed by the current flowing through these circuits, and the storage life is shortened.

[0005] The present disclosure has been made in consideration of such circumstances, and an object thereof is to provide a charge-discharge control circuit, a charge-discharge control device, and a battery device that can suppress the current consumption in the over-discharge state.

Means for Solving the Problems

[0006] One embodiment is a charge / discharge control circuit comprising: a positive power input terminal connected to the positive terminal of a battery; a negative power input terminal connected to the negative terminal of the battery; a reference voltage source that supplies a reference voltage; an over-discharge detection ladder circuit connected between the positive power input terminal and the negative power input terminal; an over-discharge detection comparator circuit that incorporates at least a part of the reference voltage source that supplies the same voltage as the reference voltage and detects an over-discharge state based on the output from the over-discharge detection ladder circuit; and a logic circuit that controls the on / off state of an internal circuit and a discharge control FET in accordance with an over-discharge detection signal output from the over-discharge detection comparator circuit. [Effects of the Invention]

[0007] According to this disclosure, the current consumption in an over-discharge state can be suppressed in a charge / discharge control circuit, a charge / discharge control device, and a battery device. [Brief explanation of the drawing]

[0008] [Figure 1] This figure shows an example configuration of a charge / discharge control circuit, a charge / discharge control device, and a battery device according to the first embodiment, as well as a first state of the battery device. [Figure 2] This figure shows the second state of the battery device according to the first embodiment. [Figure 3] This figure shows an example configuration of a comparator circuit for detecting over-discharge according to the first embodiment. [Figure 4] This figure shows an example configuration of a charge / discharge control circuit, a charge / discharge control device, and a battery device according to the second embodiment, as well as a diagram showing the first state of the battery device. [Figure 5] This figure shows the second state of the battery device according to the second embodiment. [Figure 6] This figure shows an example configuration of a comparator circuit and bias circuit for over-discharge detection according to the second embodiment. [Figure 7] This figure shows an example configuration of a charge / discharge control circuit, a charge / discharge control device, and a battery device related to a comparative example, as well as a diagram of the first state of the battery device. [Figure 8]It is a diagram showing the second state of the battery device according to the comparative example. [Figure 9A] It is a diagram showing the switch switching state in the normal state of the amplifier and the reference voltage source according to the comparative example. [Figure 9B] It is a diagram showing the switch switching state in the over-discharge state of the amplifier and the reference voltage source according to the comparative example. [Figure 10] It is a diagram showing a configuration example of the over-discharge detection comparator circuit according to the comparative example.

Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

[0010] (First Embodiment) The first embodiment will be described.

[0011] [Battery Device] FIG. 1 is a diagram showing a configuration example of the charge-discharge control circuit 30, the charge-discharge control device 20, and the battery device 10 according to the first embodiment and the first state of the battery device 10.

[0012] The battery device 10 includes a charge-discharge control device 20 and a battery 11. The charge-discharge control device 20 includes a charge-discharge control circuit 30, a discharge control FET (Field Effect Transistor) 21, and a charge control FET 22. Also, FIG. 1 shows a load 13, an external positive terminal C11, and an external negative terminal C12.

[0013] The charge-discharge control device 20 controls the charge and discharge of the battery 11. The discharge control FET 21 controls discharge. The charge control FET 22 controls charging.

[0014] The charge / discharge control circuit 30 includes an over-discharge detection ladder circuit A11 having resistors 51 and 52, a bias circuit 35, an over-discharge detection comparator circuit 61 incorporating a reference voltage source for a reference voltage Vref, a logic circuit 62, a reference voltage source 71, an amplifier 72, an over-current detection ladder resistor 53, and various detection circuits 73. Here, the various detection circuits 73 are a collective representation of various detection circuits which are examples of internal circuits for the sake of convenience in explanation, and may further include internal circuits other than the detection circuits.

[0015] The charge / discharge control circuit 30 further includes a positive power supply input terminal C1 which is a terminal of voltage VDD, a negative power supply input terminal C2 which is a terminal of voltage VSS, an external voltage input terminal C4 which is a terminal of voltage VM, a discharge control FET gate connection terminal C5 which is a terminal of voltage VDO, and a charge control FET gate connection terminal C6 which is a terminal of voltage VCO.

[0016] <Circuit connection relationship, etc.> Between the positive and negative terminals of the battery 11, in the order from the positive terminal to the negative terminal, an external positive terminal C11, a load 13, an external negative terminal C12, a charge control FET 22, and a discharge control FET 21 are connected. Here, the source (S) of the charge control FET 22 is connected to the load 13 via the external negative terminal C12, the drain (D) of the charge control FET 22 is connected to the drain (D) of the discharge control FET 21, and the source (S) of the discharge control FET 21 is connected to the negative terminal of the battery 11.

[0017] The positive power supply input terminal C1 is connected to the positive terminal of the battery 11. The negative power supply input terminal C2 is connected to the negative terminal of the battery 11. The external voltage input terminal C4 is connected to the source (S) of the charge control FET 22. The discharge control FET gate connection terminal C5 is connected to the gate (G) of the discharge control FET 21. The charge control FET gate connection terminal C6 is connected to the gate (G) of the charge control FET 22.

[0018] The over-discharge detection ladder circuit A11 is connected between the positive power input terminal C1 and the negative power input terminal C2. In the over-discharge detection ladder circuit A11, resistors 51 and 52 are connected in series between the positive power input terminal C1 and the negative power input terminal C2. The point between resistor 51 and resistor 52 is connected to the input terminal of the over-discharge detection comparator circuit 61. A voltage m_od is input to the input terminal of the over-discharge detection comparator circuit 61. The voltage m_od is the output voltage of the over-discharge detection ladder circuit A11. The output terminal of the over-discharge detection comparator circuit 61 is connected to the input terminal of the logic circuit 62.

[0019] The output terminal of the reference voltage source 71 is connected to the positive input terminal of the amplifier 72. The output terminal of amplifier 72 is connected to various detection circuits 73. Furthermore, the output terminal of amplifier 72 is connected to the negative input terminal of amplifier 72. An overcurrent detection ladder resistor 53 is connected at a point between the output terminal of the amplifier 72 and the various detection circuits 73.

[0020] Here, a reference voltage Vref is supplied from the output terminal of the reference voltage source 71. Then, the voltage Vref is supplied from the output terminal of amplifier 72.

[0021] The logic circuit 62 controls the on / off state of the internal circuit and the discharge control FET 21 in accordance with the over-discharge detection signal output from the over-discharge detection comparator circuit 61. In this embodiment, the logic circuit 62 controls the on / off states of the reference voltage source 71, the amplifier 72, the ladder resistor 53 for overcurrent detection, the various detection circuits 73, and the bias circuit 35. Furthermore, the logic circuit 62 controls the discharge control FET 21, for example, turning off the discharge control FET 21 and turning on the charge control FET 22 in an over-discharge state.

[0022] In this embodiment, although a detailed explanation is omitted, the logic circuit 62 may control the on / off state of the internal circuit and the discharge control FET 21 in response to an overcharge detection signal from an overcharge detection circuit (not shown). In this case, the logic circuit 62 controls the charge control FET 22, for example, turning on the discharge control FET 21 and turning off the charge control FET 22 in an overcharge state. In this embodiment, details of the connection of the bias circuit 35 are omitted from the illustration and description. The bias circuit 35 supplies a bias voltage to the internal circuit.

[0023] <First state according to the first embodiment> Figure 1 shows the first state of the battery device 10. The first state is the normal state. The logic circuit 62 is in its normal state. The logic circuit 62 controls the reference voltage source 71, amplifier 72, overcurrent detection ladder resistor 53, various detection circuits 73, and bias circuit 35 to the ON state. In addition, the overdischarge detection ladder circuit A11 and the overdischarge detection comparator circuit 61 are also in the ON state. In the over-discharge detection comparator circuit 61, the output terminal is in a released state when the voltage m_od at the input terminal is not in an over-discharge state, and a release signal is output to the logic circuit 62.

[0024] <Second state according to the first embodiment> Figure 2 shows the second state of the battery device 10 according to the first embodiment. The second state is a state where the device has changed from a normal state to an over-discharged state. In the over-discharge detection comparator circuit 61, when the voltage m_od at the input terminal enters an over-discharge state, the output terminal enters a detection state and outputs a detection signal to the logic circuit 62. The logic circuit 62 enters an over-discharge state. The logic circuit 62 controls the bias circuit 35, reference voltage source 71, amplifier 72, overcurrent detection ladder resistor 53, and various detection circuits 73 to the OFF state.

[0025] Thus, in this embodiment, a comparator with a built-in voltage Vref is used as the over-discharge detection comparator circuit 61. When the over-discharge detection comparator circuit 61 detects an over-discharge, the logic circuit 62 turns off all circuits other than the over-discharge detection circuit (in this embodiment, the over-discharge detection comparator circuit 61 and the over-discharge detection ladder circuit A11). This reduces current consumption compared to, for example, conventional circuits.

[0026] Figure 3 shows an example configuration of the over-discharge detection comparator circuit 61 according to the first embodiment. The over-discharge detection comparator circuit 61 is composed of a depletion-type NMOS transistor 231, an enhancement-type NMOS transistor 232, an enhancement-type PMOS transistor 233, and a depletion-type NMOS transistor 234.

[0027] In the depletion-type NMOS transistor 231, the drain (D) is connected to the voltage VDD, and the source (S) and gate (G) are connected. In the enhancement-type NMOS transistor 232, the source (S) is grounded and the gate (G) is connected to the input terminal of the voltage m_od. The source (S) of the depletion-type NMOS transistor 231 is connected to the drain (D) of the enhancement-type NMOS transistor 232, and this connection point is connected to the gate (G) of the enhancement-type PMOS transistor 233.

[0028] Here, a reference voltage circuit 211, which is an internal reference voltage source, is formed from a depletion-type NMOS transistor 231 and an enhancement-type NMOS transistor 232. The reference voltage circuit 211 supplies a reference voltage, Vref.

[0029] In the enhancement-type PMOS transistor 233, the source (S) is connected to the voltage VDD. In the depletion-type NMOS transistor 234, the source (S) and gate (G) are connected and grounded. The drain (D) of the enhancement-type PMOS transistor 233 is connected to the drain (D) of the depletion-type NMOS transistor 234, and this connection point is connected to the output terminal.

[0030] Thus, in this embodiment, the over-discharge detection comparator circuit 61 includes a reference voltage source. This reference voltage source is composed of a depletion-type NMOS transistor 231 and an enhancement-type NMOS transistor 232.

[0031] [Regarding the first embodiment] As described above, the charge / discharge control circuit 30, charge / discharge control device 20, and battery device 10 according to this embodiment can suppress current consumption in an over-discharge state. In the charge / discharge control circuit 30, charge / discharge control device 20, and battery device 10 according to this embodiment, an over-discharge detection circuit is configured using an over-discharge detection comparator circuit 61 having a built-in reference voltage source, and other internal circuits are activated by an over-discharge release signal. With this configuration, the bias circuit 35, reference voltage source 71, amplifier 72, overcurrent detection ladder resistor 53, and various detection circuits 73 can be turned off in the over-discharge state, so for example, the current consumption in the over-discharge state can be reduced compared to conventional methods. Therefore, in this embodiment, the shelf life of the battery pack can be extended. Furthermore, in this embodiment, the control of the reference voltage source circuit can be simplified. Also, in this embodiment, the control logic size can be reduced.

[0032] (Second Embodiment) A second embodiment will be described.

[0033] [Battery device] Figure 4 shows an example configuration of the charge / discharge control circuit 30A, charge / discharge control device 20A, and battery device 10A according to the second embodiment, as well as the first state of the battery device 10A. The battery device 10A according to this embodiment differs from the example in Figure 1 of the first embodiment in that it includes an over-discharge detection comparator circuit 61A and a bias circuit 35A instead of the over-discharge detection comparator circuit 61 and bias circuit 35 of the first embodiment, and is otherwise similar. In this embodiment, for the sake of explanation, the same reference numerals are used for components similar to those in the example shown in Figure 1 according to the first embodiment, and detailed explanations are omitted.

[0034] In this embodiment, the over-discharge detection comparator circuit 61A is connected to the BP terminal C31 and BN terminal C32 of the bias circuit 35A. The BP terminal C31 supplies voltage VBP, which is the gate-source voltage for the PMOS current mirror. The BN terminal C32 provides the voltage VBN, which is the gate-source voltage for the NMOS current mirror.

[0035] <First state according to the second embodiment> Figure 4 shows the first state of the battery device 10A. The first state is the normal state. In the first state, similar to the first state according to the first embodiment (example in Figure 1), the logic circuit 62 controls the bias circuit 35A, reference voltage source 71, amplifier 72, overcurrent detection ladder resistor 53, and various detection circuits 73 to be in the ON state.

[0036] <Second state according to the second embodiment> Figure 5 shows the second state of the battery device 10A according to the second embodiment. In the second state according to this embodiment, the difference from the second state according to the first embodiment (example in Figure 2) is that the bias circuit 35A is in the ON state.

[0037] Figure 6 shows an example configuration of the over-discharge detection comparator circuit 61A and bias circuit 35A according to the second embodiment. The over-discharge detection comparator circuit 61A is composed of an enhancement-type PMOS transistor 331, an enhancement-type NMOS transistor 332, an enhancement-type PMOS transistor 333, and an enhancement-type NMOS transistor 334.

[0038] In the enhancement-type PMOS transistor 331, the source (S) is connected to the voltage VDD, and the gate (G) is connected to the BP terminal C31 of the bias circuit 35A. In the enhancement-type NMOS transistor 332, the source (S) is grounded and the gate (G) is connected to the input terminal of the voltage m_od. The drain (D) of enhancement-type PMOS transistor 331 is connected to the drain (D) of enhancement-type NMOS transistor 332, and this connection point is connected to the gate (G) of enhancement-type PMOS transistor 333.

[0039] In the enhancement-type PMOS transistor 333, the source (S) is connected to the voltage VDD. In the enhancement-type NMOS transistor 334, the source (S) is grounded, and the gate (G) is connected to the BN terminal C32 of the bias circuit 35A. The drain (D) of enhancement-type PMOS transistor 333 and the drain (D) of enhancement-type NMOS transistor 334 are connected, and this connection point is connected to the output terminal.

[0040] The bias circuit 35A is composed of an enhancement-type PMOS transistor 381, a depletion-type NMOS transistor 382, ​​an enhancement-type PMOS transistor 383, and an enhancement-type NMOS transistor 384.

[0041] In the enhancement-type PMOS transistor 381, the source (S) is connected to the voltage VDD, and the source (S) is connected to the gate (G). In the depletion-type NMOS transistor 382, ​​the source (S) and gate (G) are connected and grounded. The drain (D) and gate (G) of the enhancement-type PMOS transistor 381 are connected to the drain (D) of the depletion-type NMOS transistor 382, ​​and this connection point is connected to the BP terminal C31.

[0042] In the enhancement-type PMOS transistor 383, the source (S) is connected to the voltage VDD, and the gate (G) is connected to the BP terminal C31. In the enhancement-type NMOS transistor 384, the source (S) is grounded, and the drain (D) and gate (G) are connected. The drain (D) of enhancement-type PMOS transistor 383 and the drain (D) and gate (G) of enhancement-type NMOS transistor 384 are connected, and these connection points are connected to the BN terminal C32.

[0043] In this embodiment, a reference voltage circuit (a circuit combining circuit section 311 and circuit section 361), which is an internal reference voltage source, is formed from the enhancement-type NMOS transistor 332 of the over-discharge detection comparator circuit 61A and the depletion-type NMOS transistor 382 of the bias circuit 35A. The reference voltage circuit supplies a reference voltage, Vref.

[0044] Thus, in this embodiment, the comparator circuit (over-discharge detection comparator circuit 61A) has a different configuration compared to the first embodiment. In other words, in this embodiment, the over-discharge detection comparator circuit 61A includes an enhancement-type NMOS transistor 332 as part of the reference voltage source. The reference voltage source is composed of the enhancement-type NMOS transistor 332 and the depletion-type NMOS transistor 382 of the bias circuit 35A.

[0045] In this example, the constant current source (NDTr) of the bias circuit 35A is used as a constant current source (in this example, the constant current source of the amplification stage) for the voltage Vref comparator circuit (over-discharge detection comparator circuit 61A) by current mirroring. In this example, for instance, compared to conventional designs, the current is reduced by the amount that the reference voltage source 71 can be turned off during an over-discharge state. Furthermore, the constant current source in the amplification stage of the over-discharge detection comparator circuit 61A is current-mirrored from the bias circuit 35A. As a result, in this example, a low-power current source can be realized with a small transistor, leading to a reduction in mounting area. However, in this example, compared to the first embodiment, the bias circuit 35A is activated in the over-discharge state, which increases the current path and thus the power consumption.

[0046] [Regarding the second embodiment] As described above, the charge / discharge control circuit 30A, charge / discharge control device 20A, and battery device 10A according to this embodiment can suppress current consumption in an over-discharge state. In the charge / discharge control circuit 30A, charge / discharge control device 20A, and battery device 10A according to this embodiment, an over-discharge detection circuit is configured using an over-discharge detection comparator circuit 61 having a built-in reference voltage source utilizing a bias circuit 35A, and other internal circuits are activated by an over-discharge release signal. With this configuration, the reference voltage source 71, amplifier 72, overcurrent detection ladder resistor 53, and various detection circuits 73 can be turned off in the over-discharge state, so for example, the current consumption in the over-discharge state can be reduced compared to conventional methods. Therefore, in this embodiment, the shelf life of the battery pack can be extended. Furthermore, in this embodiment, the control of the reference voltage source circuit can be simplified. Also, in this embodiment, the control logic size can be reduced. In this embodiment, unlike the first embodiment, the bias circuit 35A remains ON during the over-discharge state.

[0047] [Explanation of the comparative example] A comparative example will be explained with reference to Figures 7-8, 9A and 9B, and 10. For the sake of clarity, Figures 7 and 8 use the same reference numerals for components as those in Figures 1 and 2.

[0048] Figure 7 shows an example configuration of the charge / discharge control circuit 330, charge / discharge control device 320, and battery device 310 according to a comparative example, as well as the first state of the battery device 310. In the comparative example battery device 310, the configuration of the over-discharge detection comparator circuit 661 differs from that of the example in Figure 1, and it also includes a switch 411. Switch 411 switches between the input terminal connected to the voltage Vref of the reference voltage source 71 and the input terminal connected to the voltage Vref of the output terminal of amplifier 72, connecting one of these input terminals to the output terminal. The over-discharge detection comparator circuit 661 receives the voltage at the point between resistors 51 and 52 of the over-discharge detection ladder circuit A11 (voltage m_od) and the voltage at the output terminal of switch 411 (voltage Vref), and outputs a signal to the logic circuit 62 according to the result of comparing these two voltages.

[0049] <First state related to the comparative example> Figure 7 shows the first state of the battery device 310. The first state is the normal state. The first state is the same as the first state shown in Figure 1, except for the difference in components (such as the switching of switch 411) compared to the configuration shown in Figure 1. Switch 411 is switched to accept the voltage (voltage Vref) at the output terminal of amplifier 72 as input.

[0050] <Second state related to the comparative example> Figure 8 shows the second state of the battery device 310 according to the comparative example. The second state is the state when the system changes from the normal state to the over-discharge state. The over-discharge detection comparator circuit 661 outputs a detection signal to the logic circuit 62. The logic circuit 62 enters an over-discharge state. Switch 411 can be switched to accept the voltage Vref of the reference voltage source 71 as input. The logic circuit 62 controls the amplifier 72, the ladder resistor 53 for overcurrent detection, and the various detection circuits 73 to the OFF state.

[0051] Thus, in the comparative example, when an over-discharge condition occurs, the voltage Vref supplied from the output terminal (voltage follower) of amplifier 72 is switched to the voltage Vref supplied from the output terminal of reference voltage source 71. Also, in the comparative example, when an over-discharge condition occurs, circuits other than the over-discharge detection circuit (in this example, the over-discharge detection comparator circuit 661, the reference voltage source 71, and the bias circuit 35) are turned off to reduce current consumption.

[0052] Figure 9A shows the switch switching state of the amplifier 72 and reference voltage source 71 in the normal state according to the comparative example. In this example, the circuit portions of the amplifier 72 and the reference voltage source 71 are configured using a depletion-type NMOS transistor 731, a depletion-type NMOS transistor 732, an enhancement-type NMOS transistor 733, a switch 771, a switch 772, and a resistor 751.

[0053] Here, the circuit portion of the reference voltage source 71 is composed of a circuit portion 711 consisting of a depletion-type NMOS transistor 732 and an enhancement-type NMOS transistor 733. Furthermore, switch 411 is composed of switches 771 and 772.

[0054] Figure 9B shows the switch switching state of the amplifier 72 and reference voltage source 71 in an over-discharge state according to the comparative example. In the example shown in Figure 9A and the example shown in Figure 9B, the on / off states of switches 771 and 772 are switched. In other words, when switching from the normal state shown in Figure 9A to the over-discharge state shown in Figure 9B, the state switches from using the output from amplifier 72 as the reference voltage to using the output from reference voltage source 71 as the reference voltage source.

[0055] Figure 10 shows an example configuration of the over-discharge detection comparator circuit 661 in a comparative example. The over-discharge detection comparator circuit 661 is composed of an enhancement-type PMOS transistor 811, an enhancement-type NMOS transistor 812, an enhancement-type PMOS transistor 813, an enhancement-type NMOS transistor 814, an enhancement-type NMOS transistor 831, an enhancement-type PMOS transistor 851, and an enhancement-type NMOS transistor 852.

[0056] Compared to such comparative examples, the current consumption in the over-discharge state can be suppressed in these embodiments (first and second embodiments). In this embodiment (first embodiment, second embodiment), the over-discharge detection comparator circuit (over-discharge detection comparator circuit 61 in the first embodiment, over-discharge detection comparator circuit 61A in the second embodiment) incorporates at least a part of a reference voltage source that supplies the same voltage as the reference voltage (voltage Vref), and detects the over-discharge state based on the output from the over-discharge detection ladder circuit A11.

[0057] While embodiments of this disclosure have been described in detail above with reference to the drawings, the specific configuration is not limited to these embodiments and includes designs and the like that do not depart from the gist of this disclosure. For example, although the discharge control FET 21, charge control FET 22, external voltage input terminal C4, discharge control FET gate connection terminal C5, and charge control FET gate connection terminal C6 are arranged on the low side (negative side of the battery), the configuration is not limited to this and may be arranged on the high side (positive side of the battery). [Explanation of symbols]

[0058] 10…Battery device, 20…Charge / discharge control device, 21…FET for discharge control, 22…FET for charge control, 30…Charge / discharge control circuit, 11…Battery, 35, 35A…Bias circuit, 51, 52…Resistors, 53…Ladder resistor for overcurrent detection, 61, 61A…Comparator circuit for overdischarge detection, 62…Logic circuit, 71…Reference voltage source, 72…Amplifier, 73…Various detection circuits, 231, 234, 382…Depletion-type NMOS transistor, 232, 332, 334, 384…Enhancement-type NMOS transistor, 233, 331, 333, 381, 383…Enhancement-type PMOS transistor, A11…Ladder circuit for overdischarge detection, C1…Positive power input terminal, C2…Negative power input terminal, C4…External voltage input terminal, C5…FET gate connection terminal for discharge control, C6…FET gate connection terminal for charge control

Claims

1. The positive power input terminal connected to the positive terminal of the battery, A negative power input terminal connected to the negative terminal of the aforementioned battery, A reference voltage source that supplies a reference voltage, A ladder circuit for over-discharge detection is connected between the positive power input terminal and the negative power input terminal, An over-discharge detection comparator circuit incorporates at least a portion of a reference voltage source that supplies the same voltage as the aforementioned reference voltage, and detects the over-discharge state based on the output from the over-discharge detection ladder circuit, A logic circuit that controls the on / off state of the internal circuit and the discharge control FET in accordance with the over-discharge detection signal output from the over-discharge detection comparator circuit, A charge / discharge control circuit equipped with the following features.

2. The over-discharge detection comparator circuit includes the reference voltage source, The aforementioned reference voltage source is composed of a depletion-type NMOS transistor and an enhancement-type NMOS transistor. The charge / discharge control circuit according to claim 1.

3. The over-discharge detection comparator circuit includes an enhancement-type NMOS transistor as part of the reference voltage source. The reference voltage source is composed of the enhancement-type NMOS transistor and the depletion-type NMOS transistor of the bias circuit. The charge / discharge control circuit according to claim 1.

4. A discharge control FET that controls the discharge, A charge control FET that controls the charging process, A charge / discharge control circuit according to any one of claims 1 to 3, A charge / discharge control device equipped with the following features.

5. Battery and A charge / discharge control device according to claim 4 for controlling the charging and discharging of the battery, A battery device equipped with the following features.

Images