Charge / discharge control circuit, charge / discharge control device, and battery device

Abstract

When detecting UVLO, the circuit size should be kept to a minimum. [Solution] The charge / discharge control circuit 30 comprises a UVLO detection circuit 31 connected to a positive power input terminal C1 and detecting that the voltage of the positive power input terminal C1 is less than the UVLO detection voltage; a load short circuit detection circuit 37 connected to an overcurrent detection terminal C3 and detecting the voltage of the overcurrent detection terminal C3; a discharge control unit A2 that controls the discharge control FET 21 to turn off in accordance with the load short circuit detection signal output from the load short circuit detection circuit 37; a UVLO mask unit A3 that masks the UVLO detection signal output from the UVLO detection circuit 31 with the load short circuit detection signal output from the load short circuit detection circuit 37; and an internal circuit on / off control unit 34 that controls the on / off status of the internal circuit based on the signal output from the UVLO mask unit A3.

Description

Technical Field

[0005] , ,

[0001] The present disclosure relates to a charge-discharge control circuit, a charge-discharge control device, and a battery device.

Background Art

[0002] A charge-discharge control circuit for controlling the charge and discharge of a battery is known (see, for example, Patent Document 1). When a load short circuit occurs in a battery of a plurality of cells, the inter-electrode voltage may extremely decrease due to the internal resistance and current of the battery. In this case, before the charge-discharge control circuit detects the load short circuit, by detecting the voltage of an under-voltage lock-out (UVLO) function, the field effect transistor (FET) for discharge control is turned off to stop the discharge.

[0003] However, in such an operation, when the inter-electrode voltage returns after the discharge is stopped and the FET for discharge control is turned on by releasing the UVLO, a short-circuit current flows again. Therefore, the discharge stop and start are repeated, and the FET for discharge control may be damaged. As a measure to prevent this, in the conventional circuit, the detection voltage of the UVLO is designed to be around 2 [V], and the minimum operating voltage of other circuits is set to 2 [V] or less.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, in the conventional circuit as described above, since the minimum operating voltage is designed to be low, the circuit scale may become large. For example, one possible solution is to introduce a delay in the UVLO detection circuit that is longer than the delay when detecting a short circuit; however, this solution would also likely increase the circuit size. In other words, the above measures would result in a larger chip size.

[0006] This disclosure has been made in consideration of these circumstances, and aims to provide a charge / discharge control circuit, a charge / discharge control device, and a battery device that can reduce the circuit size when detecting UVLO. [Means for solving the problem]

[0007] One embodiment is a charge / discharge control circuit comprising: a positive power input terminal connected to the positive terminal of a battery; a negative power input terminal connected to the negative terminal of the battery; an overcurrent detection terminal connected to the negative terminal side of the battery; a UVLO detection circuit connected to the positive power input terminal and detecting that the voltage of the positive power input terminal is less than the UVLO detection voltage; a load short-circuit detection circuit connected to the overcurrent detection terminal and detecting the voltage of the overcurrent detection terminal; a discharge control unit that controls the discharge control FET to turn off in accordance with the load short-circuit detection signal output from the load short-circuit detection circuit; a UVLO mask unit that masks the UVLO detection signal output from the UVLO detection circuit with the load short-circuit detection signal output from the load short-circuit detection circuit; and an internal circuit on / off control circuit that controls the on / off of the internal circuit based on the signal output from the UVLO mask unit. [Effects of the Invention]

[0008] According to this disclosure, when detecting UVLO in a charge / discharge control circuit, charge / discharge control device, and battery device, the circuit size can be reduced. [Brief explanation of the drawing]

[0009] [Figure 1] This figure shows an example configuration of a charge / discharge control circuit, a charge / discharge control device, and a battery device according to an embodiment, as well as a diagram showing the first state of the battery device. [Figure 2] This figure shows the second state of the battery device according to the embodiment. [Figure 3] This figure shows the third state of the battery device according to the embodiment. [Figure 4] This figure shows an example of a timing chart according to the embodiment. [Figure 5] This figure shows an example configuration of a charge / discharge control circuit, a charge / discharge control device, and a battery device related to a comparative example, as well as a diagram of the first state of the battery device. [Figure 6] This figure shows the second state of the battery device according to the comparative example. [Figure 7] This figure shows the third state of the battery device according to the comparative example. [Figure 8] This figure shows an example of a timing chart related to a comparative example. [Modes for carrying out the invention]

[0010] The embodiments of this disclosure will be described below with reference to the drawings.

[0011] [Battery device] Figure 1 shows an example configuration of the charge / discharge control circuit 30, charge / discharge control device 20, and battery device 10 according to the embodiment, as well as the first state of the battery device 10. The battery device 10 comprises a charge / discharge control device 20 and a battery 11. The charge / discharge control device 20 comprises a charge / discharge control circuit 30, a discharge control FET 21, and a charge control FET 22. Figure 1 also shows the sense resistor 12 for overcurrent detection, the short-circuit load 13, and the switch 14.

[0012] The charge / discharge control device 20 controls the charging and discharging of the battery 11. The discharge control FET 21 controls the discharge. The FET22 for charge control controls the charging process.

[0013] The charge and discharge control circuit 30 includes a charge and discharge control unit A1, a UVLO detection circuit 31 having a low-voltage malfunction prevention function, a bias circuit 35, an internal low-breakdown voltage element power supply circuit 36, a load short-circuit detection circuit 37, and a POC (Power On Clear) circuit 38. The charge and discharge control unit A1 includes a discharge control unit A2, a UVLO mask unit A3, an internal circuit on / off control circuit 34, and a DO control circuit 41. The discharge control unit A2 includes a discharge overcurrent state control latch circuit 39 and a delay circuit 40. The UVLO mask unit A3 includes an inverter 32 and an AND circuit 33.

[0014] The charge and discharge control circuit 30 includes a positive power supply input terminal C1 which is a terminal of voltage VDD, a negative power supply input terminal C2 which is a terminal of voltage VSS, an overcurrent detection terminal C3 which is a terminal of voltage VINI, an external voltage input terminal C4 which is a terminal of voltage VM, a discharge control FET gate connection terminal C5 which is a terminal of a discharge control function (DO), and a charge control FET gate connection terminal C6 which is a terminal of a charge control function (CO).

[0015] <Circuit connection relationship, etc.> Between the positive and negative terminals of the battery 11, in the order from the positive terminal to the negative terminal, a switch 14, a short-circuit load 13, a charge control FET 22, a discharge control FET 21, and an overcurrent detection sense resistor 12 are connected. Here, the source (S) of the charge control FET 22 is connected to the short-circuit load 13, the drain (D) of the charge control FET 22 and the drain (D) of the discharge control FET 21 are connected, and the source (S) of the discharge control FET 21 is connected to the overcurrent detection sense resistor 12.

[0016] The positive power supply input terminal C1 is connected to the positive terminal of the battery 11. The negative power supply input terminal C2 is connected to the negative terminal of the battery 11. The overcurrent detection terminal C3 is connected to the negative terminal side of the battery 11 and is connected to the point between the discharge control FET 21 and the overcurrent detection sense resistor 12. The external voltage input terminal C4 is connected to the source (S) of the charge control FET 22. The discharge control FET gate connection terminal C5 is connected to the gate (G) of the discharge control FET 21. The charge control FET gate connection terminal C6 is connected to the gate (G) of the charge control FET 22.

[0017] The input terminal of the UVLO detection circuit 31 is connected to the positive power supply input terminal C1. The output terminal of the UVLO detection circuit 31 is connected to one of the input terminals of the AND circuit 33. The UVLO detection circuit 31 detects that the voltage VDD at the positive power supply input terminal C1 is less than the UVLO detection voltage.

[0018] The input terminal of the load short-circuit detection circuit 37 is connected to the overcurrent detection terminal C3. The output terminal of the load short-circuit detection circuit 37 is connected to the input terminal of the inverter 32 and to one of the input terminals of the discharge overcurrent state control latch circuit 39. The load short-circuit detection circuit 37 detects the voltage VINI at the overcurrent detection terminal C3.

[0019] The output terminal of the AND circuit 33 is connected to the input terminal of the internal circuit on / off control circuit 34. The inverter 32 inverts the load short-circuit detection signal output from the load short-circuit detection circuit 37. The AND gate 33 receives the UVLO detection signal output from the UVLO detection gate 31 and the signal output from the inverter 32, and outputs a signal corresponding to the input. With this configuration, the UVLO mask unit A3 masks (i.e., disables) the UVLO detection signal output from the UVLO detection circuit 31 using the load short-circuit detection signal output from the load short-circuit detection circuit 37. This configuration, using the AND circuit 33 and inverter 32, is an example of a simple circuit configuration for realizing a mask.

[0020] The output terminal of the internal low-voltage element power supply circuit 36 ​​is connected to the input terminal of the POC circuit 38 and the input terminal of the discharge control unit A2, respectively. The discharge control unit A2 controls the discharge control FET 21 to turn off in response to the load short-circuit detection signal output from the load short-circuit detection circuit 37.

[0021] The output terminal of the POC circuit 38 is connected to the other input terminal of the discharge overcurrent state control latch circuit 39. The discharge overcurrent state control latch circuit 39 is connected to the input terminal and output terminal of the delay circuit 40, respectively. The output terminal of the discharge overcurrent state control latch circuit 39 is connected to one of the input terminals of the DO control circuit 41. The control output terminal of the internal circuit on / off control circuit 34 is connected to the other input terminal of the DO control circuit 41. The internal circuit on / off control circuit 34 controls the on / off state of the internal circuit based on the signal output from the UVLO mask section A3.

[0022] The output terminal of the DO control circuit 41 is connected to the gate connection terminal C5 of the FET for discharge control. The output terminal of the charge / discharge control unit A1 is connected to the FET gate connection terminal C6 for charge control. The internal circuit on / off control circuit 34 controls the UVLO detection circuit 31, the bias circuit 35, the internal low-voltage element power supply circuit 36, the load short-circuit detection circuit 37, and the POC circuit 38.

[0023] In this embodiment, the focus is primarily on discharge control; therefore, details of charge control are omitted from the illustrations and explanations. Furthermore, in this embodiment, the details of the bias circuit 35 will not be described.

[0024] [Example of battery device operation] Refer to Figures 1 to 4 to see an example of operation when UVLO detection is masked by the load short-circuit detection signal during a load short circuit.

[0025] <First state> Figure 1 shows the first state of the battery device 10. Switch 14 is controlled to the open position. Voltage VDD is higher than the UVLO detection voltage VUVLO. The UVLO detection circuit 31 is in the deactivated state. The bias circuit 35 is in the ON state. The power supply circuit 36 ​​for the internal low-voltage element is in the ON state. The load short-circuit detection circuit 37 is in the deactivated state. The POC circuit 38 is in the deactivated state. The output terminal of the discharge overcurrent state control latch circuit 39 is in the released state. The delay circuit 40 is in the off state. The discharge control FET 21 is in the ON state.

[0026] <Second state> Figure 2 shows the second state of the battery device 10 according to the embodiment. For the first state, switch 14 is controlled to the closed (SHORT) state. As a result, a short-circuit load 13 is connected to both ends of the battery 11. Then, current flows through the battery 11. Due to the current from the short-circuit load 13 and the internal resistance of the battery 11, the voltage VDD drops to a level lower than the UVLO detection voltage VUVLO. The UVLO detection circuit 31 is in a detection state and is outputting a UVLO detection signal. The load short-circuit detection circuit 37 is in a detection state and is outputting a load short-circuit detection signal. In this example, detection by the UVLO detection circuit 31 and detection by the load short-circuit detection circuit 37 are performed simultaneously (or almost simultaneously). The UVLO mask unit A3 masks the UVLO detection signal with the load short-circuit detection signal. Therefore, the internal circuit on / off control circuit 34 does not turn off the internal circuit. Because the internal circuit does not turn off, the discharge control unit A2 initiates load short-circuit detection, and the delay circuit 40 is controlled to the ON state. The discharge overcurrent state control latch circuit 39 starts delaying the load short-circuit detection signal using the delay circuit 40.

[0027] <Third state> Figure 3 shows the third state of the battery device 10 according to the embodiment. After the second state, the voltage VDD becomes higher than the UVLO detection voltage VUVLO. The UVLO detection circuit 31 is in the deactivated state. The output terminal of the discharge overcurrent state control latch circuit 39 is in a detection state and is outputting a load short-circuit detection signal. The delay circuit 40 is in the off state. The discharge control FET 21 is controlled to the off state by a load short-circuit detection signal from the discharge overcurrent state control latch circuit 39. Thus, in the third state, once the delay circuit 40 has completed its delay, the discharge control FET 21 is controlled to turn off, and the discharge is stopped.

[0028] Figure 4 shows an example of a timing chart according to the embodiment. Figure 4 shows three graphs. The horizontal axis of the three graphs represents time, and it is a common time point. Time t1 and time t2 are shown. Furthermore, the vertical axis of each of the three graphs represents voltage.

[0029] The graph in Figure 4(A) shows the voltage characteristics VDD of the positive power supply input terminal C1. In this graph, the vertical axis shows the threshold values, the UVLO detection voltage VUVLO and the voltage VSS. Furthermore, the graph schematically shows the duration of the UVLO mask.

[0030] The graph in Figure 4(B) shows the characteristics of the voltage VINI across the overcurrent detection terminal C3. In this graph, the vertical axis shows the load short-circuit detection voltage VSHORT and the voltage VSS. Furthermore, the graph schematically shows the interval where the load short-circuit detection delay time is less than tSHORT.

[0031] The graph in Figure 4(C) shows the voltage characteristics (voltage VDO) of the discharge control FET gate connection terminal C5. In this graph, the vertical axis shows voltage VDD and voltage VSS.

[0032] Figure 4(D) shows whether or not a short-circuit load is connected. In this example, the short-circuit load 13 is connected from time t1 onwards. Figure 4(E) shows whether the system is in a normal state or a discharge overcurrent state. In this example, the system is in a normal state until time t2, and in a discharge overcurrent state from time t2 onward.

[0033] [About this embodiment] As described above, the charge / discharge control circuit 30, charge / discharge control device 20, and battery device 10 according to this embodiment detect UVLO and, when a load short circuit is detected, mask the turning off of the internal circuit due to UVLO. Therefore, in the charge / discharge control circuit 30, charge / discharge control device 20, and battery device 10 according to this embodiment, the circuit size can be reduced when detecting UVLO. In other words, the circuit size can be reduced compared to conventional circuits. In this embodiment, it is not necessary to lower the minimum operating voltage of the entire circuit, thus reducing the difficulty of circuit design. For example, it is possible to set the minimum operating voltage to around 3V.

[0034] [Explanation of the comparative example] A comparative example will be explained with reference to Figures 5 to 8. Figures 5 to 8 show an example of operation when UVLO is detected during a load short circuit. For the sake of clarity, Figures 5 to 7 use the same reference numerals for components as those in Figures 1 to 3.

[0035] Figure 5 shows an example configuration of the charge / discharge control circuit 330, charge / discharge control device 320, and battery device 310 according to a comparative example, as well as the first state of the battery device 310. The configuration and operation of the comparative battery device 310 differ from the battery device 10 according to this embodiment in that it does not have the UVLO mask section A3 shown in Figures 1 to 3.

[0036] Figure 6 shows the second state of the battery device 310 according to the comparative example. Switch 14 is controlled to the closed (SHORT) state. As a result, a short-circuit load 13 is connected to both ends of the battery 11. Then, current flows through the battery 11. Due to the current from the short-circuit load 13 and the internal resistance of the battery 11, the voltage VDD drops to a level lower than the UVLO detection voltage VUVLO. The UVLO detection circuit 31 is in a detection state and is outputting a UVLO detection signal. The internal circuit on / off control circuit 34 turns off the internal circuits (bias circuit 35, internal low-voltage element power supply circuit 36). The load short-circuit detection circuit 37 is in a detection state and is outputting a load short-circuit detection signal. The POC circuit 38 is in detection mode and is outputting a POC detection signal. Upon detection of UVLO by the internal circuit on / off control circuit 34, the discharge control FET 21 is controlled to turn off, and the discharge stops.

[0037] Figure 7 shows the third state of the battery device 310 according to the comparative example. Voltage VDD will be higher than the UVLO detection voltage VUVLO. The UVLO detection circuit 31 is in the deactivated state. The internal circuit on / off control circuit 34 turns on the internal circuits (bias circuit 35, internal low-voltage element power supply circuit 36). The load short-circuit detection circuit 37 is released. The POC circuit 38 is released. Upon the return of voltage VDD, the discharge control FET 21 is controlled to turn on, and discharge begins.

[0038] In the comparative example, after the third state, the discharge control FET 21 is turned off again by the current from the short-circuit load 13, meaning it returns to the second state. Then, in the comparative example, the second and third states are repeated.

[0039] Figure 8 shows an example of a timing chart related to a comparative example. Figure 8 shows three graphs. The horizontal axis of the three graphs represents time, and it is a common time point. It shows times t11 to t16. Furthermore, the vertical axis of each of the three graphs represents voltage.

[0040] The graph in Figure 8(A) shows the voltage VDD characteristic 2011 at the positive power supply input terminal C1. In this graph, the vertical axis shows the threshold values, the UVLO detection voltage VUVLO and the voltage VSS. Furthermore, the graph schematically shows the UVLO detection delay and UVLO release delay periods.

[0041] The graph in Figure 8(B) shows the characteristic 2012 of the voltage VINI at the overcurrent detection terminal C3. The graph also shows the load short-circuit detection voltage VSHORT and the load short-circuit detection delay time tSHORT. In this graph, the vertical axis shows the load short-circuit detection voltage VSHORT and the voltage VSS. Furthermore, the graph schematically shows the interval where the load short-circuit detection delay time is less than tSHORT.

[0042] The graph in Figure 8(C) shows the voltage characteristics (voltage VDO) of the discharge control FET gate connection terminal C5 in 2013. In this graph, the vertical axis shows voltage VDD and voltage VSS.

[0043] Figure 8(D) shows whether or not a short-circuit load is connected. In this example, the short-circuit load 13 is connected from time t11 onwards. Figure 8(E) shows whether the system is in the normal state or the UVLO state. In this example, the system is in the normal state until time t13, then in the UVLO state until time t15, then in the normal state until time t16, and then back to the UVLO state.

[0044] Thus, in the comparative example, the normal state and the UVLO state are repeated, but in this embodiment, this problem can be resolved.

[0045] While embodiments of this disclosure have been described in detail above with reference to the drawings, the specific configuration is not limited to these embodiments and includes designs and the like that do not depart from the gist of this disclosure. For example, although the discharge control FET 21, charge control FET 22, overcurrent detection sense resistor 12, overcurrent detection terminal C3, external voltage input terminal C4, discharge control FET gate connection terminal C5, and charge control FET gate connection terminal C6 are arranged on the low side (negative side of the battery), the configuration is not limited to this and may also be arranged on the high side (positive side of the battery). [Explanation of symbols]

[0046] 10...Battery device, 20...Charge / discharge control device, 30...Charge / discharge control circuit, 11...Battery, 12...Sense resistor for overcurrent detection, 13...Short-circuit load, 14...Switch, 21...FET for discharge control, 22...FET for charge control, 31...UVLO detection circuit, 32...Inverter, 33...AND circuit, 34...Internal circuit on / off control circuit, 35...Bias circuit, 36...Power supply circuit for internal low-voltage elements, 37...Load short-circuit detection circuit, 38...POC circuit, 39...Discharge overcurrent state control latch circuit, 40...Delay circuit, 41...DO control circuit, A1...Charge / discharge control unit, A2...Discharge control unit, A3...UVLO mask unit, C1...Positive power input terminal, C2...Negative power input terminal, C3...Overcurrent detection terminal, C4...External voltage input terminal, C5...FET gate connection terminal for discharge control, C6...FET gate connection terminal for charge control

Claims

1. The positive power input terminal connected to the positive terminal of the battery, A negative power input terminal connected to the negative terminal of the aforementioned battery, An overcurrent detection terminal connected to the negative terminal side of the battery, A UVLO detection circuit connected to the positive power input terminal detects that the voltage at the positive power input terminal is less than the UVLO detection voltage, A load short-circuit detection circuit connected to the overcurrent detection terminal and detecting the voltage of the overcurrent detection terminal, A discharge control unit that performs control to turn off a discharge control FET in response to a load short-circuit detection signal output from the load short-circuit detection circuit, A UVLO masking unit that masks the UVLO detection signal output from the UVLO detection circuit with the load short-circuit detection signal output from the load short-circuit detection circuit, An internal circuit on / off control circuit that controls the on / off state of the internal circuit based on the signal output from the UVLO mask section, A charge / discharge control circuit equipped with the following features.

2. The aforementioned UVLO mask portion is An inverter that inverts the load short-circuit detection signal output from the aforementioned load short-circuit detection circuit, An AND circuit receives the UVLO detection signal output from the UVLO detection circuit and the signal output from the inverter, and outputs a signal corresponding to the input. Equipped with, The charge / discharge control circuit according to claim 1.

3. The discharge control FET that controls the discharge, A charge control FET that controls the charging process, A charge / discharge control circuit according to claim 1 or claim 2, A charge / discharge control device equipped with the following features.

4. Battery and A charge / discharge control device according to claim 3 for controlling the charging and discharging of the battery, A battery device equipped with the following features.

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