Indication device

Abstract

In a display device employing pixels with a built-in boost circuit, this technology provides a way to increase the amplitude of the pixel electrodes relative to the amplitude of the source line without reducing the number of pixels per row. [Solution] In the display device, the number of signal lines is doubled, and separate signal lines are provided for pixels in odd-numbered rows and pixels in adjacent even-numbered rows. By driving the scan lines simultaneously for odd-numbered and even-numbered rows, two rows are driven in the time of one horizontal period by writing to pixels in odd-numbered rows and pixels in adjacent even-numbered rows. This makes it possible to effectively halve the time of one horizontal period.

Description

Technical Field

[0001] The present disclosure relates to a display device.

Background Art

[0002] As a display element using a polymer dispersed liquid crystal (PDLC) material, for example, Japanese Patent Laid-Open No. 5-61016 has been proposed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present inventors have studied a transparent display device using a PDLC material, that is, a so-called transparent display. In a transparent display, since a high voltage is applied to the PDLC, a dedicated source driver IC (integrated circuit) for outputting a high-voltage video signal and a dedicated gate driver IC for writing and holding a high voltage are required. Therefore, it is one of the causes of high cost factors such as the inability to use a low-voltage IC manufacturing process and the inability to use general-purpose source driver ICs and general-purpose gate driver ICs.

[0005] Therefore, a transparent display has been developed that does not require a dedicated source driver IC by creating a booster circuit in the pixel while keeping the source driver IC at the normal (general-purpose) video output voltage and increasing the range of the liquid crystal applied voltage.

[0006] However, because each pixel incorporates a boost circuit, the number of source lines (also called signal lines) and gate lines (also called scan lines) increases compared to a typical pixel circuit. Furthermore, the increased number of pixel components leads to a decrease in the aperture ratio. Additionally, the boost drive increases the duration of one horizontal period. As a result, there are limitations on the number of pixels and frame rate.

[0007] The purpose of this disclosure is to provide a technology for a display device employing pixels with a built-in boost circuit that can increase the amplitude of the pixel electrode relative to the amplitude of the source line without reducing the number of pixels in a row.

[0008] Other challenges and novel features will become apparent from the description and accompanying drawings in this specification. [Means for solving the problem]

[0009] A brief overview of some of the representative disclosures is as follows:

[0010] In other words, a display device relating to one embodiment of this disclosure is Multiple pixels arranged in a matrix, A first scan line, a second scan line, a third scan line, and a fourth scan line extending in a first direction and arranged in a second direction intersecting the first direction, It includes a first signal line, a second signal line, a third signal line, and a fourth signal line that extend in the second direction and are arranged in the first direction, The plurality of pixels include a first pixel and a second pixel adjacent to the first pixel in the second direction, The first pixel comprises a first transistor, a second transistor, a first common electrode and a first pixel electrode separated by a liquid crystal, and a reference potential is supplied to the first common electrode. The gate of the first transistor is connected to the first scan line, one of the source and drain of the first transistor is connected to the first signal line, and the other of the source and drain of the first transistor is connected to the first pixel electrode of the first pixel via a first capacitor. The gate of the second transistor is connected to the second scan line, one of the source and drain of the second transistor is connected to the second signal line, and the other of the source and drain of the second transistor is connected to the first pixel electrode of the first pixel. The second pixel has a third transistor, a fourth transistor, a second common electrode and a second pixel electrode with the liquid crystal in between, and the reference potential is supplied to the second common electrode. The gate of the third transistor is connected to the third scan line, one of the source and drain of the third transistor is connected to the third signal line, and the other of the source and drain of the third transistor is connected to the second pixel electrode via a second capacitor. The gate of the fourth transistor is connected to the fourth scan line, one of the source and drain of the fourth transistor is connected to the fourth signal line, and the other of the source and drain of the fourth transistor is connected to the second pixel electrode.

[0011] Furthermore, a display device relating to another embodiment is, Multiple pixels arranged in a matrix, A first scan line, a second scan line, a third scan line, a fourth scan line, a fifth scan line, and a sixth scan line extending in a first direction and arranged in a second direction intersecting the first direction, It includes a first signal line, a second signal line, and a third signal line extending in the second direction and arranged in the first direction, The plurality of pixels are arranged adjacently in the second direction and include a first pixel, a second pixel, and a third pixel. The first pixel has a first transistor, a second transistor, a first common electrode and a first pixel electrode separated by a liquid crystal, and a reference potential is supplied to the first common electrode. The second pixel has a third transistor, a fourth transistor, a second common electrode and a second pixel electrode with the liquid crystal in between, and the reference potential is supplied to the second common electrode. The third pixel has a fifth transistor, a sixth transistor, a third common electrode and a third pixel electrode with the liquid crystal in between, and the reference potential is supplied to the third common electrode. The gate of the first transistor of the first pixel is connected to the first scan line, one of the source and drain of the first transistor is connected to the first signal line, and the other of the source and drain of the first transistor is connected to the first pixel electrode via a first capacitor. The gate of the second transistor of the first pixel is connected to the second scan line, one of the source and drain of the second transistor is connected to the second signal line, and the other of the source and drain of the second transistor is connected to the first pixel electrode. The gate of the third transistor of the second pixel is connected to the third scan line, one of the source and drain of the third transistor is connected to the second signal line, and the other of the source and drain of the third transistor is connected to the second pixel electrode via a second capacitor. The gate of the fourth transistor of the second pixel is connected to the fourth scan line, one of the source and drain of the fourth transistor is connected to the third signal line, and the other of the source and drain of the fourth transistor is connected to the second pixel electrode. The gate of the fifth transistor of the third pixel is connected to the fifth scan line, one of the source and drain of the fifth transistor is connected to the third signal line, and the other of the source and drain of the fifth transistor is connected to the third pixel electrode via a third capacitor. The gate of the sixth transistor of the third pixel is connected to the sixth scan line, one of the source and drain of the sixth transistor is connected to the first signal line, and the other of the source and drain of the sixth transistor is connected to the third pixel electrode. [Brief explanation of the drawing]

[0012] [Figure 1] Figure 1 is a circuit diagram of a pixel in a comparative example. [Figure 2] FIG. 2 is a diagram showing the timing chart of the pixels in FIG. 1. [Figure 3] FIG. 3 is a diagram showing the voltage of the pixel electrodes of the pixels in FIG. 1. [Figure 4] FIG. 4 is a diagram showing a configuration example of the display device according to Embodiment 1. [Figure 5] FIG. 5 is a diagram showing a configuration example of two pixels shown in FIG. 4. [Figure 6] FIG. 6 is a diagram showing the timing chart of the display device according to Embodiment 1. [Figure 7] FIG. 7 is a diagram showing a configuration example of the display device according to Embodiment 2. [Figure 8] FIG. 8 is a diagram showing a configuration example of three pixels shown in FIG. 7. [Figure 9] FIG. 9 is a diagram showing the timing chart of the display device according to Embodiment 2. [Figure 10A] FIG. 10A is a diagram schematically showing the liquid crystal layer 30 in a transparent state. [Figure 10B] FIG. 10B is a diagram schematically showing the liquid crystal layer 30 in a scattered state. [Figure 11A] FIG. 11A is a cross-sectional view showing the display panel PNL when the liquid crystal layer 30 is in a transparent state. [Figure 11B] FIG. 11B is a cross-sectional view showing the display panel PNL when the liquid crystal layer 30 is in a scattered state.

MODE FOR CARRYING OUT THE INVENTION

[0013] Hereinafter, each embodiment of the present disclosure will be described with reference to the drawings. Note that the disclosure is merely an example, and for those that can be easily conceived by those skilled in the art with appropriate modifications while maintaining the gist of the disclosure, they are naturally included in the scope of the present disclosure. In addition, for the purpose of making the description clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual aspect, but this is merely an example and does not limit the interpretation of the present disclosure.

[0014] First, the comparative example will be explained using Figures 1-3. Figure 1 is a circuit diagram of a pixel related to the comparative example. Figure 2 is a timing chart of the pixel in Figure 1. Figure 3 is a diagram illustrating the voltage of the pixel electrode of the pixel in Figure 1.

[0015] The pixel PXr in the comparative example shown in Figure 1 is an example of a configuration of a single pixel (also called a boost pixel) that incorporates a boost circuit. The pixel PXr is connected to a first scan line G1A and a second scan line G1B that extend in a first direction X and are arranged in a second direction Y that intersects with the first direction X, and to a first signal line S1A and a second signal line S1B that extend in the second direction Y and are arranged in the first direction X.

[0016] Each pixel PXr comprises a first transistor TFT-A, a second transistor TFT-B, and a common electrode CE and a pixel electrode PE separated by a liquid crystal LC. The common electrode CE is supplied with a reference potential (e.g., ground potential: 0V), which is a common potential VCOM, via a common potential wiring COM. The first transistor TFT-A and the second transistor TFT-B can be constructed using thin film transistors (TFTs). In transparent displays, polymer dispersed liquid crystal (PDLC) is used as the liquid crystal LC.

[0017] The gate of the first transistor TFT-A is connected to the first scan line G1A, one of the source and drain of the first transistor TFT-A is connected to the first signal line S1A, and the other of the source and drain of the first transistor TFT-A is connected to the pixel electrode PE via the first capacitive element CB.

[0018] The gate of the second transistor TFT-B is connected to the second scan line G1B, one of the source and drain of the second transistor TFT-B is connected to the first signal line S1A, and the other of the source and drain of the second transistor TFT-B is connected to the pixel electrode PE. A capacitive element CA is connected between the pixel electrode PE and the common electrode CE as a retaining capacitive element.

[0019] The timing will be explained using Figure 2. In Figure 2, the symbol - indicates negative polarity with respect to the reference potential, and the symbol + indicates positive polarity with respect to the reference potential. Also, one horizontal period (1H_PNL) of the display panel includes the first half period P1 (also called the first half P1) and the second half period P2 (also called the second half P2). Each of the first half P1 and second half P2 corresponds to one horizontal period (1H_SIC) of the source driver IC. One horizontal period (1H_PNL) of the display panel is, for example, the period during which display data is written to multiple pixels for one row of the display panel. On the other hand, one horizontal period (1H_SIC) of the source driver IC is, for example, the period during which the source driver IC writes data once to the source lines connected to multiple pixels for one row of the display panel.

[0020] During the first half P1 of one horizontal period (1H_PNL) of the display panel, the first scan line G1A and the second scan line G1B transition from a low level (unselected state) to a high level (selected state), and both the first transistor TFT-A and the second transistor TFT-B are turned on. At this time, a voltage (-V1: e.g., -6.1V) is written from the first signal line S1A to the first capacitor element CB, and a voltage (+V1: e.g., +6.1V) is written from the second signal line S1B to the capacitor element CA. After that, the first scan line G1A remains at a high level (selected state), and the second scan line G1B transitions from a high level (selected state) to a low level (unselected state).

[0021] During the latter half of the horizontal period (1H_PNL) of the display panel, in phase P2, a voltage (+V1: e.g., +6.1V) is written from the first signal line S1A to the first capacitive element CB. This causes the first capacitive element CB to perform a capacitive coupling operation, which raises the voltage of the pixel electrode PE. The voltage of the pixel electrode PE is raised (boosted) from, for example, +V1 (e.g., +6.1V) to +V2 (e.g., +14V). In the case of negative polarity, a potential of the opposite polarity is applied, and the voltage of the pixel electrode PE is lowered (stepped down) to, for example, -V2 (e.g., -14V).

[0022] After the display data is written to multiple pixels in the first row of the display panel, the data will be written to the multiple pixels in the second row, and then to the multiple pixels in the third row, in sequence.

[0023] As a result, as shown in Figure 3, the voltage amplitude VppPE (amplitude between +V2 and -V2) of the pixel electrode PE can be made higher than the source output amplitude VppS (amplitude between +V1 and -V1) of the source driver IC, and the voltage applied to the liquid crystal LC can be made higher than the output voltage of the source driver IC.

[0024] However, in a typical pixel circuit, the source line (signal line) is written only once during one horizontal period (1H_PNL), whereas the boosted pixel PXr requires the source line (first signal line S1A) to be written twice during one horizontal period (1H_PNL).

[0025] Because the source line is heavily loaded, writing to the source line will occupy the majority of the horizontal period.

[0026] As mentioned earlier, driving a boosted pixel, such as a PXr pixel, requires writing to the source line twice during one horizontal period, meaning that one horizontal period takes almost twice as long as driving a typical pixel. Consequently, because one horizontal period takes twice as long, the number of rows that can be written to in one frame is halved, and the number of pixels (rows) that can be realized in a display panel using boosted pixels is half that of a display device using a typical pixel drive.

[0027] Furthermore, as shown in Figure 1, the PXr pixel incorporates a boost circuit, resulting in an increase in source lines (first signal line S1A and second signal line S1B) and gate lines (first scan line G1A and second scan line G1B) compared to a typical pixel circuit. Additionally, the increase in pixel components (first transistor TFT, first capacitance element CB) leads to a reduction in the aperture ratio.

[0028] Furthermore, when the display device is a field-sequential drive such as a transparent display device, there are challenges such as the reduced illumination time of the LED (light-emitting diode) that illuminates the light-receiving part of the transparent light guide plate, which is installed to cover the transparent display part of the transparent display device.

[0029] Next, the examples will be described with reference to the drawings. [Examples]

[0030] Example 1 is a technique that can increase the number of pixels (rows) on which data is written in one horizontal period (1H_PNL) of the display panel compared to the comparative example. The number of source lines (signal lines) provided on the display panel is doubled, for example, by providing separate source lines for pixels in odd-numbered rows and pixels in adjacent even-numbered rows. By driving the gate lines simultaneously for odd-numbered and even-numbered rows and writing data to the pixels at the same time, two rows can be driven in one horizontal period (1H_PNL) of the display panel, making it possible to effectively halve one horizontal period (1H_PNL) of the display panel.

[0031] In other words, by doubling the number of source lines (signal lines) and writing two rows of pixels simultaneously, two rows of pixels are driven in one horizontal period. This makes it possible to realize pixels with a built-in boost circuit (also called boost pixels) without reducing the number of pixels (rows), and the amplitude of the pixel electrode PE can be increased relative to the output amplitude of the source driver IC, thereby increasing the voltage applied to the liquid crystal LC. Therefore, it is possible to provide a transparent display with high display performance using a general-purpose source driver IC.

[0032] Figure 4 shows an example configuration of the display device according to Example 1. Figure 5 shows an example configuration of the two pixels shown in Figure 4. Figure 6 shows a timing chart of the display device according to Example 1.

[0033] As shown in Figure 4, the display device 1 includes a display area 2 in which multiple pixels PX (PX11, PX12, ..., PX44) are arranged in a matrix, a gate drive circuit (GD) 3, and a signal line drive circuit (SD) 4. The display area 2 may also be referred to as a display panel.

[0034] The display area 2 includes multiple pixels PX and multiple scan lines GL (first scan line G1A, second scan line G1B, third scan line G2A, fourth scan line G2B, fifth scan line G3A, sixth scan line G3B, seventh scan line G4A, eighth scan line G4B, etc.) that extend in the first direction X and are arranged in the second direction Y that intersects with the first direction X. The multiple scan lines GL are connected to a gate drive circuit (GD) 3 and are configured to be driven by the gate drive circuit 3.

[0035] Furthermore, the display area 2 includes a plurality of signal lines SL (first signal line S1A, second signal line S1B, third signal line S2A, fourth signal lines S2B, S3A, S3B, S4A, S4B, etc.) that extend in the second direction Y and are arranged in the first direction X. The plurality of signal lines SL are connected to the signal line drive circuit 4 and are configured to be driven by the signal line drive circuit 4.

[0036] The common potential wiring COM is connected to each pixel of a plurality of pixels PX and is configured to supply a reference potential, such as ground potential (0V).

[0037] A representative example of connecting multiple pixels PX, scan lines GL, and signal lines SL is described below.

[0038] Pixels PX11 and PX12 in the first row are connected to scan lines G1A and G1B. Pixel PX11 is connected to signal lines S1A and S1B, and pixel PX12 is connected to signal lines S3A and S3B.

[0039] Pixels PX21 and PX22 in the second row are connected to scan lines G2A and G2B. Pixel PX21 is connected to signal lines S2A and S2B, and pixel PX22 is connected to signal lines S4A and S4B.

[0040] Pixels PX31 and PX32 in the third row are connected to scan lines G3A and G3B. Pixel PX31 is connected to signal lines S1A and S1B, and pixel PX32 is connected to signal lines S3A and S3B.

[0041] Pixels PX41 and PX42 in the fourth row are connected to scan lines G4A and G4B. Pixel PX41 is connected to signal lines S2A and S2B, and pixel PX42 is connected to signal lines S4A and S4B.

[0042] In other words, a characteristic feature of Embodiment 1 is that, in multiple pixels PX, the signal lines connecting a certain pixel (for example, the first pixel PX11) and another pixel adjacent to that pixel (for example, the second pixel PX21) in the second direction Y are different: for the first pixel (for example, the first pixel PX11), the signal lines are signal line S1A and signal line S1B, while for the second pixel (for example, the second pixel PX21), the signal lines are not S1A and S1B, but S2A and S2B.

[0043] Figure 5 shows a representative example of the pixel configuration of the first pixel PX11 and the second pixel PX21 adjacent to the first pixel PX11 in the second direction Y.

[0044] The first pixel PX11 has a first transistor TFT-A, a second transistor TFT-B, and a first common electrode CE and a first pixel electrode PE separated by a liquid crystal LC. The first common electrode CE is supplied with a reference potential (e.g., ground potential: 0V) from a common potential wiring COM. A capacitive element CA, acting as a first retaining capacitance element, is connected between the first pixel electrode PE and the first common electrode CE.

[0045] The gate of the first transistor TFT-A of the first pixel PX11 is connected to the first scan line G1A, one of the source and drain of the first transistor TFT-A is connected to the first signal line S1A, and the other of the source and drain of the first transistor TFT-A is connected to the first pixel electrode PE of the first pixel PX11 via the first capacitive element CB.

[0046] The gate of the second transistor TFT-B of the first pixel PX11 is connected to the second scan line G1B, one of the source and drain of the second transistor TFT-B is connected to the second signal line S1B, and the other of the source and drain of the second transistor TFT-B is connected to the first pixel electrode PE of the first pixel PX11.

[0047] The second pixel PX21 has a third transistor TFT-A, a fourth transistor TFT-B, and a second common electrode CE and a second pixel electrode PE separated by a liquid crystal LC. The second common electrode CE is supplied with a reference potential (e.g., ground potential: 0V) from a common potential wiring COM. A capacitive element CA is connected between the second pixel electrode PE and the second common electrode CE as a second retaining capacitance element.

[0048] The gate of the third transistor TFT-A of the second pixel PX12 is connected to the third scan line G2A, one of the source and drain of the third transistor TFT-A is connected to the third signal line S2A, and the other of the source and drain of the third transistor TFT-A is connected to the second pixel electrode PE of the second pixel PX21 via the second capacitance element CB.

[0049] The gate of the fourth transistor TFT-B of the second pixel PX21 is connected to the fourth scan line G2B, one of the source and drain of the fourth transistor TFT-B is connected to the fourth signal line S2B, and the other of the source and drain of the fourth transistor TFT-B is connected to the second pixel electrode PE of the second pixel PX21. The thin-film transistor TFTs (TFT-A, TFT-B) described herein are N-channel type, and are turned off when a low level (non-selective state) is applied to their gates, and turned on when a high level (selective state) is applied to their gates.

[0050] The timing will be explained using Figure 6. In Figure 6, the symbol - indicates negative polarity with respect to the reference potential, and the symbol + indicates positive polarity with respect to the reference potential. Also, one horizontal period (1H_PNL) in the display area 2, which is the display panel, includes the first period P1 (also called the first period P1) and the second period P2 (also called the second period P2). Figure 6 depicts the first period P1, the second period P2 following the first period P1, the third period P3 following the second period P2, and the fourth period P4 following the third period P3. Furthermore, after the fourth period, the fifth period P5 following the fourth period P4, the sixth period P6 following the fifth period P5, and the seventh period P7 following the sixth period P6 are also depicted. The first period P1 and the second period P2 are, for example, considered to be the first horizontal period, and the third period P3 and the fourth period P4 are, for example, considered to be the second horizontal period.

[0051] Each of the first period P1, second period P2, third period P3, and fourth period P4 corresponds to one horizontal period (1H_SIC) of the signal line drive circuit 4 as a source driver IC. In the example of Embodiment 1, during one horizontal period (1H_PNL) of the display panel, display data is written to multiple pixels for two rows of the display area 2, and during one horizontal period (1H_SIC) of the signal line drive circuit 4, data is written once to the source lines connected to multiple pixels for two rows of the display area 2.

[0052] During the first period P1 and the second period P2, display data is written to multiple pixels in the first row (e.g., the first pixel PX11) and multiple pixels in the second row (e.g., the second pixel PX21). During the third period P3 and the fourth period P4, display data is written to multiple pixels in the third row (e.g., the third pixel PX31) and multiple pixels in the fourth row (e.g., the fourth pixel PX41). In the following explanation, the first pixel PX11, the second pixel PX21, the third pixel PX31, and the fourth pixel PX41 will be used as representative examples.

[0053] During the first period P1, the first scan line G1A and the second scan line G1B transition from a low level (unselected state) to a high level (selected state), and both the first transistor TFT-A and the second transistor TFT-B of the first pixel PX11 are turned on. At this time, a voltage (-V1: e.g., -6.1V) is written from the first signal line S1A to the first capacitive element CB of the first pixel PX11, and a voltage (+V1: e.g., +6.1V) is written from the second signal line S1B to the capacitive element CA of the first pixel PX11. After that, the first scan line G1A remains at a high level, and the second scan line G1B transitions from a high level to a low level.

[0054] Similarly, during the first period P1, the third scan line G2A and the fourth scan line G2B transition from low to high levels, and both the third transistor TFT-A and the fourth transistor TFT-B of the second pixel PX21 are turned on. At this time, a voltage (-V1: e.g., -6.1V) is written from the third signal line S2A to the second capacitive element CB of the second pixel PX21, and a voltage (+V1: e.g., +6.1V) is written from the fourth signal line S2B to the capacitive element CA of the second pixel PX21. After that, the third scan line G2A remains at a high level, and the fourth scan line G2B transitions from a high level to a low level.

[0055] During the second period P2, a voltage (+V1: e.g., +6.1V) is written from the first signal line S1A to the first capacitive element CB of the first pixel PX11. This causes the voltage of the first pixel electrode PE of the first pixel PX11 to be boosted by capacitive coupling by the first capacitive element CB. The voltage of the first pixel electrode PE is boosted (stepped up) from, for example, +V1 (e.g., +6.1V) to +V2 (e.g., +14V). Subsequently, the first scan line G1A transitions from a high level to a low level. The second scan line G1B remains at a low level. In the case of negative polarity, a potential of the opposite polarity to the above is applied, and the voltage of the first pixel electrode PE is lowered (stepped down) to, for example, -V2 (e.g., -14V).

[0056] Similarly, during the second period P2, a voltage (+V1: e.g., +6.1V) is written from the third signal line S2A to the second capacitive element CB of the second pixel PX21. This causes the voltage of the second pixel electrode PE of the second pixel PX21 to be boosted by capacitive coupling by the second capacitive element CB. The voltage of the second pixel electrode PE is boosted (stepped up) from, for example, +V1 (e.g., +6.1V) to +V2 (e.g., +14V). Subsequently, the third scan line G2A transitions from a high level to a low level. The fourth scan line G2B remains at a low level. In the case of negative polarity, a potential of the opposite polarity to the above is applied, and the voltage of the first pixel electrode PE is lowered (stepped down) to, for example, -V2 (e.g., -14V).

[0057] During the third period P3, the fifth scan line G3A and the sixth scan line G3B transition from low to high levels, and both transistors TFT-A and TFT-B of the third pixel PX31 are turned ON. At this time, a voltage (+V1: e.g., +6.1V) is written from the first signal line S1A to the capacitive element CB of the third pixel PX31, and a voltage (-V1: e.g., -6.1V) is written from the second signal line S1B to the capacitive element CA of the third pixel PX31. Subsequently, the fifth scan line G3A remains at a high level, and the sixth scan line G3B transitions from high to low levels.

[0058] Similarly, during the third period P3, the seventh scan line G4A and the eighth scan line G4B transition from low to high levels, turning on both transistors TFT-A and TFT-B of the fourth pixel PX41. At this time, a voltage (+V1: e.g., +6.1V) is written from the third signal line S2A to the capacitive element CB of the fourth pixel PX41, and a voltage (-V1: e.g., -6.1V) is written from the fourth signal line S2B to the capacitive element CA of the second pixel PX21. Subsequently, the seventh scan line G4A remains at a high level, and the eighth scan line G4B transitions from high to low levels.

[0059] During the fourth period P4, a voltage (-V1: e.g., -6.1V) is written from the first signal line S1A to the capacitive element CB of the third pixel PX31. This causes the voltage of the pixel electrode PE of the third pixel PX31 to drop due to capacitive coupling by the capacitive element CB. The voltage of the third pixel electrode PE drops (is stepped down) from, for example, -V1 (e.g., -6.1V) to -V2 (e.g., -14V). Subsequently, the seventh scan line G4A transitions from a high level to a low level. The eighth scan line G4B remains at a low level.

[0060] Similarly, in the fourth period P4, a voltage (-V1: e.g., -6.1V) is written from the third signal line S2A to the capacitive element CB of the fourth pixel PX41. This causes the voltage of the pixel electrode PE of the fourth pixel PX41 to drop due to capacitive coupling by the capacitive element CB. The voltage of the second pixel electrode PE is then dropped (stepped down) from, for example, -V1 (e.g., -6.1V) to -V2 (e.g., -14V). Subsequently, the seventh scan line G4A transitions from a high level to a low level. The eighth scan line G4B remains at a low level.

[0061] During the fifth period P5, the sixth period P6, and the seventh period P7, the operation of the first signal line S1A to the fourth signal line S2B is the same as during the first period P1, the second period P2, and the third period P3, for the pixels in the fifth, sixth, and seventh rows, respectively.

[0062] Through the operations described above, data will be written to each line of the display area 2 of the display device 1.

[0063] Therefore, it can be summarized as follows:

[0064] During the first period P1 and the fourth period P4, a negative voltage (-) relative to the reference potential (0V) is applied to the first signal line S1A and the third signal line S2A, while a positive voltage (+) relative to the reference potential is applied to the second signal line S1B and the fourth signal line S2B. During the second period P2 and the third period P3, a positive (+) voltage is applied to the first signal line S1A and the third signal line S2A relative to the reference potential, while a negative (-) voltage is applied to the second signal line S1B and the fourth signal line S2B relative to the reference potential.

[0065] During the first period P1, the second scan line G1B and the fourth scan line G2B transition in the order of low level, high level, and low level. During the first period P1, the first scan line G1A and the third scan line G2A transition from low level to high level. During the second period P2, the first scan line G1A and the third scan line G2A transition from high level to low level.

[0066] As described above, pixels with a built-in boost circuit can be realized without reducing the number of pixels (rows), the amplitude of the pixel electrode PE can be increased relative to the output amplitude of the source driver IC (signal line driving circuit 4), and the voltage applied to the liquid crystal LC can be increased.

[0067] Similarly, in boosted pixels, the number of signal lines is doubled, and two rows of pixels are written simultaneously, allowing two rows to be driven in one horizontal period. In boosted pixels, one horizontal period is twice that of a typical display device's pixels, so if we let H be the horizontal period of a typical pixel, and the number of pixels (rows) is y, then for the entire screen, (y × H × 2) This will take some time.

[0068] By doubling the number of signal lines, the apparent horizontal period can be halved, (y × H × 2) ÷ 2 = (y × H) This allows for the same processing time as a standard pixel (not a boosted pixel), effectively reducing the horizontal processing time while ensuring sufficient writing time. [Examples]

[0069] As explained earlier, a boost pixel consists of two signal lines, two capacitors, two transistors, and two scan lines per pixel. During the first half of a horizontal period (1H_PNL) (P1), the boost pixel is driven by writing to the two signal lines to charge the two capacitors. In the second half of the horizontal period (1H_PNL) (P2), a voltage is written to one of the two signal lines, and the voltage of the pixel electrode PE is increased by capacitive coupling, driving the pixel electrode PE to a voltage higher than the voltage written to the signal line.

[0070] In other words, in the latter half (P2) of one horizontal period (1H_PNL), there is one unused source line. In Example 2, the technique involves using the unused source line in the latter half (P2) of one horizontal period (1H_PNL) as the first source line of the next row to write the voltage. Therefore, in Example 2, it is possible to shorten the apparent length of one horizontal period (1H_PNL).

[0071] In Example 2, specifically, a set of pixels consisting of three rows of pixels is used, and three signal lines are shared among the three pixels. For example, the second signal line of the pixel in row m is shared with the first signal line of row (m+1), the second signal line of row (m+1) is shared with the first signal line of row (m+2), and the second signal line of row (m+2) is shared with the first signal line of row m.

[0072] The following describes Example 2 with reference to the drawings. Figure 7 is a diagram showing an example configuration of the display device according to Example 2. Figure 8 is a diagram showing an example configuration of the three pixels shown in Figure 7. Figure 9 is a diagram showing the timing chart of the display device according to Example 2.

[0073] The difference between the display device 1a in Figure 7 and the display device 1 in Figure 4 is that three signal lines (S1A, S1B, S1C) are shared by three pixels (PX11, PX21, PX31) arranged in a row in the second direction Y. In other words, the first pixel PX11, the second pixel PX21, and the third pixel PX31 of the first row, which are arranged adjacent to each other in the second direction Y, share the first signal line S1A, the second signal line S1B, and the third signal line S1C, which extend in the second direction Y and are arranged in the first direction X. The first pixel PX11 is connected to the first signal line S1A and the second signal line S1B. The second pixel PX21 is connected to the second signal line S1B and the third signal line S1C. The third pixel PX31 is connected to the third signal line S1C and the first signal line S1A. The fourth pixel PX41 is connected to the first signal line S1A and the second signal line S1B, similar to the first pixel PX11.

[0074] Furthermore, in the second row of pixels PX12, PX22, and PX32, which are arranged adjacent to each other in the second direction Y, pixel PX12 is connected to signal line S2A and signal line S2B. Pixel PX22 is connected to signal line S2B and signal line S2C. Pixel PX32 is connected to signal line S2C and signal line S2A. Pixel PX42 is connected to signal line S2A and signal line S2B, similar to pixel PX12. The other configurations of the display device 1a in Figure 7 are the same as the other configurations of the display device 1 in Figure 4, so redundant explanations are omitted.

[0075] In Figure 7, the scan lines include a first scan line G1A, a second scan line G1B, a third scan line G2A, a fourth scan line G2B, a fifth scan line G3A, and a sixth scan line G3B, which extend in a first direction X and are arranged in a second direction Y that intersects with the first direction X. Of the multiple pixels arranged in a matrix, the first pixel PX11 is connected to the first scan line G1A and the second scan line G1B. The second pixel PX21 is connected to the third scan line G2A and the fourth scan line G2B. The third pixel PX31 is connected to the fifth scan line G3A and the sixth scan line G3B.

[0076] As shown in Figure 8, the first pixel PX11 has a first transistor TFT-A, a second transistor TFT-B, and a first common electrode CE and a first pixel electrode PE separated by a liquid crystal LC. A reference potential (e.g., 0V) is supplied to the first common electrode CE from a common potential wiring COM. A capacitive element CA, acting as a first retaining capacitance element, is connected between the first pixel electrode PE and the first common electrode CE.

[0077] The second pixel PX21 has a third transistor TFT-A, a fourth transistor TFT-B, and a second common electrode CE and a second pixel electrode PE separated by a liquid crystal LC. A reference potential (e.g., 0V) is supplied to the second common electrode CE from a common potential wiring COM. A capacitive element CA, acting as a second retaining capacitance element, is connected between the second pixel electrode PE and the second common electrode CE.

[0078] The third pixel PX31 has a fifth transistor TFT-A, a sixth transistor TFT-B, and a third common electrode CE and a third pixel electrode PE separated by a liquid crystal LC. A reference potential (e.g., 0V) is supplied to the third common electrode CE from a common potential wiring COM. A capacitive element CA, acting as a third retaining capacitance element, is connected between the third pixel electrode PE and the third common electrode CE.

[0079] The gate of the first transistor TFT-A of the first pixel PX11 is connected to the first scan line G1A, one of the source and drain of the first transistor TFT-A is connected to the first signal line S1A, and the other of the source and drain of the first transistor TFT-A is connected to the first pixel electrode PE via the first capacitive element CB.

[0080] The gate of the second transistor TFT-B of the first pixel PX11 is connected to the second scan line G1B, one of the source and drain of the second transistor TFT-B is connected to the second signal line S1B, and the other of the source and drain of the second transistor TFT-B is connected to the first pixel electrode PE.

[0081] The gate of the third transistor TFT-A of the second pixel PX21 is connected to the third scan line G2A, one of the source and drain of the third transistor TFT-A is connected to the second signal line S1B, and the other of the source and drain of the third transistor TFT-A is connected to the second pixel electrode PE via the second capacitance element CB.

[0082] The gate of the fourth transistor TFT-B of the second pixel PX21 is connected to the fourth scan line G2B, one of the source and drain of the fourth transistor TFT-B is connected to the third signal line S1C, and the other of the source and drain of the fourth transistor TFT-B is connected to the second pixel electrode PE.

[0083] The gate of the fifth transistor TFT-A of the third pixel PX31 is connected to the fifth scan line G3A, one of the source and drain of the fifth transistor TFT-A is connected to the third signal line S1C, and the other of the source and drain of the fifth transistor TFT-A is connected to the third pixel electrode PE via the third capacitance element CB.

[0084] The gate of the sixth transistor TFT-B of the third pixel PX31 is connected to the sixth scan line G3B, one of the source and drain of the sixth transistor TFT-B is connected to the first signal line S1A, and the other of the source and drain of the sixth transistor TFT-B is connected to the third pixel electrode PE.

[0085] Next, Figure 9, similar to Figure 6, depicts the first period P1, the second period P2 following the first period P1, the third period P3 following the second period P2, and the fourth period P4 following the third period P3. After the fourth period P4, the fifth period P5 following the fourth period P4, the sixth period P6 following the fifth period P5, and the seventh period P7 following the sixth period P6 are depicted.

[0086] During the first period P1, the first scan line G1A and the second scan line G1B transition from a low level (unselected state) to a high level (selected state), and both the first transistor TFT-A and the second transistor TFT-B of the first pixel PX11 in the first row are turned on. At this time, a voltage (-V1: e.g., -6.1V) is written from the first signal line S1A to the first capacitive element CB of the first pixel PX11, and a voltage (+V1: e.g., +6.1V) is written from the second signal line S1B to the capacitive element CA of the first pixel PX11. The third signal line S1C is set to a voltage (-V1: e.g., -6.1V). The third scan line G2A, the fourth scan line G2B, the fifth scan line G3A, and the sixth scan line G3B are at a low level, and then the first scan line G1A remains at a high level, while the second scan line G1B transitions from a high level to a low level.

[0087] During the second period P2, a voltage (+V1: e.g., +6.1V) is written from the first signal line S1A to the first capacitive element CB of the first pixel PX11. This causes the voltage of the first pixel electrode PE of the first pixel PX11 to be boosted by capacitive coupling by the first capacitive element CB. The voltage of the first pixel electrode PE is boosted (stepped up) from, for example, +V1 (e.g., +6.1V) to +V2 (e.g., +14V). Subsequently, the first scan line G1A transitions from a high level to a low level. The second scan line G1B, the fifth scan line G3A, and the sixth scan line G3B remain at a low level.

[0088] Furthermore, during the second period P2, the third scan line G2A and the fourth scan line G2B transition from a low level (unselected state) to a high level (selected state), and both the third transistor TFT-A and the fourth transistor TFT-B of the second pixel PX21 in the second row are turned ON. At this time, a voltage (-V1: for example, -6.1V) is written from the second signal line S1B to the second capacitive element CB of the second pixel PX21, and a voltage (+V1: for example, +6.1V) is written from the third signal line S1C to the capacitive element CA of the second pixel PX21. After that, the third scan line G2A remains at a high level, and the fourth scan line G2B transitions from a high level to a low level.

[0089] During the third period P3, a voltage (+V1: e.g., +6.1V) is written from the second signal line S1B to the second capacitive element CB of the second pixel PX21. This causes the voltage of the second pixel electrode PE of the second pixel PX21 to be boosted by capacitive coupling by the second capacitive element CB. The voltage of the second pixel electrode PE is boosted (stepped up) from, for example, +V1 (e.g., +6.1V) to +V2 (e.g., +14V). Subsequently, the fifth scan line G3A transitions from a high level to a low level. The first scan line G1A, the second scan line G1B, and the fourth scan line G2B remain at a low level.

[0090] Furthermore, during the third period P3, the fifth scan line G3A and the sixth scan line G3B transition from a low level (unselected state) to a high level (selected state), and both the fifth transistor TFT-A and the fifth transistor TFT-B of the third pixel PX31 in the third row are turned ON. At this time, a voltage (-V1: for example, -6.1V) is written from the third signal line S1C to the third capacitance element CB of the third pixel PX31, and a voltage (+V1: for example, +6.1V) is written from the first signal line S1A to the capacitance element CA of the third pixel PX31. After that, the fifth scan line G3A remains at a high level, and the sixth scan line G3B transitions from a high level to a low level.

[0091] During the fourth period P4, a voltage (+V1: e.g., +6.1V) is written from the third signal line S1C to the third capacitive element CB of the third pixel PX31. This causes the voltage of the third pixel electrode PE of the third pixel PX31 to be boosted by capacitive coupling by the third capacitive element CB. The voltage of the third pixel electrode PE is boosted (stepped up) from, for example, +V1 (e.g., +6.1V) to +V2 (e.g., +14V). Subsequently, the sixth scan line G3B transitions from a high level to a low level. The first scan line G1A, the second scan line G1B, the third scan line G2A, and the fourth scan line G2B remain at a low level.

[0092] Furthermore, during the fourth period P4, the seventh scan line G4A and the eighth scan line G4B (not shown) transition from a low level (unselected state) to a high level (selected state), and both transistors TFT-A and TFT-B of the fourth pixel PX41 in the fourth row (not shown) are turned ON. At this time, a voltage (-V1: e.g., -6.1V) is written from the first signal line S1A to the capacitive element CB of the fourth pixel PX41, and a voltage (+V1: e.g., +6.1V) is written from the second signal line S1B to the capacitive element CA of the third pixel PX31. After that, the seventh scan line G4A remains at a high level, and the eighth scan line G4B transitions from a high level to a low level.

[0093] After the fourth period P4, the fifth period P5 operates similarly to the second period P2, with the first signal line S1A, second signal line S1B, and third signal line S1C performing a voltage boost operation on the pixel electrode PE of the fourth pixel PX41 in the fourth row. In the sixth period P6, the first signal line S1A, second signal line S1B, and third signal line S1C operate similarly to the third period P3, performing a voltage boost operation on the pixel electrode PE of the fifth pixel PX51 in the fifth row. In the seventh period P7, the voltage boost operation on the pixel electrode PE of the sixth pixel PX61 in the sixth row is performed. In the seventh period, a voltage (+V1: for example, +6.1V) is written from the first signal line S1A to the capacitive element CB of the seventh pixel PX71 in the seventh row, and a voltage (-V1: for example, +6.1V) is written from the second signal line S1B to the capacitive element CA of the seventh pixel PX71. After this, a negative polarity step-down operation is performed, so the potentials of the first signal line S1A, the second signal line S1B, and the third signal line S1C during periods 7-12 are changed to the opposite potentials of the first signal line S1A, the second signal line S1B, and the third signal line S1C during periods 1-6 (positive polarity is changed to negative polarity, and negative polarity is changed to positive polarity).

[0094] Through the operations described above, writing is performed to each line of the display area 2 of the display device 1a.

[0095] Therefore, it can be summarized as follows:

[0096] The first signal line S1A is set to a negative voltage relative to the reference potential during the first period P1, a positive voltage relative to the reference potential during the second period P2 and the third period P3, and a negative voltage during the fourth period P.

[0097] The second signal line S1B is set to a positive potential during the first period P1, to a negative voltage during the second period P2, and to a positive potential continuously during the third period P3 and the fourth period P4.

[0098] The third signal line S1C is subjected to a negative voltage during the first period P1, a positive voltage during the second period P2, a negative voltage during the third period P3, and a positive voltage during the fourth period P4.

[0099] The first scan line G1A transitions from a low level to a high level during the first period P1, and then transitions from a high level to a low level during the second period P2.

[0100] The second scan line G1B transitions in the order of low level, high level, and low level during the first period P1.

[0101] The third scan line G2A transitions from a low level to a high level during the second period P2, and then transitions from a high level to a low level during the third period.

[0102] The fourth scan line G2B transitions in the second period P2 in the order of low level, high level, and low level.

[0103] The fifth scan line G3A transitions from a low level to a high level in the third period P3, and then transitions from a high level to a low level in the fourth period P4.

[0104] The sixth scan line G3B transitions to a low level, then a high level, then another low level in the third period P3.

[0105] In this way, the first half of the operation of the pixel in the (m+1)th row can be superimposed on the second half of the horizontal period of the pixel in the mth row, and the first half of the operation of the pixel in the m+2nd row can be superimposed on the second half of the operation of the pixel in the m+1st row, allowing them to be driven simultaneously. Therefore, if we consider the horizontal period of a typical pixel to be H, then the pixels in the yth row as a whole can be driven simultaneously. (y+1)×H=(y×H)+H By simply increasing the H factor, it can be driven in almost the same amount of time as a typical pixel.

[0106] In the comparative example, the boosted pixels have two signal lines as a pair per pixel, and the horizontal period takes twice as long as that of a typical pixel. Therefore, in a display device with y rows for the entire screen, (y × H × 2) This takes twice as long. In other words, the number of pixel rows that can be driven per frame is halved.

[0107] In both Example 1 and Example 2, the apparent horizontal period is equivalent to that of a typical pixel, but in Example 2, the number of signal lines passing through one pixel is 3, while in Example 1, the number of signal lines passing through the same pixel is 4. Therefore, Example 2 has a higher aperture ratio compared to Example 1, which is advantageous.

[0108] This enables boosted pixels without reducing the number of pixels (rows), and allows the amplitude of the pixel electrodes to be increased relative to the output amplitude of the source driver IC (signal line driving circuit 4). Furthermore, it enables the provision of a transparent display with high display performance using a general-purpose source driver IC.

[0109] (Transparent display) Next, a transparent display will be described using Figures 10A, 10B, 11A, and 11B. Figure 10A is a schematic diagram showing the liquid crystal layer 30 in a transparent state. Figure 10B is a schematic diagram showing the liquid crystal layer 30 in a scattered state. Figure 11A is a cross-sectional view showing the display panel PNL when the liquid crystal layer 30 is in a transparent state. Figure 11B is a cross-sectional view showing the display panel PNL when the liquid crystal layer 30 is in a scattered state.

[0110] In the following description, the display devices 1 and 1a, which are transparent displays, are described as display panels, and the liquid crystal LC is described as the liquid crystal layer 30. Below, an example configuration of a display device equipped with a liquid crystal layer 30, which is a polymer-dispersed liquid crystal (PDLC) layer, is described.

[0111] Figure 10A is a schematic diagram showing the transparent liquid crystal layer 30. As shown in Figure 10A, the liquid crystal layer 30 contains a liquid crystalline polymer 31 and liquid crystalline molecules 32. The liquid crystalline polymer 31 is obtained, for example, by polymerizing liquid crystalline monomers in a state where they are oriented in a predetermined direction by the orientation restricting force of the alignment films AF1 and AF2. The liquid crystalline molecules 32 are dispersed within the liquid crystalline monomers and are oriented in a predetermined direction depending on the orientation direction of the liquid crystalline monomers when the liquid crystalline monomers are polymerized. The alignment films AF1 and AF2 may be horizontal alignment films that orient the liquid crystalline monomers and liquid crystalline molecules 32 along the XY plane defined by the first direction X and the second direction Y, or they may be vertical alignment films that orient the liquid crystalline monomers and liquid crystalline molecules 32 along the third direction Z.

[0112] The liquid crystalline molecule 32 may be a positive-type molecule with positive dielectric anisotropy, or a negative-type molecule with negative dielectric anisotropy. The liquid crystalline polymer 31 and the liquid crystalline molecule 32 each have equivalent optical anisotropy. Alternatively, the liquid crystalline polymer 31 and the liquid crystalline molecule 32 each have approximately equivalent refractive index anisotropy. That is, the ordinary refractive index and the extraordinary refractive index of the liquid crystalline polymer 31 and the liquid crystalline molecule 32 are approximately equivalent. Note that the values ​​of the ordinary refractive index and the extraordinary refractive index of the liquid crystalline polymer 31 and the liquid crystalline molecule 32 do not need to be exactly the same, and deviations due to manufacturing errors, etc., are acceptable. Furthermore, the responsiveness of the liquid crystalline polymer 31 and the liquid crystalline molecule 32 to electric fields are different. That is, the responsiveness of the liquid crystalline polymer 31 to electric fields is lower than that of the liquid crystalline molecule 32 to electric fields.

[0113] The example shown in Figure 10A corresponds, for example, to a state where no voltage is applied to the liquid crystal layer 30 (a state where the potential difference between the pixel electrode PE and the common electrode CE is zero), or to a state where the second transparency voltage, described later, is applied to the liquid crystal layer 30.

[0114] As shown in Figure 10A, the optical axis Ax1 of the liquid crystalline polymer 31 and the optical axis Ax2 of the liquid crystalline molecule 32 are parallel to each other. In the illustrated example, both optical axes Ax1 and Ax2 are parallel to the third direction Z. Here, the optical axis corresponds to a line parallel to the direction of propagation of a light ray such that the refractive index is a single value regardless of the polarization direction.

[0115] As described above, the liquid crystalline polymer 31 and the liquid crystalline molecules 32 have approximately equivalent refractive index anisotropy, and furthermore, since the optical axes Ax1 and Ax2 are parallel to each other, there is almost no difference in refractive index between the liquid crystalline polymer 31 and the liquid crystalline molecules 32 in all directions, including the first direction X, the second direction Y, and the third direction Z. For this reason, light L1 incident on the liquid crystal layer 30 in the third direction Z is transmitted within the liquid crystal layer 30 without being substantially scattered. The liquid crystal layer 30 can maintain the parallelism of light L1. Similarly, light L2 and L3 incident in an oblique direction tilted with respect to the third direction Z are also hardly scattered within the liquid crystal layer 30. For this reason, high transparency is obtained. The state shown in Figure 10A is referred to as the "transparent state".

[0116] Figure 10B schematically shows the liquid crystal layer 30 in a scattering state. As shown in Figure 10B, as described above, the response of the liquid crystalline polymer 31 to the electric field is lower than the response of the liquid crystalline molecules 32 to the electric field. Therefore, when a voltage higher than the second transparency voltage and the first transparency voltage (described later) is applied to the liquid crystal layer 30, the orientation direction of the liquid crystalline polymer 31 hardly changes, while the orientation direction of the liquid crystalline molecules 32 changes in response to the electric field. In other words, as shown in the figure, the optical axis Ax1 is almost parallel to the third direction Z, while the optical axis Ax2 is tilted with respect to the third direction Z. Therefore, the optical axes Ax1 and Ax2 intersect each other. Consequently, a large refractive index difference occurs between the liquid crystalline polymer 31 and the liquid crystalline molecules 32 in all directions, including the first direction X, the second direction Y, and the third direction Z. As a result, the light L1 to L3 incident on the liquid crystal layer 30 is scattered within the liquid crystal layer 30. The state shown in Figure 10B is called the 'scattering state'.

[0117] The above-mentioned drive unit DR switches the liquid crystal layer 30 to at least one of a transparent state and a scattered state.

[0118] Figure 11A is a cross-sectional view showing a display panel PNL when the liquid crystal layer 30 is transparent. As shown in Figure 11A, illumination light L11 emitted from a light-emitting element LS such as an LED element enters the display panel PNL from the edge 20E and propagates through the transparent substrate 20, the liquid crystal layer 30, the transparent substrate 10, etc. When the liquid crystal layer 30 is transparent, the illumination light L11 is hardly scattered by the liquid crystal layer 30, so it hardly leaks out from the lower surface 10B of the transparent substrate 10 and the upper surface 20T of the transparent substrate 20. The transparent substrate 10 can be made up of, for example, a cover glass and an array substrate provided above the cover glass. The transparent substrate 20 can be made up of a transparent light guide plate and a counter substrate facing the array substrate provided below the transparent light guide plate. The liquid crystal layer 30 is provided between the array substrate and the counter substrate.

[0119] External light L12 incident on the display panel PNL is transmitted through the liquid crystal layer 30 with almost no scattering. In other words, external light incident on the display panel PNL from the bottom surface 10B is transmitted to the top surface 20T, and external light incident on the top surface 20T is transmitted to the bottom surface 10B. Therefore, when the display panel PNL is observed from the top surface 20T side, the user can see the background on the bottom surface 10B side by looking through the display panel PNL. Similarly, when the display panel PNL is observed from the bottom surface 10B side, the user can see the background on the top surface 20T side by looking through the display panel PNL.

[0120] Figure 11B is a cross-sectional view showing a display panel PNL when the liquid crystal layer 30 is in a scattering state. As shown in Figure 11B, illumination light L21 emitted from the light-emitting element LS enters the display panel PNL from the edge 20E and propagates through the transparent substrate 20, the liquid crystal layer 30, the transparent substrate 10, etc. In the illustrated example, the liquid crystal layer 30 between the pixel electrode PEα and the common electrode CE (the liquid crystal layer to which the voltage applied between the pixel electrode PEα and the common electrode CE is applied) is transparent, so the illumination light L21 is hardly scattered in the region of the liquid crystal layer 30 facing the pixel electrode PEα. On the other hand, the liquid crystal layer 30 between the pixel electrode PEβ and the common electrode CE (the liquid crystal layer to which the voltage applied between the pixel electrode PEβ and the common electrode CE is applied) is in a scattering state, so the illumination light L21 is scattered in the region of the liquid crystal layer 30 facing the pixel electrode PEβ. Of the illumination light L21, some scattered light L211 is emitted to the outside from the upper surface 20T, and some scattered light L212 is emitted to the outside from the lower surface 10B.

[0121] At the position overlapping with the pixel electrode PEα, the external light L22 incident on the display panel PNL is transmitted through the liquid crystal layer 30 with almost no scattering, similar to the external light L12 shown in Figure 11A. At the position overlapping with the pixel electrode PEβ, the external light L23 incident from the lower surface 10B is transmitted through the upper surface 20T after some of its light L231 is scattered by the liquid crystal layer 30. Similarly, the external light L24 incident from the upper surface 20T is transmitted through the lower surface 10B after some of its light L241 is scattered by the liquid crystal layer 30.

[0122] Therefore, when the display panel PNL is observed from the top surface 20T side, the color of the illumination light L21 can be seen at the position where it overlaps with the pixel electrode PEβ. In addition, since some of the external light L231 passes through the display panel PNL, the background on the bottom surface 10B side can also be seen by looking through the display panel PNL. Similarly, when the display panel PNL is observed from the bottom surface 10B side, the color of the illumination light L21 can be seen at the position where it overlaps with the pixel electrode PEβ. In addition, since some of the external light L241 passes through the display panel PNL, the background on the top surface 20T side can also be seen by looking through the display panel PNL. Note that at the position where it overlaps with the pixel electrode PEα, the liquid crystal layer 30 is transparent, so the color of the illumination light L21 is hardly visible, and the background can be seen by looking through the display panel PNL.

[0123] All display devices that a person skilled in the art can implement by appropriately modifying the design based on the display devices described above as embodiments of this disclosure also fall within the scope of this disclosure, insofar as they encompass the gist of this disclosure.

[0124] Within the scope of the ideas presented herein, a person skilled in the art will be able to conceive of various modifications and alterations, and such modifications and alterations will also be understood to fall within the scope of this disclosure. For example, any addition, deletion, or design change of components, or addition, omission, or modification of processes, to the above embodiments, as appropriate by a person skilled in the art, will also be included within the scope of this disclosure, as long as they retain the gist of this disclosure.

[0125] Furthermore, any other effects and advantages brought about by the embodiments described herein that are obvious from this specification or that can be appropriately conceived by those skilled in the art are naturally provided by this disclosure.

[0126] Various disclosures can be formed by appropriately combining the multiple components disclosed in the above embodiments. For example, some components may be removed from all the components shown in the embodiments. Furthermore, components from different embodiments may be appropriately combined. [Explanation of symbols]

[0127] 1, 1a: Display device, 2: Display area, 3: Gate drive circuit (GD), 4: Signal line drive circuit (SD), PX: Multiple pixels, LC: Liquid crystal, CE: Common electrode, PE: Pixel electrode, SL: Signal line, TFT-A, TFT-B: Transistor, CA, CB: Capacitive elements.

Claims

1. Multiple pixels arranged in a matrix, A first scan line, a second scan line, a third scan line, and a fourth scan line extending in a first direction and arranged in a second direction intersecting the first direction, It includes a first signal line, a second signal line, a third signal line, and a fourth signal line that extend in the second direction and are arranged in the first direction, The plurality of pixels include a first pixel and a second pixel adjacent to the first pixel in the second direction, The first pixel comprises a first transistor, a second transistor, a first common electrode and a first pixel electrode separated by a liquid crystal, and a reference potential is supplied to the first common electrode. The gate of the first transistor is connected to the first scan line, one of the source and drain of the first transistor is connected to the first signal line, and the other of the source and drain of the first transistor is connected to the first pixel electrode of the first pixel via a first capacitor. The gate of the second transistor is connected to the second scan line, one of the source and drain of the second transistor is connected to the second signal line, and the other of the source and drain of the second transistor is connected to the first pixel electrode of the first pixel. The second pixel has a third transistor, a fourth transistor, a second common electrode and a second pixel electrode with the liquid crystal in between, and the reference potential is supplied to the second common electrode. The gate of the third transistor is connected to the third scanning line, one of the source and drain of the third transistor is connected to the third signal line, and the other of the source and drain of the third transistor is connected to the second pixel electrode via a second capacitor. A display device in which the gate of the fourth transistor is connected to the fourth scan line, one of the source and drain of the fourth transistor is connected to the fourth signal line, and the other of the source and drain of the fourth transistor is connected to the second pixel electrode.

2. In the display device according to claim 1, It has a first period, a second period following the first period, a third period following the second period, and a fourth period following the third period. During the first and fourth periods, a negative polarity is applied to the first and third signal lines with respect to the reference potential, and a positive polarity is applied to the second and fourth signal lines with respect to the reference potential. During the second and third periods, a positive polarity is applied to the first and third signal lines with respect to the reference potential, and a negative polarity is applied to the second and fourth signal lines with respect to the reference potential. During the first period, the second scan line and the fourth scan line transition in the order of low level, high level, and low level. During the first period, the first scan line and the third scan line transition from a low level to a high level. A display device in which, during the second period, the first scan line and the third scan line transition from a high level to a low level.

3. In the display device according to claim 1, The liquid crystal is a polymer-dispersed liquid crystal, which is used in the display device.

4. Multiple pixels arranged in a matrix, A first scan line, a second scan line, a third scan line, a fourth scan line, a fifth scan line, and a sixth scan line extending in a first direction and arranged in a second direction intersecting the first direction, It includes a first signal line, a second signal line, and a third signal line extending in the second direction and arranged in the first direction, The plurality of pixels are arranged adjacently in the second direction and include a first pixel, a second pixel, and a third pixel. The first pixel has a first transistor, a second transistor, a first common electrode and a first pixel electrode separated by a liquid crystal, and a reference potential is supplied to the first common electrode. The second pixel has a third transistor, a fourth transistor, a second common electrode and a second pixel electrode with the liquid crystal in between, and the reference potential is supplied to the second common electrode. The third pixel has a fifth transistor, a sixth transistor, a third common electrode and a third pixel electrode with the liquid crystal in between, and the reference potential is supplied to the third common electrode. The gate of the first transistor of the first pixel is connected to the first scan line, one of the source and drain of the first transistor is connected to the first signal line, and the other of the source and drain of the first transistor is connected to the first pixel electrode via a first capacitor. The gate of the second transistor of the first pixel is connected to the second scan line, one of the source and drain of the second transistor is connected to the second signal line, and the other of the source and drain of the second transistor is connected to the first pixel electrode. The gate of the third transistor of the second pixel is connected to the third scan line, one of the source and drain of the third transistor is connected to the second signal line, and the other of the source and drain of the third transistor is connected to the second pixel electrode via a second capacitor. The gate of the fourth transistor of the second pixel is connected to the fourth scan line, one of the source and drain of the fourth transistor is connected to the third signal line, and the other of the source and drain of the fourth transistor is connected to the second pixel electrode. The gate of the fifth transistor of the third pixel is connected to the fifth scan line, one of the source and drain of the fifth transistor is connected to the third signal line, and the other of the source and drain of the fifth transistor is connected to the third pixel electrode via a third capacitor. A display device wherein the gate of the sixth transistor of the third pixel is connected to the sixth scan line, one of the source and drain of the sixth transistor is connected to the first signal line, and the other of the source and drain of the sixth transistor is connected to the third pixel electrode.

5. In the display device according to claim 4, It has a first period, a second period following the first period, a third period following the second period, and a fourth period following the third period. The first signal line is negatively polarized with respect to the reference potential during the first period, positively polarized with respect to the reference potential during the second and third periods, and negatively polarized during the fourth period. The second signal line is configured to have positive polarity during the first period, negative polarity during the second period, and positive polarity continuously during the third and fourth periods. The third signal line is configured to have negative polarity during the first period, positive polarity during the second period, negative polarity during the third period, and positive polarity during the fourth period. The first scan line transitions from a low level to a high level during the first period, and transitions from the high level to the low level during the second period. The second scan line transitions in the order of low level, high level, and low level during the first period. The third scan line transitions from a low level to a high level during the second period, and transitions from the high level to the low level during the third period. The fourth scan line transitions in the order of low level, high level, and then low level again during the second period. The fifth scan line transitions from a low level to a high level during the third period, and from the high level to the low level during the fourth period. The sixth scan line is a display device that transitions in the order of low level, high level, and low level during the third period.

6. In the display device according to claim 4, The liquid crystal is a polymer-dispersed liquid crystal, which is used in the display device.

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