Information processing device and memory system

Abstract

Efficiently perform sparse vector operations on a small hardware scale. [Solution] The information processing device includes a string connected to a first wire and to a plurality of second wires. The string has a plurality of transistors connected to each other. The plurality of transistors include first and second transistors. The first transistor is set to a first threshold corresponding to the first data. The second transistor is set to a second threshold corresponding to the second data which is complementary to the first data. Two of the plurality of second wires are connected to the gates of the first and second transistors. One of the two second wires is set to a potential level corresponding to the third data, and the other is set to a potential level corresponding to the fourth data which is complementary to the third data. The string does not conduct current when the first and third data match at predetermined values, and conducts current when the first and third data match at values ​​other than the predetermined values.

Description

Technical Field

[0001] One embodiment of the present invention relates to an information processing apparatus and a memory system.

Background Art

[0002] Natural language processing needs to analyze the meaning of sentences containing a huge number of vocabulary and words. When natural language processing is performed by software, it takes a considerable amount of time to obtain the results. Therefore, research on performing natural language processing by hardware has been underway.

[0003] When each vocabulary constituting a sentence handled in natural language processing is expressed as a vector, and the number of dimensions of the vector is the number of vocabulary and the words included in the vocabulary are the element positions of the vector, since the number of words is overwhelmingly smaller than the number of vocabulary, the frequency of non-zero elements in each vector becomes a very sparse vector. By storing such sparse vectors in a semiconductor memory device and performing an inner product operation by hardware, an analog judgment between vocabularies can be made. However, storing a huge number of sparse vectors in a semiconductor memory device not only deteriorates the calculation efficiency but also becomes a factor that wastes hardware resources and power consumption.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0005] Therefore, one embodiment of the present invention provides an information processing device and memory system that can efficiently perform sparse vector operations on a small hardware scale. [Means for solving the problem]

[0006] To solve the above problems, according to one embodiment of the present invention, a string is provided which is connected to a first wiring and also connected to a plurality of second wirings, The string has a plurality of transistors, one end of which is connected to the first wiring, each of which gates is connected to a different second wiring, and which are connected to each other. The plurality of transistors include a first transistor and a second transistor, The first transistor is set to a first threshold value corresponding to the first data, The second transistor is set to a second threshold corresponding to the second data which is complementary to the first data, Two of the aforementioned plurality of second wires are connected to the gates of the first transistor and the second transistor. One of the two second wires is set to a potential level corresponding to the third data, and the other is set to a potential level corresponding to the fourth data which is complementary to the third data. The string does not conduct current when the first data and the third data match with a predetermined value, and conducts current when the first data and the third data match with a value other than the predetermined value. An information processing device is provided. [Brief explanation of the drawing]

[0007] [Figure 1] A diagram showing an arbitrary sentence, which is the target of analysis in natural language processing, represented as a vector. [Figure 2] A diagram illustrating vocabulary vectors containing specific words. [Figure 3] A diagram illustrating an example of performing an inner product operation on two sparse vectors. [Figure 4]A diagram summarizing the results of the inner product operation between two sparse vectors. [Figure 5] A circuit diagram showing an example of strings used in dot product operations. [Figure 6] A diagram showing the first and second transistors within a string when it is multi-level data. [Figure 7] A diagram showing the relationship between the threshold voltage and gate voltage of the first and second transistors. [Figure 8] A figure showing the result of the dot product operation between a 2-bit key and a 2-bit query in one comparative example. [Figure 9] A figure showing the relationship between the threshold distribution and gate voltage of the first and second transistors in one comparative example. [Figure 10] This figure shows the result of the dot product operation between a 2-bit key and a 2-bit query in this embodiment. [Figure 11] This figure shows the relationship between the threshold distribution and gate voltage of the first and second transistors in this embodiment. [Figure 12] This figure shows the relationship between the threshold voltage distribution and gate voltage of the first and second transistors in one modified example of this embodiment. [Figure 13] This diagram illustrates an example of changing the current flowing through a string based on matching values ​​between the key and the query. [Figure 14] A diagram illustrating an example of splitting a key and query vector into multiple partition vectors. [Figure 15] A diagram showing the connections between multiple partitioning strings corresponding to multiple partitioning vectors and bit lines BL. [Figure 16] A diagram showing a vector with n elements, where the 254th element is "1" and all other elements are "0". [Figure 17] This figure shows an example where both the key vector and the query vector are represented by vectors similar to those in Figure 16. [Figure 18] Figure 17 shows the result of performing a dot product operation on the two vectors shown. [Figure 19]Circuit diagram of a string for comparing keys and queries in FIGS. 17 and 18. [Figure 20] Block diagram showing a schematic configuration of an information processing apparatus according to the present embodiment. [Figure 21] Circuit diagram showing an example of dividing a string into two divided strings and connecting them to the same bit line. [Figure 22] Diagram showing inner product values in the first example of dividing a string into two divided strings. [Figure 23] Diagram showing inner product values in the second example of dividing a string into two divided strings. [Figure 24] Diagram showing inner product values in the third example of dividing a string into two divided strings. [Figure 25] Diagram showing inner product values in the fourth example of dividing a string into two divided strings.

Mode for Carrying Out the Invention

[0008] Hereinafter, embodiments of an information processing apparatus and a memory system will be described with reference to the drawings. Hereinafter, the main components of the information processing apparatus and the memory system will be mainly described, but there may be components and functions that are not shown or described in the information processing apparatus and the memory system. The following description does not exclude components and functions that are not shown or described.

[0009] FIG. 1 is a diagram showing an arbitrary sentence to be analyzed in natural language processing represented as a vector. In natural language processing, a sentence is projected onto a multi-dimensional space, each vocabulary constituting the sentence is represented as a vector, the number of dimensions of the vector is the number of vocabularies, and the words included in the vocabulary are the element positions of the vector. For example, the element position of the vector for specifying an individual word is set to "1", and the other elements are set to "0".

[0010] FIG. 1 shows a vector representing the vocabulary "Even a dog walks". Each word such as "dog", "also", "walk", "and" is identified by the position of the element "1" in the vector.

[0011] As shown in Figure 1, the vectors handled in natural language processing are sparse vectors, meaning that the number of elements "1" is overwhelmingly small compared to the number of dimensions of the vector.

[0012] Figure 2 illustrates a vector representing a vocabulary containing a specific word. A vocabulary containing a specific word is represented by a vector in which, for example, the 8th element of an n-dimensional vector (where n is an integer greater than or equal to 1) is set to "1". The position of the "1" element in the vector differs depending on the type of word included in the vocabulary.

[0013] Figure 3 shows an example of performing an inner product operation on two sparse vectors. If two sparse vectors of equal dimensions contain the same word, the same element position will be "1," so the result of the inner product operation will be "1," indicating that the two vocabulary words contain the same word.

[0014] Figure 4 summarizes the results of the dot product operation between two sparse vectors. Figure 4 shows the results of the dot product operation when each of two sparse vectors, each having (n+1) elements, contains at most one element "1". In Figure 4, the two sparse vectors are called key K and query Q. As shown in Figure 4, the dot product value is "1" when the same element position in the two sparse vectors corresponding to key K and query Q is "1". Also, the dot product value is zero when both sparse vectors are zero, i.e., do not contain the element "1".

[0015] Thus, when performing an inner product operation on sparse vectors, if all elements of the sparse vectors are zero (all zeros), the inner product value must be zero.

[0016] The dot product operation between vectors can be performed using a string of transistors connected in a cascode configuration. Figure 5 is a circuit diagram showing an example of a string 1 used for the dot product operation. The string 1 shown in Figure 5 is, for example, part of a memory cell array in a semiconductor memory device.

[0017] Here, semiconductor memory devices refer to non-volatile memories such as NAND flash memory, ReRAM (Resistive Random Access Memory), and PCM (Phase-Change Memory). Alternatively, the semiconductor memory devices mentioned above may be volatile memories such as DRAM (Dynamic RAM) or SRAM (Static RAM). This specification mainly describes an example using string 1 made of NAND flash memory, but string 1 may be constructed using semiconductor memory devices other than NAND flash memory.

[0018] String 1, shown in Figure 5, has multiple transistors connected in a cascode configuration. Figure 5 shows an example of String 1 having a cascode-connected first transistor Tr1 and a second transistor Tr2. In addition to the first transistor Tr1 and the second transistor Tr2, String 1 can be constructed by connecting any number of transistors in a cascode configuration.

[0019] One end of string 1 is connected to the bit line (first wiring) BL. Different word lines WL1 and WL2 are connected to the gates of the first and second transistors Tr1 and Tr2 in string 1, respectively. In this specification, multiple word lines WL1, WL2, etc., may be collectively referred to as word line WL.

[0020] Multiple transistors within string 1 store data supplied via the bit line BL, with the word line WL connected to their respective gates set to a predetermined potential level. For example, in the case of string 1 of NAND flash memory, each transistor within string 1 stores a charge corresponding to the data in a floating gate or charge storage film. Storing data in a transistor changes its threshold voltage. A change in the transistor's threshold voltage changes the gate potential level at which the transistor turns on.

[0021] Among the multiple transistors in each string 1, the first transistor Tr1 and the second transistor Tr2 are used to store a key K consisting of multiple bits. In this embodiment, it is assumed that each bit of key K is multi-valued data, but first, an example where each bit of key K is binary (0 or 1) will be described.

[0022] The value of each bit of key K is stored in a first transistor Tr1 and a second transistor Tr2 in separate strings 1. The first transistor Tr1 in each string 1 stores the value of the corresponding bit of key K, and the second transistor Tr2, which is cascode-connected to the first transistor Tr1, stores a value that is the complement of the value of the corresponding bit of key K. The complement value is the bit-inverted data. For example, if the first transistor Tr1 stores 0, the second transistor Tr2 stores 1. In this specification, the multi-bit key K is referred to as the first data, and the complement data of key K is referred to as the second data.

[0023] In this specification, when we say that the first transistor Tr1 stores 0, we mean that the threshold of the first transistor Tr1 is set to 0. In practice, the threshold of the first transistor Tr1 is set to a potential level corresponding to 0, but for the sake of simplicity, this specification describes the threshold as being set to 0.

[0024] Among the multiple transistors in String 1, the third data and fourth data are supplied to the two word lines WL1 and WL2 connected to the gates of the first transistor Tr1 and the second transistor Tr2, respectively. The third data and fourth data each consist of multiple bits, and the fourth data is the complement of the third data. That is, the fourth data is the data obtained by inverting each bit of the third data. Each bit of the third and fourth data is assumed to be multi-level data with potential levels of three or more values, but first, we will explain the example where each bit of the third and fourth data is binary (0 or 1). The third data is the corresponding bit of query Q. Each bit of query Q is supplied by a different word line.

[0025] The information processing device according to this embodiment determines whether a query Q input from an external source matches a key K stored in a plurality of strings 1 by performing an inner product operation, and outputs the result of the inner product operation via a bit line BL.

[0026] Query Q and key K each consist of multiple bits, and each bit is compared using a separate string. In this specification, key K is referred to as the first data, and query Q as the third data. Data that has a complement relationship with the first data is referred to as the second data, and data that has a complement relationship with the third data is referred to as the fourth data.

[0027] As described above, the corresponding bits of key K (first data) stored in the first transistor Tr1 and the corresponding bits of key / K (second data) stored in the second transistor Tr2 are complementary to each other. For example, if the corresponding bit of key K is "0", then the corresponding bit of key / K is "1". Thus, since the first transistor Tr1 and the second transistor Tr2 have corresponding bits of the first and second data that are complementary to each other written to them, the threshold values ​​of the first transistor Tr1 and the second transistor Tr2 will be different. In this specification, the threshold value of the first transistor Tr1 is referred to as the first threshold value, and the threshold value of the second transistor Tr2 is referred to as the second threshold value.

[0028] Figure 5 shows an example where each bit of query Q and key K is binary data. However, simply comparing the binary data of each bit only allows for a simple comparison of binary data. Recent non-volatile memories have increased their storage capacity by enabling the storage of multi-level data (three or more levels) within the memory cell. By utilizing such a non-volatile memory capable of storing multi-level data, it becomes possible to compare query Q and key K even when each bit of query Q and key K is multi-level data, thereby expanding the scope of application of the information processing device according to this embodiment.

[0029] Figure 6 shows the first transistor Tr1 and the second transistor Tr2 in string 1 when each bit of query Q and key K is a 2-bit, 4-value multi-level data. In this case, each bit of query Q and key K can take on four different potential levels, each consisting of two bits. The key K stored in the first transistor Tr1 (the first threshold of the first transistor Tr1) and the key / K stored in the second transistor Tr2 (the second threshold of the second transistor Tr2) are complementary to each other. If the first threshold of the first transistor Tr1 is K, then the second threshold of the second transistor Tr2 is 3-K.

[0030] Similarly, the query Q input to the gate of the first transistor Tr1 and the query / Q input to the gate of the second transistor Tr2 are complementary to each other. Therefore, if we denote the query Q input to the gate of the first transistor Tr1 as Q, then the query / Q input to the gate of the second transistor Tr2 can be expressed as 3-Q.

[0031] Figure 7 shows the relationship between the threshold voltage and gate voltage of the first transistor Tr1 and the second transistor Tr2. The first threshold voltage of the first transistor Tr1 in each string 1 is a value corresponding to the multi-level data of the corresponding bit of key K input via the bit line BL. Because there is some variation in the threshold voltage level for each transistor, the potential level of the first threshold voltage of the first transistor Tr1 fluctuates within a predetermined range, as shown in Figure 7. This range of variation is called the threshold distribution. The first transistor Tr1 turns on when the potential level of query Q input to its gate is greater than this threshold distribution, and turns off when it is less than this threshold distribution. The same applies to the second transistor Tr2.

[0032] From Figures 6 and 7, the first transistor Tr1 and the second transistor Tr2 are both turned on only when both equations (1) and (2) below are satisfied.

[0033] Q≧K …(1) 3-Q≧3-K …(2) By rearranging equation (2), we obtain equation (3).

[0034] Q ≤ K …(3) The condition that satisfies both equation (1) and equation (3) is expressed by equation (4).

[0035] Q=K …(4) Thus, both the first transistor Tr1 and the second transistor Tr2 within each string 1 are turned on only when the multi-valued data of the corresponding bits of query Q and key K match.

[0036] Figure 8 shows the result of the dot product operation between a 2-bit key K and a 2-bit query Q in one example. As shown in Figure 8, key K and query Q can take values ​​of 0, 1, 2, or 3. The dot product value is "1" only when the values ​​of key K and query Q match. That is, even when both key K and query Q are "0", the dot product value is "1". In this way, the dot product value is the result of performing a negative exclusive OR (XNOR) operation on key K and query Q.

[0037] Figure 9 shows the relationship between the threshold distribution and gate voltage of the first transistor Tr1 and the second transistor Tr2 in one comparative example. The upper part of Figure 9 shows the relationship between the threshold distribution and gate voltage of the first transistor Tr1, and the lower part of Figure 9 shows the relationship between the threshold distribution and gate voltage of the second transistor Tr2.

[0038] As shown in Figure 9, when query Q and key K match, the gate voltages of the first transistor Tr1 and the second transistor Tr2 are set to be greater than the threshold. This turns on the first transistor Tr1 and the second transistor Tr2, and current flows to string 1.

[0039] In contrast, in this embodiment, of the cascode-connected first transistor Tr1 and second transistor Tr2 in string 1, the first transistor Tr1 is set to a first threshold corresponding to the first data, and the second transistor Tr2 is set to a second threshold corresponding to the second data which is a complement to the first data. One word line (second wiring) WL1 connected to the gate of the first transistor Tr1 is set to a potential level corresponding to the third data, and the other word line (second wiring) WL2 connected to the gate of the second transistor Tr2 is set to a potential level corresponding to the fourth data which is a complement to the third data. String 1 does not conduct current when the first data and the third data match with a predetermined value (e.g., all zeros), but conducts current when they match with a value other than the predetermined value (e.g., any element is "1").

[0040] Figure 10 shows the result of the dot product operation between a 2-bit key K and a 2-bit query Q in this embodiment. This embodiment differs from Figure 8 in that the dot product value is set to "0" when both key K and query Q are "0".

[0041] Thus, in this embodiment, even if key K and query Q match, the dot product value is not necessarily "1". If key K and query Q match with "0", the dot product value is "0", and if key K and query Q match with a value other than "0", the dot product value is "1".

[0042] Figure 11 is a diagram showing the relationship between the threshold distribution and gate voltage of the first transistor Tr1 and the second transistor Tr2 in this embodiment. The upper part of Figure 11 shows the relationship between the threshold distribution and gate voltage of the first transistor Tr1, and the lower part shows the relationship between the threshold distribution and gate voltage of the second transistor Tr2.

[0043] If key K and query Q match with a value other than "0", the gate voltages of the first transistor Tr1 and the second transistor Tr2 are set to be greater than the threshold. This turns on the first transistor Tr1 and the second transistor Tr2, and current flows to string 1.

[0044] If key K and query Q match with "0", the gate voltages of the first transistor Tr1 and the second transistor Tr2 are set to be less than the threshold. As a result, the first transistor Tr1 and the second transistor Tr2 are turned off, and no current flows through string 1.

[0045] Thus, in the example in Figure 11, if key K and query Q match with a predetermined value (e.g., all zeros), the gate voltage of the first transistor Tr1 is set lower than the threshold of the first transistor Tr1 (first threshold), and the gate voltage of the second transistor Tr2 is set lower than the threshold of the second transistor Tr2 (second threshold). If key K and query Q match with a value other than "0", the gate voltage of the first transistor is set to a voltage level higher than the first threshold, and the gate voltage of the second transistor Tr2 is set to a voltage level higher than the second threshold.

[0046] The relationship between the threshold distribution and gate voltage of the first transistor Tr1 and the second transistor Tr2 in this embodiment is not necessarily as shown in Figure 11. Figure 12 shows the relationship between the threshold distribution and gate voltage of the first transistor Tr1 and the second transistor Tr2 in one modified example of this embodiment. The upper part of Figure 12 shows the relationship between the threshold distribution and gate voltage of the first transistor Tr1, and the lower part shows the relationship between the threshold distribution and gate voltage of the second transistor Tr2.

[0047] In one modified example, the relationship between the threshold distribution and gate voltage of the first transistor Tr1 is the same as the relationship between the threshold distribution and gate voltage of the first transistor Tr1 in one comparative example in Figure 9. In one modified example, the relationship between the threshold distribution and gate voltage of the second transistor Tr2 differs from one comparative example in Figure 9 in that the gate voltage of the second transistor Tr2 is lower than the threshold when key K and query Q coincide at "0". In one modified example, the gate voltage when query Q is "0" is made the same as the gate voltage when query Q is "1". As a result, when key K and query Q coincide at "0", the second transistor Tr2 is turned off and no current flows through string 1. In addition, by making the gate voltage when query Q is "0" the same as the gate voltage when query Q is "1", voltage control of the word line WL becomes easier.

[0048] In Figure 12, the relationship between the threshold distribution and gate voltage of the first transistor Tr1 is the same as in the comparative example in Figure 9, and the relationship between the threshold distribution and gate voltage of the second transistor Tr2 is set so that the gate voltage of the second transistor Tr2 is lower than the threshold when key K and query Q coincide at "0". However, the relationship between the threshold distribution and gate voltage of the second transistor Tr2 may also be set to be the same as in the comparative example in Figure 9, and the relationship between the threshold distribution and gate voltage of the first transistor Tr1 may be set so that the gate voltage of the first transistor Tr1 is lower than the threshold when key K and query Q coincide at "0".

[0049] Thus, in one modified example shown in Figure 12, when key K and query Q match with a predetermined value (e.g., all zeros), either the first transistor Tr1 or the second transistor Tr2 is turned off, and the other is turned on. When key K and query Q match with a value other than "0", the gate voltage of the first transistor is set to a voltage level higher than the first threshold, and the gate voltage of the second transistor Tr2 is set to a voltage level higher than the second threshold. More specifically, when the second transistor Tr2 is turned on when the first data (key) is "1", the potential level of word line WL2 (fourth data) of the two word lines WL1 and WL2 is set to the same as the potential level of word line WL2 (fourth data) when the second transistor Tr2 is turned off when the first data is "0".

[0050] (Multi-level valuation) As described above, this embodiment assumes that the first transistor Tr1 and the second transistor Tr2 in string 1 store multi-level data. For example, if both key K and query Q are 2 bits, one of four thresholds corresponding to key K can be set for each of the first transistor Tr1 and the second transistor Tr2. Current flows through the first transistor Tr1 and the second transistor Tr2 according to the difference between the threshold and the gate voltage. More specifically, the greater the gate voltage is than the threshold of the first transistor Tr1 and the second transistor Tr2, the greater the current that flows.

[0051] When the first transistor Tr1 and the second transistor Tr2 store multi-level data corresponding to key K, the current flowing through string 1 can be varied based on the matching values ​​of key K and query Q, thereby allowing the matching values ​​of key K and query Q to be estimated by the current flowing through string 1.

[0052] Figure 13 shows an example of changing the current flowing through string 1 based on the matching values ​​of key K and query Q. The upper part of Figure 13 shows the relationship between the threshold distribution and gate voltage of the first transistor Tr1. The lower part shows the relationship between the threshold distribution and gate voltage of the second transistor Tr2.

[0053] As shown in Figure 13, the current flowing through string 1 can be changed by controlling at least one of the threshold voltages or gate voltages of the first transistor Tr1 and the second transistor Tr2 based on the matching values ​​of key K and query Q.

[0054] For example, if key K and query Q match at "1", the current flowing through string 1 should be less than if they match at "3". To achieve this, when key K and query Q match at "1", the difference between the threshold voltage and gate voltage of at least one of the first transistor Tr1 or the second transistor Tr2 should be smaller than when they match at "3".

[0055] The current flowing through string 1 can be variably controlled by adjusting at least one of the threshold levels of the first transistor Tr1 and the second transistor Tr2, or the gate voltages of the first transistor Tr1 and the second transistor Tr2. Therefore, by adjusting at least one of the threshold levels or gate voltages based on the matching value of key K and query Q, the current flowing through string 1 can be changed according to the matching value of key K and query Q. This allows for accurate estimation of the matching value of key K and query Q based on the current flowing through string 1.

[0056] (Vector partitioning) When performing the dot product operation between the vector of key K and the vector of query Q, if each vector contains multiple elements "1", the dot product operation will not be performed correctly. For example, if two vectors each contain two elements "1", and the positions of these two elements "1" are the same in both vectors, the dot product value of the two vectors will be 2, but the current flowing through string 1 will not be twice the current that would be generated if the two vectors each contained only one element "1". This is because in string 1, multiple pairs of transistors, each consisting of a first transistor Tr1 and a second transistor Tr2, are connected in a cascode, and only the minimum current flowing through each pair flows through string 1.

[0057] Therefore, if the key vector K and the query vector Q contain multiple elements "1", it is desirable to split these vectors so that each split vector contains only one element "1". In this case, string 1 is split into multiple strings 1, and one end of each split string is connected to the same bit line BL. As a result, the sum of the currents flowing through each split string flows through bit line BL, and the current or potential of bit line BL can be used to correctly detect matches between vectors containing multiple elements.

[0058] Figure 14 shows an example of dividing the key K and query Q vectors into multiple partition vectors. To eliminate errors, it is important that each partition vector contains at most one element, "1".

[0059] Figure 15 shows the connection between multiple partition strings 1D corresponding to multiple partition vectors and the bit line BL. As shown in Figure 15, one end of each of the multiple partition strings 1D is connected to the common bit line BL. In each partition string 1D, an inner product operation is performed between the corresponding partition key K and partition query Q. Since the vector of partition key K and the vector of partition query Q contain at most one element "1", when partition key K and partition query Q match, current flows through the corresponding partition string 1D. The more partition strings 1D through which current flows, the greater the current flowing through the bit line BL increases, and the greater the bit potential decreases. Therefore, the inner product operation between the key K vector containing multiple elements "1" and the query Q vector can be performed by the current or potential of the bit line BL.

[0060] Thus, if the number of bits in the key K and query Q vector exceeds a predetermined bit length, or if the proportion of bits in the key K and query Q vector that take values ​​other than "0" (e.g., "1") exceeds a predetermined value, it is desirable to split the vector so that the number of elements in the split vector that take values ​​other than the predetermined value (e.g., "1") is 1 or less.

[0061] (Convert element positions from decimal to base m (where m is an integer less than 10 and greater than or equal to 2)) As mentioned above, in natural language processing, for example, the number of words in a sentence is used as the number of dimensions of the vector, and the words contained in each vocabulary that make up the sentence are identified by the element position of the vector. When the number of element positions becomes large (for example, 254), it becomes difficult to represent the vector with string 1 in semiconductor memory devices such as NAND flash memory.

[0062] Figure 16 shows a vector with n elements (where n is an integer greater than or equal to 255), where the 254th element is "1" and all other elements are "0". Figure 17 shows an example where both the key vector K and the query vector Q are represented as vectors similar to those in Figure 16.

[0063] Figure 18 shows the result of performing a dot product operation on the two vectors in Figure 17. As shown in the figure, the dot product value is "1" when the positions of the element "1" in both vectors coincide. Also, the dot product value is "0" when both vectors are zero.

[0064] Since it is not practical to construct String 1 by cascode-connecting more than 254 sets of first and second transistors, it is difficult to perform dot product operations between multidimensional vectors in NAND flash memory or the like in this configuration. Therefore, in this embodiment, 254 is replaced with, for example, a quaternary number. The decimal number 254 is "3332" in quaternary. The quaternary number "3332" can be represented by four sets of cascode-connected transistors. Each set of transistors stores 2 bits of data.

[0065] Figure 19 is a circuit diagram of String 1, which compares key K and query Q in Figures 17 and 18. String 1 in Figure 19 is constructed by cascode-connecting multiple pairs of first transistors Tr1 and second transistors Tr2, with each pair consisting of a first transistor Tr1 and a second transistor Tr2. Each of the multiple pairs conducts current when the two vectors representing key K and query Q coincide in a way that is not all zero.

[0066] String 1 in Figure 19 has four sets of cascode-connected first and second transistors Tr1 and Tr2. The first set 1a corresponds to the least significant digit of the quaternary number, the second set 1b to the second least significant digit, the third set 1c to the third least significant digit, and the fourth set 1d to the most significant digit. The first set 1a to the fourth set 1d in String 1 compare the key K and the query Q for the corresponding digits of the quaternary value representing the element position of element "1".

[0067] The first set, 1a, supplies current when key K and query Q are both "2". The second set, 1b through the fourth set, 1d, supplies current when key K and query Q are both "3".

[0068] In this way, by assigning each digit of the value obtained by converting the element position of vector element "1" to a base-4 number to each pair of strings 1, and detecting whether key K and query Q match the values ​​of each digit, it is possible to perform the dot product operation between key K and query Q without complicating the structure of string 1, even if the element position of element "1" has a large value.

[0069] In Figure 19, an example is shown of converting the value of a decimal element position to a quaternary number, but it may also be converted to a value in a base m (where m is an integer less than 10 and greater than or equal to 2) other than quaternary. In this case, string 1 has a cascode connection of a first transistor and a second transistor, each corresponding to the number of digits in the base m value. The first transistor Tr1 and the second transistor Tr2 of each pair in string 1 are set to a first threshold and a second threshold corresponding to the corresponding digits in the base m value. The string flows current when each of the multiple third data inputs to the multiple pairs is equal to the first data corresponding to the first threshold, and each of the multiple fourth data inputs to the multiple pairs is equal to the second data corresponding to the second threshold. (Memory system) The information processing device 10 according to this embodiment can be incorporated into a memory system using NAND flash memory or the like.

[0070] Figure 20 is a block diagram showing the schematic configuration of the information processing device 10 according to this embodiment. The information processing device 10 in Figure 20 includes a memory cell array 11, a row selection circuit 12, a sense amplifier / column selection circuit 13, a controller 14, a data input / output buffer 15, a complement generator 16, and a multiplexer 17.

[0071] The memory cell array 11 has multiple strings 1 connected to the same bit line BL, similar to Figure 15. Note that the memory cell array 11 may have multiple bit lines BL. In this case, multiple strings 1, similar to those in Figure 15, are provided for each bit line BL. Each string 1 has a first transistor Tr1 and a second transistor Tr2, similar to Figure 1, and a word line WL, set to a potential level corresponding to the query Q, is connected to the gates of the first transistor Tr1 and the second transistor Tr2.

[0072] Each string 1 has multiple transistors connected in cascode, in addition to the first transistor Tr1 and the second transistor Tr2. These multiple transistors are set to the ON state when reading the current from string 1.

[0073] The row selection circuit 12 sets the potential level of the word line WL connected to the gates of the first transistor Tr1 and the second transistor Tr2, in accordance with instructions from the controller 14 and an externally supplied query Q.

[0074] The data input / output buffer 15 acquires key K from an external source and, according to instructions from the controller 14, supplies the acquired key K to the complement generator 16 and the multiplexer 17. The complement generator 16 inverts key K from the data input / output buffer 15 bit by bit to generate the complement data of key K. The multiplexer 17, according to instructions from the controller 14, selects either key K from the data input / output buffer 15 or the complement data of key K generated by the complement generator 16 and supplies it to the sense amplifier / column selection circuit 13. A complement generator and multiplexer may also be provided on the row selection circuit 12 side where the address (query) is input. The multiplexer, according to instructions from the controller 14, can select either the input query Q or the complement data of query Q generated by the complement generator 16 and supply it to the word line WL via the row selection circuit 12.

[0075] The sense amplifier / column selection circuit 13 supplies the key K or complement data output from the multiplexer 17 to the bit line BL.

[0076] The memory cell array 11, row selection circuit 12, sense amplifier / column selection circuit 13, controller 14, data input / output buffer 15, complement generator 16, and multiplexer 17 shown in Figure 20 can also be used as a memory system 20.

[0077] The information processing device 10 in Figure 20 may include a detector 18. The detector 18 detects at least one of the current flowing through the bit line BL and the voltage across the bit line BL. The detector 18 may also output a digital signal obtained by analog-to-digital conversion of at least one of the current flowing through the bit line BL and the voltage across the bit line BL to an external source.

[0078] The information processing device 10 in Figure 20 may be configured to selectively select between a mode in which the memory cell array 11 is used as a normal memory and a mode in which key K is stored in the memory cell array 11 and compared with query Q.

[0079] Furthermore, the memory cell array 11 may include a memory cell area that stores key K and performs a comparison with query Q, and a memory cell area that is used as normal memory.

[0080] Thus, since the same processing operations as the information processing device 10 according to this embodiment can be performed using a semiconductor memory device with a configuration almost identical to that of a normal memory, the design is simple, and the information processing device 10 can be constructed with a short design time and using existing semiconductor processes.

[0081] (Error reduction when a vector contains multiple elements "1") As mentioned above, if a vector contains multiple elements of "1", the error can be reduced by splitting string 1 into multiple substrings 1D.

[0082] Figure 21 is a circuit diagram showing an example where string 1 is split into two split strings 1D and connected to the same bit line BL.

[0083] The original string 1 is assumed to contain a maximum of two non-zero elements. The following examples primarily focus on cases where the non-zero element is "1".

[0084] In Figure 21, one end of each of the two split strings 1D is connected to the same bit line BL. Each split string 1D has multiple sets of cascode-connected first transistors Tr1 and second transistors Tr2. Each split string 1D conducts current if the element position of up to one element "1" is the same for key K and query Q. Each digit of the value obtained by converting the element position of element "1" to quaternary is associated with one of the sets of split strings 1D.

[0085] Figure 22 shows the dot product value in the first example of dividing string 1 into two partitioned strings 1D. In Figure 22, the element positions of the non-zero elements, one in each of the two partitioned strings 1D, are denoted as Ka and Kb, and it is assumed that Ka > Kb > 0.

[0086] In the first example, assume that the key K combinations stored in each of the two partitioned strings 1D are (0,0), (Ka,0), and (Ka,Kb). Assume that the queries Q corresponding to key K are (0,0), (Ka,Ka), and (Ka,Kb). Let Kx and Ky be the values ​​of the query Q input to the two partitioned strings 1D that do not match Ka,Kb,0.

[0087] In this case, the possible combinations of queries Q input to the two split strings 1D are (0,0), (Ka,Ka), (Kb,Kb), (Ka,Kb), (Ka,Ky), (Kx,Ka), (Kb,Ky), (Kx,Kb), and (Kx,Ky).

[0088] In this case, the dot product values ​​for all combinations of key K and query Q are incorrect for (Ka,0)×(Kx,Ka), (Ka,Kb)×(Kx,Ka), and (Ka,Kb)×(Kb,Ky). For example, (Ka,0)×(Kx,Ka) should have a dot product of "1" but it becomes "0". Similarly, (Ka,Kb)×(Kx,Ka) should have a dot product of "1" but it becomes "0". Similarly, (Ka,Kb)×(Kb,Ky) should have a dot product of "1" but it becomes "0".

[0089] Thus, the reason why errors occur in the dot product value of key K and query Q is that the two keys K are stored separately in two partitioned strings 1D, and the result of the dot product calculation of the two partitioned strings 1D changes depending on how query Q is provided.

[0090] However, it is possible to correctly calculate values ​​that would be incorrect if the dot product of (Ka,Kb) × (Ka,Kb) were calculated using a single string 1 without splitting, such as (Ka,Kb) × (Ka,Kb) = 2. Therefore, calculating the dot product using a split string 1D can reduce the frequency of errors compared to calculating the dot product using a single string 1, but it cannot completely eliminate errors.

[0091] Figure 23 shows the dot product value in the second example of splitting string 1 into two partitioned strings 1D. The second example gives a different query Q than the first example. The queries Q in the second example are (0,0), (Ka,Ka), and (Ka,Kb). The key K in the second example is the same as in the first example.

[0092] In the second example, the query Q input to the two split strings 1D can take the following forms: (0,0), (Ka,0), (Kb,0), (Ka,Kb), (Ka,Ky), (Kx,Ka), (Kb,Ky), (Kx,Kb), (Kx,Ky).

[0093] Of these, the dot products of (Ka,Kb)×(Kb,0), (Ka,Kb)×(Kx,Ka), (Ka,Kb)×(Kb,Ky), and (Ka,0)×(Kx,Ka) will be incorrect. For example, the dot product of (Ka,Kb)×(Kb,0) should be "1" but will be "0". Similarly, the dot product of (Ka,Kb)×(Kx,Ka) should be "1" but will be "0". Similarly, the dot product of (Ka,Kb)×(Kb,Ky) should be "1" but will be "0". Similarly, the dot product of (Ka,0)×(Kx,Ka) should be "1" but will be "0".

[0094] Figure 24 shows the dot product value in the third example of splitting string 1 into two partitioned strings 1D. The third example gives a different query Q than the first example. The queries Q in the third example are (0,0), (Ka,Ka), and (Ka,Kb). The key K in the third example is the same as in the first example.

[0095] The third example has a different combination of key K than the first and second examples. The key K combinations for the third example are (0,0), (Ka,Ka), and (Ka,Kb). The queries Q corresponding to key K are (0,0), (Ka,Ka), and (Ka,Kb), similar to the first example.

[0096] In the third example, the query Q input to the two split strings 1D can take the following forms, similar to the first example: (0,0), (Ka,Ka), (Kb,Kb), (Ka,Kb), (Ka,Ky), (Kx,Ka), (Kb,Ky), (Kx,Kb), (Kx,Ky).

[0097] Of these, the dot products of (Ka,Ka)×(Ka,Ka), (Ka,Kb)×(Kx,Ka), and (Ka,Kb)×(Kb,Ky) will be incorrect. For example, the dot product of (Ka,Ka)×(Ka,Ka) should be "1" but will be "2". Similarly, the dot product of (Ka,Kb)×(Kx,Ka) should be "1" but will be "0". Similarly, the dot product of (Ka,Kb)×(Kb,Ky) should be "1" but will be "0".

[0098] Figure 25 shows the dot product in the fourth example of splitting string 1 into two partitioned strings 1D. In the fourth example, the same key K and query Q are given as in the third example, but the query Q entered into the two partitioned strings 1D is different from that in the third example. In the fourth example, the query Q entered into the two partitioned strings 1D can take the following values: (0,0), (Ka,0), (Kb,0), (Ka,Kb), (Ka,Ky), (Kx,Ka), (Kb,Ky), (Ky,Kb), (Kx,Ky).

[0099] Of these, the dot products of (Ka,Kb)×(Kb,0), (Ka,Kb)×(Kx,Ka), and (Ka,Kb)×(Kb,Ky) will be incorrect. For example, the dot product of (Ka,Kb)×(Kb,0) should be "1" but will be "0". Similarly, the dot product of (Ka,Kb)×(Kx,Ka) should be "1" but will be "0". Similarly, the dot product of (Ka,Kb)×(Kb,Ky) should be "1" but will be "0".

[0100] Thus, in this embodiment, the dot product operation of sparse vectors can be performed at high speed using hardware with a small circuit size. More specifically, by storing key K in string 1 of a semiconductor memory device and inputting query Q via word line WL, the dot product operation result can be output by the potential or current of bit line BL connected to string 1. In order to prevent current from flowing to string 1 when the sparse vectors are zero, current can be allowed to flow to string 1 only when the sparse vectors match in a way other than all zeros.

[0101] In natural language processing, where the number of words is overwhelmingly small compared to the vocabulary size, vectorizing the vocabulary results in sparse vectors. Therefore, the information processing device 10 in this embodiment can be effectively applied to determine the match or analogy between sparse vectors in natural language processing.

[0102] The aspects of this disclosure are not limited to the individual embodiments described above, but include various modifications that a person skilled in the art could conceive, and the effects of this disclosure are not limited to those described above. In other words, various additions, modifications, and partial deletions are possible, as long as they do not depart from the conceptual idea and spirit of this disclosure derived from the claims and their equivalents. [Item 1] It comprises a string that is connected to a first wire and also connected to a plurality of second wires, The string has a plurality of transistors, one end of which is connected to the first wiring, each of which gates is connected to a different second wiring, and which are connected to each other. The plurality of transistors include a first transistor and a second transistor, The first transistor is set to a first threshold value corresponding to the first data, The second transistor is set to a second threshold corresponding to the second data which is complementary to the first data, Two of the aforementioned plurality of second wires are connected to the gates of the first transistor and the second transistor. One of the two second wires is set to a potential level corresponding to the third data, and the other is set to a potential level corresponding to the fourth data which is complementary to the third data. The string does not conduct current when the first data and the third data match with a predetermined value, and conducts current when the first data and the third data match with a value other than the predetermined value. Information processing device. [Item 2] If the first data and the third data match by the predetermined value, the first transistor is turned off. If the first data and the third data match other than the predetermined value, the first transistor and the second transistor turn on. The information processing device described in item 1. [Item 3] If the first data and the third data match by the predetermined value, the gate voltage of the first transistor is lower than the first threshold. If the first data and the third data match for values ​​other than the predetermined values, the gate voltage of the first transistor becomes a potential level higher than the first threshold, and the gate voltage of the second transistor becomes a potential level higher than the second threshold. The information processing device described in item 2. [Item 4] If the first data and the third data match by the predetermined value, one of the first transistor or the second transistor is turned on and the other is turned off. If the first data and the third data match other than the predetermined value, the first transistor and the second transistor turn on. The information processing device described in item 1. [Item 5] The predetermined value is zero. An information processing device as described in any one of items 1 through 4. [Item 6] The predetermined value is zero, When the second transistor is turned on when the first data is 1, the potential level of the second wire corresponding to the fourth data among the two second wires is the same as the potential level of the second wire corresponding to the fourth data when the second transistor is turned off when the first data is zero. The information processing device described in item 4. [Item 7] The potential levels of the first threshold and the second threshold are set according to three or more values. The two second wires mentioned above have potential levels with three or more values. An information processing device as described in any one of items 1 through 6. [Item 8] The string carries a current corresponding to the multi-level when the first data and the third data match. The information processing device described in item 7. [Item 9] Depending on the values ​​when the first data and the third data match, at least one of the gate voltages of the first transistor and the second transistor and the threshold values ​​of the first transistor and the second transistor are adjusted. The information processing device described in item 8. [Item 10] The first to fourth data each have the same number of bits, If the number of bits in the first to fourth data exceeds a predetermined bit length, or if the proportion of bits in the first to fourth data that take values ​​other than the predetermined value exceeds a predetermined value, a plurality of strings corresponding to a plurality of divided bit sequences obtained by dividing each of the first to fourth data into a plurality are provided. The plurality of strings are connected to the same first wiring. An information processing device as described in any one of items 1 through 9. [Item 11] Each of the plurality of partitioned bit sequences contains at most one element other than the predetermined value. The information processing device described in item 10. [Item 12] The string has a plurality of such pairs, each consisting of a first transistor and a second transistor connected to each other. Each of the aforementioned sets flows current when the values ​​of the corresponding elements of the first data and the third data are the same. An information processing device as described in any one of items 1 through 11. [Item 13] The multiple first thresholds and second thresholds in the multiple sets are set according to the corresponding digits of the values ​​obtained by converting the first data and third data other than the predetermined value into a base m number (where m is an integer less than 10 and greater than or equal to 2), The string conducts current when each of the multiple third data input to the multiple sets is equal to the first data corresponding to the first threshold, and each of the multiple fourth data input to the multiple sets is equal to the second data corresponding to the second threshold. The information processing device described in item 12. [Item 14] The system includes a detector that detects at least one of the current flowing through the first wiring and the voltage of the first wiring. An information processing device as described in any one of items 1 through 13. [Item 15] The first wiring is a bit line, The second wire is a word wire, An information processing device according to any one of items 1 to 14, comprising a non-volatile memory having a plurality of the strings. [Item 16] The aforementioned non-volatile memory is NAND flash memory, The information processing apparatus according to item 15, wherein the charge corresponding to the corresponding bits of the first data and the second data is stored in the charge storage regions of the first transistor and the second transistor. [Item 17] Non-volatile memory and The system includes a controller that controls the writing and reading of data to and from the non-volatile memory, The aforementioned non-volatile memory is It comprises a string that is connected to a first wire and also connected to a plurality of second wires, The string has a plurality of transistors, one end of which is connected to the first wiring, each of which gates is connected to a different second wiring, and which are connected to each other. The plurality of transistors include a first transistor and a second transistor, The first transistor is set to a first threshold value corresponding to the first data, The second transistor is set to a second threshold corresponding to the second data which is complementary to the first data, Two of the aforementioned plurality of second wires are connected to the gates of the first transistor and the second transistor. One of the two second wires is set to a potential level corresponding to the third data, and the other is set to a potential level corresponding to the fourth data which is complementary to the third data. The string does not conduct current when the first data and the third data match with a predetermined value, and conducts current when the first data and the third data match with a value other than the predetermined value. Memory system. [Explanation of symbols]

[0103] 1 String, 1D partitioned string, 10 Information processing unit, 11 Memory cell array, 12 Row selection circuit, 13 Column selection circuit, 14 Controller, 15 Data input / output buffer, 16 Complement generator, 17 Multiplexer, 18 Detector, 20 Memory system

Claims

1. It comprises a string that is connected to a first wire and also connected to a plurality of second wires, The string has a plurality of transistors, one end of which is connected to the first wiring, each of which gates is connected to a different second wiring, and which are connected to each other. The plurality of transistors include a first transistor and a second transistor, The first transistor is set to a first threshold value corresponding to the first data, The second transistor is set to a second threshold value corresponding to the second data which is complementary to the first data, Two of the aforementioned plurality of second wires are connected to the gates of the first transistor and the second transistor. One of the two second wires is set to a potential level corresponding to the third data, and the other is set to a potential level corresponding to the fourth data which is complementary to the third data. The string does not conduct current when the first data and the third data match with predetermined values, and conducts current when the first data and the third data match with values ​​other than the predetermined values. Information processing device.

2. If the first data and the third data match by the predetermined value, the first transistor is turned off. If the first data and the third data match other than the predetermined value, the first transistor and the second transistor turn on. The information processing apparatus according to claim 1.

3. When the first data and the third data match by the predetermined value, the gate voltage of the first transistor is lower than the first threshold. If the first data and the third data match other than the predetermined value, the gate voltage of the first transistor becomes a potential level higher than the first threshold, and the gate voltage of the second transistor becomes a potential level higher than the second threshold. The information processing apparatus according to claim 2.

4. If the first data and the third data match by the predetermined value, one of the first transistor or the second transistor is turned on and the other is turned off. If the first data and the third data match other than the predetermined value, the first transistor and the second transistor turn on. The information processing apparatus according to claim 1.

5. The predetermined value is zero. The information processing apparatus according to claim 1.

6. The predetermined value is zero, When the second transistor is turned on when the first data is 1, the potential level of the second wire corresponding to the fourth data among the two second wires is the same as the potential level of the second wire corresponding to the fourth data when the second transistor is turned off when the first data is zero. The information processing apparatus according to claim 4.

7. The potential levels of the first threshold and the second threshold are set according to three or more values. The two second wires have potential levels of three or more values. The information processing apparatus according to claim 1.

8. The string carries a current corresponding to the multi-level when the first data and the third data match. The information processing apparatus according to claim 7.

9. Depending on the value at which the first data and the third data match, at least one of the gate voltages of the first transistor and the second transistor and the threshold values ​​of the first transistor and the second transistor are adjusted. The information processing apparatus according to claim 8.

10. The first to fourth data each have the same number of bits, If the number of bits in the first to fourth data exceeds a predetermined bit length, or if the proportion of bits in the first to fourth data that take values ​​other than the predetermined value exceeds a predetermined value, a plurality of strings corresponding to a plurality of divided bit sequences obtained by dividing each of the first to fourth data into a plurality are provided. The plurality of strings are connected to the same first wiring. The information processing apparatus according to claim 1.

11. Each of the plurality of partitioned bit sequences contains at most one element other than the predetermined value. The information processing apparatus according to claim 10.

12. The string has a plurality of such pairs, each consisting of a first transistor and a second transistor connected to one another. Each of the aforementioned sets flows current when the values ​​of the corresponding elements of the first data and the third data are the same. The information processing apparatus according to claim 1.

13. The multiple first thresholds and second thresholds in the multiple sets are set according to the corresponding digits of the values ​​obtained by converting the first data and third data other than the predetermined value into a base m number (where m is an integer less than 10 and greater than or equal to 2), The string conducts current when each of the multiple third data input to the multiple sets is equal to the first data corresponding to the first threshold, and each of the multiple fourth data input to the multiple sets is equal to the second data corresponding to the second threshold. The information processing apparatus according to claim 12.

14. The information processing apparatus according to claim 1, comprising a detector for detecting at least one of the current flowing through the first wiring and the voltage of the first wiring.

15. The first wiring is a bit line, The second wiring is a word wire, The information processing apparatus according to claim 1, comprising a non-volatile memory having a plurality of strings.

16. The aforementioned non-volatile memory is a NAND flash memory. The information processing apparatus according to claim 15, wherein the charge corresponding to the corresponding bits of the first data and the second data is stored in the charge storage regions of the first transistor and the second transistor.

17. Non-volatile memory and The system includes a controller that controls the writing and reading of data to and from the non-volatile memory, The aforementioned non-volatile memory is It comprises a string that is connected to a first wire and also connected to a plurality of second wires, The string has a plurality of transistors, one end of which is connected to the first wiring, each of which gates is connected to a different second wiring, and which are connected to each other. The plurality of transistors include a first transistor and a second transistor, The first transistor is set to a first threshold value corresponding to the first data, The second transistor is set to a second threshold value corresponding to the second data which is complementary to the first data, Two of the aforementioned plurality of second wires are connected to the gates of the first transistor and the second transistor. One of the two second wires is set to a potential level corresponding to the third data, and the other is set to a potential level corresponding to the fourth data which is complementary to the third data. The string does not conduct current when the first data and the third data match with predetermined values, and conducts current when the first data and the third data match with values ​​other than the predetermined values. Memory system.

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