Charge / discharge control circuit, charge / discharge control device, and battery device

Abstract

The present invention provides a charge / discharge control circuit, a charge / discharge control device, and a battery device that reduce the circuit size when multiple protection ICs are cascaded. [Solution] The battery device 10 includes a battery 11, a first predetermined state detection unit that detects a first predetermined state with respect to a first cell, a first logic circuit that performs first control based on the detection result, a second predetermined state detection unit that detects a second predetermined state with respect to a second cell 111B, a charger connection detection unit that detects whether or not the battery 11 is connected to a charger, and a second logic circuit 62B that performs second control based on the detection result of the second predetermined state detection unit, the detection result of the charger connection detection unit, and a first notification from the first logic circuit that the first predetermined state is present. The first and second predetermined states are overcharge or over-discharge states, and the second logic circuit 62B performs second control by masking the first notification from the first logic circuit if the detection result of the charger connection detection unit satisfies predetermined conditions.

Description

Technical Field

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[0001] The present disclosure relates to a charge-discharge control circuit, a charge-discharge control device, and a battery device.

Background Art

[0002] In a circuit including a battery (battery pack) in which a plurality of cells (single cells) are connected in series, a circuit in which a plurality of protection ICs (Integrated Circuits) are cascade-connected is known (see Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the conventional circuit as described above, when releasing the overcharge and over-discharge states during the cascade communication of a plurality of cells, a dedicated terminal for communicating the state of an external voltage input terminal, which is the terminal of the voltage VM, between the plurality of protection ICs is required. For this reason, in the conventional circuit as described above, since the number of pads increases, the chip size and the number of pins of the package may increase.

[0005] The present disclosure has been made in consideration of such circumstances, and an object thereof is to provide a charge-discharge control circuit, a charge-discharge control device, and a battery device capable of suppressing the circuit scale when a plurality of protection ICs are cascade-connected.

Means for Solving the Problems

[0006] One embodiment is a charge / discharge control circuit comprising: a battery in which a plurality of cells, including a first cell and a second cell, are connected in series; a first predetermined state detection unit that detects a first predetermined state with respect to the first cell; a first logic circuit that performs first control based on the detection result of the first predetermined state detection unit; a second predetermined state detection unit that detects a second predetermined state with respect to the second cell; a charger connection detection unit that detects whether or not the battery is connected to a charger; and a second logic circuit that performs second control based on the detection result of the second predetermined state detection unit, the detection result of the charger connection detection unit, and a first notification from the first logic circuit indicating that the first predetermined state is present, wherein the first predetermined state and the second predetermined state are an overcharge state or an over-discharge state, and the second logic circuit performs the second control by masking the first notification from the first logic circuit when the detection result of the charger connection detection unit satisfies a predetermined condition. [Effects of the Invention]

[0007] According to this disclosure, when multiple protection ICs are cascaded in a charge / discharge control circuit, charge / discharge control device, and battery device, the circuit size can be reduced. [Brief explanation of the drawing]

[0008] [Figure 1A] This figure shows an example configuration of a charge / discharge control circuit, a charge / discharge control device, and a battery device according to an embodiment, as well as a diagram showing the first state of the battery device. [Figure 1B] This figure shows an example configuration of a charge / discharge control circuit, a charge / discharge control device, and a battery device according to an embodiment, as well as a diagram showing the first state of the battery device. [Figure 2A] This figure shows the second state of the battery device according to the embodiment. [Figure 2B] This figure shows the second state of the battery device according to the embodiment. [Figure 3A] This figure shows the third state of the battery device according to the embodiment. [Figure 3B] This figure shows the third state of the battery device according to the embodiment. [Figure 4A]It is a diagram showing the fourth state of the battery device according to the embodiment. [Figure 4B] It is a diagram showing the fourth state of the battery device according to the embodiment. [Figure 5] It is a diagram showing an example of a timing chart regarding overcharge according to the embodiment. [Figure 6] It is a diagram showing an example of a timing chart regarding over-discharge according to the embodiment. [Figure 7A] It is a diagram showing a configuration example of a charge / discharge control circuit, a charge / discharge control device, and a battery device according to a comparative example and the first state of the battery device. [Figure 7B] It is a diagram showing a configuration example of a charge / discharge control circuit, a charge / discharge control device, and a battery device according to a comparative example and the first state of the battery device. [Figure 8A] It is a diagram showing the second state of the battery device according to the comparative example. [Figure 8B] It is a diagram showing the second state of the battery device according to the comparative example. [Figure 9A] It is a diagram showing the third state of the battery device according to the comparative example. [Figure 9B] It is a diagram showing the third state of the battery device according to the comparative example. [Figure 10A] It is a diagram showing the fourth state of the battery device according to the comparative example. [Figure 10B] It is a diagram showing the fourth state of the battery device according to the comparative example. [Figure 11A] It is a diagram showing the fifth state of the battery device according to the comparative example. [Figure 11B] It is a diagram showing the fifth state of the battery device according to the comparative example. [Figure 12A] It is a diagram showing the sixth state of the battery device according to the comparative example. [Figure 12B] It is a diagram showing the sixth state of the battery device according to the comparative example. [Figure 13] It is a diagram showing an example of a timing chart regarding overcharge according to the comparative example. [Figure 14] It is a diagram showing an example of a timing chart regarding over-discharge according to the comparative example. [Figure 15] It is a diagram showing the release of overcharge and overdischarge states according to the reference example.

Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

[0010] [Battery device] FIG. 1A and FIG. 1B are diagrams showing a configuration example of a charge / discharge control circuit 30, a charge / discharge control device 20, and a battery device 10 according to an embodiment, and a first state of the battery device 10. The battery device 10 includes a charge / discharge control device 20 and a battery 11. The charge / discharge control device 20 includes a charge / discharge control circuit 30, a discharge control FET (Field Effect Transistor) 21, and a charge control FET 22. In addition, FIG. 1A shows a short-circuit load 13 (RLOAD), a switch 14, and a charger 40.

[0011] For convenience of illustration, the battery device 10 is shown separately in FIG. 1A and FIG. 1B, but these are an integrated device. The lines respectively denoted by reference signs a1 to a5 shown in FIG. 1A and the lines respectively denoted by reference signs a1 to a5 shown in FIG. 1B are connected.

[0012] The charge / discharge control device 20 controls the charge / discharge of the battery 11. The discharge control FET 21 controls discharge. The charge control FET 22 controls charging.

[0013] Here, in the present embodiment, the charge / discharge control circuit 30 includes a multi-stage charge / discharge control circuit. [[ID=第二十二]]In the present embodiment, the charge / discharge control circuit 30 includes a charge / discharge control circuit of three or more stages. However, in the examples of FIGS. 1A and 1B, for simplicity of illustration, the lowermost charge / discharge control circuit 30B and the charge / discharge control circuit 30A one stage above it are shown. The charge / discharge control circuits (not shown) above the charge / discharge control circuit 30A have a similar circuit configuration to the charge / discharge control circuit 30A, but the uppermost charge / discharge control circuit (not shown) does not have a discharge control signal detection circuit or a charge control signal detection circuit (i.e., a communication circuit with the uppermost circuit). However, the charge / discharge control circuit 30 may be configured to include a two-stage charge / discharge control circuit such as a charge / discharge control circuit 30A and a charge / discharge control circuit 30B.

[0014] In this embodiment, with respect to the battery 11, the portion corresponding to the charge / discharge control circuit 30A is indicated as the battery section 11A, and the portion corresponding to the charge / discharge control circuit 30B is indicated as the battery section 11B. In this embodiment, for the sake of explanation, the charge / discharge control circuit 30A is referred to as the higher-level IC, and the charge / discharge control circuit 30B is referred to as the lower-level IC. In this embodiment, these ICs are examples of multiple protection ICs.

[0015] The charge / discharge control circuit 30A includes over-discharge detection ladder resistors 51A to 53A, a switch 71A, overcharge detection ladder resistors 54A to 56A, a switch 72A, an over-discharge detection comparator 81A, an overcharge detection comparator 82A, a first logic circuit 62A, a discharge control signal detection circuit 91A, a charge control signal detection circuit 92A, a discharge control signal output circuit 93A, and a charge control signal output circuit 94A.

[0016] The battery unit 11A has multiple cells connected in series. In the example shown in Figure 1A, for the sake of simplicity, the diagram shows the over-discharge detection ladder resistors 51A-53A, switch 71A, over-charge detection ladder resistors 54A-56A, switch 72A, over-discharge detection comparator 81A, and over-charge detection comparator 82A for one of the multiple cells in the battery unit 11A, but the other cells in the battery unit 11A are equipped with similar circuits. In this embodiment, we will describe an example of the operation of the first logic circuit 62A focusing on one first cell 111A, but a similar circuit configuration may be adopted for other cells as well, and control by the first logic circuit 62A may be performed.

[0017] The charge / discharge control circuit 30A includes a power input terminal C1A which is the terminal for voltage VDD, a power input terminal C2A which is the terminal for voltage VSS, a voltage connection terminal C11A which is the terminal for voltage VC(n), a voltage connection terminal C12A which is the terminal for voltage VC(n+1), a discharge control FET gate connection terminal C5A which is the terminal for voltage VDO, a charge control FET gate connection terminal C6A which is the terminal for voltage VCO, a DO terminal output control terminal C7A which is the terminal for voltage VCTLD, and a CO terminal output control terminal C8A which is the terminal for voltage VCTLC.

[0018] Here, within the charge / discharge control circuit 30A, the voltage VC(n) represents the positive electrode voltage of the nth (where n is an integer greater than or equal to 1)th stage cell (in the example shown in Figures 1A and 1B, the first cell 111A), and also represents the negative electrode voltage of the (n-1)th stage cell. Furthermore, the voltage VC(n+1) represents the positive electrode voltage of the (n+1)th cell and the negative electrode voltage of the nth cell (in the example in Figure 1A, the first cell 111A). Note that for the first row of cells (when n=1) and the last row of cells (when n is the maximum value), there are no adjacent cells.

[0019] The charge / discharge control circuit 30B includes over-discharge detection ladder resistors 51B to 53B, a switch 71B, overcharge detection ladder resistors 54B to 56B, a switch 72B, an over-discharge detection comparator 81B, an overcharge detection comparator 82B, a second logic circuit 62B, a discharge control signal detection circuit 91B, a charge control signal detection circuit 92B, a discharge control signal output circuit 93B, a charge control signal output circuit 94B, and a charger connection detection circuit 95B.

[0020] The battery unit 11B has multiple cells connected in series. In the example shown in Figure 1B, for the sake of simplicity, the diagram shows the over-discharge detection ladder resistors 51B-53B, switch 71B, over-charge detection ladder resistors 54B-56B, switch 72B, over-discharge detection comparator 81B, and over-charge detection comparator 82B for one of the multiple cells in the battery unit 11B, but similar circuits are provided for the other cells in the battery unit 11B. In this embodiment, we will describe an example of the operation of the second logic circuit 62B focusing on one second cell 111B. However, for example, a similar circuit configuration may be adopted for other cells as well, and control by the second logic circuit 62B may be performed accordingly.

[0021] The charge / discharge control circuit 30B includes a power input terminal C1B which is the terminal for voltage VDD, a power input terminal C2B which is the terminal for voltage VSS, a voltage connection terminal C11B which is the terminal for voltage VC(n), a voltage connection terminal C12B which is the terminal for voltage VC(n+1), a discharge control FET gate connection terminal C5B which is the terminal for voltage VDO, a charge control FET gate connection terminal C6B which is the terminal for voltage VCO, a DO terminal output control terminal C7B which is the terminal for voltage VCTLD, a CO terminal output control terminal C8B which is the terminal for voltage VCTLC, and an external voltage input terminal C4B which is the terminal for voltage VM.

[0022] Here, within the charge / discharge control circuit 30B, the voltage VC(n) represents the positive electrode voltage of the nth (where n is an integer greater than or equal to 1)th stage cell (in the example in Figure 1B, the second cell 111B), and also represents the negative electrode voltage of the (n-1)th stage cell. Furthermore, the voltage VC(n+1) represents the positive electrode voltage of the (n+1)th cell and the negative electrode voltage of the nth cell (in the example in Figure 1B, the second cell 111B). Note that for the first row of cells (when n=1) and the last row of cells (when n is the maximum value), there are no adjacent cells.

[0023] <Circuit connection details, etc.> Between the positive and negative terminals of the battery 11, in the order from the positive terminal to the negative terminal, are connected a switch 14, a charger 40, a charge control FET 22, and a discharge control FET 21. In addition, a short-circuit resistor, a short-circuit load 13 (RLOAD), is connected in parallel with the switch 14 and the charger 40 between the positive and negative terminals of the battery 11.

[0024] Here, the source (S) of the charge control FET 22 is connected to the negative terminal of the charger 40, the drain (D) of the charge control FET 22 is connected to the drain (D) of the discharge control FET 21, and the source (S) of the discharge control FET 21 is connected to the negative terminal of the battery 11. The gate (G) of the discharge control FET 21 is connected to the discharge control FET gate connection terminal C5B. The gate (G) of the charge control FET 22 is connected to the charge control FET gate connection terminal C6B. The point between the charger 40 and the charge control FET 22 is connected to the external voltage input terminal C4B.

[0025] This section explains the circuit connections and other details related to the charge / discharge control circuit 30A. Between the voltage connection terminal C11A on the power input terminal C1A side and the voltage connection terminal C12A on the power input terminal C2A side, over-discharge detection ladder resistors 51A, 52A, and 53A are connected in order from the positive side to the negative side, and in parallel with these, overcharge detection ladder resistors 54A, 55A, and 56A are connected. A switch 71A is connected in parallel with the over-discharge detection ladder resistor 52A. A 72A switch is connected in parallel with the 55A overcharge detection ladder resistor. The first logic circuit 62A controls switches 71A and 72A.

[0026] The point between the over-discharge detection ladder resistor 52A and the over-discharge detection ladder resistor 53A is connected to the input terminal of the over-discharge detection comparator 81A. The output terminal of the over-discharge detection comparator 81A is connected to one of the input terminals of the first logic circuit 62A. The point between the overcharge detection ladder resistor 55A and the overcharge detection ladder resistor 56A is connected to the input terminal of the overcharge detection comparator 82A. The output terminal of the overcharge detection comparator 82A is connected to one of the input terminals of the first logic circuit 62A.

[0027] The DO terminal output control terminal C7A is connected to the input terminal of the discharge control signal detection circuit 91A. The output terminal of the discharge control signal detection circuit 91A is connected to one of the input terminals of the first logic circuit 62A. The CO terminal output control terminal C8A is connected to the input terminal of the charging control signal detection circuit 92A. The output terminal of the charging control signal detection circuit 92A is connected to one of the input terminals of the first logic circuit 62A.

[0028] The input terminal of the discharge control signal output circuit 93A is connected to one of the output terminals of the first logic circuit 62A. The output terminal of the discharge control signal output circuit 93A is connected to the discharge control FET gate connection terminal C5A. The input terminal of the charging control signal output circuit 94A is connected to one of the output terminals of the first logic circuit 62A. The output terminal of the charging control signal output circuit 94A is connected to the charging control FET gate connection terminal C6A.

[0029] The connection relationship between charge / discharge control circuit 30A and charge / discharge control circuit 30B will be explained. The discharge control FET gate connection terminal C5A of the charge / discharge control circuit 30A is connected to the DO terminal output control terminal C7B of the charge / discharge control circuit 30B. The charge control FET gate connection terminal C6A of the charge / discharge control circuit 30A is connected to the CO terminal output control terminal C8B of the charge / discharge control circuit 30B.

[0030] This section explains the circuit connections and other details related to the charge / discharge control circuit 30B. Between the voltage connection terminal C11B on the power input terminal C1B side and the voltage connection terminal C12B on the power input terminal C2B side, over-discharge detection ladder resistors 51B, 52B, and 53B are connected in order from the positive side to the negative side, and in parallel with these, overcharge detection ladder resistors 54B, 55B, and 56B are connected. Switch 71B is connected in parallel with the over-discharge detection ladder resistor 52B. Switch 72B is connected in parallel with the overcharge detection ladder resistor 55B. The second logic circuit 62B controls switches 71B and 72B.

[0031] The point between the over-discharge detection ladder resistor 52B and the over-discharge detection ladder resistor 53B is connected to the input terminal of the over-discharge detection comparator 81B. The output terminal of the over-discharge detection comparator 81B is connected to one of the input terminals of the second logic circuit 62B. The point between the overcharge detection ladder resistor 55B and the overcharge detection ladder resistor 56B is connected to the input terminal of the overcharge detection comparator 82B. The output terminal of the overcharge detection comparator 82B is connected to one of the input terminals of the second logic circuit 62B.

[0032] The DO terminal output control terminal C7B is connected to the input terminal of the discharge control signal detection circuit 91B. The output terminal of the discharge control signal detection circuit 91B is connected to one of the input terminals of the second logic circuit 62B. The CO terminal output control terminal C8B is connected to the input terminal of the charging control signal detection circuit 92B. The output terminal of the charging control signal detection circuit 92B is connected to one of the input terminals of the second logic circuit 62B.

[0033] The input terminal of the discharge control signal output circuit 93B is connected to one of the output terminals of the second logic circuit 62B. The output terminal of the discharge control signal output circuit 93B is connected to the discharge control FET gate connection terminal C5B. The input terminal of the charging control signal output circuit 94B is connected to one of the output terminals of the second logic circuit 62B. The output terminal of the charging control signal output circuit 94B is connected to the charging control FET gate connection terminal C6B.

[0034] The input terminal of the charger connection detection circuit 95B is connected to the external voltage input terminal C4B. The output terminal of the charger connection detection circuit 95B is connected to one of the input terminals of the second logic circuit 62B.

[0035] <First State: Explanation of Overcharge State Release During Cascade Communication> Figures 1A and 1B show the first state of the battery device 10. Switch 14 is controlled to the closed (SHORT) state. This connects the charger 40 to the battery device 10.

[0036] This section describes the state of the charge / discharge control circuit 30A. Under normal conditions, the voltage VBATn of the first cell 111A is higher than the overcharge release voltage VCL and lower than the overcharge detection voltage VCU. Here, when the voltage VBATn of the first cell 111A exceeds the overcharge detection voltage VCU, the first logic circuit 62A enters an overcharge state. The output terminal of the over-discharge detection comparator 81A is in the deactivated state. The output terminal of the overcharge detection comparator 82A is in the deactivated state. The output terminal of the discharge control signal detection circuit 91A is in the released state. The output terminal of the charging control signal detection circuit 92A is in the released state.

[0037] The first logic circuit 62A controls the switch 71A to the ON state based on the over-discharge state release signal. The first logic circuit 62A controls switch 72A to the ON state based on the overcharge state release signal.

[0038] The output terminal of the discharge control signal output circuit 93A is in a released state by the first logic circuit 62A. The output terminal of the charging control signal output circuit 94A is detected by the first logic circuit 62A and outputs a charging control signal.

[0039] The state of the charge / discharge control circuit 30B will be explained. The voltage VM is lower than 0[V] (VM<0). As a result, the output terminal of the charger connection detection circuit 95B is in a detection state.

[0040] The voltage VBATn of the second cell 111B is higher than the over-discharge detection voltage VDL and lower than the overcharge release voltage VCL. The output terminal of the over-discharge detection comparator 81B is in the deactivated state. The output terminal of the overcharge detection comparator 82B is in the deactivated state. The output terminal of the discharge control signal detection circuit 91B is in the released state. The output terminal of the charging control signal detection circuit 92B is in the detection state. As a result, the second logic circuit 62B is in a charge control state. The second logic circuit 62B controls the switch 71B to the ON state based on the over-discharge release signal. The second logic circuit 62B controls the switch 72B to the OFF state based on the overcharge state release signal.

[0041] The output terminal of the discharge control signal output circuit 93B is in a released state by the second logic circuit 62B. As a result, the discharge control FET 21 is controlled to be in the ON state. The output terminal of the charging control signal output circuit 94B is detected by the second logic circuit 62B and outputs a charging control signal. As a result, the FET22 for charge control is controlled to the off state.

[0042] Thus, the higher-level IC (charge / discharge control circuit 30A) transitions to an overcharge state when the voltage VBATn of the first cell 111A connected to the higher-level IC exceeds the overcharge detection voltage VCU. In the lower-level IC (charge / discharge control circuit 30B), a detection signal is input to the CO terminal output control terminal C8B of the lower-level IC, and the second logic circuit 62B transitions to the charge control state. As a result, the second logic circuit 62B turns off the charge control FET 22. When charging stops, the voltage VBATn of the first cell 111A drops slightly and falls below the overcharge detection voltage VCU.

[0043] <Second State: Explanation of Overcharge State Release During Cascade Communication> Figures 2A and 2B show the second state of the battery device 10 according to the embodiment. Let's explain the changes from the first state. Switch 14 is controlled to the open position. This means that the charger 40 is not connected to the battery device 10 (disconnected). The voltage VM becomes higher than 0[V] (VM>0). As a result, the output terminal of the charger connection detection circuit 95B is released. The second logic circuit 62B returns to its normal state. The output terminal of the charging control signal output circuit 94B is released by the second logic circuit 62B. As a result, the FET22 for charge control is controlled to be in the ON state.

[0044] Thus, by removing the charger 40, the voltage VM increases. As a result, the charger connection detection circuit 95B of the lower IC outputs a release signal. Accordingly, the second logic circuit 62B masks the detection signal from the output terminal of the charge control signal detection circuit 92B and transitions to the normal state. Then, the second logic circuit 62B turns on the charge control FET 22. Here, the second logic circuit 62B maintains masking the detection signal of the CO terminal output control terminal C8B when the voltage VM is higher than 0[V] (when the charger 40 is open).

[0045] Furthermore, in the higher-level IC, the overcharge state of the first logic circuit 62A is maintained. In other words, in the examples of the first and second states, the higher-level IC, for example, detects an overcharge condition after the power is turned on, notifies the lower-level IC of this, and then maintains the overcharge condition. In this embodiment, the lower-level IC performs the masking using software, thus eliminating the need for complex circuits, for example.

[0046] <Third State: Explanation of Over-Discharge State Release During Cascade Communication> Figures 3A and 3B show the third state of the battery device 10 according to the embodiment. Switch 14 is controlled to the open position. This means that the charger 40 is not connected to the battery device 10 (disconnected).

[0047] This section describes the state of the charge / discharge control circuit 30A. Under normal conditions, the voltage VBATn of the first cell 111A is higher than the over-discharge detection voltage VDL and lower than the over-discharge release voltage VDU. Here, when the voltage VBATn of the first cell 111A falls below the over-discharge detection voltage VDL, the first logic circuit 62A enters an over-discharge state.

[0048] The output terminal of the over-discharge detection comparator 81A is in the detection state. The output terminal of the overcharge detection comparator 82A is in the deactivated state. The output terminal of the discharge control signal detection circuit 91A is in the released state. The output terminal of the charging control signal detection circuit 92A is in the released state.

[0049] The first logic circuit 62A controls the switch 71A to the OFF state based on the over-discharge state release signal. The first logic circuit 62A controls the switch 72A to the ON state based on the overcharge state release signal.

[0050] The output terminal of the discharge control signal output circuit 93A is detected by the first logic circuit 62A and outputs a discharge control signal. The output terminal of the charging control signal output circuit 94A is released by the first logic circuit 62A.

[0051] The state of the charge / discharge control circuit 30B will be explained. The voltage VM is higher than 0[V] (VM>0). As a result, the output terminal of the charger connection detection circuit 95B is in the disconnected state.

[0052] The voltage VBATn of the second cell 111B is higher than the over-discharge detection voltage VDL and lower than the overcharge release voltage VCL. The output terminal of the over-discharge detection comparator 81B is in the deactivated state. The output terminal of the overcharge detection comparator 82B is in the deactivated state. The output terminal of the discharge control signal detection circuit 91B is in the detection state. The output terminal of the charging control signal detection circuit 92B is in the released state.

[0053] The second logic circuit 62B is in a discharge control state. The second logic circuit 62B controls switch 71B to the ON state based on the over-discharge release signal. The second logic circuit 62B controls switch 72B to the OFF state based on the overcharge state release signal.

[0054] The output terminal of the discharge control signal output circuit 93B is detected by the second logic circuit 62B and outputs a discharge control signal. As a result, the discharge control FET 21 is controlled to the off state. The output terminal of the charging control signal output circuit 94B is released by the second logic circuit 62B. As a result, the FET22 for charge control is controlled to be in the ON state.

[0055] Thus, when the first cell 111A connected to the higher-level IC falls below the over-discharge detection voltage VDL, the first logic circuit 62A transitions to an over-discharge state. A detection signal is input to the DO terminal output control terminal C7B of the lower IC, and the second logic circuit 62B transitions to the discharge control state. As a result, the second logic circuit 62B turns off the discharge control FET 21. When the discharge stops, the voltage VBATn of the first cell 111A rises slightly and becomes higher than the over-discharge release voltage VDU.

[0056] <Fourth state: Explanation of over-discharge state release during cascade communication> Figures 4A and 4B show the fourth state of the battery device 10 according to the embodiment. Let's explain the changes from the third state. Switch 14 is controlled to the closed (SHORT) state. This connects the battery device 10 and the charger 40. The voltage VM becomes lower than 0[V] (VM<0). As a result, the output terminal of the charger connection detection circuit 95B enters a detection state. The second logic circuit 62B returns to its normal state. The output terminal of the discharge control signal output circuit 93B is released by the second logic circuit 62B. As a result, the discharge control FET 21 is controlled to be in the ON state.

[0057] Thus, connecting the charger 40 causes the voltage VM to decrease. As a result, the charger connection detection circuit 95B of the lower IC outputs a detection signal. Accordingly, the second logic circuit 62B masks the detection signal from the output terminal of the discharge control signal detection circuit 91B and transitions to the normal state. Then, the second logic circuit 62B turns on the discharge control FET 21. Here, the second logic circuit 62B maintains masking the detection signal of the DO terminal output control terminal C7B when the voltage VM is lower than 0[V] (when the charger 40 is connected).

[0058] Furthermore, in the higher-level IC, the over-discharge state of the first logic circuit 62A is maintained. In other words, in the examples of the third and fourth states, the higher-level IC, for example, detects the over-discharge condition after the power is turned on, notifies the lower-level IC of this, and then maintains the over-discharge condition. In this embodiment, the lower-level IC performs the masking using software, thus eliminating the need for complex circuits, for example.

[0059] <Example of a timing chart related to overcharging> Figure 5 shows an example of a timing chart related to overcharging according to the embodiment. Figure 5 shows five graphs. In the five graphs, the horizontal axis of each graph represents time, and it is a common time period. Time points t1 through t6 are shown. In each of the five graphs, the vertical axis represents voltage. In the example in Figure 5, (top) represents the state of the upper-level charge / discharge control circuit 30A, and (bottom) represents the state of the lower-level charge / discharge control circuit 30B.

[0060] The graph in Figure 5(A) shows the voltage VBATn characteristics of the first cell 111A of the higher-level IC. In this graph, the vertical axis shows the overcharge detection voltage VCU and the overcharge release voltage VCL.

[0061] The graph in Figure 5(B) shows the voltage VCO characteristics 1012 of the FET gate connection terminal C6A for charge control of the higher-level IC. In this graph, the vertical axis shows the voltage VCOH, which is the CO terminal voltage H, and the voltage VDD of the lower IC. Furthermore, the graph schematically shows the overcharge detection delay time tCU.

[0062] The graph in Figure 5(C) shows the voltage VM characteristics of the lower-end ICs 1013. In this graph, the vertical axis shows the charger detection voltage VCHG and the voltage VEB-.

[0063] The graph in Figure 5(D) shows the voltage characteristics of VCTLC 1014 at the CO terminal output control terminal C8B of the lower IC. In this graph, the vertical axis shows the sum of voltage VDD and voltage VCOH (VDD+VCOH), the CTLC terminal detection voltage VCTLCDET, and voltage VDD.

[0064] The graph in Figure 5(E) shows the voltage VCO characteristics 1015 of the FET gate connection terminal C6B for charge control of the lower IC. In this graph, the vertical axis shows the voltage VCOH. Furthermore, the graph schematically shows the CTLC terminal detection delay time tCTLC and the CTLC terminal release delay time tRCTLC.

[0065] Figure 5(F) shows whether or not the charger is connected. Figure 5(G) shows the state of the higher-level IC, indicating whether it is in a normal state or an overcharged state. Figure 5(H) shows the state of the lower-level IC, indicating whether it is in the normal state or the charge control state.

[0066] Here, time t1 is the time when the charger 40 is connected to the battery device 10. Time t2 is the time when the voltage VBATn of the first cell 111A of the higher-level IC exceeds the overcharge detection voltage VCU. Time t3 is the time it takes for the higher-level IC to transition from the normal state to the overcharged state. Time t4 is the time it takes for the lower-level IC to transition from the normal state to the charge control state. Time t5 is the time when the charger 40 is removed from the battery device 10. Time t6 is the time it takes for the lower-level IC to return from the charge control state to the normal state.

[0067] <Example of a timing chart related to over-discharge> Figure 6 shows an example of a timing chart related to over-discharge according to the embodiment. Figure 6 shows five graphs. In the five graphs, the horizontal axis of each graph represents time, and it is a common time point. Time points t11 through t16 are shown. In each of the five graphs, the vertical axis represents voltage. In the example in Figure 6, (top) represents the state of the upper-level charge / discharge control circuit 30A, and (bottom) represents the state of the lower-level charge / discharge control circuit 30B.

[0068] The graph in Figure 6(A) shows the voltage VBATn characteristics of the first cell 111A of the higher-level IC 1111. In this graph, the vertical axis shows the over-discharge release voltage VDU and the over-discharge detection voltage VDL.

[0069] The graph in Figure 6(B) shows the voltage VDO characteristics of the discharge control FET gate connection terminal C5A of the higher-level IC. In this graph, the vertical axis shows the voltage VDOH, which is the DO terminal voltage H, and the voltage VDD of the lower IC. Furthermore, the graph schematically shows the over-discharge detection delay time tDL.

[0070] The graph in Figure 6(C) shows the voltage VM characteristics of the lower-end IC 1113. In this graph, the vertical axis shows the charger detection voltage VCHG and the voltage VEB-.

[0071] The graph in Figure 6(D) shows the voltage characteristics of the VCTLD 1114 at the DO terminal output control terminal C7B of the lower IC. In this graph, the vertical axis shows the sum of voltage VDD and voltage VDOH (VDD+VDOH), the CTLD terminal detection voltage VCTLDDET, and voltage VDD.

[0072] The graph in Figure 6(E) shows the voltage VDO characteristics of the discharge control FET gate connection terminal C5B of the lower IC. In this graph, the vertical axis represents voltage VDOH. Furthermore, the graph schematically shows the CTLD terminal detection delay time tCTLD and the CTLD terminal release delay time tRCTLD.

[0073] Figure 6(F) shows whether or not the charger is connected. Figure 6(G) shows the state of the higher-level IC, indicating whether it is in a normal state or an over-discharged state. Figure 6(H) shows the state of the lower IC, indicating whether it is in the normal state or the discharge control state.

[0074] Here, time t11 is the time when the charger 40 is removed from the battery device 10. Time t12 is the time when the voltage VBATn of the first cell 111A of the higher-level IC falls below the over-discharge detection voltage VDL. Time t13 is the time it takes for the higher-level IC to transition from the normal state to the over-discharge state. Time t14 is the time it takes for the lower IC to transition from the normal state to the discharge control state. Time t15 is the time when the charger 40 is connected to the battery device 10. Time t16 is the time it takes for the lower IC to return from the discharge control state to the normal state.

[0075] [Regarding the implementation] As described above, in the charge / discharge control circuit 30, charge / discharge control device 20, and battery device 10 according to this embodiment, the lower-level IC (charge / discharge control circuit 30B) masks the cascade communication signals (charge control signal, discharge control signal) from the higher-level IC (charge / discharge control circuit 30A) according to the voltage VM of the external voltage input terminal C4B, thereby simulating the release of overcharge and over-discharge states. For example, when an overcharge condition occurs, the lower-level IC determines that the charger 40 is not connected if the voltage VM > 0[V], masks the charge control signal (a signal to prohibit charging) from the higher-level IC, and turns on the charge control FET 22. For example, when an over-discharge condition occurs, the lower-level IC determines that the charger 40 is connected if the voltage VM < 0[V], masks the discharge control signal (a signal to prohibit discharge) from the higher-level IC, and turns on the discharge control FET 21.

[0076] Thus, in the charge / discharge control circuit 30, charge / discharge control device 20, and battery device 10 according to this embodiment, by masking the cascade communication signal according to the voltage VM, it is possible to release the state for overcharging and over-discharging without adding a dedicated terminal for the cascade communication signal, for example.

[0077] Therefore, in the charge / discharge control circuit 30, charge / discharge control device 20, and battery device 10 according to this embodiment, the circuit size can be reduced when multiple protection ICs are cascaded. In this embodiment, for example, a dedicated terminal for cascade communication signals is not required, thus reducing the chip size and the number of pins in the package compared to conventional circuits. In this embodiment, for example, the absence of additional pads makes it possible to reduce the chip size. Furthermore, in this embodiment, the lower-level IC controls its output based on voltage VM, without relying on communication signals from the higher-level IC. For example, when an overcharge or over-discharge state is released, the FET (charge control FET 22 or discharge control FET 21) can be turned on more quickly than in conventional circuits. This reduces damage to the body diode (not shown) of the FET.

[0078] Here, we show an example configuration of the charge / discharge control circuit 30, charge / discharge control device 20, and battery device 10 according to this embodiment. The first logic circuit 62A performs first control based on the detection result of the first predetermined state detection unit. The first predetermined state detection unit detects a first predetermined state with respect to the first cell 111A. The first predetermined state detection unit includes a first ladder resistor, a first switch connected in parallel to the first ladder resistor, and a first comparator connected to one end of the first ladder resistor. With this configuration, the first predetermined state detection unit can perform operations related to overcharging or over-discharging. The first logic circuit 62A performs control such as controlling the on / off state of the first switch based on the output from the first comparator.

[0079] The second logic circuit 62B performs second control based on the detection result of the second predetermined state detection unit, the detection result of the charger connection detection unit, and the cascade communication signal from the first logic circuit 62A (first notification indicating that the first predetermined state is in place). The charger connection detection unit (charger connection detection circuit 95B) detects whether or not the battery 11 and the charger 40 are connected. The second predetermined state detection unit detects a second predetermined state with respect to the second cell 111B. The second predetermined state detection unit includes a second ladder resistor, a second switch connected in parallel to the second ladder resistor, and a second comparator connected to one end of the second ladder resistor. With this configuration, the second predetermined state detection unit can perform operations related to overcharging or over-discharging. The second logic circuit 62B performs control such as controlling the on / off state of the second switch based on the output from the second comparator. The second logic circuit 62B performs the second control by masking (disabling) the first notification from the first logic circuit 62A when the detection result of the charger connection detection unit satisfies predetermined conditions. In this way, the first notification is masked in the second logic circuit 62B, which makes it possible to avoid adding a dedicated terminal for, for example, cascaded communication signals.

[0080] As an example, the first predetermined state is an overcharge state. In this case, the predetermined conditions include the condition that the charger 40 has been removed from the battery 11. The second control by the second logic circuit 62B includes control to turn on the charge control FET 22. Furthermore, on the first logic circuit 62A side, regarding the overcharge condition, the first ladder resistor is an overcharge detection ladder resistor 54A~56A, the first switch is switch 72A, and the first comparator is an overcharge detection comparator 82A. Furthermore, on the second logic circuit 62B side, regarding the overcharge condition, the second ladder resistor is the overcharge detection ladder resistor 54B~56B, the second switch is switch 72B, and the second comparator is the overcharge detection comparator 82B. This configuration allows for the device to be reset when it is overcharged. In this embodiment, the release of the overcharge state (the release of the overcharge state performed by the second logic circuit 62B using a mask) may be referred to by any name, for example, VCU release.

[0081] Another example is that the first predetermined state is an over-discharge state. In this case, the predetermined conditions include the condition that the charger 40 is connected to the battery 11. The second control by the second logic circuit 62B includes control to turn on the discharge control FET 21. Furthermore, on the first logic circuit 62A side, regarding the over-discharge condition, the first ladder resistor is the over-discharge detection ladder resistor 51A~53A, the first switch is switch 71A, and the first comparator is the over-discharge detection comparator 81A. Furthermore, on the second logic circuit 62B side, regarding the over-discharge condition, the second ladder resistor is the over-discharge detection ladder resistor 51B~53B, the second switch is switch 71B, and the second comparator is the over-discharge detection comparator 81B. This configuration allows for the device to be reset in the event of an over-discharge. In this embodiment, the release of the over-discharge state (the release of the over-discharge state performed by the second logic circuit 62B using a mask) may be referred to by any name, for example, VDL release.

[0082] Here, we have described configuration examples where the first predetermined state is an overcharge state and configuration examples where the first predetermined state is an over-discharge state. However, as in this embodiment, a configuration that can handle both overcharge and over-discharge states may be used. Furthermore, a configuration corresponding to either the configuration example where the first predetermined state is an overcharged state or the configuration example where the first predetermined state is an over-discharged state may be used.

[0083] [Explanation of the comparative example] Comparative examples will be explained with reference to Figures 7 (Figures 7A and 7B) to 12 (Figures 12A and 12B), and Figures 13 to 14. For the sake of explanation, in Figures 7A and 7B to 12A and 12B, the same reference numerals are used to denote the same components as in Figures 1A and 1B to 4A and 4B.

[0084] Figures 7A and 7B show examples of the configuration of the charge / discharge control circuit 330, charge / discharge control device 320, and battery device 310 according to the comparative example, as well as the first state of the battery device 310 (first state in the comparative example). The comparative example battery device 310 differs from the battery device 10 according to the embodiment (examples in Figures 1A and 1B) in that it is equipped with a charge / discharge control circuit 330A and a charge / discharge control circuit 330B instead of the charge / discharge control circuit 30A and charge / discharge control circuit 30B in the battery device 10 according to the embodiment.

[0085] For illustrative purposes, the battery device 310 is shown separately in Figure 7A and Figure 7B, but these are actually a single, integrated device. The lines labeled a1 to a6 in Figure 7A are connected to the lines labeled a1 to a6 in Figure 7B.

[0086] The charge / discharge control circuit 330B differs from the charge / discharge control circuit 30B in the battery device 10 according to the embodiment in that it includes a charger connection detection signal output circuit 511B and a charger connection signal output terminal C31B, and that it includes a second logic circuit 562B instead of the second logic circuit 62B in the embodiment. The charge / discharge control circuit 330A differs from the charge / discharge control circuit 30A in the battery device 10 according to the embodiment in that it includes a charger connection detection circuit 95A and an external voltage input terminal C4A, and a charger connection detection signal output circuit 511A, and that it includes a first logic circuit 562A instead of the first logic circuit 62A in the embodiment.

[0087] The input terminal of the charger connection detection signal output circuit 511B is connected to one of the output terminals of the second logic circuit 562B. The output terminal of the charger connection detection signal output circuit 511B is connected to the charger connection signal output terminal C31B. The charger connection signal output terminal C31B of the lower-level IC (charge / discharge control circuit 330B) is connected to the external voltage input terminal C4A of the higher-level IC (charger connection signal output terminal C31A). External voltage input terminal C4A is connected to the input terminal of charger connection detection circuit 95A. The output terminal of the charger connection detection circuit 95A is connected to one of the input terminals of the first logic circuit 562A. The input terminal of the charger connection detection signal output circuit 511A is connected to one of the output terminals of the first logic circuit 562A. The output terminal of the charger connection detection signal output circuit 511A is connected to the charger connection signal output terminal C31A.

[0088] <Explanation of the first state in the comparative example: Overcharge state release during cascade communication> Figures 7A and 7B show the first state of the battery device 310. In the first state of the comparative example, compared to the first state of the battery device 10 shown in Figures 1A and 1B of this embodiment, the charger connection detection signal output circuit 511B is in a detection state, the charger connection detection circuit 95A is in a detection state, the charger connection detection signal output circuit 511A is in a deactivated state, and the overcharge detection comparator 82A is in a detection state.

[0089] Here, if the first cell 111A connected to the higher-level IC exceeds the overcharge detection voltage VCU, the first logic circuit 562A transitions to an overcharge state. The first logic circuit 562A controls the charging control signal output circuit 94A to a detection state, and the detection signal is input to the charging control signal detection circuit 92B of the lower IC, causing the second logic circuit 562B to transition to a charging control state. As a result, the second logic circuit 562B controls the charging control FET 22 to an OFF state. When charging stops, the voltage VBATn of the first cell 111A drops slightly and falls below the overcharge detection voltage VCU.

[0090] <Second state in the comparative example: Explanation of overcharge state release during cascade communication> Figures 8A and 8B show the second state of the battery device 310 according to the comparative example. Let's explain the changes from the first state. Switch 14 is controlled to the open position. This results in the battery unit 310 and the charger 40 being disconnected. The voltage VM becomes higher than 0[V] (VM>0). As a result, the output terminal of the charger connection detection circuit 95B is released. The charger connection detection signal output circuit 511B is released by the second logic circuit 562B. As a result, the charger connection detection circuit 95A is also released. The first logic circuit 562A controls switch 72A to turn off.

[0091] Thus, by removing the charger 40, the voltage VM increases. As a result, the lower-level IC's charger connection detection circuit 95B outputs a release signal. Accordingly, the second logic circuit 562B sets the charger connection detection signal output circuit 511B to a released state, and the charger connection detection signal output circuit 511B outputs a release signal. The higher-level IC clears the overcharge condition by turning off the 72A switch for the 55A overcharge detection ladder resistor. The overcharge detection comparator 82A enters a deactivated state and outputs a deactivated signal.

[0092] <Third state in the comparative example: Explanation of overcharge state release during cascade communication> Figures 9A and 9B show the third state of the battery device 310 according to the comparative example. Let's explain the changes from the second state. The first logic circuit 562A returns to its normal state. The output terminal of the charging control signal output circuit 94A is controlled to a released state by the first logic circuit 562A. As a result, the output terminal of the charging control signal detection circuit 92B is also released. The second logic circuit 562B returns to its normal state. The output terminal of the charging control signal output circuit 94B is released by the second logic circuit 562B. This controls the charging control FET 22 to be turned ON.

[0093] Thus, the higher-level IC transitions to the normal state after the overcharge detection comparator 82A outputs a release signal. As a result, a release signal is output from the charging control signal output circuit 94A, and a release signal is output from the charging control signal detection circuit 92B. The lower-level IC transitions to the normal state and controls the charge control FET22 to the ON state.

[0094] <Explanation of the fourth state in the comparative example: over-discharge state release during cascade communication> Figures 10A and 10B show the fourth state of the battery device 310 according to the comparative example. In this example, compared to the third state of the battery device 10 shown in Figures 3A and 3B according to this embodiment, the charger connection detection signal output circuit 511B is in a deactivated state, the charger connection detection circuit 95A is in a deactivated state, and the charger connection detection signal output circuit 511A is in a deactivated state.

[0095] Here, if the first cell 111A connected to the higher-level IC falls below the over-discharge detection voltage VDL, the first logic circuit 562A transitions to an over-discharge state. The first logic circuit 562A controls the discharge control signal output circuit 93A to a detection state, and the detection signal is input to the discharge control signal detection circuit 91B of the lower IC, causing the second logic circuit 562B to transition to a discharge control state. As a result, the second logic circuit 562B controls the discharge control FET 21 to an OFF state. When the discharge stops, the voltage VBATn of the first cell 111A rises slightly and becomes higher than the over-discharge release voltage VDU.

[0096] <Explanation of the fifth state in the comparative example: over-discharge state release during cascade communication> Figures 11A and 11B show the fifth state of the battery device 310 according to the comparative example. Let's explain the changes from the fourth state. Switch 14 is controlled to the closed (SHORT) state. This connects the battery device 10 and the charger 40. The voltage VM becomes lower than 0[V] (VM<0). As a result, the output terminal of the charger connection detection circuit 95B enters a detection state. The charger connection detection signal output circuit 511B is controlled to a detection state by the second logic circuit 562B. As a result, the charger connection detection circuit 95A enters a detection state. The first logic circuit 562A controls switch 71A to turn on.

[0097] Thus, connecting the charger 40 causes the voltage VM to decrease. As a result, the lower-level IC's charger connection detection circuit 95B outputs a detection signal. Accordingly, the second logic circuit 562B sets the charger connection detection signal output circuit 511B to a detected state, and the charger connection detection signal output circuit 511B outputs a detection signal. The higher-level IC clears the over-discharge state by turning on switch 71A of the over-discharge detection ladder resistor 52A. The over-discharge detection comparator 81A enters a deactivated state and outputs a deactivated signal.

[0098] <Sixth state in the comparative example: Explanation of over-discharge state release during cascade communication> Let's explain the changes from the fifth state. Figures 12A and 12B show the sixth state of the battery device 310 according to the comparative example. The first logic circuit 562A returns to its normal state. The output terminal of the discharge control signal output circuit 93A is controlled to a released state by the first logic circuit 562A. As a result, the output terminal of the discharge control signal detection circuit 91B is also released. The second logic circuit 562B returns to its normal state. The output terminal of the discharge control signal output circuit 93B is controlled to the release state by the second logic circuit 562B. This controls the discharge control FET 21 to the ON state.

[0099] Thus, the higher-level IC transitions to the normal state after the over-discharge detection comparator 81A outputs a release signal. As a result, a release signal is output from the discharge control signal output circuit 93A, and a release signal is output from the discharge control signal detection circuit 91B. The lower-level IC transitions to the normal state and controls the discharge control FET 21 to the ON state.

[0100] <Example of a timing chart for overcharging in a comparative example> Figure 13 shows an example of a timing chart related to overcharging in a comparative example. Figure 13 shows six graphs. In all six graphs, the horizontal axis represents time, and the same time period is common to all of them. Time points t21 through t27 are shown. In each of the six graphs, the vertical axis represents voltage. In the example in Figure 13, (top) represents the state of the upper-level charge / discharge control circuit 330A, and (bottom) represents the state of the lower-level charge / discharge control circuit 330B.

[0101] The graph in Figure 13(A) shows the voltage VBATn characteristics of the first cell 111A of the higher-level IC 1211. In this graph, the vertical axis shows the overcharge detection voltage VCU and the overcharge release voltage VCL.

[0102] The graph in Figure 13(B) shows the voltage VCO characteristics of the charge control FET gate connection terminal C6A of the higher-level IC. In this graph, the vertical axis shows the voltage VCOH, which is the CO terminal voltage H, and the voltage VDD of the lower IC. Furthermore, the graph schematically shows the overcharge detection delay time tCU and the overcharge release delay time tCL.

[0103] The graph in Figure 13(C) shows the voltage VM characteristics of the lower-end IC 1213. In this graph, the vertical axis shows the charger detection voltage VCHG and the voltage VEB-.

[0104] The graph of FIG. 13(D) shows the characteristic 1216 of the voltage VMO at the charger connection signal output terminal C31B of the lower IC. In the graph, the vertical axis shows the voltage VDD and the voltage VMOL which is the terminal voltage L of the charger connection signal output terminal C31B. The graph shows that an output inversion (VM < VCHG) has occurred.

[0105] The graph of FIG. 13(E) shows the characteristic 1214 of the voltage VCTLC at the CO terminal output control terminal C8B of the lower IC. In the graph, the vertical axis shows the sum of the voltage VDD and the voltage VCOH (VDD + VCOH), the CTLC terminal detection voltage VCTLCDET, and the voltage VDD.

[0106] The graph of FIG. 13(F) shows the characteristic 1215 of the voltage VCO at the charger control FET gate connection terminal C6B of the lower IC. In the graph, the vertical axis shows the voltage VCOH. Also, in the graph, the CTLC terminal detection delay time tCTLC and the CTLC terminal release delay time tRCTLC are schematically shown.

[0107] FIG. 13(G) shows the presence or absence of charger connection. FIG. 13(H) shows whether the upper IC is in a normal state or an overcharge state. FIG. 13(I) shows whether the lower IC is in a normal state or a charge control state.

[0108] Here, the time t21 is the time when the charger 40 is connected to the battery device 310. The time t22 is the time when the voltage VBATn of the first cell 111A of the upper IC exceeds the overcharge detection voltage VCU. The time t23 is the time when the upper IC transitions from the normal state to the overcharge state. The time t24 is the time when the lower IC transitions from the normal state to the charge control state. Time t25 is the time when the charger 40 was removed from the battery device 310. Time t26 is the time it takes for the higher-level IC to return from an overcharged state to a normal state. Time t27 is the time it takes for the lower-level IC to return from the charge control state to the normal state.

[0109] <Example of a timing chart related to over-discharge in a comparative example> Figure 14 shows an example of a timing chart related to over-discharge in a comparative example. Figure 14 shows six graphs. In all six graphs, the horizontal axis represents time, and the same time period is used for all of them. The graphs show time points t31 through t37. In each of the six graphs, the vertical axis represents voltage. In the example in Figure 14, (top) represents the state of the upper-level charge / discharge control circuit 330A, and (bottom) represents the state of the lower-level charge / discharge control circuit 330B.

[0110] The graph in Figure 14(A) shows the voltage VBATn characteristics of the first cell 111A of the higher-level IC 1311. In this graph, the vertical axis shows the over-discharge release voltage VDU and the over-discharge detection voltage VDL.

[0111] The graph in Figure 14(B) shows the voltage VDO characteristic of the discharge control FET gate connection terminal C5A of the higher-level IC. In this graph, the vertical axis shows the voltage VDOH, which is the DO terminal voltage H, and the voltage VDD of the lower IC. Furthermore, the graph schematically shows the over-discharge detection delay time tDL and the over-discharge release delay time tDU.

[0112] The graph in Figure 14(C) shows the voltage VM characteristics of the lower-end IC 1313. In this graph, the vertical axis shows the voltage VEB- and the charger detection voltage VCHG.

[0113] The graph in Figure 14(D) shows the voltage VMO characteristic of the lower IC's charger connection signal output terminal C31B. In this graph, the vertical axis shows the voltage VDD and the voltage VMOL, which is the terminal voltage L of the charger connection signal output terminal C31B. The graph shows that the output (VM>VCHG) occurred.

[0114] The graph in Figure 14(E) shows the voltage characteristics of the VCTLD 1314 at the DO terminal output control terminal C7B of the lower IC. In this graph, the vertical axis shows the sum of voltage VDD and voltage VDOH (VDD+VDOH), the CTLD terminal detection voltage VCTLDDET, and voltage VDD.

[0115] The graph in Figure 14(F) shows the voltage VDO characteristic of the lower IC's discharge control FET gate connection terminal C5B. In this graph, the vertical axis represents voltage VDOH. Furthermore, the graph schematically shows the CTLD terminal detection delay time tCTLD and the CTLD terminal release delay time tRCTLD.

[0116] Figure 14(G) shows whether or not the charger is connected. Figure 14(H) shows the state of the higher-level IC, indicating whether it is in a normal state or an over-discharged state. Figure 14(I) shows the state of the lower-level IC, indicating whether it is in the normal state or the discharge control state.

[0117] Here, time t31 is the time when the charger 40 is removed from the battery device 310. Time t32 is the time when the voltage VBATn of the first cell 111A of the higher-level IC falls below the over-discharge detection voltage VDL. Time t33 is the time it takes for the higher-level IC to transition from the normal state to the over-discharged state. Time t34 is the time it takes for the lower-level IC to transition from the normal state to the discharge control state. Time t35 is the time when the charger 40 is connected to the battery device 310. Time t36 is the time it takes for the higher-level IC to return from an over-discharged state to a normal state. Time t37 is the time when the lower-level IC returns from the discharge control state to the normal state.

[0118] As described above, the battery device 310 in the comparative example requires dedicated terminals for cascade communication signals between the higher-level IC and the lower-level IC (in this example, the charger connection signal output terminal C31B on the lower-level IC, and the charger connection detection circuit 95A and charger connection signal output terminal C31A on the higher-level IC). In contrast, the battery device 10 according to this embodiment does not require such dedicated terminals.

[0119] (Examples of overcharging and over-discharging conditions being resolved in reference cases) Figure 15 shows the process of releasing overcharge and over-discharge states in a reference example. Here, we will provide a brief overview of the example, omitting detailed explanations.

[0120] In the graphs shown in Figures 15(A) to 15(E), the horizontal axis represents time, and the vertical axis represents the respective voltages. Figure 15(A) shows the battery voltage characteristics 2011. Figure 15(B) shows the DO terminal voltage characteristics 2012. Figure 15(C) shows the CO terminal voltage characteristics 2013. Figure 15(D) shows the VM voltage characteristics for 2014. Figure 15(E) shows the VINI terminal voltage characteristics 2015. The VINI terminal (not shown) is a terminal for detecting overcurrent conditions. Figure 15(F) shows whether or not the charger is connected. When the charger is connected, the VINI terminal voltage drops from the VSS voltage, and when the VINI terminal voltage falls below the charging overcurrent detection voltage VCIOV, a charging overcurrent condition (not shown) is detected. Figure 15(G) shows whether or not a load is connected. When a load is connected, the VINI terminal voltage rises from the VSS voltage, and when the VINI terminal voltage exceeds the discharge overcurrent detection voltage VDIOV, a discharge overcurrent condition (not shown) is detected. Figure 15(H) shows the state of the IC, whether it is (1) in a normal state, (2) in an overcharged state, or (3) in an over-discharged state. Figure 15 schematically shows the overcharge state release 2111 and the over-discharge state release 2112.

[0121] <About overcharging and its release> If the normal battery voltage exceeds the overcharge detection voltage VCU during charging, and this condition persists for longer than the overcharge detection delay time tCU, the charge control FET is turned off and charging is stopped. This condition is an overcharge state. Furthermore, one way to release the overcharge state is the overcharge state release 2111 shown in Figure 15. In this type of overcharge release mechanism 2111, when the voltage VM is above a predetermined value, the overcharge state is released when the battery voltage drops to or below the overcharge release voltage VCL.

[0122] <About over-discharge and its release> If the normal battery voltage falls below the over-discharge detection voltage VDL during discharge, and this state persists for longer than the over-discharge detection delay time tDL, the discharge control FET is turned off to stop the discharge. This state is considered an over-discharge state. When the voltage VM exceeds a predetermined value in an over-discharge state, the power-down function activates, reducing the current consumption to the power-down current consumption level. The power-down function is deactivated by connecting the charger and allowing the voltage VM to fall below the predetermined value. One way to release the over-discharge state is through the over-discharge state release 2112 shown in Figure 15. In this type of over-discharge state release 2112, the over-discharge state is released when the charger is connected, the voltage VM is below a predetermined value, and the battery voltage is equal to or greater than the over-discharge release voltage VDU.

[0123] The overcharge state release process according to this embodiment can be applied, for example, instead of the overcharge state release 2111 shown in Figure 15. Similarly, the over-discharge state release process according to this embodiment can be applied, for example, instead of the over-discharge state release 2112 shown in Figure 15. However, the overcharge state release process and over-discharge state release process according to this embodiment may be applied to any circuit or any device.

[0124] While embodiments of this disclosure have been described in detail above with reference to the drawings, the specific configuration is not limited to these embodiments and includes designs and the like that do not depart from the gist of this disclosure. For example, although the discharge control FET 21, charge control FET 22, external voltage input terminal C4B, discharge control FET gate connection terminal C5B, and charge control FET gate connection terminal C6B are arranged on the low side (negative side of the battery), the configuration is not limited to this and may also be arranged on the high side (positive side of the battery). [Explanation of Symbols]

[0125] 10…Battery device, 11…Battery, 11A, 11B…Battery section, 13…Short-circuit load, 14…Switch, 20…Charge / discharge control device, 21…FET for discharge control, 22…FET for charge control, 30, 30A, 30B…Charge / discharge control circuit, 40…Charger, 111A…First cell, 111B…Second cell, 51A~53A, 51B~53B…Over-discharge detection ladder resistor, 54A~56A, 54B~56B…Overcharge detection ladder resistor, 62A…First logic circuit, 62B…Second logic circuit, 81A, 81B…Over-discharge detection comparator, 82A, 82B…Overcharge detection comparator

Claims

1. A battery in which multiple cells, including the first and second cells, are connected in series, A first predetermined state detection unit for detecting a first predetermined state with respect to the first cell, A first logic circuit that performs first control based on the detection result of the first predetermined state detection unit, A second predetermined state detection unit detects a second predetermined state with respect to the second cell, A charger connection detection unit that detects whether or not the battery and charger are connected, A second logic circuit that performs second control based on the detection result of the second predetermined state detection unit, the detection result of the charger connection detection unit, and the first notification from the first logic circuit that the first predetermined state is met, Equipped with, The first predetermined state and the second predetermined state are an overcharge state or an over-discharge state, The second logic circuit, when the detection result of the charger connection detection unit satisfies predetermined conditions, masks the first notification from the first logic circuit and performs the second control. Charge / discharge control circuit.

2. The first predetermined state detection unit includes a first ladder resistor, a first switch connected in parallel to the first ladder resistor, and a first comparator connected to one end of the first ladder resistor. The first logic circuit controls the on / off state of the first switch based on the output from the first comparator. The second predetermined state detection unit includes a second ladder resistor, a second switch connected in parallel to the second ladder resistor, and a second comparator connected to one end of the second ladder resistor. The second logic circuit controls the on / off state of the second switch based on the output from the second comparator. The charge / discharge control circuit according to claim 1.

3. The first predetermined state is an overcharge state, The aforementioned predetermined conditions include the condition that the charger has been disconnected from the battery. The charge / discharge control circuit according to claim 1.

4. The first predetermined state is an over-discharge state, The aforementioned predetermined conditions include the condition that the charger is connected to the battery, The charge / discharge control circuit according to claim 1.

5. The first predetermined state is an overcharge state, The second control includes a control that turns on a charge control FET that controls charging, The charge / discharge control circuit according to claim 1.

6. The first predetermined state is an over-discharge state, The second control includes a control that turns on a discharge control FET that controls the discharge, The charge / discharge control circuit according to claim 1.

7. A discharge control FET that controls the discharge, A charge control FET that controls the charging process, A charge / discharge control circuit according to claim 1, A charge / discharge control device equipped with the following features.

8. Battery and A charge / discharge control device according to claim 7 for controlling the charging and discharging of the battery, A battery device equipped with the following features.

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