Indication device

Abstract

This invention provides a technology that enables both high resolution and high pixel count in display devices. [Solution] The display device includes a plurality of pixels arranged in a matrix, a plurality of gate lines connected to pixels arranged in the row direction, a plurality of signal lines connected to pixels arranged in the column direction, a gate line driving circuit that scans the plurality of gate lines, and a signal line driving circuit that supplies grayscale signals to the plurality of signal lines. The pixels arranged in the column direction include a plurality of first pixels connected to a first signal line and a plurality of second pixels connected to a second signal line. The first signal line and the second signal line are provided running parallel to the pixels arranged in the column direction.

Description

Technical Field

[0001] The present disclosure relates to a display device.

Background Art

[0002] A display device capable of reducing the number of video lines has been proposed, for example, in Japanese Patent Application Laid-Open No. 2010-97067.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In Japanese Patent Application Laid-Open No. 2010-97067, scanning lines are assigned for each color, but the method for generating the drive signals for the scanning lines is not disclosed.

[0005] The present disclosure was devised by the present inventor in the process of studying a technique that can achieve both high definition and a high number of pixels in a display device.

[0006] The present disclosure aims to provide a technique that can achieve both high definition and a high number of pixels in a display device.

[0007] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0008] The outline of typical aspects of the present invention will be briefly described as follows.

[0009] That is, a display device according to one aspect includes a plurality of pixels arranged in a matrix, Multiple gate lines connected to pixels arranged in the row direction, Multiple signal lines connected to pixels arranged in a column, A gate line driving circuit that scans the plurality of gate lines, A signal line drive circuit that supplies grayscale signals to the plurality of signal lines, Includes, The pixels arranged in the column direction include a plurality of first pixels connected to a first signal line and a plurality of second pixels connected to a second signal line. The first signal line and the second signal line are provided running parallel to the pixels arranged in the column direction.

[0010] Furthermore, other display devices relating to one embodiment are, Multiple pixels arranged in a matrix, Multiple gate lines connected to pixels arranged in the row direction, Multiple signal lines connected to pixels arranged in a column, A gate line driving circuit that scans the plurality of gate lines, The circuit includes a signal line drive circuit that supplies grayscale signals to the plurality of signal lines, The gate line drive circuit includes a first selection signal for selecting one of two adjacent gate lines, and a second selection signal for selecting the other of two adjacent gate lines. [Brief explanation of the drawing]

[0011] [Figure 1] Figure 1 shows an example of the configuration of a display device related to a comparative example. [Figure 2] Figure 2 shows an example of the timing of the display device in Figure 1. [Figure 3] Figure 3 illustrates the parasitic elements between the source terminal and signal line of the display device shown in Figure 1. [Figure 4] Figure 4 shows an example of the configuration of the display device according to Example 1. [Figure 5] Figure 5 shows an example of the timing of the display device in Figure 4. [Figure 6] Figure 6 illustrates the parasitic elements between the source terminal and signal line of the display device shown in Figure 4. [Figure 7] FIG. 7 is a diagram showing a configuration example of a display device according to a modified example. [Figure 8] FIG. 8 is a diagram showing a configuration example of a display device according to Example 2. [Figure 9] FIG. 9 is a diagram showing a timing example of the display device of FIG. 8. [Figure 10] FIG. 10 is a diagram for explaining parasitic elements between a source terminal and a signal line of the display device of FIG. 8. [Figure 11] FIG. 11 is a diagram showing a configuration example of a gate driver selection circuit and a gate driving circuit. [Figure 12] FIG. 12 is a diagram for explaining a timing example of the gate driver selection circuit and the gate driving circuit. [Figure 13] FIG. 13 is a diagram for explaining a state where the display devices (10a, 10b) have a flexible printed wiring board (FPC). [Figure 14] FIG. 14 is a diagram for explaining a state where the display device (10c) has a flexible printed wiring board (FPC). [Figure 15] FIG. 15 is a diagram showing a configuration example of an intersection portion of a selection signal wiring MUXL and a common potential wiring COML in FIG. 14. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, each embodiment of the present invention will be described with reference to the drawings.

[0013] Note that the disclosure is merely an example, and for those that can be easily conceived by those skilled in the art with appropriate modifications while maintaining the gist of the invention, they are naturally included in the scope of the present invention. In addition, for the purpose of making the description clearer, the drawings may schematically show the width, thickness, shape, etc. of each part compared to the actual aspect, but it is merely an example and does not limit the interpretation of the present invention.

[0014] Furthermore, in this specification and in each figure, elements similar to those described above for previously shown figures are denoted by the same reference numerals, and detailed explanations may be omitted as appropriate.

[0015] In this embodiment, a liquid crystal display device is disclosed as an example of a display device. This liquid crystal display device can be used in various devices such as AR / VR / MR terminals, smartphones, tablet terminals, mobile phone terminals, personal computers, television receivers, in-vehicle devices, goggles, and game devices.

[0016] The term "display device" refers to all display devices that display images using a display panel. The term "display panel" refers to a structure that displays images using an electro-optic layer. For example, the term "display panel" may refer to a display cell that includes an electro-optic layer, or it may refer to a structure in which a semiconductor device equipped with other optical components (e.g., polarizing components, backlights, touch panels, etc.) or a drive circuit such as a source driver IC is attached to the display cell. Here, the "electro-optic layer" may include liquid crystal layers, electrochromic (EC) layers, etc., as long as it does not create a technical contradiction. Therefore, although the embodiments described later will use a liquid crystal panel including a liquid crystal layer as an example of a display panel, this does not preclude its application to display panels including other electro-optic layers as described above.

[0017] First, the display device related to the comparative example will be explained using diagrams. Figure 1 is a diagram showing an example configuration of the display device related to the comparative example. Figure 2 is a diagram showing an example of the timing of the display device in Figure 1. Figure 3 is a diagram illustrating the parasitic elements between the source terminal and the signal line of the display device in Figure 1.

[0018] As shown in Figure 1, the display device 10r has an active area (display area) AA provided with multiple gate lines, multiple signal lines, and multiple pixels. In the active area AA, multiple pixels PIX are formed in a matrix (matrix) arrangement along a first direction X and a second direction Y that intersects the first direction X. Each pixel PIX includes one red pixel R, one blue pixel B, and one green pixel G as subpixels. In this example, a total of 16 pixels are depicted as a representative example, consisting of multiple pixels PIX arranged in a 4x4 matrix, i.e., 4 pixels in the first direction X (horizontal direction, row direction) and 4 pixels in the second direction Y (vertical direction, column direction) that intersects the first direction X.

[0019] Multiple gate lines (GateN, GateN+1, GateN+2, GateN+3) are arranged to extend along the first direction X and are also arranged to be adjacent to the second direction Y. The first row of 4 pixels is connected to gate line GateN. The second row of 4 pixels is connected to gate line GateN+1. The third row of 4 pixels is connected to gate line GateN+2. The fourth row of 4 pixels is connected to gate line GateN+3.

[0020] Multiple gate drivers GD1-GD4 are provided to drive multiple gate lines (GateN, GateN+1, GateN+2, GateN+3). Gate driver GD1 drives gate line GateN, gate driver GD2 drives gate line GateN+1, gate driver GD3 drives gate line GateN+2, and gate driver GD4 drives gate line GateN+3.

[0021] Gate drivers GD1 and GD3 are configured to receive a first enable signal EN1, and gate drivers GD2 and GD4 are configured to receive a second enable signal EN2. Gate drivers GD1 and GD2 are configured to receive a first transfer signal TRNm, and gate drivers GD3 and GD4 are configured to receive a second transfer signal TRNm+1.

[0022] The first transfer signal TRNm is generated by the first shift register S / R, and the second transfer signal TRNm+1 is generated by the second shift register S / R. The first shift register S / R is configured to receive a start pulse STV and a transfer clock CKV, and it takes the high-level start pulse STV in synchronization with the high-level transfer clock CKV to generate a high-level first transfer signal TRNm. The second shift register S / R is configured to receive the first transfer signal TRNm and a transfer clock CKV, and it takes the high-level first transfer signal TRNm in synchronization with the low-level transfer clock CKV to generate a high-level second transfer signal TRNm+1. In other words, the first shift register S / R and the second shift register S / R are configured to sequentially shift high-level transfer signals in synchronization with the transfer clock CKV.

[0023] Gate driver GD1 supplies a high-level drive signal to gate line GateN based on a high-level first transfer signal TRNm and a high-level first enable signal EN1. Gate driver GD2 supplies a high-level drive signal to gate line GateN+1 based on a high-level first transfer signal TRNm and a high-level second enable signal EN2. Gate driver GD3 supplies a high-level drive signal to gate line GateN+2 based on a high-level second transfer signal TRNm+1 and a high-level first enable signal EN1. Gate driver GD4 supplies a high-level drive signal to gate line GateN+3 based on a high-level second transfer signal TRNm+1 and a high-level second enable signal EN2. In this way, multiple gate lines (GateN, GateN+1, GateN+2, GateN+3) are scanned. Gate lines can be rephrased as scan lines.

[0024] On the other hand, the multiple signal lines Sig(SR1-SR4, SG1-SG4, SB1-SB4) include signal lines SR1-SR4 for red pixels, signal lines SG1-SG4 for green pixels, and signal lines SB1-SB4 for blue pixels, which are provided extending in the second direction Y.

[0025] Signal line SR1 is connected to each of the four red pixels R in the first row. Signal line SG1 is connected to each of the four green pixels G in the first row. Signal line SB1 is connected to each of the four blue pixels B in the first row.

[0026] Signal line SR2 is connected to each of the four red pixels R in the second row. Signal line SG2 is connected to each of the four green pixels G in the second row. Signal line SB2 is connected to each of the four blue pixels B in the second row.

[0027] Signal line SR3 is connected to each of the four red pixels R in the third row. Signal line SG3 is connected to each of the four green pixels G in the third row. Signal line SB3 is connected to each of the four blue pixels B in the third row.

[0028] Signal line SR4 is connected to each of the four red pixels R in the fourth row. Signal line SG4 is connected to each of the four green pixels G in the fourth row. Signal line SB4 is connected to each of the four blue pixels B in the fourth row.

[0029] A multiplexer 110r is provided between multiple signal lines Sig and source line driver ICs 100r. The multiplexer 110r is configured to include multiple first switches SW1 which are controlled to be on or off according to the level of a first selection signal MUX1, and multiple second switches SW2 which are controlled to be on or off according to the level of a second selection signal MUX2.

[0030] The source line driver 100r includes multiple source line terminals S1-S6 for supplying signals to multiple signal lines Sig. The multiplexer 110r and the source line driver 100r can be described as a signal line drive circuit that supplies grayscale signals to multiple signal lines.

[0031] The first source line terminal S1 is connected to signal line SR1 via the first switch SW1, and also to signal line SB1 via the second switch SW2. The second source line terminal S2 is connected to signal line SG1 via the first switch SW1, and also to signal line SR2 via the second switch SW2. The third source line terminal S3 is connected to signal line SG2 via the first switch SW1, and also to signal line SR3 via the second switch SW2.

[0032] The fourth source line terminal S4 is connected to signal line SB2 via the first switch SW1, and also to signal line SG3 via the second switch SW2. The fifth source line terminal S5 is connected to signal line SB3 via the first switch SW1, and also to signal line SG4 via the second switch SW2. The sixth source line terminal S6 is connected to signal line SR4 via the first switch SW1, and also to signal line SB4 via the second switch SW2.

[0033] Next, we will explain an example of timing using Figure 2. Since we have already explained the transfer clock CKV, the first transfer signal TRNm, the second transfer signal TRNm+1, the first enable signal EN1, and the second enable signal EN2, we will now explain the gate lines GateN, GateN+1, GateN+2, GateN+3, the first selection signal MUX1, the second selection signal MUX2, and the multiple source line terminals S1-S6.

[0034] When the gate line GateN is set to a high level and the first selection signal MUX1 is set to a high level, grayscale signals of red signal R1, green signal G1, green signal G2, blue signal B2, blue signal B3, and red signal R4 are supplied from source line terminals S1-S6 to signal lines SR1, SG1, SG2, SB2, SB3, and SR4, and grayscale signals corresponding to the red pixel R, green pixel G, green pixel G, blue pixel B, blue pixel B, and red pixel R of the corresponding pixels in the four pixels of the first row are written.

[0035] When the gate line GateN is set to a high level and the second selection signal MUX2 is set to a high level, the grayscale signals B1 (blue), R2 (red), R3 (red), G3 (green), G4 (green), and B4 (blue) signals are supplied from the source line terminals S1-S6 to the signal lines SB1, SR2, SR3, SG3, SG4, and SB4, respectively, and the grayscale signals corresponding to the blue pixel B, red pixel R, red pixel R, green pixel G, green pixel G, and blue pixel R of the corresponding pixels in the four pixels of the first row are written.

[0036] When the gate line GateN+1 is set to a high level and the first selection signal MUX1 is set to a high level, grayscale signals of red signal R1, green signal G1, green signal G2, blue signal B2, blue signal B3, and red signal R4 are supplied from source line terminals S1-S6 to signal lines SR1, SG1, SG2, SB2, SB3, and SR4, and grayscale signals corresponding to the red pixel R, green pixel G, green pixel G, blue pixel B, blue pixel B, and red pixel R of the corresponding pixels in the four pixels of the second column are written.

[0037] When the gate line GateN+1 is set to a high level and the second selection signal MUX2 is set to a high level, the grayscale signals B1 (blue), R2 (red), R3 (red), G3 (green), G4 (green), and B4 (blue) signals are supplied from the source line terminals S1-S6 to the signal lines SB1, SR2, SR3, SG3, SG4, and SB4, respectively, and the grayscale signals corresponding to the blue pixel B, red pixel R, red pixel R, green pixel G, green pixel G, and blue pixel R of the corresponding pixels in the four pixels of the second column are written.

[0038] When the gate line GateN+2 is set to a high level and the first selection signal MUX1 is set to a high level, grayscale signals of red signal R1, green signal G1, green signal G2, blue signal B2, blue signal B3, and red signal R4 are supplied from source line terminals S1-S6 to signal lines SR1, SG1, SG2, SB2, SB3, and SR4, and grayscale signals corresponding to the red pixel R, green pixel G, green pixel G, blue pixel B, blue pixel B, and red pixel R of the corresponding pixels in the four pixels of the third column are written.

[0039] When the gate line GateN+2 is set to a high level and the second selection signal MUX2 is set to a high level, the grayscale signals B1 (blue), R2 (red), R3 (red), G3 (green), G4 (green), and B4 (blue) signals are supplied from the source line terminals S1-S6 to the signal lines SB1, SR2, SR3, SG3, SG4, and SB4, respectively, and the grayscale signals corresponding to the blue pixel B, red pixel R, red pixel R, green pixel G, green pixel G, and blue pixel R of the corresponding pixels in the four pixels of the third column are written.

[0040] When the gate line GateN+3 is set to a high level and the first selection signal MUX1 is set to a high level, grayscale signals for red signal R1, green signal G1, green signal G2, blue signal B2, blue signal B3, and red signal R4 are supplied from source line terminals S1-S6 to signal lines SR1, SG1, SG2, SB2, SB3, and SR4, and grayscale signals corresponding to the red pixel R, green pixel G, green pixel G, blue pixel B, blue pixel B, and red pixel R of the corresponding pixels in the four pixels of the corresponding fourth column are written.

[0041] When the gate line GateN+3 is set to high level and the second selection signal MUX2 is set to high level, grayscale signals of blue signal B1, red signal R2, red signal R3, green signal G3, green signal G4, and blue signal B4 are supplied from source line terminals S1-S6 to signal lines SB1, SR2, SR3, SG3, SG4, and SB4, and the grayscale signals corresponding to the blue pixel B, red pixel R, red pixel R, green pixel G, green pixel G, and blue pixel R of the corresponding pixels in the four pixels of the corresponding fourth column are written.

[0042] Next, we will explain the parasitic elements between the source terminal and signal lines of the display device using Figure 3. Figure 3 shows parasitic resistive elements and parasitic capacitive elements as parasitic elements between the source terminal (S1...) and the signal lines (Sig: SR1-SR4, SG1-SG4, SB1-SB4). As shown in Figure 3, the following parasitic elements exist between the source terminal S1 and the signal line Sig.

[0043] 1) Inside the source wire driver 100r, the parasitic resistance element Ric of the wiring connected to source terminal S1, 2) Parasitic resistance element Rv and parasitic capacitance element Cs based on the video cable and its routing between the wiring connected to source terminal S1 and the first switch SW1 and second switch SW2 in the multiplexer 110r. 3) Internal parasitic resistance element Rmux of the first switch SW1 and second switch SW2 in the multiplexer 110r, 4) Parasitic resistance element Rsig and parasitic capacitance element Csig of the signal line Sig.

[0044] Therefore, the following problems can be considered with the display device 10r in the comparative example shown in Figure 1. (1) High resolution and increased pixel count (while maintaining the same screen size) are difficult. (2) As the aperture ratio decreases, the optical properties deteriorate. (3) There are no or few source line drivers capable of handling a significant increase in the number of pixels. (4) As the time constant of the video line to the signal line Sig increases, it becomes difficult to complete writing the signal to each pixel within the specified time.

[0045] (Example 1) Field sequential driving is known as a method to improve the decrease in aperture ratio that occurs with higher resolution. If field sequential driving is adopted and the number of pixels in the vertical and horizontal directions is to be increased, a display device 10a with a signal line and gate line connection configuration as shown in Figure 4 can be considered. The display device 10a according to Embodiment 1 will be described below with reference to the figures. Figure 4 is a diagram showing an example of the configuration of the display device according to Embodiment 1. Figure 5 is a diagram showing an example of the timing of the display device in Figure 4. Figure 6 is a diagram illustrating the parasitic elements between the source terminal and the signal line of the display device in Figure 4.

[0046] As shown in Figure 4, the display device 10a has an active region AA, in which multiple pixels PIX are formed in a matrix along a first direction X and a second direction Y that intersects the first direction X. Each pixel PIX is driven by a driving method in which one frame period has multiple subframe (field) periods. Such a driving method is called, for example, a field sequential method. In the field sequential method, images of red (R), green (G), and blue (B) are selectively displayed for each subframe period. The images of each color displayed in time division are perceived by the user as a multicolor display image. The display device 10r described in Figure 1 is a color filter method, and one pixel is created by dividing the pixel PIX into subpixels for each of the first color (red), second color (green), and third color (blue), whereas in the field sequential method, such subpixel division is not necessary. This makes it possible to increase the number of pixels.

[0047] In this example, a total of 48 pixels are depicted as representative examples, consisting of multiple pixels arranged in a 6x8 matrix (row-like) configuration: 6 pixels in the first direction X (horizontal, row direction) and 8 pixels in the second direction Y (vertical, column direction).

[0048] Here, we will describe typical configurations for pixel PIX and field sequential scanning. As shown in an enlarged view in Figure 4, a thin-film transistor is used as the switching element Tr provided in each pixel PIX. Examples of thin-film transistors include bottom-gate transistors and top-gate transistors. A single-gate thin-film transistor is shown as an example of the switching element Tr, but a double-gate transistor may also be used. One of the source and drain electrodes of the switching element Tr is connected to the signal line (Sig), the gate electrode is connected to the gate line (GateN), which is the scanning line, and the other of the source and drain electrodes is connected to one end of the capacitance of the polymer-dispersed liquid crystal (LC). One end of the capacitance of the polymer-dispersed liquid crystal (LC) is connected to the switching element Tr via the pixel electrode PE, and the other end is connected to the common potential wiring COML via the common electrode CE. In addition, a retaining capacitance HC is generated between the pixel electrode PE and the retaining capacitance electrode IO, which is electrically connected to the common potential wiring COML. The common voltage VCOM is supplied to the common potential wiring COML from the common potential drive circuit 45.

[0049] The light-emitting unit 31 used in the field sequential method includes a first-color (e.g., red) light-emitting element 33R, a second-color (e.g., green) light-emitting element 33G, and a third-color (e.g., blue) light-emitting element 33B. The light source control unit 32 controls the first-color light-emitting element 33R, the second-color light-emitting element 33G, and the third-color light-emitting element 33B to emit light in a time-division manner based on the light source control signal. In this way, the first-color light-emitting element 33R, the second-color light-emitting element 33G, and the third-color light-emitting element 33B are driven in a field sequential manner.

[0050] Furthermore, in this example, multiple pixels (PIX) are configured using a column inversion method. In this example, for the six pixels in one line (one row) in the first direction X, bit inversion driving is represented, where the voltage applied to the liquid crystal layer (the voltage written to the pixel PIX) is inverted between positive (+) and negative (-) polarity for each pixel PIX. Between lines (i.e., multiple pixels in the column direction), the polarity of the pixels is assumed to be the same.

[0051] Multiple gate lines (GateN, GateN+1, GateN+2, GateN+3) are arranged to extend along the first direction X and are also arranged to be adjacent to the second direction Y. The gate line GateN is connected to the 6 pixels of the first row and the 6 pixels of the second row. The gate line GateN+1 is connected to the 6 pixels of the third row and the 6 pixels of the fourth row. The gate line GateN+2 is connected to the 6 pixels of the fifth row and the 6 pixels of the sixth row. The gate line GateN+3 is connected to the 6 pixels of the seventh row and the 6 pixels of the eighth row.

[0052] Multiple gate drivers GD1-GD4 are provided to drive multiple gate lines (GateN, GateN+1, GateN+2, GateN+3). Gate driver GD1 drives gate line GateN, gate driver GD2 drives gate line GateN+1, gate driver GD3 drives gate line GateN+2, and gate driver GD4 drives gate line GateN+3. Note that the driving of the multiple gate drivers GD1-GD4 is the same as that of the display device 10r in Figure 1, so redundant explanations are omitted. Here, the first shift register S / R, the second shift register S / R, and the multiple gate drivers GD1-GD4 of the display device 10a can be rephrased as the first gate line driving circuit GDC1.

[0053] Multiple signal lines Sig (S11, S21, S31, S41, S51, S61, or S12, S22, S32, S42, S52, S62) are provided extending in the second direction Y. In this example, two signal lines (S11 and S12, S21 and S22, S31 and S32, S41 and S42, S51 and S52, S61 and S62) are arranged adjacent to each other and running parallel. Each of the signal lines S11, S21, S31, S41, S51, S61 is connected to the pixels in the 1st, 3rd, 5th, and 7th rows. Each of the signal lines S12, S22, S32, S42, S52, S62 is connected to the pixels in the 2nd, 4th, 6th, and 8th rows.

[0054] A multiplexer 110r is provided between multiple signal lines Sig and a source line driver 100. The multiplexer 110r is configured to include multiple first switches SW1 which are controlled to be on or off according to the level of a first selection signal MUX1, and multiple second switches SW2 which are controlled to be on or off according to the level of a second selection signal MUX2.

[0055] The source line driver IC 100 includes multiple source line terminals S1-S6 for supplying signals to multiple signal lines Sig. The multiplexer 110 and the source line driver IC 100 can be described as a signal line drive circuit that supplies grayscale signals to multiple signal lines.

[0056] The first source line terminal S1 is connected to signal line S11 via the first switch SW1, and also to signal line S12 via the second switch SW2. The second source line terminal S2 is connected to signal line S21 via the first switch SW1, and also to signal line S22 via the second switch SW2. The third source line terminal S3 is connected to signal line S31 via the first switch SW1, and also to signal line S32 via the second switch SW2. The fourth source line terminal S4 is connected to signal line S41 via the first switch SW1, and also to signal line S42 via the second switch SW2. The fifth source line terminal S5 is connected to signal line S51 via the first switch SW1, and also to signal line S52 via the second switch SW2. The sixth source line terminal S6 is connected to signal line S61 via the first switch SW1, and also to signal line S62 via the second switch SW2.

[0057] Next, we will explain an example of timing using Figure 5. We will describe the source signals supplied to source line terminals S1-S6 at each timing.

[0058] When the gate line GateN is set to a high level and the first selection signal MUX1 is set to a high level, gradation signals P11, P12, P13, P14, P15, and P16 are supplied from source line terminals S1-S6 to signal lines S11, S21, S31, S41, S51, and S61, and the corresponding gradation signals for the six pixels in the first row are written.

[0059] Next, when the gate line GateN is at a high level and the second selection signal MUX2 is at a high level, the grayscale signals P21, P22, P23, P24, P25, and P26 are supplied from the source line terminals S1-S6 to the signal lines S12, S22, S32, S42, S52, and S62, and the grayscale signals corresponding to the six pixels in the second row are written.

[0060] Next, when the gate line GateN+1 is set to a high level and the first selection signal MUX1 is set to a high level, the grayscale signals P31, P32, P33, P34, P35, and P36 are supplied from the source line terminals S1-S6 to the signal lines S11, S21, S31, S41, S51, and S61, and the grayscale signals corresponding to the six pixels in the third column are written.

[0061] Next, when the gate line GateN+1 is at a high level and the second selection signal MUX2 is at a high level, the grayscale signals P41, P42, P43, P44, P45, and P46 are supplied from the source line terminals S1-S6 to the signal lines S12, S22, S32, S42, S52, and S62, and the grayscale signals corresponding to the six pixels in the fourth column are written.

[0062] Next, when the gate line GateN+2 is set to a high level and the first selection signal MUX1 is set to a high level, the grayscale signals P51, P52, P53, P54, P55, and P56 are supplied from the source line terminals S1-S6 to the signal lines S11, S21, S31, S41, S51, and S61, and the grayscale signals corresponding to the six pixels in the fifth column are written.

[0063] Next, when the gate line GateN+2 is set to a high level and the second selection signal MUX2 is set to a high level, the grayscale signals P61, P62, P63, P64, P65, and P66 are supplied from the source line terminals S1-S6 to the signal lines S12, S22, S32, S42, S52, and S62, and the signals are written to the corresponding six pixels in the sixth column.

[0064] Next, when the gate line GateN+3 is set to a high level and the first selection signal MUX1 is set to a high level, the grayscale signals P71, P72, P73, P74, P75, and P76 are supplied from the source line terminals S1-S6 to the signal lines S11, S21, S31, S41, S51, and S61, and the grayscale signals corresponding to the six pixels in the corresponding seventh column are written.

[0065] Next, when the gate line GateN+3 is at a high level and the second selection signal MUX2 is at a high level, the grayscale signals P81, P82, P83, P84, P85, and P86 are supplied from the source line terminals S1-S6 to the signal lines S12, S22, S32, S42, S52, and S62, and the grayscale signals corresponding to the six pixels in the corresponding 8th column are written.

[0066] Next, we will explain the parasitic elements between the source terminal and signal lines of the display device using Figure 6. Figure 6 shows parasitic resistive elements and parasitic capacitive elements as parasitic elements between the source terminal (S1...) and the signal lines (Sig: S11, S21, S31, S41, S51, S61, S12, S22, S32, S42, S52, S62). As shown in Figure 6, the following parasitic elements exist between the source terminal S1 and the signal line Sig.

[0067] 1) Within the source wire driver 100, the parasitic resistance element Ric of the wiring connected to source terminal S1, 2) Parasitic resistance element Rv and parasitic capacitance element Cs based on the video cable and its routing between the wiring connected to source terminal S1 and the first switch SW1 and second switch SW2 in the multiplexer 110r. 3) The internal parasitic resistance element Rmux of the first switch SW1 and the second switch SW2 in the multiplexer 110, 4) The signal line Sig has a parasitic resistance element Rsig, a parasitic capacitance element Csig, and a crossover capacitance Csigc between the two signal lines. In other words, the crossover capacitance Csigc increases. The crossover capacitance Csigc occurs in the areas indicated by the dotted circles in Figure 4 (lines 3, 5, and 7).

[0068] Therefore, the display device 10a in Figure 4 can be considered as follows.

[0069] (1) The aperture ratio and optical characteristics are improved compared to the display device 10r in Figure 1, but there is an aperture ratio loss because two signal lines run in parallel. It is preferable to provide a black matrix layer for light shielding above the area AB where the multiple gate lines (GateN, GateN+1, GateN+2, GateN+3) are arranged in Figure 4. On the other hand, it is preferable to provide a black matrix layer for light in the areas AC between the 2nd and 3rd rows, AC between the 4th and 5th rows, and AC between the 6th and 7th rows, where no gate lines are arranged, considering the continuity of the pixels.

[0070] (2) The number of pixels can be increased to 1.5 times the number of pixels in the first direction X and twice the number of pixels in the second direction compared to the display device 10r in Figure 1.

[0071] (3) The time constant of the video line to the signal line Sig is not improved compared to the display device 10r in Figure 1, making it difficult to complete writing the signal to each pixel within the specified time.

[0072] (modified version) Next, a modified display device 10b of Example 1 will be described using Figure 7. Figure 7 is a diagram showing an example of the configuration of a modified display device. The difference between the display device 10b in Figure 7 and the display device 10a in Figure 4 is that two signal lines (S11 and S12, S21 and S22, S31 and S32, S41 and S42, S51 and S52, S61 and S62) are arranged to the left and right of the corresponding pixels in the corresponding columns along the second direction Y and connected to the corresponding pixels. This makes it possible to reduce the cross capacitance Csigc between the two signal lines. Here, the first shift register S / R, the second shift register S / R, and the multiple gate drivers GD1-GD4 of the display device 10b can be rephrased as the first gate line drive circuit GDC1. The other configurations of the display device 10b in Figure 7 are the same as those of the display device 10a in Figure 4, so redundant explanations will be omitted.

[0073] The display devices 10a and 10b of Example 1 can be summarized as follows.

[0074] Display devices 10a and 10b are, Multiple pixels (PIX: P11-P86) arranged in a matrix in the row direction (first direction X) and column direction (second direction Y), In a set of multiple pixels (PIX), each pixel arranged in a row is connected to a single gate line, with multiple gate lines (GateN-GateN+3) connected to the pixels arranged in the row. In a multi-pixel PIX, multiple signal lines (S11-S61, S12-S62) are connected to pixels arranged in the column direction, A gate line drive circuit GDC1 that scans the aforementioned multiple gate lines (GateN-GateN+3), A signal line drive circuit (100, 110) that supplies gradation signals to multiple signal lines (S11-S61, S12-S62), Includes.

[0075] The pixels arranged in the column direction include a plurality of first pixels (P11-P16, P31-P36, P51-P56, P71-P76) connected to the first signal line (S11-S61), and a plurality of second pixels (P21-P26, P41-P46, P61-P66, P81-P86) connected to the second signal line (S12-S62).

[0076] The first signal line (S11-S61) and the second signal line (S12-S62) are provided running parallel to the pixels arranged in the column direction.

[0077] Multiple first pixels (P11-P16, P31-P36, P51-P56, P71-P76) and multiple second pixels (P21-P26, P41-P46, P61-P66, P81-P86) are arranged alternately in the column direction.

[0078] In the display device 10a, the first signal lines (S11-S61) and the second signal lines (S12-S62) are arranged parallel to one side of the pixels that are arranged in the column direction.

[0079] In the display device 10b, the first signal line (S11-S61) and the second signal line (S12-S62) are arranged parallel to each other, flanking the pixels that are arranged in the column direction.

[0080] When the gate line drive circuit GDC1 selects one gate line, the signal line drive circuits (100, 110) write the corresponding gradation signals from the first signal lines (S11-S61) to multiple first pixels (P11-P16, P31-P36, P51-P56, P71-P76), and then write the corresponding gradation signals from the second signal lines (S12-S62) to multiple second pixels (P21-P26, P41-P46, P61-P66, P81-P86).

[0081] (Example 2) In Example 2, the first selection signal MUX1 and the second selection signal MUX2 described in Example 1 are assigned to the generation of gate signals, reducing the number of signal lines Sig and the number of multiplexers between the signal line Sig and the source line driver. This example describes the configuration of the display device 10c. Figure 8 is a diagram showing the configuration example of the display device according to Example 2. Figure 9 is a diagram showing an example of the timing of the display device in Figure 8. Figure 10 is a diagram illustrating the parasitic elements between the source terminal and the signal line of the display device in Figure 8.

[0082] The display device 10c shown in Figure 8 has a field sequential configuration, similar to that of Embodiment 1. The display device 10c has an active region AA, in which a plurality of pixels PIX are formed in a matrix along a first direction X and a second direction Y that intersects the first direction X. Each pixel PIX is driven by a driving method in which one frame period has a plurality of subframe (field) periods.

[0083] In this example, a typical representation is shown of multiple pixels (PIX) arranged in a 6x8 matrix, specifically 6 pixels in the first direction X (horizontal, row direction) and 8 pixels in the second direction Y (vertical, column direction), for a total of 48 pixels. Typical configurations of pixels (PIX) and the field sequential method have been explained in Figure 4, so redundant explanations will be omitted.

[0084] Multiple gate lines (GateNa, GateNb, GateN+1a, GateN+1b, GateN+2a, GateN+2b, GateN+3a, GateN+3b) are arranged to extend along the first direction X and are also arranged to run alongside the second direction Y.

[0085] The gate line GateNa is connected to the 6 pixels of the 1st row. The gate line GateNb is connected to the 6 pixels of the 2nd row. The gate line GateN+1a is connected to the 6 pixels of the 3rd row. The gate line GateN+1b is connected to the 6 pixels of the 4th row. The gate line GateN+2a is connected to the 6 pixels of the 5th row. The gate line GateN+2b is connected to the 6 pixels of the 6th row. The gate line GateN+3a is connected to the 6 pixels of the 7th row. The gate line GateN+3b is connected to the 6 pixels of the 8th row.

[0086] The final stage gate drive circuits DR1-DR8 are provided to drive multiple gate lines (GateNa, GateNb, GateN+1a, GateN+1b, GateN+2a, GateN+2b, GateN+3a, GateN+3b). Gate drive circuit DR1 drives gate line GateNa, and gate drive circuit DR2 drives gate line GateNb. Gate drive circuit DR3 drives GateN+1a, and gate drive circuit DR4 drives GateN+1b. Gate drive circuit DR5 drives gate line GateN+2a, and gate drive circuit DR6 drives gate line GateN+2b. Gate drive circuit DR7 drives gate line GateN+3a, and gate drive circuit DR8 drives gate line GateN+3b.

[0087] The first selection signal MUX1 is supplied to the second inputs of gate drive circuits DR1, DR3, DR5, and DR7, and the second selection signal MUX2 is supplied to the second inputs of gate drive circuits DR2, DR4, DR6, and DR8. Here, the first selection signal MUX1 is set to a selection level (high level) when selecting one of two adjacent gate lines (GateNa, GateN+1a, GateN+2a, GateN+3a). The second selection signal MUX2 is set to a selection level (high level) when selecting the other of two adjacent gate lines (GateNb, GateN+1b, GateN+2b, GateN+3b). Two adjacent gate lines can be, for example, (GateNa and GateNb), (GateN+1a and GateN+1b), (GateN+2a and GateN+2b), and (GateN+3a and GateN+3b).

[0088] The circuit preceding the final stage gate drive circuits DR1-DR8 (two shift registers S / R, gate drivers GD1-GD4, and each control signal (STV, CKV, TRNm, TRNm+1, EN1, EN2)) has the same circuit configuration as the display device 10a in Embodiment 1. A redundant explanation of the part of the circuit configuration that is the same as the display device 10a in Embodiment 1 will be omitted. The first shift register S / R, the second shift register S / R, the multiple gate drivers GD1-GD4, and the gate drive circuits DR1-DR8 of the display device 10c can be rephrased as the second gate line drive circuit GDC2.

[0089] Here, the outputs of gate drivers GD1-GD4 are configured to be connected to the first inputs of the final stage gate drive circuits DR1-DR8. In other words, the output of gate driver GD1 is connected to the first inputs of gate drive circuits DR1 and DR2. The output of gate driver GD2 is connected to the first inputs of gate drive circuits DR3 and DR4. The output of gate driver GD3 is connected to the first inputs of gate drive circuits DR5 and DR6. The output of gate driver GD4 is connected to the first inputs of gate drive circuits DR7 and DR8. Gate drivers GD1-GD4 can be rephrased as gate driver selection circuits GD1-GD4.

[0090] The signal lines Sig(Sg1-Sg6) are arranged to extend along the second direction Y and are aligned with the first direction X. The first signal line Sg1 is connected to the 8 pixels of the first column. The second signal line Sg2 is connected to the 8 pixels of the second column. The third signal line Sg3 is connected to the 8 pixels of the third column. The fourth signal line Sg4 is connected to the 8 pixels of the fourth column. The fifth signal line Sg5 is connected to the 8 pixels of the fifth column. The sixth signal line Sg6 is connected to the 8 pixels of the sixth column.

[0091] The source line driver IC 100 includes multiple source line terminals S1-S6 for supplying signals to multiple signal lines Sig (Sg1-Sg6). Source line terminal S1 is connected to signal line Sg1. Source line terminal S2 is connected to signal line Sg2. Source line terminal S3 is connected to signal line Sg3. Source line terminal S4 is connected to signal line Sg4. Source line terminal S5 is connected to signal line Sg5. Source line terminal S6 is connected to signal line Sg6. The source line driver IC 100 can be described as a signal line drive circuit that supplies grayscale signals to multiple signal lines.

[0092] Next, the timing of the display device 10c will be explained using Figure 9. The transfer clock CKV, the first transfer signal TRNm, the second transfer signal TRNm+1, the first enable signal EN1, and the second enable signal EN2 are the same as in Example 1. Below, we will mainly explain the gate lines (GateNa, GateNb, GateN+1a, GateN+1b, GateN+2a, GateN+2b, GateN+3a, GateN+3b), the first selection signal MUX1, the second selection signal MUX2, and the multiple source line terminals S1-S6.

[0093] When the first transfer signal TRNm is set to a high level, the first enable signal EN1 is set to a high level, and the first selection signal MUX1 is set to a high level, the gate line GateNa is set to a high level. At this point, grayscale signals P11, P12, P13, P14, P15, and P16 are supplied from source line terminals S1-S6 to signal lines Sg1, Sg2, Sg3, Sg4, Sg5, and Sg6, and the grayscale signals corresponding to the six pixels in the first row are written.

[0094] Next, when the first transfer signal TRNm is at a high level and the first enable signal EN1 is at a high level, the second selection signal MUX2 is set to a high level, and the gate line GateNb is set to a high level. At this point, grayscale signals P21, P22, P23, P24, P25, and P26 are supplied from source line terminals S1-S6 to signal lines Sg1, Sg2, Sg3, Sg4, Sg5, and Sg6, and the grayscale signals corresponding to the six pixels of the second row are written.

[0095] Next, when the first transfer signal TRNm is at a high level, the second enable signal EN2 is set to a high level, and the first selection signal MUX1 is also set to a high level, then the gate line GateN+1a is set to a high level. At this point, grayscale signals P31, P32, P33, P34, P35, and P36 are supplied from source line terminals S1-S6 to signal lines Sg1, Sg2, Sg3, Sg4, Sg5, and Sg6, and the grayscale signals corresponding to the six pixels in the third column are written.

[0096] Next, when the first transfer signal TRNm is at a high level and the second enable signal EN2 is at a high level, the second selection signal MUX2 is set to a high level, and the gate line GateN+1b is set to a high level. At this point, grayscale signals P41, P42, P43, P44, P45, and P46 are supplied from source line terminals S1-S6 to signal lines Sg1, Sg2, Sg3, Sg4, Sg5, and Sg6, and the grayscale signals corresponding to the six pixels in the corresponding fourth column are written.

[0097] Next, when the second transfer signal TRNm+1 is set to high level, the first enable signal EN1 is set to high level, and the first selection signal MUX1 is set to high level, the gate line GateN+2a is set to high level. At this point, grayscale signals P51, P52, P53, P54, P55, and P56 are supplied from source line terminals S1-S6 to signal lines Sg1, Sg2, Sg3, Sg4, Sg5, and Sg6, and the grayscale signals corresponding to the six pixels in the corresponding fifth column are written.

[0098] Next, when the second transfer signal TRNm+1 is at a high level and the first enable signal EN1 is at a high level, the second selection signal MUX2 is set to a high level, and the gate line GateN+2b is set to a high level. At this point, grayscale signals P61, P62, P63, P64, P65, and P66 are supplied from source line terminals S1-S6 to signal lines Sg1, Sg2, Sg3, Sg4, Sg5, and Sg6, and the grayscale signals corresponding to the six pixels in the corresponding sixth column are written.

[0099] Next, when the second transfer signal TRNm+1 is at a high level, the second enable signal EN2 is set to a high level, and the first selection signal MUX1 is also set to a high level, then the gate line GateN+3a is set to a high level. At this point, the grayscale signals P71, P72, P73, P74, P75, and P76 are supplied from the source line terminals S1-S6 to the signal lines Sg1, Sg2, Sg3, Sg4, Sg5, and Sg6, and the grayscale signals corresponding to the six pixels in the corresponding seventh column are written.

[0100] Next, when the second transfer signal TRNm+1 is at a high level and the second enable signal EN2 is at a high level, the second selection signal MUX2 is set to a high level, and the gate line GateN+3b is set to a high level. At this point, grayscale signals P81, P82, P83, P84, P85, and P86 are supplied from source line terminals S1-S6 to signal lines Sg1, Sg2, Sg3, Sg4, Sg5, and Sg6, and the grayscale signals corresponding to the six pixels in the corresponding 8th column are written.

[0101] Next, we will explain the parasitic elements between the source terminal and signal lines of the display device using Figure 10. Figure 10 shows parasitic resistive elements and parasitic capacitive elements as parasitic elements between the source terminal (S1...) and the signal lines (Sig: Sg1, Sg2, Sg3, Sg4, Sg5, Sg6). As shown in Figure 10, the following parasitic elements exist between the source terminal S1 and the signal line Sig.

[0102] 1) Within the source wire driver 100, the parasitic resistance element Ric of the wiring connected to source terminal S1, 2) Parasitic resistance element Rv and parasitic capacitance element Cs based on the video line and its routing. 3) The signal line Sig has parasitic resistance elements Rsig and parasitic capacitance elements Csig.

[0103] Since a multiplexer 110 is not provided between the source terminal S1 and the signal line Sig, the parasitic resistance and capacitance elements of the multiplexer 110 are reduced.

[0104] Therefore, the display device 10c in Figure 8 can be considered as follows:

[0105] (1) The aperture ratio and optical characteristics are improved compared to the display devices 10a and 10b because one signal line and one gate line are provided for each pixel. It is preferable to provide a black matrix layer for light shielding above the arrangement of multiple gate lines (GateNa, GateNb, GateN+1a, GateN+1b, GateN+2a, GateN+2b, GateN+3a, GateN+3b) in Figure 7.

[0106] (2) The number of pixels is the same as that of the display devices 10a and 10b, and compared to the display device 10r in Figure 1, the number of pixels can be increased by 1.5 times in the first direction X and by 2 times in the second direction.

[0107] (3) The time constant of the video line to the signal line Sig has been improved compared to the display devices 10a and 10b, so that the writing of the signal to each pixel can be completed within a specified time.

[0108] Note that while Figures 8 and 9 illustrate the use of two signals, the first enable signal EN1 and the second enable signal EN2, as examples, the configuration is not limited to these. For example, the period of the transfer clock CKV can be twice that of Figure 9, and the enable signals can be composed of four signals. Alternatively, the period of the transfer clock CKV can be half that of Figure 9, and a configuration without enable signals can be adopted.

[0109] The display device 10c of Example 2 can be summarized as follows.

[0110] The display device 10c is Multiple pixels (PIX: P11-P86) arranged in a matrix in the row direction (first direction X) and column direction (second direction Y), In a set of multiple pixels (PIX), each pixel arranged in a row is connected to a single gate line, with multiple gate lines (GateNa, GateNb-GateN+3a, GateN+3b) connected to pixels arranged in a row. In a multi-pixel PIX, each pixel arranged in a single column is connected to a single signal line, with multiple signal lines (Sg1-Sg6) connected to the pixels arranged in the column direction. A gate line drive circuit GDC2 that scans multiple gate lines (GateNa, GateNb-GateN+3a, GateN+3b), It includes a signal line driving circuit that supplies grayscale signals to multiple signal lines (Sg1-Sg6).

[0111] The gate line drive circuit GDC2 includes a first selection signal MUX1 that selects one of two adjacent gate lines ((GateNa and GateNb), (GateN+1a and GateN+1b), (GateN+2a and GateN+2b), (GateN+3a and GateN+3b)) (GateNa, GateN+1a, GateN+2a, GateN+3a), and a second selection signal MUX2 that selects the other of two adjacent gate lines (GateNb, GateN+1b, GateN+2b, GateN+3b).

[0112] Next, we will explain an example configuration of the gate driver selection circuit (GD1-GD4) and gate drive circuit (DR1-DR8) using Figure 11. Figure 11 is a diagram illustrating an example configuration of the gate driver selection circuit and gate drive circuit. Figure 12 is a diagram illustrating an example of the timing of the gate driver selection circuit and gate drive circuit.

[0113] As shown in Figure 11, the gate driver selection circuit GDn includes an inverter circuit IV1 and transistors Q1, Q2, and Q3. The input terminal of the inverter circuit IV1 is connected to the output terminal of the shift register S / R and is configured to receive the transfer signal TRN from the shift register S / R. The output terminal of the inverter circuit IV1 is connected to the gate electrode of the P-channel (first conductivity type) transistor Q1 and is configured to receive the inverted signal XTRN of the transfer signal TRN from the inverter circuit IV1.

[0114] The source electrode of transistor Q1 is configured to receive the enable signal EN1 (or EN2), and the drain electrode of transistor Q1 is connected to the drain electrode of N-channel (second conductivity type) transistor Q3. The gate electrode of transistor Q3 is connected to the gate electrode of transistor Q1, and the source electrode of transistor Q3 is connected to the ground potential line VGL to which the ground potential is supplied. Transistors Q1 and Q3 constitute an inverter circuit. In addition, the source-drain path of N-channel (second conductivity type) transistor Q2 is provided in parallel with the source-drain path of transistor Q1, forming a CMOS switch configuration. The gate electrode of transistor Q2 is connected to the input terminal of inverter circuit IV1.

[0115] The gate drive circuit DRi includes the inverter circuit IV2 and transistors Q4, Q5, and Q6. The input terminal of the inverter circuit IV2 is connected to the drain electrode of transistor Q1 and is configured to receive the signal TRNe. The output terminal of the inverter circuit IV2 is connected to the gate electrode of the P-channel (first conductivity type) transistor Q4 and is configured to receive the inverted signal XTRNe of the signal TRNe from the inverter circuit IV2.

[0116] The source electrode of transistor Q4 is configured to receive the selection signal MUX1 (or MUX2), and the drain electrode of transistor Q4 is connected to the drain electrode of N-channel (second conductivity type) transistor Q6. The gate electrode of transistor Q6 is connected to the gate electrode of transistor Q4, and the source electrode of transistor Q6 is connected to the ground potential line VGL, which supplies the ground potential. Transistors Q4 and Q6 constitute an inverter circuit. In addition, the source-drain path of N-channel (second conductivity type) transistor Q5 is provided in parallel with the source-drain path of transistor Q4, forming a CMOS switch configuration. The gate electrode of transistor Q5 is connected to the input terminal of inverter circuit IV2. The drain electrode of transistor Q4 is connected to the gate line (GateN).

[0117] As shown in Figure 12, the gate driver selection circuit GDn and the gate drive circuit DRi selectively set the gate line GateN to a high level (selection level) when a high-level transfer signal TRN is supplied from the shift register S / R, the enable signal EN1 is set to a high level, and the selection signal MUX1 is set to a high level.

[0118] As shown in Figure 11, the gate driver selection circuit GDn and the gate drive circuit DRi, as explained above, connect all signals (EN1, EN2, MUX1, MUX2) to the source, thus reducing the load capacitance compared to gate connections. Logically, gate connections are also possible for the signals (EN1, EN2, MUX1, MUX2). Furthermore, although the above describes all single-gate transistors, double-gate transistors can also be used.

[0119] Next, we will describe examples of connections between the display devices (10a, 10b, 10c) and the flexible printed circuit board (FPC). Figure 13 shows an example of connections between the display devices (10a, 10b) and the flexible printed circuit board (FPC). Figure 14 shows an example of connections between the display device (10c) and the flexible printed circuit board (FPC). Figure 15 shows an example of the configuration of the intersection of the selection signal wiring MUXL and the common potential wiring COML in Figure 14.

[0120] Figure 13 illustrates a display device (10a, 10b) having a flexible printed circuit board (FPC). The display device (10a, 10b) has a display panel (DISP) and a source line driver (Driver IC) 100. The display panel (DISP) includes an active area AA, a multiplexer 110, and gate line drive circuits GDC1 arranged to the left and right of the active area AA.

[0121] The active region AA is formed by multiple pixels (PIX), multiple gate lines (GateN, GateN+1, GateN+2, GateN+3), and multiple signal lines (Sig). Common potential wiring COML (shown as a thin dotted line in Figure 13), to which the common potential VCOM is supplied, is connected to the multiple pixels (PIX). Common potential wiring COML is connected to a portion of the multiple pads FPCPAD provided on the flexible printed circuit board (FPC) via source line driver 100.

[0122] The multiplexer 110 includes a plurality of first switches SW1 supplied with a first selection signal MUX1, and a plurality of second switches SW2 supplied with a second selection signal MUX2. The first selection signal MUX1 and the second selection signal MUX2 are supplied to the multiplexer 110 from the source line driver 100 via first signal wiring MUXL (shown as a thin solid line in Figure 13) formed on a flexible printed circuit board (FPC). The first signal wiring MUXL can be rephrased as selection signal wiring MUXL, which includes selection signal wiring for the first selection signal MUX1 and selection signal wiring for the second selection signal MUX2.

[0123] The gate line drive circuit GDC1 includes the first shift register S / R and second shift register S / R of the display device (10a, 10b), and a plurality of gate drivers GD1-GD4. Control signals (STV, CKV, EN1, EN2) supplied from the source line driver 100 are supplied to the gate line drive circuit GDC1 via the second signal wiring CTSL (shown as a thin dashed line in Figure 13) formed on the flexible printed circuit board FPC.

[0124] Although there may be cases where this differs depending on the signal pin arrangement specifications of the source line driver 100, basically the first signal line MUXL and the common potential line COML are connected to each part of the display panel DISP without crossing. Therefore, the first signal line MUXL and the common potential line COML can always be wired using low-resistance material (for example, the source layer where the signal line Sig is formed), thus reducing the resistance value.

[0125] When placing the test pad TPAD, the first signal wiring MUXL and the common potential wiring COML will cross over the connection wiring to the test pad TPAD (thick dashed line), but the first signal wiring MUXL and the common potential wiring COML will not cross, so this will not cause any problems.

[0126] At the point where the first signal wiring MUXL and the common potential wiring COML intersect with the connection wiring (thick dashed line) to the test pad TPAD, the connection wiring can be made into a Gate layer with multiple gate lines.

[0127] Figure 14 illustrates the state in which the display device 10c has a flexible printed circuit board (FPC). The display device 10c has a display panel (DISP) and a source line driver (Driver IC) 100. The display panel (DISP) includes an active area (AA) and gate line drive circuits (GDC2) arranged to divide the active area (AA) into left and right sides. The gate line drive circuits (GDC2) include a first shift register (S / R), a second shift register (S / R), a plurality of gate drivers (GD1-GD4), and gate drive circuits (DR1-DR8) of the display device 10c.

[0128] The differences between Figure 14 and Figure 13 are that the multiplexer 110 has been removed, the first signal wiring MUXL is supplied to the gate line drive circuit GDC2, and the first signal wiring MUXL and the common potential wiring COML intersect (cross) at the intersection RR shown by the thick circle.

[0129] Therefore, it is necessary to devise a wiring method at the intersection RR between the first signal wiring MUXL and the common potential wiring COML. In other words, since the first signal wiring MUXL and the common potential wiring COML cross at least once, it is necessary to reconnect either the first signal wiring MUXL or the common potential wiring COML to a wiring layer on a different layer (Gate layer) than the wiring layer of the Source layer.

[0130] Figure 15 shows three examples of the configuration of the intersection of the first signal wiring MUXL and the common potential wiring COML in Figure 14. It is assumed that the first signal wiring MUXL extends along the first direction X and is mainly formed by the source layer wiring. The common potential wiring COML extends along the second direction Y and is mainly formed by the source layer wiring.

[0131] The first configuration example 151 is a case in which the first signal wiring MUXL is made of wiring formed from a low-resistance material (for example, the wiring layer of the source layer in which the signal line Sig is formed) to reduce the resistance value. This configuration is a wiring structure that prioritizes the first signal wiring MUXL. At the intersection of the first signal wiring MUXL and the common potential wiring COML, the common potential wiring COML is formed in the third direction Z below the first signal wiring MUXL using a short-distance and wide gate layer wiring, thereby intersecting the first signal wiring MUXL.

[0132] The second configuration example 152 is a case in which the common potential wiring COML is made of wiring formed from a low-resistance material (for example, the wiring layer of the source layer where the signal line Sig is formed) to reduce the resistance value. This configuration is a wiring structure that prioritizes the common potential wiring COML. At the intersection of the first signal wiring MUXL and the common potential wiring COML, the first signal wiring MUXL is formed in the third direction Z below the common potential wiring COML using a long-distance and narrow gate layer wiring layer, thereby intersecting the common potential wiring COML.

[0133] In other words, in the first configuration example 151 and the second configuration example 152, the portion where the common potential wiring COML and the selection signal wiring MUXL intersect is such that one of the common potential wiring COML and the selection signal wiring MUXL is formed on a different wiring layer than the other.

[0134] The third configuration example 153 is a modification of the second configuration example 152, in which the length of the first signal wiring MUXL, formed by the gate layer wiring layer routed below the common potential wiring COML, is shortened as much as possible to reduce the increase in the wiring resistance of the first signal wiring MUXL. On the other hand, the width of the common potential wiring COML located above the first signal wiring MUXL, formed by the gate layer wiring layer, is locally shortened to reduce the increase in the wiring resistance of the common potential wiring COML.

[0135] All display devices that a person skilled in the art can implement by appropriately modifying the design based on the display devices described above as embodiments of this disclosure also fall within the scope of this disclosure, insofar as they encompass the gist of this disclosure.

[0136] Within the scope of the ideas presented hereto, a person skilled in the art will be able to conceive of various modifications and alterations, and such modifications and alterations will also be understood to fall within the scope of this disclosure. For example, any addition, deletion, or design change of components, or addition, omission, or modification of processes, made by a person skilled in the art to the above-described embodiments, will also fall within the scope of this disclosure, as long as they retain the essence of this disclosure.

[0137] Furthermore, any other effects and advantages brought about by the embodiments described herein that are obvious from this specification or that can be appropriately conceived by those skilled in the art are naturally considered to be brought about by the present invention.

[0138] Various inventions can be formed by appropriately combining the multiple components disclosed in the above embodiments. For example, some components may be removed from all the components shown in the embodiments. Furthermore, components from different embodiments may be appropriately combined. [Explanation of Symbols]

[0139] 10a, 10b, 10c: Display device PIX, P11-P86: Pixels GateN-GateN+3, GateNa-GateN+3a, GateNb-GateN+3b: Gate lines (scan lines) S11-S61, S12-S62, Sg1-Sg6: Signal lines (source lines) GDC1, GDC2: Gate wire drive circuits 100: Source wire driver 110: Multiplexer

Claims

1. Multiple pixels arranged in a matrix, Multiple gate lines connected to pixels arranged in the row direction, Multiple signal lines connected to pixels arranged in a column, A gate line driving circuit that scans the plurality of gate lines, A signal line drive circuit that supplies grayscale signals to the plurality of signal lines, Includes, The pixels arranged in the column direction include a plurality of first pixels connected to a first signal line and a plurality of second pixels connected to a second signal line. The first signal line and the second signal line are provided running parallel to the pixels arranged in the column direction, Display device.

2. In the display device according to claim 1, A display device in which, when the gate line drive circuit selects one gate line, the signal line drive circuit writes a corresponding grayscale signal from the first signal line to the plurality of first pixels, and then writes a corresponding grayscale signal from the second signal line to the plurality of second pixels.

3. In the display device according to claim 1, A display device in which the plurality of first pixels and the plurality of second pixels are arranged alternately in the column direction.

4. In the display device according to claim 2, The first signal line and the second signal line are arranged parallel to one side of the pixels arranged in the column direction in a display device.

5. In the display device according to claim 2, The first signal line and the second signal line are arranged in parallel so as to sandwich the pixels arranged in the column direction, in a display device.

6. In the display device according to claim 1, A display device in which the plurality of pixels are driven by the gate line drive circuit and the signal line drive circuit based on a field sequential method.

7. Multiple pixels arranged in a matrix, Multiple gate lines connected to pixels arranged in the row direction, Multiple signal lines connected to pixels arranged in a column, A gate line driving circuit that scans the plurality of gate lines, The circuit includes a signal line drive circuit that supplies grayscale signals to the plurality of signal lines, The gate line drive circuit includes a first selection signal that selects one of two adjacent gate lines, and a second selection signal that selects the other of two adjacent gate lines. Display device.

8. In the display device according to claim 7, A common potential wiring that supplies a common potential to the plurality of pixels, Includes a selection signal wiring that supplies the first selection signal and the second selection signal from the signal line drive circuit to the signal line drive circuit, A display device in which the common potential wiring and the selection signal wiring intersect at a portion where one of the common potential wiring and the selection signal wiring is formed by a different wiring layer than the other of the common potential wiring and the selection signal wiring.

9. In the display device according to claim 7, A display device in which the plurality of pixels are driven by the gate line drive circuit and the signal line drive circuit based on a field sequential method.

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