Semiconductor equipment

Abstract

This suppresses the deterioration of the voltage resistance characteristics of semiconductor devices. [Solution] The semiconductor device of the embodiment includes a first wiring and a second wiring adjacent to each other in a first direction within a first plane, wherein the first wiring includes a first extended portion 12-1B extending in a second direction intersecting the first direction within the first plane, and a first plug portion 12-1A extending in a third direction intersecting the first plane and in contact with the first extended portion on one side of the third direction, wherein the second wiring is included in the same layer as the first extended portion and includes a second extended portion 12-2B extending in the second direction, and a first connecting portion 12-2A adjacent to the first plug portion in the first direction and in contact with the second extended portion in the second direction, wherein the first position of the first connecting portion on the other side of the third direction is different from the second position of the second extended portion on the other side of the third direction.

Description

Technical Field

[0004] , , , , , , , , , , ,

[0005] ,

[0001] Embodiments relate to semiconductor devices.

Background Art

[0002] Semiconductor devices including wirings formed using techniques such as single damascene technology and dual damascene technology are known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Summary of the Invention

Problems to be Solved by the Invention

[0004] Suppress a decrease in the breakdown voltage characteristics of a semiconductor device.

Means for Solving the Problems

[0005] The semiconductor device of the embodiment includes a first wiring and a second wiring adjacent to each other in a first direction within a first plane, wherein the first wiring includes a first extended portion extending in a second direction intersecting the first direction within the first plane, and a first plug portion extending in a third direction intersecting the first plane and in contact with the first extended portion on one side of the third direction, wherein the second wiring is included in the same layer as the first extended portion and includes a second extended portion extending in the second direction, and a first connecting portion adjacent to the first plug portion in the first direction and in contact with the second extended portion in the second direction, wherein the first position of the first connecting portion on the other side of the third direction is different from the second position of the second extended portion on the other side of the third direction. [Brief explanation of the drawing]

[0006] [Figure 1] A cross-sectional view showing an example of a part of the semiconductor device according to the first embodiment. [Figure 2] A cross-sectional view showing an example of a part of the semiconductor device according to the first embodiment. [Figure 3] A cross-sectional view along line III-III in Figure 2, showing an example of a part of the semiconductor device according to the first embodiment. [Figure 4] A cross-sectional view along line IV-IV in Figure 2, showing an example of a part of the semiconductor device according to the first embodiment. [Figure 5] A cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 6] A top view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 7] A cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 8] A cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 9] A cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 10] A cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 11]Top view for explaining an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 12] Cross-sectional view for explaining an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 13] Cross-sectional view for explaining an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 14] Cross-sectional view for explaining an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 15] Cross-sectional view showing an example of a part of a semiconductor device according to the first modification of the first embodiment. [Figure 16] Cross-sectional view for explaining an example of a method for manufacturing a semiconductor device according to the first modification of the first embodiment. [Figure 17] Cross-sectional view showing an example of a part of a semiconductor device according to the second modification of the first embodiment. [Figure 18] Cross-sectional view showing an example of a part of a semiconductor device according to the third modification of the first embodiment. [Figure 19] Cross-sectional view showing an example of a part of a semiconductor device according to the third modification of the first embodiment. [Figure 20] Cross-sectional view for explaining an example of a method for manufacturing a semiconductor device according to the third modification of the first embodiment. [Figure 21] Cross-sectional view for explaining an example of a method for manufacturing a semiconductor device according to the third modification of the first embodiment. [Figure 22] Cross-sectional view showing an example of a part of a semiconductor device according to the fourth modification of the first embodiment. [Figure 23] Cross-sectional view for explaining an example of a method for manufacturing a semiconductor device according to the fourth modification of the first embodiment. [Figure 24] Cross-sectional view for explaining an example of a method for manufacturing a semiconductor device according to the fourth modification of the first embodiment. [Figure 25] Cross-sectional view showing an example of a part of a semiconductor device according to the fifth modification of the first embodiment. [Figure 26] Cross-sectional view showing an example of a part of a semiconductor device according to the fifth modification of the first embodiment. [Figure 27]A cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to a fifth modified example of the first embodiment. [Figure 28] A cross-sectional view showing an example of a portion of a semiconductor device according to a sixth modified example of the first embodiment. [Figure 29] A cross-sectional view showing an example of a part of a semiconductor device according to the second embodiment. [Figure 30] A cross-sectional view showing an example of a part of a semiconductor device according to the second embodiment. [Figure 31] A cross-sectional view along the line XXXI-XXXI in Figure 30, showing an example of a part of the semiconductor device according to the second embodiment. [Figure 32] A cross-sectional view along the line XXXII-XXXII in Figure 30, showing an example of a part of the semiconductor device according to the second embodiment. [Figure 33] A cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 34] A top view illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 35] A cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 36] A cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 37] A cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment. [Modes for carrying out the invention]

[0007] Embodiments will be described below with reference to the drawings. Note that the dimensions and proportions in the drawings are not necessarily the same as those of reality. In the following description, components having substantially the same function and configuration will be denoted by the same reference numeral. Furthermore, when elements with similar configurations are to be specifically distinguished, different letters or numbers may be added to the end of the same reference numeral.

[0008] 1. First Embodiment The semiconductor device according to the first embodiment will be described below.

[0009] In the following description, the X direction is approximately parallel to the substrate of the semiconductor device. The Y direction is approximately parallel to the substrate and perpendicular to the X direction. The Z direction is approximately perpendicular to the substrate.

[0010] 1.1 Configuration The configuration of the semiconductor device according to the first embodiment will be described below. The configuration of the parts included in the semiconductor device will be described below.

[0011] Figure 1 is a cross-sectional view showing an example of a portion of a semiconductor device according to the first embodiment. Figure 1 shows the configuration of a portion of the semiconductor device 1 in a YZ cross-section.

[0012] The semiconductor device 1 includes conductive layers 11, 12-1, 12-2, and 12-3, and an insulating layer 20. The conductive layers 11, 12-1, 12-2, and 12-3 function as wiring that is electrically connected to a circuit provided on a substrate (not shown), for example.

[0013] The conductive layer 11 is provided, for example, above a substrate (not shown). The conductive layer 11 is electrically connected to a circuit provided on the substrate.

[0014] A conductive layer 12-1 is provided on the upper surface of the conductive layer 11. As will be described later, the conductive layer 12-1 includes portions 12-1A, 12-1B, and 12-1C. As shown in Figure 1, the conductive layer 12-1 is provided such that the lower surface of portion 12-1A is in contact with the upper surface of the conductive layer 11. Portion 12-1A extends in the Z direction. Portion 12-1A has a width W1 in the Y direction at its upper end. Portion 12-1A functions as a via or plug that is electrically connected to the conductive layer 11.

[0015] Conductive layers 12-2 and 12-3 are each provided adjacent to conductive layer 12-1 in the Y direction, for example. Conductive layers 12-2 and 12-3 are provided so as to sandwich conductive layer 12-1 in the Y direction. As will be described later, conductive layer 12-2 includes portions 12-2A, 12-2B, and 12-2C. Conductive layer 12-3 also includes portions 12-3A, 12-3B, and 12-3C. In the cross-section shown in Figure 1, portions 12-2A and 12-3A are included. The width W2 in the Y direction at the upper end of portions 12-2A and 12-3A is smaller than the width W1 of portion 12-1A (W1 > W2). In the Z direction, the lower surfaces of portions 12-2A and 12-3A are located above the lower surface of portion 12-1A, for example.

[0016] The conductive layers 11, 12-1, 12-2, and 12-3 are contained within the insulating layer 20. The upper surfaces of conductive layer 12-1, conductive layer 12-2, and conductive layer 12-3 are, for example, provided to be flush with the upper surface of the insulating layer 20.

[0017] The configuration of the semiconductor device 1 in an XY cross-section including the upper surfaces of the conductive layers 12-1, 12-2, and 12-3 will be explained with reference to Figure 2. Figure 2 is a cross-sectional view showing an example of a portion of the semiconductor device according to the first embodiment. Figure 2 shows the configuration of a portion of the semiconductor device 1 in an XY cross-section at a position equivalent to the upper surfaces of the conductive layers 12-1 to 12-3.

[0018] In the conductive layer 12-1, portions 12-1B, 12-1A, and 12-1C are arranged in this order in the X direction. Portions 12-1B and 12-1C each extend in the X direction. Portions 12-1B and 12-1C are, for example, contained substantially on the same line. Portion 12-1A has, for example, a substantially circular shape when viewed from above. Portion 12-1A is in contact with portion 12-1B on one side in the X direction. Also, portion 12-1A is in contact with portion 12-1C on the other side in the X direction. Furthermore, the width W1 of portion 12-1A is, for example, wider than the width of portion 12-1B in the Y direction and the width of portion 12-1C in the Y direction.

[0019] In the conductive layer 12-2, portions 12-2B, 12-2A, and 12-2C are arranged in this order in the X direction. Portions 12-2B and 12-2C each extend in the X direction. Portions 12-2B and 12-2C are, for example, contained within a substantially collinear plane. Portion 12-2A has a substantially elliptical shape, for example, with the X direction as its major axis when viewed from above. Portion 12-2A is in contact with portion 12-2B on one side in the X direction. Portion 12-2A is also in contact with portion 12-2C on the other side in the X direction. When viewed from above, the conductive layer 12-2 has a stepped shape at the point where portions 12-2A and 12-2B are connected, for example, due to the shapes of these portions. Furthermore, the conductive layer 12-2, when viewed from above, has a stepped shape at the point where it is connected, for example, due to the shapes of portions 12-2A and 12-2C. Figure 2 illustrates the steps ST1 and ST2 on one and the other side in the Y direction at the point where portions 12-2A and 12-2B are connected, and the steps ST3 and ST4 on one and the other side in the Y direction at the point where portions 12-2A and 12-2C are connected.

[0020] In the conductive layer 12-3, portions 12-3B, 12-3A, and 12-3C are arranged in this order in the X direction. Portions 12-3A, 12-3B, and 12-3C correspond to portions 12-2A, 12-2B, and 12-2C, respectively. The structure of conductive layer 12-3 is substantially equivalent to the structure of conductive layer 12-2.

[0021] In the configuration described above, sections 12-1A and 12-2A, and sections 12-1A and 12-3A are arranged to be adjacent to each other in the Y direction. Furthermore, sections 12-2A and 12-3A are provided so as to overlap each other with section 12-1A in the Y direction.

[0022] The Y-center of section 12-1A and the Y-centers of sections 12-1B and 12-1C may be offset in the Y direction or aligned in the Y direction. Figure 2 shows an example where the Y-center of section 12-1A is offset in the Y direction relative to the Y-centers of sections 12-1B and 12-1C. Viewed from above, the arrangement of sections 12-2A, 12-2B, and 12-2C, and the arrangement of sections 12-3A, 12-3B, and 12-3C, are similar to, for example, the arrangement of sections 12-1A, 12-1B, and 12-1C. In other words, if the center of section 12-1A in the Y direction is offset to one or the other side in the Y direction relative to the centers of sections 12-1B and 12-1C in the Y direction, then the center of section 12-2A in the Y direction will be offset to one or the other side in the Y direction relative to the centers of sections 12-2B and 12-2C in the Y direction. Also in this case, the center of section 12-3A in the Y direction will be offset to one or the other side in the Y direction relative to the centers of sections 12-3B and 12-3C in the Y direction. If the center of section 12-1A in the Y direction is aligned with the centers of sections 12-1B and 12-1C in the Y direction, then the center of section 12-2A in the Y direction will be aligned with the centers of sections 12-2B and 12-2C in the Y direction. Also in this case, the center of section 12-3A in the Y direction will be aligned with the centers of sections 12-3B and 12-3C in the Y direction.

[0023] Furthermore, the distance D1 between the center of portion 12-1A in the Y direction and the center of portion 12-2A in the Y direction is approximately equivalent to, for example, the distance D2 between the centers of portions 12-1B and 12-1C in the Y direction and the centers of portions 12-2B and 12-2C in the Y direction. Also, the distance D3 between the center of portion 12-1A in the Y direction and the center of portion 12-3A in the Y direction is approximately equivalent to the distance D4 between the centers of portions 12-1B and 12-1C in the Y direction and the centers of portions 12-3B and 12-3C in the Y direction.

[0024] The configuration of the semiconductor device 1 in the XZ cross-section including the conductive layer 12-1 will be explained with reference to Figure 3. Figure 3 is a cross-sectional view along line III-III in Figure 2, showing an example of a portion of the semiconductor device according to the first embodiment.

[0025] The upper surfaces of section 12-1B and section 12-1C are provided to be flush with the upper surface of section 12-1A. The lower surfaces of section 12-1B and section 12-1C are located above the lower surface of section 12-1A. Sections 12-1B and 12-1C have an approximate height ht1 in the Z direction.

[0026] The configuration of the semiconductor device 1 in the XZ cross-section including the conductive layer 12-2 will be explained with reference to Figure 4. Figure 4 is a cross-sectional view along line IV-IV in Figure 2, showing an example of a portion of the semiconductor device according to the first embodiment.

[0027] The upper surfaces of section 12-2A, section 12-2B, and section 12-2C are provided to be flush with each other. Section 12-2A includes sub-sections 12-2A-1, 12-2A-2, and 12-2A-3. Sub-sections 12-2A-2 and 12-2A-3 sandwich sub-section 12-2A-1 in the X direction. Sub-section 12-2A-2 is sandwiched in the X direction by sub-sections 12-2A-1 and section 12-2B. Sub-section 12-2A-2 is also in contact with sub-sections 12-2A-1 and section 12-2B. Sub-section 12-2A-3 is sandwiched in the X direction by sub-sections 12-2A-1 and section 12-2C. Sub-section 12-2A-3 is also in contact with sub-sections 12-2A-1 and section 12-2C.

[0028] Sub-part 12-2A-1 has a lower surface that is substantially parallel to the substrate. The position of this lower surface in the Z direction is position BA1. Position BA1 is, for example, lower than position BB1 in the Z direction of the lower surface of part 12-2B and part 12-2C. Parts 12-2B and 12-2C have an approximate height ht1 in the Z direction, similar to parts 12-1B and 12-1C.

[0029] Section 12-2A has a stepped shape in the XZ cross-section, for example, due to a manufacturing process described later, at the point where sub-sections 12-2A-1 and 12-2A-2 are connected and at the point where sub-sections 12-2A-1 and 12-2A-3 are connected. Sub-section 12-2A-2 constitutes a protruding portion that extends downward from position BB1 between sub-section 12-2A-1 and section 12-2B. The height in the Z direction between the position of the lower end at the boundary where sub-section 12-2A-2 and sub-section 12-2A-1 meet and the position of the lower end of sub-section 12-2A-2 is, for example, an approximate height ht1. Sub-section 12-2A-3 also constitutes a protruding portion that extends downward from position BB1 between sub-section 12-2A-1 and section 12-2C. The height in the Z direction between the position of the lower end at the boundary where sub-part 12-2A-3 and sub-part 12-2A-1 meet and the position of the lower end of sub-part 12-2A-3 is, for example, an approximate height ht1.

[0030] Although not shown in the diagram, the structure of the conductive layer 12-3 in the XZ cross-section is substantially equivalent to the structure of the conductive layer 12-2 shown in Figure 4.

[0031] 1.2 Manufacturing method The method for manufacturing the semiconductor device 1 will be explained using Figures 5 to 14. Figures 5, 7 to 10, and 12 to 14 are cross-sectional views illustrating an example of the method for manufacturing the semiconductor device according to the first embodiment. Figures 6 and 11 are top views illustrating an example of the method for manufacturing the semiconductor device according to the first embodiment. The cross-sectional views shown in Figures 5, 7, and 10 show the region corresponding to Figure 1. The figures shown in Figures 6 and 11 are top views of the region corresponding to Figure 2, viewed from above. The cross-sectional views shown in Figures 8 and 13 show the region corresponding to Figure 3. The cross-sectional views shown in Figures 9, 12, and 14 show the region corresponding to Figure 4.

[0032] First, a conductive layer 11 and an insulating layer 20 are formed on the upper surface of the substrate. Then, as shown in Figures 5 and 6, for example, resist RL1, intermediate layer M1, and resist RU1 are laminated in this order on the upper surface of the insulating layer 20. Resist RU1 has openings O1, O2, and O3. Openings O1, O2, and O3 are formed in the portions where portions 12-1A, 12-2A, and 12-3A are to be formed, respectively. The width W3 of opening O1 in the Y direction is greater than the width W4 of openings O2 and O3 in the Y direction. Widths W3 and W4 are approximately equivalent to, for example, widths W1 and W2, respectively.

[0033] Next, etching using the resist RL1, intermediate layer M1, and resist RU1 formed as described above removes portions of the insulating layer 20 along with resist RL1 and intermediate layer M1 at openings O1, O2, and O3. After etching, resist RL1, intermediate layer M1, and resist RU1 are removed. Through the above process, holes H1, H2, and H3 are formed as shown in Figures 7, 8, and 9. Holes H1, H2, and H3 correspond to the portions where portions 12-1A, 12-2A, and 12-3A are to be formed, respectively. As shown in Figures 7 and 8, the upper surface of the conductive layer 11 is exposed at the bottom of hole H1. As described above, the width W4 of openings O2 and O3 is smaller than the width W3 of opening O1. As a result, in the above etching process, the etching rate at openings O2 and O3 is slower than the etching rate at opening O1 due to the microloading effect. Therefore, during etching, when the upper surface of the conductive layer 11, which functions as a stopper, is exposed and hole H1 is formed, the bottom surfaces of holes H2 and H3 are located above the bottom surface of hole H1. Holes H1, H2, and H3 each have a tapered shape, for example, such that their width in the X direction and Y direction widen from bottom to top.

[0034] Then, as shown in Figures 10, 11, and 12, for example, resist RL2, intermediate layer M2, and resist RU2 are laminated in this order on the upper surface of the insulating layer 20 in which holes H1, H2, and H3 are formed. In Figure 11, the areas where portions 12-1A, 12-2A, and 12-3A are to be formed are shown by dotted lines. Resist RL2 is formed, for example, to be embedded in holes H1, H2, and H3. The upper surface of resist RL2 is formed, for example, to be flush with the insulating layer 20. Resist RU2 has openings O4, O5, O5', O6, and O6'. Opening O4 is formed in a linear shape extending in the X direction, overlapping with the area where portion 12-1A is to be formed when viewed from above, and including the areas where portions 12-1B and 12-1C are to be formed. Opening O4 is formed so as to cross the area where portion 12-1A is to be formed in the X direction when viewed from above. Openings O5 and O5' are each formed in a linear shape extending in the X direction, including the portions where portions 12-2B and 12-2C are to be formed. As shown in Figure 12, opening O5 overlaps with a portion of the portion corresponding to one side of hole H2 in the X direction in the process described using Figures 7 to 9. The portion of the surface of the insulating layer 20 corresponding to one side of hole H2 in the X direction is called portion SL1. In the XZ cross section, the position P1 on the other side of opening O5 in the X direction is located between the positions on one side and the other side of portion SL1 in the X direction. Similarly, opening O5' overlaps with a portion of the portion corresponding to the other side of hole H2 in the X direction in the process described using Figures 7 to 9. The portion of the surface of the insulating layer 20 corresponding to the other side of hole H2 in the X direction is called portion SL2. In the XZ cross section, the position P2 on one side of opening O5 in the X direction is located between the positions on one side and the other side of portion SL2 in the X direction. Openings O6 and O6' are each formed in a linear fashion extending in the X direction, including the portions where sections 12-3B and 12-3C are to be formed. Although the XZ section including openings O6 and O6' is not shown, it is substantially equivalent to the XZ section including openings O5 and O5' shown in Figure 12.

[0035] Then, by etching using the resist RL2, intermediate layer M2, and resist RU2 formed as described above, portions of the insulating layer 20 are removed along with resist RL2 and intermediate layer M2 at the openings O4, O5, O5', O6, and O6'. After etching, resist RL2, intermediate layer M2, and resist RU2 are removed. Through the above process, holes are formed in the areas where conductive layers 12-1, 12-2, and 12-3 are to be formed, as shown in Figures 13 and 14. In Figures 13 and 14, the insulating layer 20 in the areas where no holes are formed is shown by dotted lines. In the area overlapping with the opening O4 when viewed from above, the insulating layer 20 is removed by the above etching by approximately a height ht1. As a result, a hole H4 is formed in the area where conductive layer 12-1 is to be formed, as shown in Figure 13. Furthermore, in the portions that overlap with openings O5 and O5' when viewed from above, the insulating layer 20 is removed by, for example, an approximate height ht1, similar to the portion that overlaps with opening O4 when viewed from above. As a result, as shown in Figure 14, a hole H5 corresponding to the portion where the conductive layer 12-2 is to be formed is formed. As explained using Figure 12, when viewed from above, openings O5 and O5' overlap with portions SL1 and SL2, respectively, which correspond to the sides of hole H2. As a result, in the etching described above, the portion of the portion corresponding to hole H2 that is on one side of position P1 in Figure 12, and the portion on the other side of position P2 are removed by an approximate height ht1. Therefore, as shown in Figure 14, a hole H5 having a shape corresponding to sub-parts 12-2A-2 and 12-2A-3 is formed. The hole corresponding to the portion where the conductive layer 12-3 is to be formed is the same as the hole H5 corresponding to the portion where the conductive layer 12-2 is to be formed.

[0036] Furthermore, the conductive layers 12-1, 12-2, and 12-3 are formed so as to be embedded in the holes H4 and H5 formed by the process described with reference to Figures 13 and 14.

[0037] The semiconductor device 1 is formed through the process described above.

[0038] 1.3 Effects According to the first embodiment, the decrease in the breakdown voltage characteristics of the semiconductor device 1 can be suppressed. The effects of the embodiment will be described below.

[0039] The semiconductor device 1 according to the first embodiment comprises conductive layers 12-1 and 12-2 adjacent to each other in the Y direction. Conductive layer 12-1 includes portions 12-1A and 12-1B. Portion 12-1A is a via or plug extending in the Z direction. Portion 12-1B extends in the X direction. Portion 12-1A is in contact with portion 12-1B above portion 12-1A. Conductive layer 12-2 includes portions 12-2A and 12-2B. Portions 12-2A and 12-2B are aligned and in contact with each other in the X direction. Portion 12-2A is adjacent to portion 12-1A in the Y direction. Portion 12-2B is in the same layer as portion 12-1B and extends in the X direction. The position in the Z direction of the lower surface of portion 12-2A is different from the position in the Z direction of the lower surface of portion 12-2B. With the above configuration, according to the first embodiment, it is possible to suppress a decrease in the breakdown voltage characteristics of the semiconductor device 1 due to misalignment of the via or plug portion with respect to the wiring portion extending in the X direction.

[0040] The effects of the semiconductor device 1 according to the first embodiment will be further explained.

[0041] A comparative example of forming three adjacent wirings in the Y direction using dual damascene technology is described. In the comparative example, the central wiring in the Y direction has, for example, a via or plug and an extended portion that extends linearly in the X direction. The two adjacent wirings that sandwich the central wiring in the Y direction also extend linearly in the X direction. In the manufacturing process of the comparative example, first, for example, holes corresponding to vias or plugs are formed in the insulating layer. Then, above the holes corresponding to vias or plugs, holes corresponding to the two adjacent wirings are formed, along with a hole corresponding to the extended portion of the central wiring. Then, the three wirings are formed so that conductors are embedded in these holes. In the above process, because the holes corresponding to vias or plugs and the holes corresponding to the extended portion and adjacent wirings are formed in different processes, there are cases where the center position in the Y direction of the via or plug and the center position in the Y direction of the extended portion are misaligned (a misalignment occurs). In such cases, the via or plug of the central wiring comes closer to one of the two adjacent wirings in the Y direction. This can reduce the withstand voltage characteristics of the semiconductor device.

[0042] In the semiconductor device 1 according to the first embodiment, adjacent conductive layers 12-1 and 12-2 include adjacent portions 12-1A and 12-2A in the Y direction. Furthermore, in the manufacturing method of the semiconductor device 1 according to the first embodiment, as explained with reference to Figures 5 and 6, holes H1 and H2 are formed in the portions where portions 12-1A and 12-2A are to be formed by etching using a resist RU1 having openings O1 and O2 corresponding to portions 12-1A and 12-2A, respectively, as shown in Figures 7, 8, and 9. Subsequently, as explained with reference to Figures 10, 11, and 12, holes H4 and H5 are formed in the portions where conductive layers 12-1 and 12-2 are to be formed by etching using a resist RU2 having openings O4 and O5 corresponding to portions 12-1B and 12-2B extending in the X direction, respectively, as shown in Figures 13 and 14. As described above, in the first embodiment, the portion where portions 12-1A and 12-2A are to be formed and the portion where portions 12-1B and 12-2B are to be formed are formed separately. As a result, even if the center position of portion 12-1A in the Y direction is shifted relative to the center position of portion 12-1B in the Y direction, portion 12-2A adjacent to portion 12-1A in the Y direction will also be shifted similarly, so the distance D1 between portion 12-1A and the conductive layer 12-2 will not change. Therefore, a decrease in the breakdown voltage characteristics of the semiconductor device 1 is suppressed.

[0043] 2. Modified Examples of the First Embodiment The first embodiment described above can be modified in various ways. A semiconductor device according to a modified version of the first embodiment will be described below.

[0044] 2.1 First Modification of the First Embodiment In the first embodiment described above, as shown in Figure 12, the openings O5 and O5' overlap in the Z direction with a portion of part SL1 corresponding to one side surface of hole H2 and a portion of part SL2 corresponding to the other side surface of hole H2, respectively, during the manufacturing process. However, the invention is not limited to this. In the manufacturing process, the opening O5 may overlap entirely with part SL1, and the opening O5' may overlap entirely with part SL2. Below, the configuration and manufacturing method of a semiconductor device according to a first modification of the first embodiment will be described, highlighting the differences from the configuration and manufacturing method of a semiconductor device according to the first embodiment.

[0045] The configuration of the semiconductor device 1 according to the first modified example of the first embodiment will be described with reference to Figure 15. Figure 15 is a cross-sectional view showing an example of a part of the semiconductor device according to the first modified example of the first embodiment. The cross-section shown in Figure 15 corresponds to the cross-section shown in Figure 4 of the first embodiment.

[0046] The position of the lower surface of sub-part 12-2A-1 in the Z direction is position BA2. Position BA2 is below, for example, the position BB2 in the Z direction of the lower surface of part 12-2B and the lower surface of part 12-2C.

[0047] In the Z direction, the lower end of sub-part 12-2A-2 and the lower end of sub-part 12-2A-3 are located at position BA3. Position BA3 is lower than positions BA2 and BB2. Sub-parts 12-2A-2 and 12-2A-3 may have, for example, a lower surface that is substantially parallel to the substrate.

[0048] The method for manufacturing the semiconductor device 1 according to the first modified example of the first embodiment is the same as the method for manufacturing the semiconductor device according to the first embodiment, except for the steps described using Figures 10, 11, and 12 of the first embodiment. Hereinafter, the method for manufacturing the semiconductor device 1 according to the first modified example of the first embodiment will be described using Figure 16. Figure 16 corresponds to the cross-section shown in Figure 15.

[0049] As shown in Figure 16, opening O5 overlaps with the entirety of portion SL1. In the XZ section, position P3 on the other side of opening O5 in the X direction is located on the other side of portion SL1 in the X direction. As a result, opening O5 overlaps with a portion of the part corresponding to the bottom surface of hole H2. Also, opening O5' overlaps with the entirety of portion SL2. In the XZ section, position P4 on one side of opening O5' in the X direction is located on the other side of portion SL2 in the X direction. As a result, opening O5' overlaps with a portion of the part corresponding to the bottom surface of hole H2. Note that position P4 is located on the other side of position P3 in the X direction. The illustration of the XZ section including openings O6 and O6' is omitted, but the XZ section including openings O6 and O6' is substantially equivalent to the XZ section including openings O5 and O5' shown in Figure 16.

[0050] Using the resist RU2 having the openings described above, the portion on one side of position P3 and the portion on the other side of position P4 in Figure 16 are removed in the same process as described with reference to Figures 13 and 14 of the first embodiment. This forms a hole corresponding to the conductive layer 12-2 according to the first modified example of the first embodiment.

[0051] As described above, the semiconductor device 1 according to the first modification of the first embodiment is manufactured.

[0052] The first modification of the first embodiment also produces the same effects as the first embodiment.

[0053] 2.2 Second Modification of the First Embodiment In the first embodiment and the first modification of the first embodiment described above, the case in which the lower surface of sub-part 12-2A-1 is lower than the lower surfaces of part 12-2B and part 12-2C was shown, but it is not limited to this. The lower surface of sub-part 12-2A-1 may be located above the lower surfaces of part 12-2B and part 12-2C. Below, the differences between the configuration and manufacturing method of the semiconductor device according to the second modification of the first embodiment and the configuration and manufacturing method of the semiconductor device according to the first modification of the first embodiment will be described.

[0054] The configuration of the semiconductor device 1 according to a second modification of the first embodiment will be described with reference to Figure 17. Figure 17 is a cross-sectional view showing an example of a part of the semiconductor device according to the second modification of the first embodiment. The cross-section shown in Figure 17 corresponds to the cross-section shown in Figure 4 of the first embodiment.

[0055] In the second modification of the first embodiment, the position of the lower surface of sub-part 12-2A-1 in the Z direction is position BA4. In the Z direction, position BA4 is at a height greater than or equal to position BB3 on the lower surface of part 12-2B and part 12-2C, for example.

[0056] In the Z direction, the lower surface of sub-part 12-2A-2 and the lower end of sub-part 12-2A-3 are located at position BA5. Position BA5 is lower than positions BB3 and BA4.

[0057] The method for manufacturing the semiconductor device 1 according to the second modified example of the first embodiment can be the same as the first modified example of the first embodiment, except that the depth of the hole H2 is different in the steps corresponding to the steps described using Figures 7, 8, and 9 of the first embodiment.

[0058] The second modification of the first embodiment also produces the same effects as the first embodiment.

[0059] 2.3 Third Modification of the First Embodiment In the first embodiment, the first modification of the first embodiment, and the second modification of the first embodiment described above, it was shown that in the manufacturing process, the lower surfaces of portion 12-2A and portion 12-3A are formed to be located above the lower surface of portion 12-1A due to the microloading effect, but the invention is not limited to this. Conductive layers 12-1, 12-2, and 12-3 may be formed such that the lower surfaces of portion 12-2A and portion 12-3A are located above the lower surface of portion 12-1A due to stoppers. Below, the configuration and manufacturing method of a semiconductor device according to the third modification of the first embodiment will be described in terms of differences from the configuration and manufacturing method of a semiconductor device according to the first embodiment.

[0060] The configuration of the semiconductor device 1 according to the third modification of the first embodiment will be described with reference to Figures 18 and 19. Figures 18 and 19 are cross-sectional views showing an example of a part of the semiconductor device according to the third modification of the first embodiment. The cross-sections shown in Figures 18 and 19 correspond to the cross-sections shown in Figures 1 and 4 of the first embodiment, respectively.

[0061] The configuration of the semiconductor device 1 in the YZ cross-section will be explained using Figure 18.

[0062] The semiconductor device 1 includes conductive layers 11, 12-1, 12-2, and 12-3, stoppers STP1 and STP2, and insulating layers 21 and 22.

[0063] The insulating layers 21 and 22 are provided above the substrate in this order. The conductive layer 11 is provided within the insulating layer 21. The upper surface of the conductive layer 11 is located below the upper surface of the insulating layer 21. The conductive layers 12-2 and 12-3, as well as the stoppers STP1 and STP2, are provided within the insulating layer 22. The conductive layer 12-1 is provided within the insulating layers 21 and 22.

[0064] Stoppers STP1 and STP2 are provided on the upper surface of the insulating layer 21. Stoppers STP1 and STP2 are provided corresponding to the conductive layers 12-2 and 12-3, respectively. Stoppers STP1 and STP2 are, for example, insulators. However, stoppers STP1 and STP2 may also be conductors.

[0065] Part 12-2A contacts the upper surface of stopper STP1. Part 12-3A contacts the upper surface of stopper STP2.

[0066] Figure 18 shows a case, similar to the first embodiment, where the width W6 in the Y direction of portions 12-2A and 12-3A is smaller than the width W5 in the Y direction of portion 12-1A, but is not limited to this. The width W6 in the Y direction of portions 12-2A and 12-3A may be greater than or equal to the width W5 in the Y direction of portion 12-1A.

[0067] Furthermore, as shown in Figure 19, the lower surface of sub-part 12-2A-1 of part 12-2A is in contact with stopper STP1. Although not shown in the figure, the structure of the conductive layer 12-3 in the XZ cross-section is substantially the same as the structure of conductive layer 12-2 shown in Figure 19.

[0068] A method for manufacturing a semiconductor device 1 according to a third modification of the first embodiment will be described with reference to Figures 20 and 21. Figures 20 and 21 are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to a third modification of the first embodiment. Figures 20 and 21 correspond to the cross-section shown in Figure 18.

[0069] First, a conductive layer 11 and an insulating layer 21 are formed on the upper surface of the substrate. Then, as shown in Figure 20, stoppers STP1 and STP2 are formed on the upper surface of the insulating layer 21. More specifically, an insulator is formed entirely on the upper surface of the insulating layer 21. Then, etching is performed on the upper surface of the insulator using a mask that has openings surrounding the areas where stoppers STP1 and STP2 are to be formed. In this way, stoppers STP1 and STP2 are formed on the upper surface of the insulating layer 21.

[0070] Then, an insulating layer 22 is formed on the upper surfaces of stoppers STP1 and STP2 and on the upper surface of insulating layer 21. Next, a resist and an intermediate layer are formed in the same manner as the process described with reference to Figures 5 and 6 of the first embodiment. Also, etching is performed using the resist and intermediate layer in the same manner as the process described with reference to Figures 7, 8, and 9 of the first embodiment. After etching, the resist and intermediate layer are removed. As a result of the above process, holes H6, H7, and H8 are formed as shown in Figure 21. Holes H6, H7, and H8 correspond to portions 12-1A, 12-2A, and 12-3A, respectively. Holes H7 and H8 are formed corresponding to stoppers STP1 and STP2. Thus, in the etching process, the formation of holes H7 and H8 is stopped on the upper surfaces of stoppers STP1 and STP2. The upper surfaces of stoppers STP1 and STP2 are exposed at the bottom of holes H7 and H8.

[0071] The other steps are substantially the same as the method for manufacturing a semiconductor device according to the first embodiment, except that the insulating layers 21 and 22 are treated instead of the insulating layer 20.

[0072] The third modification of the first embodiment also produces the same effects as the first embodiment.

[0073] 2.4 Fourth Modified Example of the First Embodiment In the third modification of the first embodiment described above, the stopper STP is shown to be provided above the conductive layer 11, but the invention is not limited to this. The stopper STP may be included in the same layer as the conductive layer 11. Below, the differences between the configuration and manufacturing method of the semiconductor device according to the fourth modification of the first embodiment and the configuration and manufacturing method of the semiconductor device according to the third modification of the first embodiment will be explained.

[0074] The configuration of the semiconductor device 1 according to the fourth modification of the first embodiment will be described with reference to Figures 22 and 23. Figures 22 and 23 are cross-sectional views showing an example of a part of the semiconductor device according to the fourth modification of the first embodiment. The cross-sections shown in Figures 22 and 23 correspond to the cross-sections shown in Figures 1 and 4 of the first embodiment, respectively.

[0075] The configuration of the semiconductor device 1 in the YZ cross-section will be explained using Figure 22.

[0076] The semiconductor device 1 includes conductive layers 11, 12-1, 12-2, and 12-3, insulating layers 23 and 24, and stoppers STP1 and STP2.

[0077] Insulator layers 23 and 24 are provided above the substrate in this order. The conductive layer 11 and stoppers STP1 and STP2 are provided within the insulating layer 23. The upper surface of the insulating layer 23, the upper surface of the conductive layer 11, and the upper surfaces of the two stoppers STP are provided to be flush, for example. The two stoppers STP are included in the same layer as the conductive layer 11.

[0078] The conductive layers 12-1, 12-2, and 12-3 are provided within the insulating layer 24. The lower surfaces of the insulating layer 24, the conductive layer 12-1, the conductive layer 12-2, and the conductive layer 12-3 are provided flush with each other.

[0079] As shown in Figure 23, in the XZ cross-section including the conductive layer 12-2, the lower surface of the sub-part 12-2A-1 is in contact with the stopper STP1, similar to the third modified example of the first embodiment. Although not shown, the structure of the conductive layer 12-3 in the XZ cross-section is substantially equivalent to the structure of the conductive layer 12-2 shown in Figure 23.

[0080] A method for manufacturing a semiconductor device 1 according to a fourth modification of the first embodiment will be described with reference to Figure 24. Figure 24 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to a fourth modification of the first embodiment. Figure 24 corresponds to the cross-section shown in Figure 22.

[0081] First, as shown in Figure 24, an insulating layer 23 and stoppers STP1 and STP2 are formed on the upper surface of the substrate. The upper surfaces of the insulating layer 23 and stoppers STP1 and STP2 are formed to be flush with each other.

[0082] The other steps are the same as those in the third modification of the first embodiment, except that the depth of the holes corresponding to sections 12-2A and 12-3A is different, and that the treatment is performed on the insulating layer 24 instead of the insulating layers 21 and 22.

[0083] The fourth modification of the first embodiment also produces the same effects as the first embodiment.

[0084] 2.5 Fifth Modification of the First Embodiment In the fourth modification of the first embodiment described above, a case was shown in which stoppers STP1 and STP2 are provided in the same layer as the conductive layer 11, but the invention is not limited to this. For example, a conductor provided by the same process as the conductive layer 11 may be provided as a stopper. Below, the differences between the configuration and manufacturing method of the semiconductor device according to the fifth modification of the first embodiment and the configuration and manufacturing method of the semiconductor device according to the first embodiment will be explained.

[0085] The configuration of the semiconductor device 1 according to the fifth modification of the first embodiment will be described with reference to Figures 25 and 26. Figures 25 and 26 are cross-sectional views showing an example of a part of the semiconductor device according to the fifth modification of the first embodiment. The cross-sections shown in Figures 25 and 26 correspond to the cross-sections shown in Figures 1 and 4 of the first embodiment, respectively.

[0086] The semiconductor device 1 includes conductive layers 11, 12-1, 12-2, 12-3, 13-1, and 13-2, and an insulating layer 20.

[0087] Conductive layers 13-1 and 13-2 are provided corresponding to conductive layers 12-2 and 12-3, respectively. Conductive layers 13-1 and 13-2 are provided in the same layer as conductive layer 11. Furthermore, in the Z direction, the position of the upper surface of conductive layer 13-1 and the upper surface of conductive layer 13-2 are approximately the same as the position of the upper surface of conductive layer 11. Furthermore, in the Z direction, the position of the lower surface of conductive layer 13-1 and the lower surface of conductive layer 13-2 are approximately the same as the position of the lower surface of conductive layer 11. With the above configuration, conductive layers 11, 13-1, and 13-2 have an approximate height ht2.

[0088] The conductive layer 12-2 is in contact with the upper surface of the conductive layer 13-1. The conductive layer 13-1 is provided, for example, spaced apart from a different conductor than the conductive layer 12-2 in the semiconductor device 1.

[0089] The upper surface of the conductive layer 13-2 is in contact with the conductive layer 12-3. The conductive layer 13-2 is provided, for example, spaced apart from a different conductor than the conductive layer 12-3 in the semiconductor device 1.

[0090] The configuration of the semiconductor device 1 in the XZ cross-section including the conductive layer 12-2 is substantially equivalent to the structure according to the fourth modification of the first embodiment, except that it includes a conductive layer 13-1 instead of a stopper, as shown in Figure 26.

[0091] A method for manufacturing a semiconductor device 1 according to a fifth modification of the first embodiment will be described with reference to Figure 27. Figure 27 is a cross-sectional view showing an example of a part of the semiconductor device according to the fifth modification of the first embodiment. The cross-section shown in Figure 27 corresponds to the cross-section shown in Figure 1 of the first embodiment.

[0092] In the manufacturing method of the semiconductor device 1 according to the fifth modified example of the first embodiment, in the steps corresponding to the steps described with reference to Figures 7, 8, and 9 of the first embodiment, the formation of holes H9, H10, and H11 corresponding to portions 12-1A, 12-2A, and 12-3A is stopped by conductive layers 11, 13-1, and 13-2 formed in the same layer, respectively.

[0093] The other steps are the same as those in the first embodiment.

[0094] The fifth modification of the first embodiment also produces the same effects as the first embodiment.

[0095] 2.6 Sixth Modification of the First Embodiment In the first embodiment described above, a case was shown in which portion 12-1A is connected to the upper surface of the conductive layer 11 provided above the substrate, but the invention is not limited to this. Portion 12-1A may be provided so as to be in contact with the substrate. Below, the configuration and manufacturing method of a semiconductor device according to the sixth modification of the first embodiment will be described in terms of differences from the configuration and manufacturing method of a semiconductor device according to the first embodiment.

[0096] The configuration of the semiconductor device 1 according to the sixth modified example of the first embodiment will be described with reference to Figure 28. Figure 28 is a cross-sectional view showing an example of a part of the semiconductor device according to the sixth modified example of the first embodiment. The cross-section shown in Figure 28 corresponds to the cross-section shown in Figure 1 of the first embodiment.

[0097] As shown in Figure 28, in the sixth modified example of the first embodiment, an insulating layer 20 is provided on the upper surface of the substrate S. The conductive layer 12-1 is provided such that a portion 12-1A is in contact with the substrate. The portion 12-1A is in contact with, for example, electrodes or impurity diffusion regions provided on the substrate S.

[0098] Other configurations can be the same as those of the semiconductor device according to the first embodiment.

[0099] Furthermore, the method for manufacturing the semiconductor device 1 according to the sixth modified example of the first embodiment is the same as the method for manufacturing the semiconductor device according to the first embodiment, except that the substrate S functions as a stopper instead of a conductive layer in the same steps as those described using Figures 7, 8, and 9 of the first embodiment.

[0100] The sixth modification of the first embodiment also produces the same effects as the first embodiment.

[0101] 3. Second Embodiment In the first embodiment described above, an example was shown in which a via or plug and a wiring layer are integrally formed using dual damascene technology, but the invention is not limited thereto. For example, a structure may be used in which a via or plug and a wiring layer are provided separately using single damascene technology.

[0102] 3.1 Configuration The configuration of the semiconductor device according to the second embodiment will be described, primarily focusing on the differences from the configuration of the semiconductor device according to the first embodiment. The configuration of the parts included in the semiconductor device will be described below.

[0103] The configuration of the semiconductor device 1 in the YZ cross-section will be explained with reference to Figure 29. Figure 29 is a cross-sectional view showing an example of a part of the semiconductor device according to the second embodiment. The cross-section in Figure 29 corresponds to the cross-section in Figure 1 of the first embodiment.

[0104] The semiconductor device 1 includes conductive layers 11, 121-1, 121-2, 121-3, and 122-1, as well as insulating layers 25 and 26. The conductive layers 11, 121-1, 121-2, 121-3, and 122-1 function as wiring that is electrically connected to a circuit provided on a substrate (not shown), for example.

[0105] A conductive layer 121-1 is provided above the conductive layer 11. The lower surface of the conductive layer 121-1 is electrically connected, for example, to the upper surface of the conductive layer 11. The conductive layer 121-1 extends in the Z direction. The conductive layer 121-1 functions as a via or plug that is electrically connected to the conductive layer 11.

[0106] Conductive layers 121-2 and 121-3 are each provided adjacent to conductive layer 121-1 in the Y direction, for example. Conductive layer 121-1 is sandwiched in the Y direction by conductive layers 121-2 and 121-3. The width W7 in the Y direction at the upper end of conductive layer 121-1 is wider than the width W8 in the Y direction at the upper ends of conductive layers 121-2 and 121-3. In the Z direction, the lower surfaces of conductive layers 121-2 and 121-3 are located above the lower surface of conductive layer 121-1, for example.

[0107] The conductive layers 11, 121-1, 121-2, and 121-3 are provided within the insulating layer 25. The upper surfaces of conductive layer 121-1, conductive layer 121-2, and conductive layer 121-3 are provided, for example, flush with the upper surface of the insulating layer 25.

[0108] A conductive layer 122-1 is provided on the upper surface of the conductive layer 121-1. The conductive layer 122-1 extends in the X direction in a cross-section not shown in Figure 29, as will be described later. The conductive layer 122-1 is provided, for example, in the same layer as the insulating layer 26. The upper and lower surfaces of the conductive layer 122-1 are provided so as to be flush with the upper and lower surfaces of the insulating layer 26.

[0109] The configuration of the semiconductor device 1 in the XY cross-section will be explained with reference to Figure 30. Figure 30 is a cross-sectional view showing an example of a portion of the semiconductor device according to the second embodiment. Figure 30 shows the configuration of a portion of the semiconductor device 1 in the XY cross-section at a position equivalent to the upper surface of the conductive layer 122-1.

[0110] In Figure 30, the regions where conductive layers 121-1, 121-2, and 121-3 are provided are indicated by dotted lines. Conductive layer 121-1 has a circular shape when viewed from above. Conductive layer 121-2 has a substantially elliptical shape when viewed from above, with the X direction as its major axis. Conductive layer 121-3 also has a substantially elliptical shape when viewed from above, with the X direction as its major axis. Conductive layers 121-1, 121-2, and 121-3 are provided so as to be aligned in the Y direction.

[0111] The semiconductor device 1 further includes conductive layers 122-2A, 122-2B, 122-3A, and 122-3B. Conductive layers 122-2A, 122-2B, 122-3A, and 122-3B are provided in the same layer as the insulating layer 26, similar to conductive layer 122-1. Conductive layers 122-2A, 122-2B, 122-3A, and 122-3B function as wiring that is electrically connected to a circuit provided on a substrate (not shown), for example.

[0112] The conductive layer 122-1 is extended in the X direction so that, when viewed from above, it overlaps with the portion of the conductive layer 122-1.

[0113] Conductive layers 122-2A and 122-2B are provided in correspondence with conductive layer 121-2. Conductive layers 122-2A and 122-2B each extend in the X direction. Conductive layers 122-2A and 122-2B are, for example, included on substantially the same straight line. Conductive layer 122-2A is provided so as viewed from above, overlaps with one portion of conductive layer 122-2 in the X direction. Conductive layer 122-2B is provided so as viewed from above, overlaps with the other portion of conductive layer 122-2 in the X direction.

[0114] Conductive layers 122-3A and 122-3B are provided in correspondence with conductive layer 121-3. Conductive layers 122-3A and 122-3B each extend in the X direction. Conductive layers 122-3A and 122-3B are, for example, included on substantially the same straight line. Conductive layer 122-3A is provided so as viewed from above, overlaps with one portion of conductive layer 122-3 in the X direction. Conductive layer 122-3B is provided so as viewed from above, overlaps with the other portion of conductive layer 122-3 in the X direction.

[0115] The center of the conductive layer 121-1 in the Y direction and the center of the conductive layer 122-1 in the Y direction may be offset in the Y direction or they may be aligned in the Y direction. Figure 30 shows an example where the center of the conductive layer 121-1 in the Y direction is offset in the Y direction relative to the center of the conductive layer 122-1 in the Y direction. The arrangement relationships of conductive layers 121-2, 122-2A, and 122-2B, and the arrangement relationships of conductive layers 121-3, 122-3A, and 122-3B, respectively, are the same as, for example, the arrangement relationship of conductive layers 121-1 and 122-1. If the center of conductive layer 121-1 in the Y direction is offset to one or the other side in the Y direction relative to the center of conductive layer 122-1 in the Y direction, then the center of conductive layer 121-2 in the Y direction will be offset to one or the other side in the Y direction relative to the centers of conductive layers 122-2A and 122-2B in the Y direction. In this case, the center of conductive layer 121-3 in the Y direction will be offset to one or the other side in the Y direction relative to the centers of conductive layers 122-3A and 122-3B in the Y direction. If the center of conductive layer 121-1 in the Y direction is aligned with the center of conductive layer 122-1 in the Y direction, then the center of conductive layer 121-2 in the Y direction will be aligned with the centers of conductive layers 122-2A and 122-2B in the Y direction. In this case, the center of the conductive layer 121-3 in the Y direction aligns with the center of the conductive layers 122-3A and 122-3B in the Y direction.

[0116] Furthermore, the distance D5 between the center of conductive layer 121-1 in the Y direction and the center of conductive layer 121-2 in the Y direction is approximately equivalent to the distance D6 between the center of conductive layer 122-1 in the Y direction and the centers of conductive layers 122-2A and 122-2B in the Y direction. Also, the distance D7 between the center of conductive layer 121-1 in the Y direction and the center of conductive layer 121-3 in the Y direction is approximately equivalent to the distance D8 between the center of conductive layer 122-1 in the Y direction and the centers of conductive layers 122-3A and 122-3B in the Y direction.

[0117] The configuration of the semiconductor device 1 in the XZ cross-section, including the conductive layers 121-1 and 122-1, will be explained with reference to Figure 31. Figure 31 is a cross-sectional view along the line XXXI-XXXI in Figure 30, showing an example of a portion of the semiconductor device according to the second embodiment.

[0118] In the XZ section, the conductive layer 121-1 is in contact with the upper surface of the conductive layer 11, similar to the configuration of the conductive layer 121-1 in the YZ section of Figure 29. The lower surface of the conductive layer 122-1 is, for example, at a height greater than the lower surface of the other parts in the portion in contact with the conductive layer 121-1. Although not shown in Figure 31, the upper surface of the conductive layer 122-1 is provided to be flush with the upper surface of the insulating layer 26, for example. The conductive layer 122-1 has an approximate height ht3 in the Z direction.

[0119] The configuration of the semiconductor device 1 in the XZ cross-section, including the conductive layers 121-2, 122-2A, and 122-2B, will be explained with reference to Figure 32. Figure 32 is a cross-sectional view along the line XXXII-XXXII in Figure 30, showing an example of a portion of the semiconductor device according to the second embodiment.

[0120] The conductive layer 121-2 has, for example, an upper surface and a lower surface that are substantially parallel to the substrate.

[0121] The upper surfaces of the conductive layer 122-2A, the conductive layer 122-2B, and the insulating layer 26 are arranged to be flush with each other. The lower surfaces of the conductive layer 122-2A and the conductive layer 122-2B are located, for example, below the upper surface of the conductive layer 121-2. In the Z direction, the positions of the lower surfaces of the conductive layer 122-2A and the conductive layer 122-2B are, for example, equivalent to the position of the lower surface of the conductive layer 122-1. With this configuration, the conductive layers 122-2A and 122-2B have an approximate height ht3 in the Z direction, similar to the conductive layer 122-1.

[0122] Conductive layers 121-2 and 122-2A are in contact with each other in the region where conductive layers 121-2 and 122-2A overlap in the Z direction. Conductive layers 121-2 and 122-2B are in contact with each other in the region where conductive layers 121-2 and 122-2B overlap in the Z direction.

[0123] Although not shown in the diagram, the structures of conductive layers 121-3, 122-3A, and 122-3B in the XZ cross-section are substantially equivalent to the structures of conductive layers 121-2, 122-2A, and 122-2B shown in Figure 32.

[0124] 3.2 Manufacturing method A method for manufacturing the semiconductor device 1 will be explained using Figures 33, 34, 35, 36, and 37. Figures 33 and 35-37 are cross-sectional views illustrating an example of a semiconductor device manufacturing method according to the second embodiment. Figure 34 is a top view illustrating an example of a semiconductor device manufacturing method according to the second embodiment. The cross-sectional views shown in Figures 33 and 36 show the region corresponding to Figure 29. The figure shown in Figure 34 is a top view of the region corresponding to Figure 30, viewed from above. The cross-sectional views shown in Figures 35 and 37 show the region corresponding to Figure 32.

[0125] First, holes corresponding to the conductive layers 121-1, 121-2, and 121-3 are formed in the insulating layer 25 by a process similar to the process for forming holes H1, H2, and H3 described using Figures 7, 8, and 9 of the first embodiment. Then, conductive layers 121-1, 121-2, and 121-3 are formed to fill the formed holes.

[0126] Then, as shown in Figures 33, 34, and 35, the insulating layer 26, resist RL3, intermediate layer M3, and resist RU3 are stacked in this order on the upper surface of the insulating layer 25, the upper surface of the conductive layer 121-1, the upper surface of the conductive layer 121-2, and the upper surface of the conductive layer 121-3. The resist RU3 has openings O7, O8, O8', O9, and O9' which are substantially equivalent to the openings O4, O5, O5', O6, and O6' of the resist RU2 in the process described using Figures 10, 11, and 12 of the first embodiment. The openings O7, O8, O8', O9, and O9' correspond to the portions on which conductive layers 122-1, 122-2A, 122-2B, 122-3A, and 122-3B are to be formed, respectively.

[0127] Then, as in the first embodiment, the portions of the insulating layers 25 and 26 are removed along with the resist RL3 and the intermediate layer M3 by etching using the resist RL3, intermediate layer M3, and resist RU3 formed as described above. After etching, the resist RL3, intermediate layer M3, and resist RU3 are removed. Through the above process, holes are formed in the portions where the conductive layers 122-1, 122-2A, 122-2B, 122-3A, and 122-3B are to be formed. Figure 36 shows hole H12 corresponding to conductive layer 122-1. Figure 37 shows holes H13 and H13' corresponding to conductive layers 122-2A and 122-2B.

[0128] Furthermore, the conductive layers 122-1, 122-2A, 122-2B, 122-3A, and 122-3B are formed so as to be embedded in the holes H12, H13, and H13' formed by the process described with reference to Figures 36 and 37.

[0129] As described above, the semiconductor device 1 according to the second embodiment is formed.

[0130] The second embodiment also achieves the same effects as the first embodiment.

[0131] 4. Others It should be noted that the embodiments are not limited to the forms described above, and various modifications are possible. For example, the structure in the modified form of the first embodiment can also be applied to the second embodiment.

[0132] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of symbols]

[0133] 1... Semiconductor device, 11, 12, 121, 122... Conductive layer, 20, 21, 22, 23, 24, 25, 26... Insulating layer.

Claims

1. It comprises a first wiring and a second wiring that are adjacent to each other in a first direction within the first plane, The first wiring is, A first extended portion extending in a second direction intersecting the first direction within the first plane, A first plug portion extends in a third direction intersecting the first surface and contacts the first extended portion on one side in the third direction, Includes, The second wiring is, A second extended portion, which is contained in the same layer as the first extended portion and extends in the second direction, The first plug portion is adjacent to the first connecting portion in the first direction, and the second extending portion is in contact with the first connecting portion in the second direction, Includes, The first position of the other side surface of the first connecting portion in the third direction is different from the second position of the other side surface of the second extending portion in the third direction. Semiconductor equipment.

2. The first position is located on the other side of the third direction from the second position. The semiconductor device according to claim 1.

3. The second wiring further includes a third extended portion that extends in the second direction and is in the same layer as the second extended portion. The first connecting portion is sandwiched in the second direction by the second extending portion and the third extending portion, and is in contact with each of the second extending portion and the third extending portion. The semiconductor device according to claim 1.

4. The first connection part is A first sub-part having the other side of the first connecting portion in the third direction along the first surface, The second sub-part is sandwiched in the second direction by the first sub-part and the second extended part, and is in contact with each of the first sub-part and the second extended part, The third sub-part is sandwiched in the second direction by the first sub-part and the third extended part, and is in contact with each of the first sub-part and the third extended part, Includes, In a cross-section including the second and third directions, the first connecting portion has a stepped shape at the location where the first sub-part and the second sub-part are connected, and at the location where the first sub-part and the third sub-part are connected. The semiconductor device according to claim 3.

5. It comprises a first wiring and a second wiring that are adjacent to each other in a first direction within the first plane, The first wiring is, A first extended portion extending in a second direction intersecting the first direction within the first plane, A first plug portion extends in a third direction intersecting the first surface and contacts the first extended portion on one side in the third direction, Includes, The second wiring is, A second extended portion, which is contained in the same layer as the first extended portion and extends in the second direction, The first plug portion is adjacent to the first connecting portion in the first direction, and the second extending portion is in contact with the first connecting portion in the second direction, Includes, The second wiring, when viewed in the third direction, has a stepped shape at the point where the first connection portion and the second extension portion are connected. Semiconductor equipment.

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