Control device, method of operating the control device, and program

Abstract

This technology provides a way to determine which bank to refresh with limited hardware resources. [Solution] A control device for controlling access to DRAM, comprising: generation means for generating access commands in response to access requests to the DRAM and storing them in a buffer; classification means for classifying a plurality of banks contained in the DRAM into a plurality of candidate groups; selection means for selecting a candidate group from the plurality of candidate groups based on the storage status of the access commands stored in the buffer; and determination means for determining a bank for which a refresh request will be made from the selected candidate group.

Description

Technical Field

[0001] The present invention relates to a control device, an operation method of the control device, and a program.

Background Art

[0002] DRAM (Dynamic Random Access Memory) is widely adopted as the main memory device of a computer system. With the increase in speed and functionality of computer systems, the requirements for DRAM access performance have been continuously increasing, and DRAMs that operate at higher speeds have been developed.

[0003] DRAM is a device that requires a periodic refresh operation to continuously hold data. In DRAMs up to DDR2 (Double Data Rate 2), memory access during the refresh operation is prohibited, and even when memory access requests occur continuously, it is necessary to interrupt the memory access in order to perform the periodic refresh operation. Therefore, this has contributed to the degradation of memory access performance.

[0004] Therefore, LPDDR2 added a function to refresh DRAM on a bank-by-bank basis, making it possible to access the memory area of ​​a bank that has not been refreshed while a bank is being refreshed. Here, LPDDR stands for Low-Power Double Data Rate. The bank-by-bank refresh specification adopted in LPDDR2 is such that when the DRAM receives a refresh command, it refreshes the banks in a predetermined order, switching between banks such as bank 0, bank 1, bank 2, etc. In LPDDR4, a function to specify which bank to refresh was added to the bank-by-bank refresh, increasing the degree of freedom in controlling so that the bank being accessed and the bank being refreshed do not overlap. Furthermore, in LPDDR5, the number of banks installed has increased, and in the bank-by-bank refresh, a function has been adopted to refresh two banks of a specific combination, such as bank 0 and bank 8, or bank 1 and bank 9, simultaneously.

[0005] Furthermore, Patent Document 1 discloses a method for refreshing a bank that is not being accessed while performing memory access in a memory controller that controls memory including multiple memory regions.

[0006] The refresh method described in Patent Document 1 compares the number of read commands and write commands that can be executed during the refresh with the number of read commands and write commands in banks other than the bank on which the refresh is performed. Then, it controls the system to perform the refresh on banks where the number of read commands and write commands in banks other than the bank on which the refresh is performed is greater than the number of read commands and write commands that can be executed during the refresh.

[0007] LPDDR5 is designed to refresh two of its 16 banks simultaneously. When a bank is refreshed, the other banks refreshed at the same time are fixed to a specific pair of banks. Therefore, there are 16 ÷ 2 = 8 possible combinations of banks to refresh. When counting the number of read and write commands for banks other than those being refreshed, eight counters can be used. [Prior art documents] [Patent Documents]

[0008] [Patent Document 1] Japanese Patent Publication No. 2021-47829 [Overview of the project] [Problems that the invention aims to solve]

[0009] However, when refreshing two of the 16 banks simultaneously, if the banks are classified into multiple groups, and any two banks can be selected from each group, the number of possible combinations of banks to be refreshed increases. As a result, the number of counters used to count the number of read and write commands for banks other than those being refreshed increases. For example, if the 16 banks are classified into four groups of four banks each, and any two banks from each group can be refreshed, the technology described in Patent Document 1 would require 24 counters. Thus, the number of combinations when selecting two banks is large, and a large amount of hardware resources are consumed when totaling the access times for banks other than those selected.

[0010] This invention has been made in view of the above problems, and aims to provide a technology for determining the bank to refresh with limited hardware resources. [Means for solving the problem]

[0011] The control device according to the present invention, which achieves the above objective, A control device for controlling access to DRAM, A generation means that generates an access command in response to an access request to the DRAM and stores it in a buffer, A classification means for classifying multiple banks contained in the DRAM into multiple candidate groups, A selection means for selecting a candidate group from the plurality of candidate groups based on the storage status of the access command stored in the buffer, A decision means for determining which bank to request a refresh from the selected candidate group, It is characterized by being equipped with [the following features]. [Effects of the Invention]

[0012] According to the present invention, it is possible to determine the bank to refresh with fewer hardware resources. [Brief explanation of the drawing]

[0013] [Figure 1] A diagram illustrating the DRAM refresh issuance according to one embodiment. [Figure 2] A diagram illustrating a bank-specific refresh operation according to one embodiment. [Figure 3] A diagram illustrating the configuration of a DRAM control device according to one embodiment. [Figure 4] A diagram illustrating the constraints on bank-specific refresh according to one embodiment. [Figure 5] A diagram illustrating an example of a refresh management table according to one embodiment. [Figure 6] A diagram illustrating the operation of a refresh state counter according to one embodiment. [Figure 7] A flowchart illustrating the procedure for generating a refresh request according to one embodiment. [Figure 8] A diagram illustrating a method for determining a refresh bank group according to one embodiment. [Figure 9]A flowchart showing the procedure of determining a bank to be refreshed according to an embodiment. [Figure 10] A flowchart showing the procedure of controlling the issuance order of access commands according to an embodiment. **[Embodiments for Carrying Out the Invention]**

[0014] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the invention according to the claims. Although a plurality of features are described in the embodiments, not all of these plurality of features are essential for the invention, and the plurality of features may be arbitrarily combined. Further, in the accompanying drawings, the same or similar configurations are denoted by the same reference numerals, and redundant descriptions are omitted.

[0015] (Embodiment) FIG. 1 is a diagram for explaining the issuance of DRAM refresh. A DRAM can hold data by performing a refresh once at an average refresh interval defined by the specification, such as the average refresh issuance shown at 100. A common command signal is used for both DRAM refresh and memory access. Also, there are many timing constraints for issuing commands to a DRAM, and it is difficult to always perform a refresh at the average refresh interval.

[0016] Therefore, a DRAM allows issuing a refresh prior to the timing of the average refresh issuance, such as the refresh early issuance shown at 101. Also, it allows delaying the issuance of a refresh with respect to the timing of the average refresh issuance, such as the refresh late issuance shown at 102. The number of refresh times that can be issued early and the number of refresh times that can be issued late are defined by the specification, and the DRAM control device can change the refresh issuance timing within this allowable range.

[0017] FIG. 2 is a diagram for explaining the bank-specified refresh operation in LPDDR5. FIG. 2(A) shows the refresh operation specifying bank 0 and bank 8. In the bank-specified refresh, during the execution of the refresh of the specified bank, other banks can perform memory access operations such as read operations and write operations. On the other hand, as shown in FIG. 2(B), memory access cannot be performed on the bank during which the refresh is being executed. Therefore, when a memory access request for the bank during which the refresh is being executed occurs, as indicated by arrow 200, the memory access is performed after waiting for the completion of the refresh operation. Thus, the bank-specified refresh allows memory access of other banks during the refresh of a certain bank and is provided to effectively use the memory bandwidth. However, it is necessary to control so that the timings of the refresh bank and the memory access bank do not overlap.

[0018] <Configuration of DRAM control device> FIG. 3 is a diagram for explaining the configuration of the DRAM control device according to the present embodiment. The DRAM control device 300 includes a bus interface 302, a command storage unit 303, a command issuing unit 304, a refresh timer 305, and a refresh generation unit 306.

[0019] The DRAM control device 300 issues a DRAM command to the DRAM 301 in response to a memory access request issued by an initiator not shown.

[0020] The memory access request issued by the initiator is received by the bus interface 302. The bus interface 302 converts the received memory access request into an access command in units of a lower address specifying a region called a page of the DRAM 301 and transmits it to the command storage unit 303.

[0021] The command storage unit 303 monitors the refresh requests generated by the refresh generation unit 306 and the refresh responses notified by the command issuing unit 304 to recognize the bank in which a refresh is being performed. The command storage unit 303 has a buffer that holds multiple access commands generated by the bus interface 302 and controls the order in which commands are issued according to the state of the DRAM 301, including the status of the refresh, and the urgency of the memory access request. When an access command is stored in the buffer, it sends the access command to the command issuing unit 304. When the command issuing unit 304 receives an access command, it notifies the command storage unit 303 that it has received the access command.

[0022] The refresh timer 305 is a timer that counts the elapsed average refresh period and notifies the refresh generation unit 306 of the elapsed average refresh period.

[0023] The refresh generation unit 306 generates a bank-specified refresh request in accordance with the average refresh period information notified by the refresh timer 305 and the access command stored in the command storage unit 303, and notifies the command issuing unit 304 (request generation process).

[0024] The command issuing unit 304 receives access commands in low-address units from the command storage unit 303 and sends a response. The command issuing unit 304 generates a DRAM access command to access the DRAM 301 from the received low-address access command. The command issuing unit 304 also generates a refresh command to refresh the DRAM 301 in response to a bank-level refresh request generated by the refresh generation unit 306. The command issuing unit 304 also adjusts the timing of issuing the DRAM access command and the refresh command and issues a DRAM command to the DRAM 301. When the command issuing unit 304 issues a refresh command, it sends a refresh response to the refresh generation unit 306.

[0025] <Refresh limitations> Next, Figure 4 illustrates the constraints on bank-specific refresh in LPDDR5. Bank-specific refresh became possible from LPDDR4 onwards, but there are constraints on the order in which banks can be specified. In LPDDR4 and later, while it is possible to specify the banks to refresh, each bank cannot issue a second refresh because it is necessary to refresh each bank evenly. In a 16-bank DRAM configuration, if we focus on a particular bank, it is possible to refresh the same bank (the bank shown at position 400) at a minimum of two times consecutively. However, if the same bank is refreshed consecutively, the next refresh will be at least eight times later (the bank shown at position 401).

[0026] In the first round shown in Figure 4, refreshes are issued in the following order: Bank 0 and Bank 8, Bank 1 and Bank 9, Bank 2 and Bank 10, Bank 3 and Bank 11, Bank 4 and Bank 12, Bank 5 and Bank 13, Bank 6 and Bank 14, and Bank 7 and Bank 15. Then, in the second round, refreshes are issued starting from Bank 7 and Bank 15, which were the last banks to be refreshed in the first round. This allows the same banks (Bank 7 and Bank 15, shown at position 400) to be refreshed twice in a minimum.

[0027] In the second round, refreshes were issued in the following order: Bank 7 and Bank 15, Bank 0 and Bank 8, Bank 1 and Bank 9, Bank 6 and Bank 14, Bank 2 and Bank 10, Bank 5 and Bank 13, Bank 3 and Bank 11, and Bank 4 and Bank 12.

[0028] In the third round, refreshes are issued in the following order: Bank 7 and Bank 15, Bank 3 and Bank 11, Bank 6 and Bank 14, Bank 2 and Bank 10, Bank 4 and Bank 12, Bank 5 and Bank 13, Bank 1 and Bank 9, and Bank 0 and Bank 8. In the third round, refreshes are issued for Bank 7 and Bank 15 to minimize the number of refreshes, but this is 8 times after the start of the second round.

[0029] <Refresh Management Table> Figure 5 shows an example of a refresh management table implemented to satisfy the bank-specific refresh constraints of LPDDR5. As shown in the figure, when a refresh is issued for a bank, the system is configured to set a flag for that bank, and the next bank to be refreshed is selected from among the banks whose flags are not set. Although not shown in the figure, once the flags for all banks are set, the flags for all banks are reset, and a refresh can be issued for all banks.

[0030] Specifically, in Figure 5, the refresh management table 501 shows all banks with flags set to zero. When banks 2 and 10 are refreshed, the flags for banks 2 and 10 are set to 1, as shown in the refresh management table 502. The flags for the other banks remain at zero. Furthermore, when banks 0 and 8 are refreshed, the flags for banks 0 and 8 are set to 1, in addition to banks 2 and 10, as shown in the refresh management table 503. In this manner, once the flags for all banks are set, the flags for all banks are reset, and a refresh can be issued for all banks.

[0031] <Refresh status counter> Next, Figure 6 illustrates the refresh status counter of the refresh generation unit 306. The refresh status counter is a counter that detects whether the refresh issuance status to the DRAM is in a pre-refresh state or a delayed refresh state. As shown in the figure, the refresh status counter counts up when a refresh command is issued to all banks. A refresh command is issued to all banks at the timing indicated by the arrow, and the count value increases by 1.

[0032] There are two types of refresh commands: the all-bank refresh command, which refreshes all banks, and the bank-specific refresh command, which refreshes a specified bank. Therefore, the refresh status counter increments when a refresh has been issued to all banks, either by issuing the all-bank refresh command once or the bank-specific refresh command multiple times. The counter also increments when the refresh period, which is the period during which a refresh must be issued to all banks, has elapsed (i.e., the count value decreases by 1). A positive counter value (1, 2, 3, 4, 5, ...) indicates a proactive refresh state, while a negative counter value (-1, -2, -3, -4, -5, ...) indicates a delayed refresh state.

[0033] <Processing> Figure 7 is a flowchart showing the processing steps performed by the DRAM control device according to this embodiment. The processing performed by the DRAM control device can be achieved by one or more CPUs in the DRAM control device reading and executing programs stored in one or more memories. This flow is the refresh request generation flow executed by the refresh generation unit 306. This flow is started when no bank is currently performing a refresh.

[0034] In S701, the refresh generation unit 306 determines whether the number of preceding refreshes is greater than or equal to a predetermined number. The refresh generation unit 306 recognizes whether the current refresh issuance status is a preceding refresh state or a delayed refresh state using the refresh state counter explained in Figure 6. The maximum number of preceding refreshes is determined by the DRAM specifications. Therefore, if the number of preceding refreshes is greater than or equal to the predetermined number, the refresh must be stopped, and the unit waits until the number of preceding refreshes falls below the predetermined number. If the number of preceding refreshes falls below the predetermined number, the process proceeds to S702.

[0035] In S702, the refresh generation unit 306 calculates the number of DRAM commands to be issued for each refresh bank group. Specifically, it calculates the total number of read and write commands to be issued for each refresh bank group from the access command information stored in the buffer of the command storage unit 303 shown in Figure 3.

[0036] Here, a refresh bank group is a group of banks that can perform refreshes simultaneously. In this embodiment, banks 0 / 4 / 8 / 12 are designated as refresh bank group 0, and banks 1 / 5 / 9 / 13 are designated as refresh bank group 1. In addition, banks 2 / 6 / 10 / 14 are designated as refresh bank group 2, and banks 3 / 7 / 11 / 15 are designated as refresh bank group 3.

[0037] In S703, the refresh generation unit 306 selects a refresh bank group candidate (candidate group). The refresh bank group candidate is selected based on the number of read / write commands in banks other than that refresh bank group, which is calculated for each refresh bank group. In this way, the candidate group is selected based on the storage status of access commands stored in the buffer of the command storage unit 303.

[0038] In S704, the refresh generation unit 306 determines whether or not there are any refresh bank group candidates. If there are refresh bank group candidates, the process proceeds to S705. On the other hand, if there are no refresh bank group candidates, the process proceeds to S706.

[0039] In S705, the refresh generation unit 306 determines whether a refresh bank group candidate is refreshable, or more specifically, whether multiple banks within the refresh bank group candidate are refreshable. The determination is made by checking the refresh management table explained in Figure 5 and determining whether a bank does not have a flag set. If this step is Yes, the process proceeds to S710. On the other hand, if this step is No, the process proceeds to S706. That is, if there are no refreshable refresh bank group candidates, the process proceeds to S706, similar to the case where there are no refresh bank group candidates in the determination of S704, in order to determine whether a delayed refresh needs to be issued.

[0040] In S706, the refresh generation unit 306 determines whether the number of delayed refreshes is greater than or equal to a predetermined number. If there are no refresh bank group candidates, it is necessary to decide whether to wait for a refresh to be issued or to issue a refresh. Since the maximum number of delayed refreshes is determined by the DRAM specifications, it is determined whether the number of delayed refreshes is greater than or equal to a predetermined number. If this step is Yes, the process proceeds to S707. On the other hand, if this step is No, the process ends. That is, in 704, if the number of delayed refreshes is less than the predetermined number, there is no need to rush the issuance of a refresh command, so the process ends without generating a refresh request.

[0041] In S707, the refresh generation unit 306 determines the refresh bank group. When determining the refresh bank group, it checks the refresh management table explained in Figure 5 and selects one refresh bank group from among the refresh bank groups that include multiple banks for which no flags are set.

[0042] Subsequently, in S708, the refresh generation unit 306 selects two banks from the refresh bank group determined in S707.

[0043] Finally, in S709, the refresh generation unit 306 generates a refresh request for the bank determined in S708, notifies the command issuance unit 304, waits for a response, and terminates the process.

[0044] In S710, the refresh generation unit 306 determines a refresh bank group from the candidates for refreshable refresh bank groups. Then, in S711, the refresh generation unit 306 determines two banks from the refresh bank group determined in S709. Finally, in S712, the refresh generation unit 306 generates a refresh request for the banks determined in S710, notifies the command issuance unit 304, waits for a response, and terminates the process. This completes the series of processes shown in Figure 7.

[0045] <How Refresh Bank Group Candidates are Selected> Figure 8 is a diagram illustrating the method for determining refresh bank group candidates executed by the refresh generation unit 306 according to this embodiment. The refresh generation unit 306 counts the total number of read commands and write commands (hereinafter referred to as read / write commands) for each refresh bank group, totaling 801, from the access command information stored in the command storage unit 303.

[0046] Next, the refresh generation unit 306 calculates the total number of read and write commands (802) for the other refresh bank groups. For example, the total number of read and write commands accessing banks other than refresh bank group 0 is 68, which is the total number of read and write commands for banks from refresh bank group 1 to refresh bank group 3.

[0047] Finally, the refresh generation unit 306 determines the refresh priority 803. Here, we assume that the number of read / write commands that can be issued to other banks in parallel during refresh execution is 50 (a predetermined number). If a refresh bank group with 50 or more (a predetermined number or more) read / write commands to other refresh bank groups is selected as the refresh bank, it becomes possible to continuously issue read / write commands to other banks in parallel with the refresh. This suppresses the degradation of memory access performance during the refresh. Therefore, a refresh bank group with more than 50 read / write commands to other refresh bank groups becomes a refresh candidate.

[0048] Furthermore, if there are multiple candidates for a refresh bank group, the bank with the most read / write commands to other refresh bank groups will be given higher priority. In Figure 8, among the refresh candidates, refresh bank group 2, which has the most read / write commands to other refresh bank groups (88), will have the highest priority, while refresh bank group 3, which has the fewest (60), will have the lowest priority. Refresh bank group 1 has 48 (<50) read / write commands to other refresh bank groups, compared to a total of 802. Therefore, it will not be a refresh candidate because it may issue all available read / write commands during the refresh process, potentially preventing it from issuing any more read / write commands until the refresh is complete.

[0049] Here, refresh bank groups with a higher total number of read / write commands (802) were given higher refresh priority, but this is not always the case.

[0050] Any refresh bank group may be selected if the total number of read / write commands across all refresh bank groups is greater than 50, and the priority may be fixed or periodically switched.

[0051] Furthermore, although not shown in Figure 8, if the buffer of the command storage unit 303 becomes empty, there will be no memory access, and therefore it will not be necessary to consider the degradation of memory access performance due to refreshing. In this case, all refresh bank groups may be considered as refresh candidates.

[0052] In this way, when a bank-specific refresh is issued, the refresh bank group is determined in which the total access time (total number of commands) of banks other than the refresh bank group to which the specified bank belongs is greater than the refresh time.

[0053] LPDDR5 is designed to refresh two of its 16 banks simultaneously. However, when refreshing two of the 16 banks simultaneously, if the banks are classified into multiple groups and any two banks can be selected from within those groups, the number of possible combinations of banks to refresh increases. As a result, the number of counters used to count the number of read and write commands for banks other than those being refreshed increases. However, according to this embodiment, the number of counting combinations can be reduced from 24 to 4, making it possible to determine which banks to refresh with fewer hardware resources.

[0054] <How to decide which bank to refresh> Next, Figure 9 is a flowchart illustrating the method for determining which banks to refresh, as executed by the refresh generation unit 306 according to this embodiment. As shown in Figure 4, DRAM refresh control needs to be issued in a way that is not biased across all banks. In this embodiment, each refresh bank group has four banks, and when a refresh bank group is selected, there are cases where not all banks have been refreshed, and cases where two banks have been refreshed.

[0055] Therefore, in S901, the refresh generation unit 306 determines whether or not there are banks that have already been refreshed. If there are banks that have already been refreshed, the process proceeds to S902. On the other hand, if there are no banks that have already been refreshed, the process proceeds to S903.

[0056] In S902, the refresh generation unit 306 selects two banks that have not yet been refreshed. If no refresh has been performed on any of the banks in the refresh bank group, the refresh generation unit 306 selects any two banks from within the refresh bank group. Here, the refresh generation unit 306 may prioritize the selection of banks that are frequently accessed and control the system to perform the refresh first. Alternatively, the refresh generation unit 306 may select a combination of banks N and bank N+8 (where N is between 0 and 7), which is a combination of banks that can issue refreshes simultaneously in LPDDR4. Furthermore, if there are transfers with high memory access priority, the refresh generation unit 306 may control the system to avoid selecting banks with high-priority memory accesses, as it may be better to prioritize memory accesses over refreshes in such cases.

[0057] In S903, the refresh generation unit 306 issues refreshes to two banks within the refresh bank group. This completes the series of processes shown in Figure 9.

[0058] <Controlling the order in which access commands are issued> Figure 10 is a flowchart illustrating the procedure by which the command storage unit 303 controls the order in which access commands are issued according to this embodiment. Some DRAM control devices have a function to rearrange the order of received memory access requests in order to improve the efficiency of DRAM access or according to the urgency of the memory access request. In this embodiment, the method for controlling the order in which memory access requests are issued is switched based on whether or not a bank-specific refresh is being performed. This flow is started when the command issuing unit 304 is notified that an access command has been stored, and / or when the state of the DRAM changes due to the issuance of a DRAM command.

[0059] In S1001, the command storage unit 303 monitors the refresh requests and responses from the refresh generation unit 306 and the command issuance unit 304 to determine whether a bank-specific refresh is currently being performed. If a bank-specific refresh is currently being performed, the process proceeds to S1002. If a bank-specific refresh is not currently being performed, the process proceeds to S1003.

[0060] In S1002, the command storage unit 303 controls the order in which access commands are issued to prioritize memory access requests to banks other than the bank being refreshed. In S1003, the command storage unit 303 controls the order in which access commands are issued for all memory access requests.

[0061] When controlling the order in which access commands are issued, you can prioritize memory access requests that do not degrade memory access performance, or you can prioritize memory access requests of high urgency. As mentioned above, by selecting banks that do not affect memory access and performing a bank-specific refresh, and then rearranging the order of memory access requests according to the refresh execution status, it is possible to perform a refresh while suppressing a degradation in memory access performance.

[0062] As explained above, according to this embodiment, by issuing a bank-specific refresh to banks that do not affect memory access, the performance degradation of memory access can be suppressed by reducing the waiting time for memory access due to the refresh. Furthermore, even if the number of combinations of banks to be refreshed simultaneously increases, the banks to be refreshed can be determined with a small number of counters. In other words, it becomes possible to determine the banks to be refreshed with fewer hardware resources.

[0063] The disclosures herein include the following control devices, methods for operating the control devices, and programs.

[0064] (Item 1) A control device for controlling access to DRAM, A generation means that generates an access command in response to an access request to the DRAM and stores it in a buffer, A classification means for classifying multiple banks contained in the DRAM into multiple candidate groups, A selection means for selecting a candidate group from the plurality of candidate groups based on the storage status of the access command stored in the buffer, A decision means for determining which bank to request a refresh from the selected candidate group, A control device characterized by comprising:

[0065] (Item 2) The aforementioned selection means is, The access commands stored in the buffer are monitored, and the number of access commands to be issued to each candidate group is calculated. The control device according to item 1, characterized in that it selects a candidate group from the plurality of candidate groups based on the number of access commands for each candidate group.

[0066] (Item 3) The control device according to item 2, characterized in that the selection means selects a candidate group from among the plurality of candidate groups such that the total number of access commands to other candidate groups is equal to or greater than a predetermined number.

[0067] (Item 4) The control device according to item 2 or 3, wherein the selection means is characterized by prioritizing the selection of candidate groups in which the total number of access commands to other candidate groups among the plurality of candidate groups is equal to or greater than a predetermined number, and selecting the candidate group with the largest total number.

[0068] (Item 5) The control device according to any one of items 1 to 4, characterized in that the selection means selects all of the plurality of candidate groups as candidate groups when the buffer is empty.

[0069] (Item 6) The control device according to any one of items 1 to 5, characterized in that the determination means determines a group from the selected candidate group and determines a bank to which the refresh request will be made from the determined group.

[0070] (Item 7) The control device according to item 6, characterized in that, if there is a bank in the determined group that has already undergone a refresh, the control device determines two banks that have not yet undergone a refresh as the banks to which the refresh request will be made.

[0071] (Item 8) Request generation means for generating a refresh request for the determined bank, An issuing means for issuing a DRAM command to the DRAM based on the access command and the refresh request, A control device according to any one of items 1 to 7, further comprising the above.

[0072] (Item 9) The control device according to item 8, characterized in that the issuing means controls the order in which the access commands stored in the buffer are issued according to the refresh execution status.

[0073] (Item 10) The control device according to item 9, characterized in that, when the issuing means is performing the refresh, it controls the order in which the access commands are issued to prioritize access requests to banks other than the bank in which the refresh is being performed.

[0074] (Item 11) A method for operating a control device that controls access to DRAM, The process involves generating an access command in response to an access request to the DRAM and storing it in a buffer. A step of classifying multiple banks contained in the DRAM into multiple candidate groups, A step of selecting a candidate group from the plurality of candidate groups based on the storage status of the access command stored in the buffer, The process of determining a bank to which a refresh request will be made from the selected candidate group, A method for operating a control device, characterized by having the following features.

[0075] (Item 12) A program that causes a computer to execute the operation method of the control device described in item 11.

[0076] (Other embodiments) The present invention can also be realized by supplying a program that implements one or more of the functions of the above-described embodiments to a system or device via a network or storage medium, and by having one or more processors in the computer of that system or device read and execute the program. It can also be realized by a circuit (e.g., an ASIC) that implements one or more functions.

[0077] The invention is not limited to the embodiments described above, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, claims are attached to disclose the scope of the invention. [Explanation of symbols]

[0078] 300: DRAM control unit, 301: DRAM, 302: Bus interface, 303: Command storage unit, 304: Command issuing unit, 305: Refresh timer, 306: Refresh generation unit

Claims

1. A control device for controlling access to DRAM, A generation means that generates an access command in response to an access request to the DRAM and stores it in a buffer, A classification means for classifying multiple banks contained in the DRAM into multiple candidate groups, A selection means for selecting a candidate group from the plurality of candidate groups based on the storage status of the access command stored in the buffer, A decision means for determining which bank to request a refresh from the selected candidate group, A control device characterized by comprising:

2. The aforementioned selection means is, The access commands stored in the buffer are monitored, and the number of access commands to be issued to each candidate group is calculated. The control device according to claim 1, characterized in that it selects a candidate group from the plurality of candidate groups based on the number of access commands for each candidate group.

3. The control device according to claim 2, wherein the selection means selects a candidate group from among the plurality of candidate groups such that the total number of access commands to other candidate groups is equal to or greater than a predetermined number.

4. The control device according to claim 2 or 3, wherein the selection means prioritizes selecting the candidate group whose total number of access commands to other candidate groups among the plurality of candidate groups is greater than or equal to a predetermined number, and which candidate group has the largest total number.

5. The control device according to any one of claims 1 to 4, characterized in that the selection means selects all of the plurality of candidate groups as candidate groups when the buffer is empty.

6. The control device according to any one of claims 1 to 5, characterized in that the determination means determines a group from the selected candidate group and determines a bank to make the refresh request from the determined group.

7. The control device according to claim 6, characterized in that, if there is a bank in the determined group that has already undergone a refresh, the determination means determines two banks that have not yet undergone a refresh as the banks to which the refresh request will be made.

8. Request generation means for generating a refresh request for the determined bank, An issuing means for issuing a DRAM command to the DRAM based on the access command and the refresh request, The control device according to any one of claims 1 to 7, further comprising the above.

9. The control device according to claim 8, characterized in that the issuing means controls the order in which the access commands stored in the buffer are issued according to the refresh execution status.

10. The control device according to claim 9, characterized in that, when the issuing means is performing the refresh, it controls the order in which the access commands are issued to prioritize access requests to banks other than the bank in which the refresh is being performed.

11. A method for operating a control device that controls access to DRAM, The process involves generating an access command in response to an access request to the DRAM and storing it in a buffer. A step of classifying multiple banks contained in the DRAM into multiple candidate groups, A step of selecting a candidate group from the plurality of candidate groups based on the storage status of the access command stored in the buffer, The process of determining a bank to which a refresh request will be made from the selected candidate group, A method for operating a control device, characterized by having the following features.

12. A program for causing a computer to execute the operation method of the control device described in claim 11.

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